CN1159769C - A kind of single-electron transistor and its preparation method - Google Patents

Abstract

The present invention relates to microelectronics and micromachining methods. The invention provides a single electron transistor composed of a one-dimensional waveguide and a linear grid. The single-electron transistor is prepared by utilizing the technologies of forming quantum dots by combining a one-dimensional waveguide and a line grating and the like. The invention reduces the process damage and improves the yield through the application of the technology such as 'grooving' and the like. The single-electron transistor has good working stability and is suitable for integration. The size of the quantum dot can be reduced to nanometer level, so that the working temperature of the device is greatly improved.

Description

A kind of single-electron transistor and its preparation method

technical field

The present invention relates to microelectronic devices and micromachining methods.

Background technique

Traditional electronic transistors realize functions such as switching, oscillation, and amplification by controlling the collective movement of more than tens of millions of electrons in groups; single-electron transistors can achieve specific functions only through the behavior of one electron. With the improvement of integration, power consumption has become a limiting factor for the circuit stability of microelectronic devices. Components composed of single-electron transistors can greatly increase the integration of microelectronics and reduce power consumption to 10 ^-5 .

1 is a schematic diagram of a known single-electron transistor, which consists of a source 1, a drain 2, a quantum dot (or Coulomb island) 3, two tunneling nodes 4 and 5, and a gate 6 that regulates the number of electrons in the Coulomb island. Its normal operation requires two basic conditions: (1) The resistance between the source and the drain is greater than the quantum resistance R _q = h/e2≈26kΩ; (2) The capacitance of the quantum dot is small enough so that e ² /2C＞＞k _B T. Among them: C is the capacitance of the quantum dot, k _B is the Boltzmann constant, and T is the working temperature. When the quantum dots have an effective diameter of less than 10 nanometers, single-electron transistors can operate at room temperature.

At present, single-electron transistors can be divided into material systems: (1) metal single-electron transistors, (2) organic material single-electron transistors, and (3) semiconductor single-electron transistors. The first two types of single-electron transistors are mainly used for technology exploration and basic characteristic research, and the last one can be used for applied research and even product development. The preparation methods of these single-electron transistors mainly include: (1) scanning probe microscope SPM technology, (2) focused ion beam implantation FIB technology, (3) electron beam lithography technology. The repeatability and stability of single-electron transistors prepared by the first two techniques are relatively poor, and the microfabrication time of the first technique is too long. Therefore, the use of electron beam lithography to prepare semiconductor single-electron transistors has more important significance, especially the use of high-mobility two-dimensional electron gas structure samples to prepare single-electron transistors has more potential significance. The quantum dot structure of the single-electron transistors in this aspect is realized by the negative bias depletion of the large-area surface gate. Figure 2 is a schematic diagram of the structure and principle of a typical single-electron transistor. It is mainly composed of a capping layer 7, a two-dimensional electron gas layer 8, a capping surface layer 9, and a surface gate 6. A sufficiently large negative electrode is added to the gate 6. The bias voltage forms the quantum dot 3 (Document 1, R.C. Ashooriza, February 1, 1996, Nature). This surface-gate single-electron transistor has the following disadvantages: (1) The large negative bias on the surface gate leads to a large depletion region, so that the geometric size of the quantum dot cannot be too small (as shown in Figure 3), and must be larger than (B1 +B2), otherwise the transistor will not conduct. The quantum dot potential energy distribution of this kind of transistor is flat, the depletion width is large, and the geometric size of the quantum dot cannot be small to the nanometer level, so it can only work at extremely low temperature. (2) The potential energy profile of quantum dots is not steep and the number of impurities under the potential barrier caused by the large-area surface gate increases, which leads to the unstable working state of the single-electron transistor. (3) Quantum dots are realized entirely by surface gates, which limits their applications and makes their integration impossible.

Contents of the invention

The object of the present invention is to overcome the deficiencies of the prior art, and provide a single-electron transistor composed of one-dimensional waveguide and line grid, which has high working temperature, stable performance and is suitable for integration. The single-electron transistor of the present invention is prepared by using the technology of combining one-dimensional waveguide and line grid to form quantum dots. Through the application of technologies such as "grooving", the process damage is reduced and the yield rate is improved.

The purpose of the present invention is achieved like this:

The single-electron transistor of the present invention is constituted as follows: between the substrate, the buffer layer and the mesa is a two-dimensional electron gas layer, and utilizes the two-dimensional electron gas layer to form an ohmic contact as a source and a drain through an alloy, and utilizes "grooving "Technology forms a one-dimensional waveguide between the source and the drain. The one-dimensional waveguide is isolated from other mesas through the groove. Two barrier line grids and two side line grids are deposited on the one-dimensional waveguide. The barrier line Applying a negative bias to the grid depletes the electron gas beneath the two barrier bars, forming quantum dots in the waveguide between them.

Its quantum dots are formed by a one-dimensional waveguide and a negative bias applied to the line barrier grid. The waveguide region under the two potential barrier line grids is the two tunnel junctions of the single electron transistor. A bias voltage on the side gate changes the number of electrons in the quantum dot.

The preparation single-electron transistor method of the present invention is realized according to the following steps:

(1) For samples with a two-dimensional electron gas layer grown by methods such as molecular beam epitaxy, liquid phase epitaxy, or gas phase epitaxy, the thickness from the sample surface to the electron gas layer is not greater than 60 nanometers.

(2) Overlay marks are prepared by conventional photolithography or electron beam lithography by metal deposition stripping or mesa corrosion technology, and the height of the marks must be greater than 200 nanometers, otherwise the overlay accuracy will be affected.

(3) The large-area part of the device is prepared by ordinary photolithography, including the device mesa prepared by the deep etching method, the ohmic contact prepared by rapid annealing and the lead contact part of the Schottky gate prepared by metal evaporation.

(4) Prepare a one-dimensional waveguide with a width Ww of 1000 nanometers ≥ Ww ≥ 200 nanometers by wet etching, using the "grooving" technique (as shown in Figure 4, and controlling the corrosion section of the "inverted triangle", "grooving" The depth Hw is 70 nanometers≥Hw≥40 nanometers, and the width Wc of the groove is 1000 nanometers≥Wc≥50 nanometers. If the groove is to be used to form a planar grid, its width is preferably limited to about 500 nanometers. This step can also be used dry etched to complete.

(5) Fabricate a line grid on the waveguide by electron beam lithography, X-ray or phase shift mask. If the suspended grid technology (shown in Figure 5) is used, the yield of the device can be improved. Because the grid on the step undulating surface has strong local stress, it is easy to break locally during peeling; in addition, the uneven local stress of the grid will make the grid and the surface of the waveguide virtual contact and cannot form a Schottky The potential barrier will also make the bar grid contact with the two-dimensional electron gas on the corrosion surface, resulting in a large leakage current. In order to avoid the occurrence of the above situation, during the evaporation process, the source evaporation angle and the grid orientation are evaporated at 90 degrees, and the evaporation source metal is selected so that it has good adhesion to the sample surface and a good Schottky formation with the sample. The potential barrier has a high barrier height, good stability and is not easy to oxidize. During the process, the sample can only be approached after the induction of the human body is released, otherwise its discharge will destroy the waveguide of the narrow channel and the extremely fine line grid.

The working principle of the single-electron transistor of the present invention is that electrons are restricted to move in a one-dimensional waveguide, and this electronic waveguide is equivalent to the Fabry-Parot cavity in optics, so this single-electron transistor is more likely to display quantum effects such as phase coherence; In the single-electron transistor structure, the reduction of the surface gate area also reduces the probability of impurities in the barrier region and improves the stability of the device; the use of the inverted triangular corrosion section and the hanging gate technology avoids the contact between the gate and the channel layer, reducing The leakage current is reduced, and the yield of the device is improved; the use of the line grid instead of the large-area surface grid weakens the shielding effect of the metal grid on electrons, and reduces the capacitance of the quantum dots, thereby increasing the operating temperature of the device; small The gate bias can form a tunnel junction under the gate, making the potential energy profile of the quantum dots steep and regular (Figure 6) and making the performance of the device stable and reliable. The size of its quantum dots can be as small as nanometers, thereby greatly increasing the operating temperature of the device.

Description of drawings

Figure 1: Schematic diagram of a known single-electron transistor.

Figure 2: Schematic diagram of the structure and principle of a traditional single-electron transistor.

Figure 3: Quantum dot potential energy distribution diagram of a conventional single-electron transistor.

Fig. 4: Schematic diagram of the structure of the single-electron transistor of the present invention.

Figure 5: A 1D waveguide and a suspended wire grid fabricated using the wet etch "trench" technique.

Fig. 6: The quantum dot potential energy distribution diagram of the single-electron transistor of the present invention.

Detailed ways

Example 1

Using AlGaAs/InGaAs/AlGaAs modulation doped two-dimensional electron gas samples to prepare single-electron transistors with stable performance, high operating temperature and suitable for applications (as shown in Figure 4).

Sample growth: 1) Grow a 750nm thick buffer layer 11 on a Si-GaAs substrate by molecular beam epitaxy at a growth temperature of 750°C; 2) grow a two-dimensional electron gas layer 8 at 650°C on the buffer layer: namely 14.5nm InGaAs layer and 1nm GaAs layer, in which the In content is 0.18; 3) The substrate temperature is raised to 780°C, and a 10nm AlGaAs layer and a Si-doped 30nm AlGaAs layer are grown, 4) The substrate temperature is lowered to 750°C ℃ to grow a 10nm GaAs capping layer. Steps 3) and 4) are etched to form the mesa 10 .

Device preparation: 1) overlay marking preparation: 1) ultrasonically clean the sample in trichlorethylene, acetone, and absolute ethanol for 5 minutes; 2) bake at 110° C. for 30 minutes to remove moisture on the surface of the sample; The glue machine casts 600nm electron beam photoresist PMMA on the surface of the sample and bakes it at 170°C for 60 minutes; 4) Use electron beam lithography to prepare left and right symmetrical double "+" marks with a line width of 1- 5 microns, the length is 1000 microns; 5) develop with methyl isobutyl ketone for 30 seconds and fix with isopropanone for 50 seconds; 6) wash the sample with absolute ethanol for 60 seconds and put it into the electron beam evaporation chamber; 7) when the evaporation chamber When the vacuum degree reaches above 7×10 ^-4 Pa, evaporate titanium (or niobium, road) 50nm-100nm and gold above 150nm; 8) Ultrasonic peeling; 9) Long-term UV exposure for more than 60 minutes and repeat the second step step to remove residual e-beam photoresist. II) Preparation of device mesas 10, ohmic contact source 1 and drain 2, and large-area lead contact parts by conventional photolithography; III) Preparation of one-dimensional waveguide 12: 10) Preparation of "grooves" by electron beam lithography Graphics, repeat the steps of the first 5 steps, but the thickness of the electron beam photoresist at this time is 100 nanometers, and the photoresist can be PMMA or ZIP and so on. 11) The sample was washed with absolute ethanol, and the system of H ₂ SO ₄ : _{H 2} O ₂ : _{H 2} O was selected to “dig a groove” whose depth just reached the two-dimensional electron gas layer. Wet heterogeneous etching is used to control the corrosion section of the "inverted triangle" to form grooves 17 and 18. On the one hand, the effective waveguide width is made as narrow as possible to increase the operating temperature of the device, and on the other hand, the two-dimensional electron gas 19 and the bar grid in the channel are avoided. Possible direct contact of 13, 14, 15, 16. In order to realize the "inverted triangle" corrosion section, the corrosion edge should be along the <011> and <011> directions, and electrochemically controlled corrosion solutions such as dilute sulfuric acid, phosphoric acid and acidic acid corrosion systems should be selected, and the corrosion rate should be controlled at 0.1 per second. between nanometers and 1.6 nanometers. 12) Remove photoresist with acetone and repeat step 9 to remove residual e-beam photoresist. IV) Line grid preparation: 15) Repeat steps 10, 7 and 8, but this time evaporate titanium (or niobium, chromium) 5nm-30nm and gold 20nm-30nm. The waveguide between the barrier bar grids 13 and 15 is the quantum dot 3 .

Device performance: The yield of the device is over 95% and has a fairly good stability. (1) in a month

Repeat the measurement of 8 devices 60 times, and the single-electron Coulomb oscillation curves are completely coincident; (2) The devices with a one-dimensional waveguide width of 280 nanometers, a width of 4 bar grids and a mutual spacing of 50 nanometers can all be above 20K The temperature shows clear single-electron Coulomb oscillation; (3) Using this single-electron transistor, we detected the single-electron storage process of the single-electron memory and successfully developed it into an ultra-sensitive coulomb counter for charge.

Example 2

Using AlGaAs/GaAs modulation doped two-dimensional electron gas samples (basically the same technique as in Example 1, except that InGaAs is replaced by a GaAs layer) to prepare single-electron transistors with various quantum characteristics: (1) single-electron transistors of quantum waveguide type Electron transistor, observed the modulation effect of quantum coherence characteristic to single electron Coulomb oscillation amplitude; The energy-level coupling effect of quantum dots; (2) The single-electron transistor with the width and spacing of the gates equal to 50 nanometers shows obvious spin Coulomb blocking effect.

Example 3

Using "conventional lithography" to replace "electron beam lithography" in Example 1 to prepare overlay marks, a low-temperature single-electron transistor was fabricated. Its yield rate is 76%, far lower than the yield rate in Example 1.

Example 4

"Mesa corrosion" was used to replace the "metal deposition stripping technique" in Example 1 to prepare overlay marks, and the depth of mesa corrosion was 500 nanometers. The yield of single-electron transistors was 68%.

Example 5

"Mesa corrosion" was used to replace the "metal deposition stripping technique" in Example 3 to prepare overlay marks, and the depth of mesa corrosion was 500 nanometers. The yield of single-electron transistors was 56%.

Example 6

The one-dimensional waveguide was prepared by dry etching instead of the wet etching in Example 1, and the yield of the single-electron transistor was 89%. Repeated measurements of single-electron Coulomb oscillation curves are difficult to completely coincide. This is mainly due to the damage to the sample caused by dry etching.

Example 7

The sample in embodiment 1 is changed to following sample: 1) Utilize molecular beam epitaxy technique to grow 750 nanometer thick buffer layer on Si-GaAs substrate, growth temperature is 750 ℃, 2) grow 14.5 nanometer Si-InGaAs at 650 ℃ layer and 1 nanometer GaAs layer, in which the In content is 0.18. 3) The substrate temperature is raised to 780°C to grow a 40nm AlGaAs layer 4) The substrate temperature is lowered to 750°C to grow a 10nm GaAs capping layer.

The properties of their single-electron transistors are complex, showing aperiodic single-electron Coulomb oscillations. This is mainly due to the fact that the one-dimensional waveguide contains multiple quantum dots.

Claims (6)

1. single-electronic transistor, it is characterized in that: between substrate and resilient coating (11) and table top (10) is two-dimensional electron gas layer (8), utilize the two-dimensional electron gas layer to form ohmic contact as source electrode (1) and drain electrode (2) by alloy, " grooving " technology of utilization forms one-dimensional wave guide (12) between source electrode and drain electrode, one-dimensional wave guide is partly isolated with other table tops by groove (17) and (18), deposition forms two potential barrier lines grid (13) on one-dimensional wave guide, (15) and two sideline bar grid (14), (16), at potential barrier lines grid (13), (15) add back bias voltage on, exhaust the electron gas under these two potential barrier lines grid, thereby form quantum dot (3) in the waveguide between them.

2. method for preparing the single-electronic transistor of claim 1 is characterized in that: carry out according to the following steps:

(1) sample of two-dimensional electron gas layer is arranged with molecular beam epitaxial method growth, be not more than 60 nanometers to the electronics thickness of gas from sample surfaces;

(2) prepare overlay mark with the electron beam photoetching process by the mesa etch technology, the height that makes mark is greater than 200 nanometers;

(3) be equipped with the large tracts of land part of device with common photoetching legal system, promptly be equipped with the lead-in wire contact portion that part table, annealing preparation ohmic contact and evaporation of metal prepare Schottky gate with the deep etch legal system;

(4) be equipped with the one-dimensional wave guide that width W w is 1000 nanometers 〉=Ww 〉=200 nanometers with the wet corrosion legal system, the corrosion cross section of " grooving " technology of employing and control " del ", " grooving " depth H w is 70 nanometers 〉=Hw 〉=40 nanometers, and the width W c of groove is 1000 nanometers 〉=Wc 〉=50 nanometers;

(5) utilize the electron beam lithography method in waveguide, to prepare lines grid (13), (14), (15) and (16), in evaporation process, make source evaporation angle become 90 degree evaporations with bar grid orientation, select the evaporation source metal so that the Schottky barrier that adhesiveness is good and sample forms of itself and sample surfaces and high barrier height, good stability are arranged and be difficult for oxidation, in the technical process, just can be after discharging the human body sensing electricity near sample.

3. by the described preparation method of claim 2, it is characterized in that: wherein step (1) can also adopt liquid phase epitaxy or vapour phase epitaxy to grow the sample of two-dimensional electron gas layer.

4. by the described preparation method of claim 2, it is characterized in that: wherein step (2) can also adopt conventional photoetching process to prepare overlay mark.

5. by the described preparation method of claim 2, it is characterized in that: wherein step (2) can also prepare overlay mark by the metal deposition lift-off technology.

6. by the described preparation method of claim 2, it is characterized in that: wherein step (4) can also prepare one-dimensional wave guide with dry etching.

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