CN115966594A - MOSFET device with protected gate charge balance and method of making the same - Google Patents
MOSFET device with protected gate charge balance and method of making the same Download PDFInfo
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Abstract
The application relates to a MOSFET device with a protected gate and a charge balance function, which comprises a substrate, a first epitaxial structure used for forming a multi-layer isolation gate well, a second epitaxial structure used for forming a shielding electric field and a third epitaxial structure which forms a space charge area together with the second epitaxial structure. And a plurality of grid grooves are formed in the third epitaxial structure. And forming a shielding electric field through the second epitaxial structure to protect the position with higher electric field line density at the bottom surface of the gate trench. Meanwhile, the second epitaxial structure and the third epitaxial structure are combined to form a space charge region, so that an electric field part at the bottom of the grid groove is transferred to the space charge region, the electric field at the bottom of the grid groove is reduced, the working reliability of the MOSFET is improved, and lower switching loss is realized. And finally, the JFET effect in the MOSFET is reduced through the isolation gate well, and the JFET effect and a space charge region formed by the second epitaxial structure and the third epitaxial structure act together to reduce the conduction loss of the MOSFET.
Description
Technical Field
The present disclosure relates to the field of semiconductor devices, and more particularly, to a MOSFET device with a balanced gate charge and a method for manufacturing the MOSFET device.
Background
A MOSFET is a short term Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and is a type of MOSFET widely used in analog circuits and digital circuits. The MOSFET includes a source, a gate and a drain, and the charge balance of the gate affects the gate voltage, which determines the on or off state between the source and the drain, and also affects the on performance and the operational reliability of the entire MOSFET.
Chinese patent publication No. CN113851524A discloses a multi-source MOS transistor shared gate charge balance chip structure and a manufacturing method thereof, the structure mainly includes a drain substrate, a shared gate filler, a charge balance filler, a plurality of contact hole structures, and a source cover layer and a gate cover layer. The source covering layer is driven by a common gate filling body communicated with the gate covering layer and conducted to the back surface of the drain substrate; the charge balance filling body is provided with a balance part which is positioned below the bottom of the common gate filling body and a source contact part which is integrally connected and positioned in the balance groove, so that the height difference of the top surface is formed. In the step of opening the trench once, when the gate contact hole structure is drilled in the common gate filler, the balance gate contact hole structure is also drilled in the source contact part, so that the field effect transistor framework has the effect of balancing the charges of the gate bottom part shared by the MOS tubes, the resistance of the drift layer is stably reduced, the trench type MOS tube is densified, and the surface contact hole process is in place in one step.
Chinese patent publication No. CN114242768A discloses a silicon carbide MOSFET device with improved gate bottom charge balance and a manufacturing method thereof, the device includes an epitaxial wafer structure with a charge balance column, an embedded gate structure, a source structure located at the top layer and a drain structure located at the bottom layer, and a channel compliance layer after trenching is formed on the silicon carbide epitaxial layer of the epitaxial wafer structure. And forming non-planar ohmic contact between the source electrode structure and the epitaxial wafer structure by utilizing the contact grooves positioned at the two sides of the grid electrode structure. The charge balance column is arranged below the gate trench and the contact trench and is basically formed by a preset laminated well, so that the charge balance column is prevented from penetrating into a silicon carbide substrate of the epitaxial wafer structure. The method has the effect of standardizing the bottom depth and the appearance of the gate bottom charge balance junction by a better section column shape, so as to solve the defects that the charge balance junction can not adjust the injection concentration and can not form a junction side column shape and the electrical property of the junction bottom depth is unstable along with the change of the trench depth on the basis of the arrangement of the channel compliant layer.
Disclosure of Invention
In view of the above, there is a need to provide a MOSFET device with a balanced protection gate charge to improve the reliability and turn-on performance of the MOSFET device.
A protected gate charge balanced MOSFET device comprising:
a substrate;
the first epitaxial structure is formed on the substrate, and a multi-layer isolation gate well is formed in the first epitaxial structure;
a second epitaxial structure formed on the first epitaxial structure; the second epitaxial structure is provided with a connecting junction the bottom end of which is connected with the multi-layer isolation gate well, and the width of the connecting junction is smaller than that of the multi-layer isolation gate well;
a third epitaxial structure formed on the second epitaxial structure; the top end of the connecting junction is connected with the active layer of the third epitaxial structure; the third epitaxial structure is provided with a plurality of grid grooves, the multi-layer isolation grid well is positioned between the grid grooves, the grid grooves penetrate through the third epitaxial structure, and corners on the bottom surface and two sides of the bottom surface of each grid groove are positioned in the second epitaxial structure; a source electrode field layer is formed in the surface layer of the third epitaxial structure and is positioned on the active layer;
the grid filling body is arranged in the grid groove;
an interlayer film disposed on the third epitaxial structure to cover the source field layer;
the third epitaxial structure is provided with a contact groove for filling a source electrode, the contact groove is aligned to the connecting junction and penetrates through the interlayer film, the source electrode field layer is exposed on the side wall of the contact groove, and the bottom surface and the corners on the two sides of the bottom surface of the contact groove are positioned in the active layer of the third epitaxial structure.
Through the technical scheme, the second epitaxial structure can form a shielding electric field, and the expanded shielding electric field can protect the grid electrode in the grid electrode groove so as to relieve the electron tunneling effect generated by the intensive electric field lines on the bottom surface of the grid electrode and the corner positions on two sides of the bottom surface, so that charges cross potential energy barriers from the bottom of the grid electrode to generate leakage current and increase the power consumption of the MOSFET. The third epitaxial structure and the second epitaxial structure are combined to form a space charge area, so that the electric field part at the bottom of the grid groove is transferred to the space charge area, the electric field at the bottom of the grid groove is reduced, the working reliability of the MOSFET is improved, and lower switching loss is realized. The isolation gate well can reduce JFET effect in the MOSFET and can reduce conduction loss of the MOSFET by coaction with the space charge region formed by the second epitaxial structure and the third epitaxial structure.
In one embodiment, the first epitaxial structure is formed by overlapping a plurality of epitaxial layers, and the thickness of the second epitaxial structure is smaller than that of the epitaxial layers.
Through the technical scheme, the first epitaxial structure is formed by overlapping the multiple epitaxial layers, and the problems that the isolation gate well in the first epitaxial structure is deep in thickness, the accuracy of the isolation gate well at the bottom cannot be controlled, so that the electrical performance is unstable and the concentration cannot be adjusted can be solved. The thickness of the second epitaxial structure is less than the thickness of the epitaxial layer so that the second epitaxial structure is relatively more easily depleted to form a shielded electric field.
In one embodiment, the ion doping concentration in the second epitaxial structure is less than the ion doping concentration of the epitaxial layer and not less than 20% of the ion doping concentration of the epitaxial layer.
Through the technical scheme, the ion doping concentration of the second epitaxial structure is controlled to be 20% of that of the epitaxial layer, so that majority carriers in the second epitaxial structure can be quickly depleted to form a shielding electric field, and the concentration is sufficient for maintaining the carrier requirement during conduction.
In one embodiment, a gate oxide layer is formed on the inner wall of the gate trench, and the thickness of the bottom surface of the gate oxide layer is greater than that of the side surface of the gate oxide layer.
Through the technical scheme, the electric field line density at the bottom surface of the grid groove and the corner positions at two sides of the bottom surface is higher, and the electronic tunneling is relatively easier to occur. The thickening of the gate oxide layer on the bottom surface of the gate groove can prevent the charges from crossing the groove to generate leakage current, thereby reducing the conduction loss of the MOSFET.
In one embodiment, the source electrode includes a source contact layer and a source pad layer, which are sequentially disposed on the interlayer film.
Through the technical scheme, the source electrode liner layer is used for forming the contact electrode so as to conduct an external circuit. The source contact layer is filled between the contact trench of the third epitaxial structure and the source liner layer, so that metal atoms of the source liner layer are prevented from diffusing towards the direction of the third epitaxial structure while ohmic contact is formed.
In one embodiment, a protection region is formed on the bottom surface of the contact trench, and the ion doping concentration of the protection region is greater than that of the surrounding region.
Through the technical scheme, the contact trench is used for being directly electrically contacted with the source electrode, so that the protection region ensures that enough carriers are available at the contact position of the source electrode in the contact trench for charge transfer by using high ion doping concentration, and the problem of poor conduction of a contact point caused by insufficient carrier quantity due to diffusion of ions at the bottom of the contact trench to the periphery is prevented.
In one embodiment, the width ratio of the connecting junction to the isolation gate well ranges from 0.2 to 1.
Through the technical scheme, the third epitaxial structure is connected to the isolation gate well through the connecting junction, the width of the connecting junction is set to be 0.2 of the width of the isolation gate well, the electric connection between the third epitaxial structure and the isolation gate well can be guaranteed, and the phenomenon that the space of the second epitaxial structure is occupied to influence the formation of a shielding electric field is avoided.
The present application further provides a method for manufacturing a MOSFET device with a balanced gate charge, comprising:
providing a substrate;
forming a first epitaxial structure for arranging an isolation gate on the substrate, and forming a multi-layer isolation gate well in the first epitaxial structure;
forming a second epitaxial structure for shielding an electric field on the first epitaxial structure; the second epitaxial structure is provided with a connecting junction the bottom end of which is connected with the multi-layer isolation gate trap, and the width of the connecting junction is smaller than that of the multi-layer isolation gate trap;
forming a third epitaxial structure for providing a channel on the second epitaxial structure; the top end of the connecting junction is connected with the active layer of the third epitaxial structure;
a plurality of grid grooves are formed in the upper surface of the third epitaxial structure, the multi-layer isolation grid well is located between the grid grooves, the grid grooves penetrate through the third epitaxial structure, and corners on the bottom surface and two sides of the bottom surface of each grid groove are located in the second epitaxial structure;
arranging a grid filling body in the grid groove;
forming a source electrode field layer in the surface layer of the third epitaxial structure, wherein the source electrode field layer is positioned on the active layer;
disposing an interlayer film on the third epitaxial structure to cover the source field layer;
and opening a contact groove in the third epitaxial structure so as to fill a source electrode layer, wherein the contact groove is aligned to the connecting junction and penetrates through the interlayer film, the source electrode field layer is exposed on the side wall of the contact groove, and the bottom surface and the corner angles at two sides of the bottom surface of the contact groove are positioned in the active layer of the third epitaxial structure.
According to the technical scheme, the multilayer isolation gate wells are arranged in the first epitaxial structure, the second epitaxial structure is formed on the first epitaxial structure to generate the shielding electric field, and the expanded shielding electric field can protect the gate in the gate groove to relieve the electron tunneling effect generated by the intensive electric field lines on the bottom surface of the gate and the corner positions on two sides of the bottom surface, so that charges cross potential energy barriers from the bottom of the gate to generate leakage current to increase the power consumption of the MOSFET. The third epitaxial structure and the second epitaxial structure are combined to form a space charge region, so that the electric field part at the bottom of the grid groove is transferred to the space charge region, the electric field at the bottom of the grid groove is reduced, and the working reliability of the MOSFET is improved. The isolation gate well can reduce the JFET effect in the MOSFET and can reduce the conduction loss of the MOSFET by the combined action of the space charge region formed by the second epitaxial structure and the third epitaxial structure.
In one embodiment, the step of forming the first epitaxial structure specifically includes:
growing an epitaxial layer to form an upper surface of the first epitaxial structure;
forming an injection window on the upper surface of the epitaxial layer;
implanting ions into the epitaxial layer from the implantation window to form a single-layer isolation gate well in the epitaxial layer;
and repeating the steps of growing the epitaxial layer, opening the implantation window and implanting ions in sequence until the thickness of the first epitaxial structure formed by overlapping a plurality of epitaxial layers reaches a set value.
Through the technical scheme, the first epitaxial structure is formed by overlapping multiple epitaxial layers, multiple layers of isolation gate wells are formed by injecting ions for multiple times along with the growth of the epitaxial layers, and compared with the method of directly injecting ions on the formed first epitaxial structure to form the isolation gate wells, the problems that the isolation gate wells in the first epitaxial structure are unstable in electrical performance and unadjustable in concentration due to the fact that the thickness is deep, and the accuracy of the isolation gate wells at the bottom cannot be controlled can be solved.
In one embodiment, the thickness of the isolation gate well is smaller than that of the epitaxial layer, and multiple layers of the isolation gate wells are arranged to be separated from each other, and after the step of forming the first epitaxial structure, the method further includes the steps of:
implanting ions through the implantation window;
and heating the epitaxial region at a high temperature to enable the plurality of layers of isolation gate traps to be connected into a whole through ion diffusion.
Through the technical scheme, ions in the isolation gate wells are spontaneously diffused by high-temperature heating, so that a plurality of layers of originally separated isolation gate wells are uniformly connected together to form a whole, and the connection consistency of each layer of isolation gate wells is ensured.
In summary, the present application at least includes the following beneficial technical effects:
1. a MOSFET device having high reliability, high turn-on performance and high switching performance is provided.
2. The second epitaxial structure can form a shielding electric field, and the expanded shielding electric field can protect a gate filling body in the gate groove so as to relieve electron tunneling effect generated by intensive electric field lines on the bottom surface of the gate and the corner positions on two sides of the bottom surface, so that charges cross potential energy barriers from the bottom of the gate to generate leakage current and increase MOSFET power consumption.
3. The third epitaxial structure and the second epitaxial structure are combined to form a space charge area, so that an electric field part at the bottom of the grid groove is transferred to the space charge area, the electric field at the bottom of the grid groove is reduced, the working reliability of the MOSFET is improved, and lower switching loss is realized.
4. The isolation gate well can reduce JFET effect in the MOSFET and can reduce conduction loss of the MOSFET by coaction with the space charge region formed by the second epitaxial structure and the third epitaxial structure.
Drawings
FIG. 1 is a schematic cross-sectional view of a MOSFET device according to an embodiment of the present application;
fig. 2 is a schematic structural cross-sectional view of a MOSFET device in step S1 in an embodiment of the present application;
fig. 3 is a schematic structural cross-sectional view of a MOSFET device in step S2 in an embodiment of the present application;
fig. 4 is a schematic structural cross-sectional view of a MOSFET device in step S3 in an embodiment of the present application;
fig. 5 is a schematic structural cross-sectional view of a MOSFET device in step S3 in an embodiment of the present application;
fig. 6 is a schematic structural cross-sectional view of a MOSFET device in step S3 in an embodiment of the present application;
fig. 7 is a schematic structural cross-sectional view illustrating a final state of the MOSFET device of step S3 in an embodiment of the present application;
fig. 8 is a schematic structural cross-sectional view of a MOSFET device in step S4 in an embodiment of the present application;
fig. 9 is a schematic cross-sectional view of the MOSFET device in step S5 in an embodiment of the present application;
fig. 10 is a schematic cross-sectional view of the MOSFET device in step S6 in an embodiment of the present application;
fig. 11 is a schematic structural cross-sectional view of a MOSFET device in step S7 in an embodiment of the application;
fig. 12 is a schematic cross-sectional view of the MOSFET device in step S8 in an embodiment of the present application;
fig. 13 is a schematic cross-sectional view of the MOSFET device of step S9 in an embodiment of the present application;
fig. 14 is a schematic structural cross-sectional view of a MOSFET device in step S10 in an embodiment of the present application;
fig. 15 is a schematic cross-sectional view of the MOSFET device in step S11 of the present application;
fig. 16 is a schematic cross-sectional view of the MOSFET device of step S12 in the embodiment of the present application;
fig. 17 is a schematic structural cross-sectional view of a MOSFET device in step S13 in an embodiment of the present application.
Description of reference numerals:
10. a substrate; 20. a first epitaxial structure; 21. an isolation gate well; 22. an epitaxial layer; 23. an oxide film; 23A, an injection window; 30. a second epitaxy structure; 31. connecting the knot; 40. a third epitaxial structure; 41. an active layer; 42. a source field layer; 43. a gate trench; 43A, a gate oxide layer; 44. a contact trench; 44A, a protection area; 50. a gate fill; 60. an interlayer film; 70. a source electrode; 71. a source contact layer; 72. a source electrode pad layer; 73. a passivation layer; 80. a drain electrode; 900. and (5) masking.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. This application is capable of embodiments in many different forms than those described herein and that modifications may be made by one skilled in the art without departing from the spirit and scope of the application and it is therefore not intended to be limited to the specific embodiments disclosed below.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specified otherwise.
In this application, unless expressly stated or limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can include, for example, fixed connections, removable connections, or integral parts; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature "under," "beneath," and "under" a second feature may be directly under or obliquely under the second feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like as used herein are for illustrative purposes only and do not denote a unique embodiment.
Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a MOSFET device according to an embodiment of the present application. The MOSFET device includes a substrate 10, a first epitaxial structure 20, a second epitaxial structure 30, a third epitaxial structure 40, a gate filling body 50, an interlayer film 60, a source electrode 70, and a drain electrode 80. The first epitaxial structure 20, the second epitaxial structure 30 and the third epitaxial structure 40 are sequentially disposed on the substrate 10, a multi-layer isolation gate well 21 is formed in the first epitaxial structure 20, and a connection junction 31 connecting the isolation gate well 21 and an active layer 41 of the third epitaxial structure 40 is formed in the second epitaxial structure 30. The third epitaxial structure 40 includes an active layer 41 and a source region layer 42, the third epitaxial structure 40 further has a gate trench 43 and a contact trench 44, and the gate trench 43 passes through the third epitaxial structure 40 until the bottom is located on the second epitaxial structure 30. An interlayer film 60 is also provided on the source region layer 42, and the contact trench 44 penetrates the interlayer film 60 and the source region layer 42.
The first epitaxial structure 20 is formed on the upper side of the substrate 10 and is formed by a homoepitaxial growth with the substrate 10. Specifically, the substrate 10 is a wafer of heavily doped n-type ions, and the first epitaxial structure 20 is a wafer of lightly doped n-type ions, which together form an n-type drift region of the MOSFET device. Specifically, in the present embodiment, the first epitaxial structure 20 is formed by stacking a plurality of epitaxial layers 22, and the total thickness is 1um to 6um, which can avoid the problems that the isolation gate well 21 in the first epitaxial structure 20 has a relatively deep thickness, and the accuracy of the isolation gate well 21 at the bottom cannot be controlled, which results in unstable electrical performance and unadjustable concentration. The drain 80 is disposed on the bottom surface of the substrate 10 to have the same width as the substrate 10, so as to facilitate parallel connection of the drains 80.
An isolation gate well 21 is disposed in the first epitaxial structure 20 to isolate the gates at both sides. Specifically, the isolation gate well 21 includes multiple layers, each layer of isolation gate well 21 is formed synchronously with the corresponding epitaxial layer 22, and the multiple layers of isolation gate wells 21 are connected into a whole along with the superposition of the epitaxial layers 22. The bottom surface of the isolation gate well 21 does not penetrate the bottom surface of the first epitaxial structure 20 to prevent the substrate 10 from being directly conductive to the isolation gate well 21. Specifically, in the present embodiment, the width of the isolation gate well 21 is 1um-5um, and the implanted ions are p-type ions.
A second epitaxial structure 30 is formed on the first epitaxial structure 20 for forming a shield electric field. Specifically, the thickness of the second epitaxial structure 30 is less than the thickness of the single-layer epitaxial layer 22, and the ion doping concentration is less than the ion doping concentration of the first epitaxial structure 20, so that the second epitaxial structure 30 is relatively easier to deplete carriers, and the ions left after carrier depletion generate a shielding electric field to prevent further carrier diffusion.
Specifically, in the present embodiment, the second epitaxial structure 30 is doped with n-type ions, and the doping concentration thereof is 20% of that of the first epitaxial structure 20, so that majority carriers in the second epitaxial structure 30 are quickly depleted to form a shielding electric field, and the concentration is sufficient to maintain the carrier requirement at the time of conducting.
The second epitaxial structure 30 further has a connection node 31 therein, and the connection node 31 connects the isolation gate well 21 on the bottom surface and the active layer 41 on the top surface. Specifically, the connecting junction 31 is disposed through the second epitaxial structure 30, and the width is smaller than the width of the isolation gate well 21, so as to ensure the electrical connection between the third epitaxial structure 40 and the isolation gate well 21, and avoid occupying the space of the second epitaxial structure 30 and affecting the formation of the shielding electric field. Specifically, in the present embodiment, the width of the connection junction 31 is preferably 0.2 of the width of the isolation gate well 21.
The third epitaxial structure 40 includes an active layer 41 and a source region layer 42. Specifically, the active layer 41 is disposed on the upper side of the second epitaxial structure 30, the source region layer 42 covers the active layer 41, and the active layer 41 and the source region layer 42 are implanted with different types of dopant ions to form space charge regions. Specifically, in the present embodiment, the source region layer 42 is doped with n-type ions, the active layer 41 is doped with p-type ions, and the n-type doped second epitaxial structure 30 is combined to form an npn-type space charge region.
The gate trench 43 is opened on the third epitaxial structure 40 for disposing the gate filling body 50. The opening of the gate trench 43 is located on the upper surface of the source region layer 42, passing through the source region layer 42 and the active layer 41, until the bottom of the gate trench 43 is located in the second epitaxial structure 30. Specifically, the bottom surface and two side corners of the bottom surface of the gate trench 43 are located in the second epitaxial structure 30, so that the shielded electric field expanded in the second epitaxial structure 30 can protect the position where the electric field lines are dense at the bottom surface of the gate trench 43, prevent the leakage current formed by the leakage of the charges from the bottom of the gate trench 43, and increase the power consumption of the MOSFET. Specifically in this embodiment, the gate fill 50 is formed by polysilicon deposition.
In some embodiments, a gate oxide layer 43A is further formed on the inner wall of the gate trench 43 to protect the gate filling body 50. Specifically, the bottom thickness of the gate oxide layer 43A is greater than the side thickness to further protect the bottom surface of the gate trench 43 and prevent the charge from generating electron tunneling at the bottom of the gate trench 43 to form leakage current.
The interlayer film 60 is disposed on the third epitaxial structure 40 to cover the source region layer 42 and electrically isolate the source 70 on the upper side of the interlayer film 60 from the third epitaxial structure 40 on the lower side of the interlayer film 60.
The interlayer film 60 is formed with a contact trench 44, the contact trench 44 penetrates through the interlayer film 60 and the source region layer 42, and the bottom of the contact trench 44 is located in the active layer 41 for filling the source electrode 70, so that the source electrode 70 is electrically connected to the third epitaxial structure 40 through the contact trench 44.
In some embodiments, the contact trench 44 has a protection region 44A formed at the bottom thereof, and the protection region 44A is ion-doped with an ion doping concentration greater than that of the surrounding region. Specifically, the protection region 44A ensures sufficient charge transfer of carriers at the contact position of the source electrode 70 in the contact trench 44 by using a high p-type ion doping concentration, and prevents the problem of poor contact conduction due to insufficient number of carriers caused by diffusion of ions at the bottom of the contact trench 44 to the periphery.
The source electrode 70 includes a source contact layer 71 and a source pad layer 72. The source pad layer 72 is used to form a contact electrode to conduct an external circuit. The source contact layer 71 is filled between the contact trench 44 of the third epitaxial structure 40 and the source liner layer 72 to form an ohmic contact and prevent metal atoms of the source liner layer 72 from diffusing toward the third epitaxial structure 40. Specifically, in the present embodiment, the source pad layer 72 is made of Al metal material, and the source contact layer 71 is made of Ti metal material.
In other embodiments, the top surface of the source pad layer 72 is further formed with a passivation layer 73 to protect the source electrode 70 from the external air. Specifically, the passivation layer 73 may be dense Al2O3 formed by oxidation of Al, which can prevent air corrosion. The person skilled in the art is able to adapt the passivation layer 73 according to common general knowledge in the art.
In addition, the application also provides a manufacturing method of the MOSFET device with the protection grid electrode charge balance, and the processing steps are introduced as follows.
Referring to fig. 2, a substrate 10 is provided corresponding to step S1 and a first epitaxial structure 20 is formed on the substrate 10. The method comprises the following specific steps: firstly, a layer with the concentration of 10 is grown on a substrate 10 heavily doped with n-type ions 15 ions/cm 2 To 10 17 ions/cm 2 The epitaxial layer 22 is doped with n-type ions, and the thickness of the epitaxial layer 22 is 1um-6um. An oxide film 23 having a thickness of 300 a-500 a is then grown on the surface of epitaxial layer 22 for protecting the wafer from scratches and isolating contaminants during processing, and also for implant masking during ion doping. Finally, a mask 900 is provided on the surface of the oxide film 23 to etch the oxide film 23 to open the implantation window 23A.
Referring to fig. 3, ions are implanted from the implantation window 23A to form the isolation gate well 21 in step S2. Specifically, p-type ions are implanted into the epitaxial layer 22 through the implantation window 23A, the width of the implantation region is 1um to 5um, and the implantation dose is 10 12 ions/cm 2 To 10 14 ions/cm 2 The implantation energy is 60keV to 1000keV. An ion-implanted isolation gate well 21 is located inside the epitaxial layer 22.
Referring to fig. 4, the first two steps of the steps of growing the epitaxial layer 22, opening the implantation window 23A and implanting ions are repeated corresponding to step S3. The method comprises the following steps: the oxide film 23 on the surface is removed from the original epitaxial layer 22, a new epitaxial layer 22 is grown on the original epitaxial layer 22, the oxide film 23 is grown on the new epitaxial layer 22, and the implantation window 23A is opened by using the mask 900.
It should be noted that parameters such as the thickness of each epitaxial layer 22, the ion doping concentration, and the position of the implantation window 23A are fixed to ensure that each epitaxial layer 22 has the same properties, and the first epitaxial structure 20 formed by stacking the multiple epitaxial layers 22 has better uniformity.
Referring to fig. 5 and 6, the epitaxial layer 22 is repeatedly grown, the implantation window 23A is opened, and the ion implantation step is repeated corresponding to step S3. Specifically, p-type ions are implanted into the latest epitaxial layer 22 through the implantation window 23A to form the isolation gate well 21, so that a corresponding isolation gate well 21 is formed in each epitaxial layer 22. The multi-layer isolation gate wells 21 are aligned in the same vertical region and are spaced apart from each other.
Referring to fig. 7, fig. 7 shows a final state of the MOSFET device in step S3 according to an embodiment of the present invention, when the thickness of the first epitaxial structure 20 formed by repeatedly growing the epitaxial layers 22 of the MOSFET device reaches a predetermined value, the growth is stopped for the next step.
Referring to fig. 8, a second epitaxial structure 30 is formed corresponding to step S4. The method comprises the following steps: and continuing to epitaxially grow the wafer on the first epitaxial structure 20, and controlling the ion doping concentration of the grown second epitaxial structure 30 to be smaller than that of the first epitaxial structure 20. Furthermore, the thickness of the second epitaxial structure 30 that is controlled to grow is less than the thickness of the epitaxial layer 22. Specifically, in the present embodiment, the second epitaxial structure 30 is doped with n-type ions, and the ion doping concentration thereof is 20% of that of the first epitaxial structure 20.
Referring to fig. 9, a connecting junction 31 is formed corresponding to step S5. The method comprises the following steps: an oxide film 23 is also formed on the surface of the second epitaxial structure 30, and then an implantation window 23A is formed on the oxide film 23 using a mask 900, and p-type ions are implanted from the implantation window 23A to form a junction 31. The connecting junction 31 is aligned to the isolation gate well 21, and the implantation width of the connecting junction 31 is smaller than that of the isolation gate well 21. In the present embodiment, the width of the connecting junction 31 is one fifth of the width of the isolation gate well 21.
Referring to fig. 10, a third epitaxial structure 40 is formed corresponding to step S6. The method comprises the following steps: the epitaxial layer 22 is again grown to a thickness of 1um-3um on the surface of the second epitaxial structure 30, and p-type ions are implanted to form the active layer 41 of the third epitaxial structure 40. Then, by heating the MOSFET device, p-type ions are subjected to ion diffusion at high temperature, so that the originally separated isolation gate wells 21 are uniformly connected together to form a whole, and the connection consistency of each layer of isolation gate wells 21 is ensured.
Referring to fig. 11, a gate trench 43 is formed by etching corresponding to step S7. The method comprises the following steps: an oxide film 23 is formed on the surface of the active layer 41, and a photolithography region is defined by using a mask 900. Thereafter, the photo-etched region is etched to form a gate trench 43. Specifically, the gate trench 43 is a U-shaped trench, and the bottom surface of the gate trench 43 is etched to the second epitaxial structure 30.
Referring to fig. 12, a gate oxide layer 43A is formed corresponding to step S8. The method comprises the following steps: the oxide film 23 on the surface of the active layer 41 is removed first, and then a new oxide layer is formed on the surface of the active layer 41 and the surface of the gate trench 43, where the oxide layer grown on the inner wall surface of the gate trench 43 is the gate oxide layer 43A. The growth thickness of the gate oxide layer 43A on the bottom surface of the control gate trench 43 is greater than the growth thickness of the gate oxide layer 43A on the side surface, so as to achieve better protection of the bottom surface of the gate trench 43.
Referring to fig. 13, a gate fill 50 is formed corresponding to step S9. The method comprises the following steps: a gate filling body 50 is formed on the gate trench 43 and the active layer 41 by chemical vapor deposition of polysilicon. Chemical vapor deposition is a common technique in the art, and is not the focus of the process in this application, and can be performed by those skilled in the art without description, and thus is not described herein.
Referring to fig. 14, the polysilicon surface is planarized corresponding to step S10. The method comprises the following steps: the excess gate filling body 50 on the surface of the active layer 41 is removed by using a Chemical Mechanical Polishing (CMP) process, so that the gate filling body 50 is only filled in the gate trench 43, and the gate filling body 50 and the active layer 41 are located on the same flat horizontal plane. The CMP process is also common knowledge in the art and is not the focus of the process, and therefore is not described herein.
Referring to fig. 15, a source region layer 42 and a dielectric film are formed corresponding to step S11. The method comprises the following steps: a mask 900 is provided on the surface of the active layer 41 for patterning, and n-type ions with high concentration are implanted into the surface of the active layer 41 according to a pattern preset by the mask 900 for doping, so as to form an n-type source region layer 42. Finally, an insulating interlayer film 60 is formed on the entire source region layer 42 and the upper side of the gate filling body 50 to isolate the third epitaxial structure 40 and the source 70 at both sides of the interlayer film 60.
Referring to fig. 16, a contact trench 44 is formed corresponding to step S12. The method comprises the following steps: the contact trench 44 area is defined and patterned on the surface of the interlayer film 60, and then etched in the contact trench 44 area to form the contact trench 44 of the U-shape. The contact trench 44 penetrates the interlayer film 60 and the source region layer 42 for communicating the source 70 with the third epitaxial structure 40. The bottom surface of the contact trench 44 is etched into the active layer 41, and then p-type ions with high concentration are implanted into the bottom surface of the contact trench 44 for doping, so as to form a protection region 44A, and the ion doping concentration of the protection region 44A is made greater than that of the peripheral region, so as to prevent the problem of poor contact conduction caused by insufficient carrier number due to diffusion of ions at the bottom of the contact trench 44 to the periphery. Finally, in N 2 Annealing under protective gas atmosphere to recover crystal structure and eliminate lattice defectAnd (5) sinking.
Referring to fig. 17, the source 70 is filled in step S13. The method comprises the following steps: the source contact layer 71 is filled on the interlayer film 60 and in the contact trench 44, and then the source contact layer 71 is annealed to reduce residual stress of the source contact layer 71 and eliminate structural defects of the metal. Then, a source pad layer 72 is formed on the source contact layer 71 by a sputtering process on the source contact layer 71. Then, an etching region is defined on the surface of the source pad layer 72 by patterning using the mask 900 and etching is performed accordingly to form a contact electrode.
Specifically, in the present embodiment, the source contact layer 71 is a metal Ti material, and the source pad layer 72 is a metal Al material.
Referring to fig. 1 again, a passivation layer 73 is formed corresponding to step S14. The method comprises the following steps: a metal passivation is performed on the backside of the source liner layer 72 to form a passivation layer 73, which protects the source electrode 70 and other structures from the outside air.
The implementation principle of the MOSFET device of the embodiment of the present application is as follows: a shield electric field is formed by the second epitaxial structure 30 to protect a position where the electric field line density of the bottom surface of the gate trench 43 is high. Meanwhile, the second epitaxial structure 30 and the third epitaxial structure 40 are combined to form a space charge region, so that the electric field at the bottom of the gate trench 43 is partially transferred into the space charge region, thereby reducing the electric field at the bottom of the gate trench 43, improving the reliability of the MOSFET operation, and realizing lower switching loss. Finally, the JFET effect in the MOSFET is reduced by the isolation gate well 21, which cooperates with the space charge region formed by the second epitaxial structure 30 and the third epitaxial structure 40 to reduce the turn-on loss of the MOSFET.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several implementation modes of the present application, and the description thereof is specific and detailed, but not construed as limiting the scope of the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A protected gate charge balanced MOSFET device comprising:
a substrate (10);
a first epitaxial structure (20) formed on the substrate (10), a multi-layer isolation gate well (21) being formed within the first epitaxial structure (20);
a second epitaxial structure (30) formed on the first epitaxial structure (20); the second epitaxial structure (30) is provided with a connecting junction (31) with the bottom end connected with the multi-layer isolation gate well (21), and the width of the connecting junction (31) is smaller than that of the multi-layer isolation gate well (21);
a third epitaxial structure (40) formed on the second epitaxial structure (30); the top end of the connecting junction (31) is connected with the active layer (41) of the third epitaxial structure (40); the third epitaxial structure (40) is provided with a plurality of grid grooves (43), the multi-layer isolation grid wells (21) are located between the grid grooves (43), the grid grooves (43) penetrate through the third epitaxial structure (40), and corners of the bottom surface and two sides of the bottom surface of each grid groove (43) are located in the second epitaxial structure (30); a source electrode (70) field layer (42) is formed in the surface layer of the third epitaxial structure (40), and the source electrode field layer (42) is positioned on the active layer (41);
a gate fill (50) disposed within the gate trench (43);
an interlayer film (60) provided on the third epitaxial structure (40) so as to cover the source region layer (42);
the third epitaxial structure (40) is provided with a contact groove (44) for filling a source electrode (70), the contact groove (44) is aligned to the connecting junction (31) and penetrates through the interlayer film (60), the source electrode field layer (42) is exposed on the side wall of the contact groove (44), and the bottom surface and two side corners of the bottom surface of the contact groove (44) are located in the active layer (41) of the third epitaxial structure (40).
2. The shielded gate charge balanced MOSFET device according to claim 1, wherein the first epitaxial structure (20) is formed by a stack of multiple epitaxial layers (22), and the thickness of the second epitaxial structure (30) is less than the thickness of the epitaxial layers (22).
3. The shielded gate charge balanced MOSFET device according to claim 2, wherein the second epitaxial structure (30) has an ion doping concentration that is less than the ion doping concentration of the epitaxial layer (22) but not less than 20% of the ion doping concentration of the epitaxial layer (22).
4. The shielded gate charge balanced MOSFET device of claim 1 wherein the gate trench (43) has a gate oxide layer (43A) formed on its inner walls, the gate oxide layer (43A) having a bottom thickness greater than a side thickness.
5. The shielded gate charge balanced MOSFET device according to claim 1, wherein the source (70) comprises a source contact layer (71) and a source pad layer (72), the source contact layer (71) and the source pad layer (72) being sequentially disposed on the interlayer film (60).
6. The shielded gate charge balanced MOSFET device of claim 1 wherein a guard region (44A) is formed on the bottom surface of the contact trench (44), the guard region (44A) having an ion doping concentration greater than that of the surrounding area.
7. A protected gate charge balanced MOSFET device according to any of claims 1 to 6, characterized in that the ratio of the width of the connecting junction (31) to the width of the isolation gate well (21) is in the range of 0.2-1.
8. A method of fabricating a shielded gate charge balanced MOSFET device, comprising:
providing a substrate (10);
forming a first epitaxial structure (20) for arranging an isolation gate on the substrate (10), and forming a multi-layer isolation gate well (21) in the first epitaxial structure (20);
forming a second epitaxial structure (30) for shielding an electric field on the first epitaxial structure (20); the second epitaxial structure (30) is provided with a connecting junction (31) with the bottom end connected with the multi-layer isolation gate well (21), and the width of the connecting junction (31) is smaller than that of the multi-layer isolation gate well (21);
forming a third epitaxial structure (40) for providing a channel on the second epitaxial structure (30); the top end of the connecting junction (31) is connected with the active layer (41) of the third epitaxial structure (40);
a plurality of grid grooves (43) are formed in the upper surface of the third epitaxial structure (40), the multi-layer isolation grid well (21) is located between the grid grooves (43), the grid grooves (43) penetrate through the third epitaxial structure (40), and corners of the bottom surface and two sides of the bottom surface of each grid groove (43) are located in the second epitaxial structure (30);
disposing a gate fill (50) within the gate trench (43);
forming a source-domain layer (42) in a surface layer of the third epitaxial structure (40), the source-domain layer (42) being located on the active layer (41);
disposing an interlayer film (60) on the third epitaxial structure (40) to cover the source region layer (42);
and opening a contact trench (44) in the third epitaxial structure (40) for filling a source electrode (70) layer, wherein the contact trench (44) is aligned to the connection junction (31) and penetrates through the interlayer film (60), the source electrode field layer (42) is exposed on the side wall of the contact trench (44), and corners of the bottom surface and two sides of the bottom surface of the contact trench (44) are located in the active layer (41) of the third epitaxial structure (40).
9. Method for manufacturing a MOSFET device with a protected gate charge balance according to claim 8, characterized in that the step of forming the first epitaxial structure (20) comprises in particular:
growing an epitaxial layer (22) to form an upper surface of the first epitaxial structure (20);
forming an implantation window (23A) on the upper surface of the epitaxial layer (22);
implanting ions into the epitaxial layer (22) through the implantation window (23A) to form a single-layer isolated gate well (21) in the epitaxial layer (22);
and repeating the steps of growing the epitaxial layer (22), forming the implantation window (23A) and implanting ions in sequence until the thickness of the first epitaxial structure (20) formed by overlapping the plurality of epitaxial layers (22) reaches a set value.
10. The method of fabricating a shielded gate charge balanced MOSFET device according to claim 9, wherein the thickness of said isolation gate well (21) is less than the thickness of said epitaxial layer (22), and wherein multiple layers of said isolation gate well (21) are spaced apart from each other, further comprising, after said step of forming said first epitaxial structure (20), the steps of:
implanting ions from the implantation window (23A);
and heating the epitaxial region at a high temperature to enable the isolation gate wells (21) to be integrated into a whole through ion diffusion connection.
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| US20100044792A1 (en) * | 2008-08-20 | 2010-02-25 | Alpha & Omega Semiconductor, Inc. | Charged balanced devices with shielded gate trench |
| US20100171171A1 (en) * | 2009-01-07 | 2010-07-08 | Hsu Hsiu-Wen | Trench mosfet device with low gate charge and the manfacturing method thereof |
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