CN1159619A

CN1159619A - IC input/output processor for improving timer performance

Info

Publication number: CN1159619A
Application number: CN96121310A
Authority: CN
Inventors: 沃奥·博纳德·高勒; 格日·林恩·米勒; 大卫·里沃拉
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1995-11-13
Filing date: 1996-11-12
Publication date: 1997-09-17
Also published as: EP0773491A3; KR970028966A; TW309603B; JPH09146779A; KR100459738B1; US5634045A; EP0773491A2

Abstract

Referring to FIGS. 1 and 2, I/O control modules (IOCMs 25-29) have channels which communicate by way of timer buses (71, 72) and pin/status buses (75-77). Channels (86, 87) are partitioned by each timer bus (71, 72) into separate blocks of channels (86, 87) which are provided with access to different timebase values from timebase channels (80, 81) by their respective timer bus (71, 72), so there is no loss of resolution because each channel in a timer bus block (e.g. 86) can concurrently receive the same timebase value from its corresponding timer bus (71). Pin/status buses (75-77) allow simultaneity of control among the channels (e.g. 58) coupled to the same pin/status bus (e.g. 76). Pin/status buses (75-77) and timer buses (71, 72) can be independently partitioned.

Description

Improve the integrated circuit input/output processor of timer performance

Present invention generally relates to the I/O processor, refer more particularly to I/O processor with improvement timer (timer) performance.

Complicated real-time control system, for example automobile and robot control system require data handling system to have better control, faster system responses and more I/O (I/O) ability.Therefore, can carry out the data disposal system more, faster and improve the requirement that I/O (I/O) handles and increase rapidly.

People expect that microcomputer can provide the higher numeral and the decomposition output of simulation, in the hope of more accurate control.Because the extra expenses of handling, CPU (central processing unit) (CPU) may not be with required rate response very high frequency(VHF) control function.Need a solution, provide more, faster and improved I/O processing power not making under the CPU prerequisite that over-burden.

In addition, people expect that microcomputer can be fit to various different application very neatly.In the former microcomputer, the dirigibility that I/O handles is provided port or simple timer channel operation by CPU (central processing unit) (CPU) software.Analog-and digital-I/O also connects by CPU.Yet because CPU relates to all I/O, the I/O bandwidth mainly has been wasted in the extra expenses of system.Like this, need the I/O performance that a solution provides dirigibility and enhancement simultaneously.

Fig. 1 shows data handling system 10 according to one embodiment of the invention with the form of block diagram;

Fig. 2 shows a part according to circuit 25 among Fig. 1 of one embodiment of the invention with the form of block diagram;

Fig. 3 shows a part according to circuit 26 among Fig. 1 of one embodiment of the invention with the form of block diagram;

Fig. 4 shows a part according to circuit 25 among Fig. 1 of one embodiment of the invention with the form of block diagram;

Fig. 5 shows a part according to circuit 25 among Fig. 1 of one embodiment of the invention with the form of block diagram;

Fig. 6 shows a truth table with the form of tabulation, and pin control circuit 64 uses this list deciding logic level of lead 168 as a result among Fig. 5;

Fig. 7 shows according to the part of control register 166 among Fig. 5 of one embodiment of the invention and the part of control register 167 with the form of tabulation;

Fig. 8 shows the user with the form of tabulating can be by one group of function of pin output drive control bit 182 among Fig. 7 or 183 programming realizations;

Fig. 9 shows in Fig. 5 pin one 65 example as a result that logical and and logical OR were produced by coupling passage 160 and 161 states with the form of tabulation;

Figure 10 shows a part according to circuit 26 among Fig. 1 of one embodiment of the invention and 27 with the form of block diagram;

Figure 11 shows a part according to control register 226 among Figure 10 of one embodiment of the invention with the form of block diagram;

Figure 12 shows a part according to circuit 26 among Figure 10 of one embodiment of the invention with the form of block diagram;

Figure 13 shows a part according to each passage in circuit among Fig. 2 of one embodiment of the invention 61,62,80,81 and 86 with the form of block diagram;

Figure 14 shows a part according to circuit 25 among Fig. 2 of one embodiment of the invention with the form of block diagram;

8 examples of base value when Figure 15 shows the user how optionally to provide one or more in the different time-gap of timer bus with the form of tabulation;

Figure 16 shows a kind of timer system integrated circuit 280 according to one embodiment of the invention with the form of block diagram;

Figure 17 shows a kind of data handling system 315 according to one embodiment of the invention with the form of block diagram;

Figure 18 shows among Figure 16 according to one embodiment of the invention the part of base passage 285 when main with the form of block diagram and the part of base passage 288 when auxilliary;

Figure 19 shows among Figure 17 according to one embodiment of the invention the part of base passage 304 when main with the form of block diagram and the part of base passage 310 when auxilliary;

Figure 20 shows a part according to circuit 25 among Fig. 1 of one embodiment of the invention with the form of block diagram;

Figure 21 shows a part of catching passage 401 among Figure 20 according to one embodiment of the invention with the form of block diagram;

Figure 22 shows a part of catching passage 401 among Figure 20 according to one embodiment of the invention with the form of block diagram;

Figure 23 shows the behavior of the DVB bit (as among Figure 22 425) of set and each passage of zero clearing with the form of tabulation, when this bit is configured to its each operator scheme, can support data transfer operation;

Figure 24 shows the data transfer operation pattern by data transmission control bits (DTC) (for example 423-424 among Figure 21 and 22) control of each passage that carries out data transfer operation with the form of tabulation;

Figure 25 shows according to the improving one's methods of the performance period cumulative measurement of one embodiment of the invention with the form of Time Index Chart, and its cumulative errors is lacked than the implementation method of prior art;

Figure 26 shows improving one's methods according to the performance period cumulative measurement of one embodiment of the invention with the form of Time Index Chart;

Figure 27 shows a part according to counting channel 58 among Fig. 2 of one embodiment of the invention with the form of block diagram;

Figure 28 shows first according to register 67 among Fig. 2 of one embodiment of the invention with the form of block diagram;

Figure 29 shows second portion according to register 67 among Fig. 2 of one embodiment of the invention with the form of block diagram;

Figure 30 shows third part according to register 67 among Fig. 2 of one embodiment of the invention with the form of block diagram;

Figure 31 shows improving one's methods according to the performance period cumulative measurement of one embodiment of the invention with the form of Time Index Chart;

Figure 32 shows a part according to counting channel 58 among Fig. 2 of one embodiment of the invention with the form of block diagram;

Base value improved one's methods when Figure 33 showed according to the catching of one embodiment of the invention with the form of Time Index Chart;

Base value improved one's methods when Figure 34 showed according to the catching of one embodiment of the invention with the form of Time Index Chart;

Figure 35 shows first according to register 66 among Fig. 2 of one embodiment of the invention with the form of block diagram;

Figure 36 shows second portion according to register 66 among Fig. 2 of one embodiment of the invention with the form of block diagram;

Figure 37 shows a part of catching passage 55 among Fig. 2 according to one embodiment of the invention with the form of block diagram;

Figure 38 shows first according to register 65 among Fig. 2 of one embodiment of the invention with the form of block diagram;

Figure 39 shows second portion according to register 65 among Fig. 2 of one embodiment of the invention with the form of block diagram;

Figure 40 shows according to a part of mating passage 57 among Fig. 2 of one embodiment of the invention with the form of block diagram;

Term " bus " is meant the one or more different types of information of transmission, as data, and address, a plurality of signals or the lead of control or status information.Term " is just got " and " getting negative " refers to separately with signal, status bits, ic pin or its logical truth of similar devices regeneration or logical falsehood state.If the logical truth state is a logic level 1, the logical falsehood state then is a logic level 0.If the logical truth state is a logic level 0, the logical falsehood state then is a logic level 1.

Term " set " is meant signal, status bits, ic pin or its logic level of similar devices regeneration 1.Term " zero clearing " is meant signal, status bits, ic pin or its logic level of similar devices regeneration 0.Term " upset " is meant if signal, and status bits, the current state of ic pin or similar devices are logic levels 1, and then the regeneration logic level 0.If current state is a logic level 0, then the regeneration logic level 1.

This numeral of a numeral explanation of symbol " % " prefix represents that with binary mode this numeral of a numeral explanation of symbol " " prefix is represented with the sexadecimal form.Term " ic pin " with " pin " but mutually trans-substitution use.In addition, use term " ic pin " and " pin " to locate, also can replace with land or any lead that electrical couplings is provided between integrated circuit and external unit.

Many concrete details have been proposed in the following description, as length of specific word and byte or the like so that thorough understanding of the present invention to be provided.Yet those skilled in the art knows that obviously the present invention can not have the enforcement of obtaining under the situation of these details.In other examples, the present invention takes the form of circuit block diagram to avoid unnecessary details.In most cases, relate to the details of timing considerations and analogue, because do not influence, and be that those skilled in the art are familiar with in the association area, thereby be left in the basket complete understanding of the present invention.

Although in presents, use term " ic pin " and " pin " (as 31-35 among Fig. 1 and 19) in the whole text, these terms should comprise and being used for to certain integrated circuit transmission electric signal, or any kind equipment of reception electric signal, for example, the integrated circuit land, welding block, lead or the like.

Referring now to figure,, wherein the element of Miao Shuing not necessarily shows calibration, and similar components marks with same parameter in several figure.

I/O control module (referring to IOCM 25-29 among Fig. 1) provides the I/O performance of the dirigibility and the enhancement of data handling system.In one embodiment of this invention, one or more IOCM25-29 are distributed in the integrated circuit different with CPU (central processing unit) (CPU) 13, but one or more IOCM 25-29 communicate by letter with CPU 13 by bus 30.In optional embodiment of the present invention, one or more IOCM can be in the same integrated circuit with CPU.For example, referring to Fig. 1, other circuit 15 may be realized as I/O control module (IOCM), communicate by letter with CPU13 by bus 17.

Each of IOCM 25-29 is designed to a very modular system architecture.Top, each of IOCM 25-29 is a module by internal module bus 24 and other module communication.For example, in one embodiment, each of IOCM 25-29 can be a module that is used for MC68HC300 family microcomputer, and such microcomputer is produced by the Motorola Austin company of Texas.

Except itself being a module, each of IOCM 25-29 also is made of a plurality of submodules or modular i/O passage.By the modularization passage in the combination in any " silicon channel pool ", can create different IOCM versions at an easy rate.Passage can have different hardware, comprises data and Simulation with I/O electric capacity, to finish specific operation.The I/O function that can not expect by the mode increase that new tunnel is joined in the storehouse.Like this, merge the different editions that different modularization channel layout just can generate IOCM 25-29.

Another important performance of IOCM 25-29 is that their structure allows user's differentiation task between software and hardware.Passage can be programmed in the hardware and move to finish simple high-frequency functions jointly.In fact the passage of function operation serves as the pretreater of high-frequency I/O incident.By alleviating the software service of CPU, or only require CPU to carry out the software service of low frequency I/O incident, in fact better control and system responses faster are provided all I/O incidents.

The digital processing of each IOCM 25-29 part all is flexibly on the quantity of the I/O function that can carry out and performance.Because at pin, be modular on the quantity of passage and bus, each IOCM 25-29 can both realize this dirigibility.That is to say that different I CM version can be created from " silicon channel pool " at an easy rate, ic pin also can increase, and irrelevant with number of channels.When number of channels increased in different I CM version to some extent, this structure of IOCM 25-29 also supported to increase more data and control bus.Can design new tunnel and join in the storehouse, think that I/O function in the future provides a kind of growth pattern.

Second importance of IOCM 25-29 system architecture is that passage can be programmed, and moves jointly in hardware, to realize simple high-frequency functions.When the maximization system exported by reducing the system CPU number of interruptions, it was important allowing user's differentiation task between hardware and software.

The a large amount of I/O of complicated real-time control system needs that relates to timer function of the same type handles.Like this, relatively little channel pool can merge in a different manner, forms a plurality of IOCM 25-29 to solve most of users' demand.

In one embodiment of this invention, channel pool comprises the passage of a plurality of different classes of or types, i.e. " service aisle ", " time base passage " and " other passage ".This kind name is divided in the passage of similar functions or structure together." service aisle " comprises the passage of carrying out typical timer function, as catch an input value when the time incident takes place, when match event takes place, provides a signal and statistics.Service aisle also comprises the more complicated passage of being made up of basic timer function.For example, carry out the quantity that the passage of coupling and tally function can the statistical match incident, and a signal only is provided when match event quantity reaches certain predetermined value.

In one embodiment of this invention, service aisle comprises: (1) catches passage (CC); (2) coupling passage (MC); (3) counting channel (CMTC); (4) spark integrated channel (SIC) is carried out a plurality of timer functions so that the spark timing of engine to be provided; (5) fuel integrated channel (FIC) is carried out a plurality of timer functions and is injected regularly with the fuel that engine is provided; (6) two-way FIFO passage (DFC) provides a 2-degree of depth FIFO who stores data value.Notice that two-way FIFO passage (DFC) do not carry out the timer function, and in generation, is to provide data storage function.

In one embodiment of this invention, the base passage comprises the time: (1) timer bus control channel (TBCC) provides the main control or the auxilliary control of timer bus; (2) number of degrees clock passage (DC) can provide base when reaching four; (3) timer passage (TC) provides to result from inside or outside time base; Notice that in one embodiment of this invention the timer passage can be by one or more service aisles or one or more external signal control (as regularly, load a certain modularization value, or determine directivity by statistics).

In one embodiment of this invention, other passage comprises: (1) carries out the synchronizing sequence passage of synchronizing sequence conversion; (2) carry out the asynchronous sequence passage that synchronizing sequence is changed; (3) pin control channel (PCC), the interface of responsible service aisle and ic pin; (4) auxiliary external bus interface passage (SEBI), the interface between responsible internal module between the bus of bus and this integrated circuit outside; (5) global resource passage (GRC) comprises possibility is different between different editions customization circuit or specified circuit (as specific timer and some system protection characteristics); (6) secondary bus interface channel (SBIU), be used for and internal module between bus interface; (7) host bus interface passage (MBIU), the interface that is used for bus between internal module (IMB) and number of degrees timer is (under the situation of cpu fault, all CPU write and are limited to write to a predetermined register, do not having under the situation of CPU, MBIU allows number of degrees timer to take over IMB, and reconfigure special modality with operational system, as motor car engine); (8) test channel comprises the circuit that is used for test purpose.

Notice that sequence of channels can directly be controlled one or more corresponding integrated circuit pins in one embodiment of this invention, also can use the corresponding integrated circuit pin by pin control channel.

In one embodiment of this invention, may exist other not strict is the adjunct circuit of a channel pool part, but these circuit design in modular mode, can be in order to one or more passages that are coupled.For example, pin control shared logic two the adjacent tubes foot control systems (PCC) that can be coupled allow two adjacent PCC shared bus information.In optional embodiment of the present invention, all this connecting circuit can be as the part of channel pool.

Each service aisle provides many programmable attributes, comprises the input and output incident.The incoming event source can be ic pin or other service aisle, and outgoing event can influence ic pin and other service aisle.Channel operation as the data transmission between input capture and adjacent service aisle, can be controlled by incoming event.On the contrary, the outgoing event of service aisle or ic pin can influence the operation of service aisle and the data transmission between service aisle.Another characteristic of each service aisle is optional configuration mode, and this mode-definition is to incoming event or cause the service aisle of the required execution of operation of outgoing event to be operated.These characteristics and other characteristic can be programmed service aisle and are moved jointly, finish many I/O functions.

Passage in the channel pool can add by different way, to create the different editions of IOCM 25-29.In optional embodiment of the present invention, can have more, still less or the passage in the different channel pools be used to form IOCM 25-29.By using modular architecture and modularization channel pool flexibly, many I/O demands of user can with a kind of rapidly, the effective and efficient manner solution.

Fig. 1 shows data handling system 10.Data handling system 10 has a CPU integrated circuit 12 and I/O (I/O) integrated circuit 22.CPU integrated circuit 12 comprises a CPU (central processing unit) (CPU) 13, and system integration module 14 and other circuit 15 all pass through bus 17 bidirectional coupled.System integration module 14 comprises the external bus module interface circuit 16 with bus 30 bidirectional coupled.Other circuit 15 comprises bus interface circuit 18.Other circuit 15 can be by ic pin 19 and CPU integrated circuit 12 coupled outside.

I/O integrated circuit 22 comprises circuit 25-29 and external interface circuit 23, all passes through bus 24 bidirectional coupled.External bus interface circuit 23 bidirectional coupled are to bus 30, to CPU integrated circuit 12 transmission information or from CPU integrated circuit 12 reception information.I/O control module circuit 25-29 is by ic pin 31-35 and I/O integrated circuit 22 coupled outside.In optional embodiment of the present invention, the piece 31-35 among Fig. 1 represents integrated circuit land rather than ic pin.Each of module 25-29 comprises the passage (referring to the example among Fig. 2) in one or more channel pools.Each of module 25-29 also comprises secondary bus interface channel (SBIU) 36-40, is used to realize the interface of bus 24 between one or more passages and internal module.

In optional embodiment of the present invention, have one or more module 25-29.Because the restriction of module 25-29 internal bus load is divided into one or more module 25-29 with passage, each module has the bus interface 36-40 of oneself.The quantity of passage is by the final load decision of the internal bus of each module 25-29 among each module 25-29.The modularization of architecture allows each module 25-29 to be made up of different passages in the channel pool.Like this, each module 25-29 can customization to satisfy the needs of different user.

Modularization channel system architectural characteristic

Except using the modularization channel pool, the present invention also adopts modular mode to realize channel bus, in order to transmit information at different interchannels.Because the channel layout difference of IOCM different editions, the channel bus structure must be flexibly.

Referring to Fig. 1 and 2, in one embodiment of this invention, the passage among the IOCM (as IOCM 25) is by channel bus communication.Following channel bus can be realized the lateral communications of passage in IOCM: the address and the data conductor of (1) intermodule bus (IMB) 24; (2) one or more timer buses; (3) one or more pin/status bus.Passage also can set up interconnected path to carry out the streams data of adjacency channel between any two.Address in the intermodule bus 24 and data conductor provide the access path register, the mode of control register and status register.In one embodiment of this invention, bus interface circuit 36-40 (referring to Fig. 1) carries out global address decoding to judge whether specific IOCM25-29 is addressed.Yet all local address decodings are all finished in each passage.

The timer bus structure

Referring to Fig. 2, the present invention uses one or more timer bus 71-72, can by master timer bus control channel and auxilliary timer bus control channel (TBCC) 61-64 these timer buses be divided into a plurality of sections simply, with increase can to other passage broadcasting the time base quantity.

The architecture of IOCM 25-29 and bus structure provide along timer bus direction the timer bus method of the section of being divided into simply.Consequently, each root timer bus is divided into different passage blocks with passage, and passage block is not basic simultaneously by their timer bus access separately.Because each passage in the timer bus block can receive identical time base value from the timer bus, so the interior passage of timer bus block can be carried out different functions and not lose resolution ratio.

As an example, referring to Fig. 2, note timer bus 71 corresponding to the passage block that is marked with work and other passage 86 in the passage block, timer bus 72 is corresponding to the passage block that is marked with work and other passage 87 in the passage block.Timer bus 71 is used for base value when work transmits with other passage 86, and is same, and timer bus 72 is used for base value when work and 87 transmission of other passage.

An end of noting each timer bus 71-72 is marked by a master timer control channel (TBCC), and the other end of timer bus is marked by an auxilliary timer control channel (TBCC).For example, an end of timer bus 71 is marked by master timer control channel (TBCC) 61, and the other end of timer bus 71 is marked by auxilliary timer control channel (TBCC) 62.Equally, an end of timer bus 72 is marked by master timer control channel (TBCC) 63, and the other end of timer bus 72 is marked by auxilliary timer control channel (TBCC) 64.The auxilliary timer control channel of master timer control channel is used to indicate each part or each section of timer bus.

Referring to Fig. 2, recognize that it is important that timer bus 71 must be used different leads with timer bus 72, because they must transmit different time base values simultaneously.Yet timer bus 71 and timer bus 72 can be considered as independent bus line from conceptive, perhaps also can be from conceptive different piece or the section of regarding same global timing device bus as.In this sense, global timing's device bus be point to all necessary work of IC22 and other all requirements of channel transfer the time base value bus.Key is the time base value that must transmit simultaneously each group, must use different timer bus conductors.These different leads can be considered to independent bus line, perhaps are considered to the different piece or the section of a global bus.

In some embodiments of the invention, master timer control channel (TBCC) can be controlled the timer bus separately.Auxilliary timer control channel (TBCC) only the time base passage block time base value that provided just need need on two timer buses, share the time.In addition, main TBCC also can substitute auxilliary TBCC and shares with the time base value that allows two timer buses.For example, referring to Fig. 2,, can not need auxilliary TBCC 64 if timer bus 72 only needs from the time base value of time base passage 81.Auxilliary TBCC64 in order to from the time base passage 82 base value when timer bus 72 provides.Auxilliary TBCC 64 is controlled by main TBCC63.

Attention is in optional embodiment of the present invention, and each passage block can have still less, and more or different passages is coupled to the timer bus.For example, work and other passage 86 and 87 can comprise still less the service aisle in the more or different channel pools or other passage.

In the timer system that comprises modularization channels configuration piece, the timer bus structure of segmentation provide at any place along timer bus direction and provide a plurality of and not basic simultaneously modes easily to the different piece of timer system, and do not lose resolution ratio.

For example, in a typical timer system, some in base when identical that base when work and other passage 86 are may be with the first predetermined decomposition rate access specific, work and other passage 87 may need that access and passage 86 be associated, base when adding other of the second predetermined decomposition rate.The present invention with global timing's device bus need be to the local segmentation of each IOCM 25-29 output.Consequently, corresponding to the passage (as 71 and 72) of each single timer bus receive that their need the time base carrying out the function that requires, and do not lose resolution ratio.

Also be in the timer system of the timer bus that needs may be grown very much,, the invention provides mode, have enough driving forces with each part that guarantees the timer bus with the timer bus sectionalization because need to support a large amount of functions.

In the present invention, the timer bus is (as among Fig. 2 the time in the base passage 80 one) base value when receiving from time base passage, and to one or more work and other passage (working in as Fig. 2 and other passage 86) base value when this is provided.By while base value when a plurality of work and other passage provide, between work and other passage, be consistent.

In one embodiment of this invention, the timer bus is a time division multiplex bus, and the base passage provides nearly 8 not base values simultaneously, time division multiplexing in same timer bus when allowing nearly 8.In optional embodiment of the present invention, the timer bus may not be a time division multiplexing, and perhaps time division multiplexing becomes the time period of varying number.

Referring to Fig. 2, in one embodiment of this invention, when master timer bus control channel (TBCC) 61 is selected in the base passage 80 and 81 which or which can provide the time base value to drive timer bus 71.When if main TBCC 61 selects in the base passage 80 one, for example the timer passage 91, and then main TBCC 61 drives timer bus 71 with the time base value that timer passage 91 is provided.If but main TBCC 61 one in the base passage 81 when selecting, for example the timer passage 92, and then auxilliary TBCC 62 drives timer bus 71 with the time base value that timer passage 92 is provided.Like this, base value when having only main TBCC to select which timer passage to provide, but main TBCC and auxilliary TBCC can from the time base passage base value when receiving, and base value drives the timer bus during with this.

In one embodiment of this invention, each main TBCC provides all controls to respective secondary TBCC.Control register stored bits in each main TBCC (as the control register stored bits 68 among the TBCC 61 and the control register stored bits 69 among the TBCC 63) is used between each active period of 8 time division multiplexing windows of timer bus, and base was selected signal when control activated certain.The time base that comes from main TBCC selects signal to be used to select the time base that activates, by main TBCC (from the time base passage 80) or auxilliary TBCC (from the time base passage 81) be strobed into corresponding time division multiplexing timer bus 71.

Referring to Fig. 2, select signal 50 and must extend to base passage 80 when relevant with main TBCC 61 from main TBCC 61, and basic passage 81 from main TBCC 61 leap work and other passage 86 to auxilliary TBCC 62 and during it relevant.In addition, base was that physics is active on the timer bus when time base selected signal 50 also to be used to which is judged by work and other passage 86, to determine when execution such as coupling and the specific operation of catching.Like this, time base select signal 50 effectively from main TBCC 61 to work and other passage 86 and Shi Ji passage 80, the time base passage 81 transmitted an ident value.This ident value selects signal 50 to transmit by time base, with indication on timer bus 71 which the time base available at present.

Notice that in one embodiment of this invention, each channel shown in Fig. 2 has one or more user-programmable channel control registers 260 (referring to Figure 13).Dissimilar passages can have some identical registers.Referring to Fig. 2 and Figure 13, in one embodiment of this invention, the channel register 260 that each passage in 80,81 and 86 and each passage 61 and 62 all have one or more couplings as shown in figure 13.

Referring to Figure 13, a part 264 storage user program ident values of channel control register 260, this value can be selected to encode or do not encode.If ident value is encoded, this code identification value offers decoding scheme 261, and this circuit provides a decoding ident value in output.This decoding ident value selects ident value that signal 50 provides relatively with time base subsequently.If base is selected the ident value of driving on the signal 50 during this ident value coupling, then matched signal 263 just got with indicate this passage to this passage or when the timer bus provides one base value (for the time base passage), perhaps from timer bus interface time receiving base value (for work and other passage).

In optional embodiment of the present invention, this ident value is stored in 264 parts of channel control register 260, encodes.Consequently no longer need code translator 261.What replace is, 264 parts are directly as the input of multiplexer (MUX) circuit 262.The input of 264 parts control MUX circuit, basic of selecting in the signal 50 during selection provides as matched signal 263 when output.

Timer bus structure of the present invention are supported following function.At first, the timer bus structure allow any place segmentation along its length direction.Secondly, allow a pair of timer bus control channel (TBCC), promptly main TBCC and auxilliary TBCC, the segmentation of control timer bus.The 3rd, allow identical time base passage (for example time base passage 81 among Fig. 2) simultaneously to two different timer total segments (as timer bus 71 and 72) base passage when providing identical.

The 4th, timer bus structure of the present invention allow each timer bus to be divided into N time-division multiplex timesharing window.The 5th, any one when timer bus structure support user program is selected M in the base value drives in each in N the timesharing window in each timer total segment.For example, base passage 81 can comprise the time basic passage (for example timer passage 92 and timer passage 95) of varying number in the time of among Fig. 2.Each time base passage can be to timer bus 71, timer bus 72 or base value when timer bus 71 and 72 provides one or more simultaneously.Numeral M and N are positive integers.

As an example, referring to Fig. 2, in one embodiment of this invention, base value (M=5 just) when time base passage 81 can provide 5, base value when wherein timer passage 92 provides 2 " A " and " B ", base value when timer passage 95 provides 3 " C ", " D " and " E "; Timer bus 71 and timer bus 72 can each all time division multiplex become 8 timesharing windows (N=8 just).Split window can drive base value: A when following during 8 of timer bus 71, D, and A, B, A, D, A, C repeats in 8 timesharing windows of next group of timer bus 71 certainly.On the other hand, split window can drive base value: B when following during 8 of timer bus 72, D, and B, D, B, D, B, D repeats in 8 timesharing windows of next group of timer bus 72 certainly.In second and the 6th timesharing window, the same time base value " D " that is provided by timer passage 95 is provided for timer bus 71 and timer bus 72.

Figure 15 show 8 about the user base value (TB1, TB2, TB3, TB4, TB5, TB6, TB7, example TB8) when how selectivity provides one or more between the different time-gap of timer bus.When each time base passage 80 provides among the base value TB1-TB8 one.Each time base passage 80 is by user program register-stored circuit 264 (referring to Figure 13) storaging mark value.Timer selects signal 50 to drive an ident value in each time slot, programming ident value during this ident value coupling in the base passage, base source bus 271 (referring to Figure 14) during time base channels drive, thus base value during with this (among the instant base value TB1-TB8) has driven timer bus 71.

Attention is in optional embodiment of the present invention, and base value (TB1-TB8) had one group of programmable register stored bits when the base access needle was to each in the time of one, and this passage can provide these bits to timer bus 71.Every group of programmable register stored bits 264 can be programmed stored bits 264 is carried out write operation (as the CPU from Fig. 1 13).In optional embodiment of the present invention, sign stored bits 264 can shield programmability, and they can become certain fixed value at I/O integrated circuit 22 production period one-time programmings like this.

Attention is except time base passage 81, the time base passage 80 also can be by user program, base value when providing one or more for timer bus 71.Equally, except time base passage 81, the time base passage 82 also can be by user program, base value when providing one or more for timer bus 72.Like this, available and on timer bus 71, drive the time base value total quantity be by the time base passage 80 and Shi Ji passage 81 provide the time base value summation.Equally, available and on timer bus 72, drive the time base value total quantity be by the time base passage 81 and Shi Ji passage 82 provide the time base value summation.

Timer bus structure of the present invention also have more property.The 6th, base value was strobed into common timer total segment (as timer bus 71) to timer bus structure of the present invention when control was a plurality of by master timer bus control channel and auxilliary timer bus control channel (base passage 61 and Shi Ji passage 62 as among Fig. 2 the time).Select signal for one during when time base selects signal 50 to be included in base passage 80 and the Shi Ji passage 81 each on the base passage.Select some in the signal by get the timing base between suitable timesharing window phase, the base passage was strobed into timer bus 71 when base passage 61 was selected one when main.

The 7th, base is selected signal 50, base value when which the present forward timer bus during with judgement in the base passage provides when timer bus structure permission work of the present invention and 86 monitoring of other passage.Consequently, work and each of other passage 86 can determine when to carry out their operations separately, base value as coupling or when catching selected on the timer bus 71.Work and other passage 86 marquis when being selected signal 50 decisions suitable by time base reads timer bus 71, and uses the time base value executable operations of reading to come from timer bus 71.

Time base passage and Shi Ji are synchronous

Referring to Fig. 2, the present invention uses one or more time base passages (as 81) base value when producing, and provides to work and other passage 86 and 87 by timer bus (as 71,72).The architecture of IOCM 25-29 is divided into different work and other passage block (as 85-87) with bus structure (referring to Fig. 1) with each IOCM, and these passage blocks can the not basic simultaneously passage of access (as 80-81).Because each work in each piece and other passage can receive base value when identical from the timer bus, the work in a passage block can be used to carry out difference in functionality with other passage and not lose resolution ratio.

In one embodiment of this invention, time base passage (as 80,81) can comprise following one or more: (1) timer bus control channel (TBC) provides the main control or the auxilliary control of timer bus; (2) number of degrees timer passage (DC) can provide base when reaching four; (3) timer passage (TC) provides to result from inside or outside time base.

Referring to Fig. 2 and Figure 14, in one embodiment of this invention, each of time base passage 80 with the time base source bus 271 be coupled.Time base source bus 271 carries out time division multiplex in the mode identical with timer bus 71.Each of time base passage 80 relatively the time base select signal and be stored in the user program ident value (referring to Figure 13) of register section 264.If coupling, base source 271 when base drove when this mated passage with passage.Base source bus 271 when unmatched passage does not drive in this specified time interval.Coupling logic 270 (referring to Figure 14) is used for suitable transmission number of times from time base source bus 271 base value when timer bus 71 provides the next one.

Driving force for the timer bus, data transmitted frequency on the timer bus, the consideration of different timer system physical locations or route aspect, the data handling system of a complexity (as the data handling system among Figure 17 315) just possibly can't be finished its function if too big in the base when single.In some data handling systems, dividing timer system between data module is necessary (referring to Figure 16).Because the scale of total system, perhaps because the requirement of different technologies is exported driving as power, simulated input condition and complicated digital circuit, it is necessary dividing between a plurality of integrated circuit.Referring to Figure 17, under interface integrated circuit and the existing packaging technique of power integrated circuit, base value is infeasible during to interface integrated circuit 301 or to power integrated circuit one 16 bit of 302 distributions or 32 bits.

Referring to Figure 16-19, the present invention is only by two signals, and a timer signal 328 and a synchronizing signal 329 make base passage when two or more (during as main among Figure 16 and Figure 18 base passage 285 and when auxilliary base passage 288) synchronously or keep synchronously.Timer signal 328 and synchronizing signal 329 can be between the timer systems of different integrated circuit (referring to Figure 17), or (referring to Figure 16) broadcasts between the disparate modules of an integrated circuit.The base passage produces or receives the master timer signal when main, connects one or more auxilliary timer channels to guarantee when main that base passage and auxilliary timer channel are simultaneously with identical rate increase or successively decrease.

For example, in Figure 18, base passage 285 produces a master timer signal 328 by number system timer signal 327 when main.Base passage 285 offers master timer signal 328 one or more auxilliary time base passages (as 288) subsequently to guarantee when main that base passage and auxilliary timer channel are simultaneously with identical rate increase or successively decrease when main.In the optional embodiment of the present invention shown in Figure 19, base passage 304 all receives identical master timer signal 348 with auxilliary time base passage 310 when main, the master timer signal is the signal (referring to Figure 18) identical with system timer 327 in some embodiments of the invention.Yet base passage 304 and auxilliary time base passage 310 are all with equal number counting master timer signal 348 when main.Like this, base down counter 340 successively decreases with identical speed with Shi Ji down counter 341 simultaneously the time.

If data handling system (as 315 among Figure 17) is used the system timer of a fixed frequency, and this system timer can be used as input and one or more input of base passage when auxilliary of main time base passage, so main when main the base passage and the pre-calibration circuit 326 of base passage when auxilliary, select identical pre-calibration score value among 346 and 350 (referring to Figure 18 and Figure 19), this system timer promptly can be used as the master timer signal.In fact this saved a new interconnected lead of master timer signal of necessary increase.In the data handling system of the system timer signal that uses non-time domain or irregular frequency, the base passage must produce the master timer signal when main.Key is that all base passage (as 285 among Figure 18 and 288,304 among Figure 19 and 310) must be with the master timer signal (as 348 among 328 among Figure 18 and Figure 19) of same frequency and phase place regularly when synchronous.

Need then synchronizing signal (as 349 among 327 among Figure 18 and Figure 19) with basic sometimes passage (as 285 among Figure 18 and 288,304 among Figure 19 and 310) be arranged to identical initial value, carry out increment/decrement by above-mentioned master timer signal on this basis.To using the time basic passage of self-excitation timer, the synchronous points of most convenient is the overturn point to $0000 Huo $FFFF, depends on that it is a count-up counter or a down counter (referring to Figure 18).Base during for modulus, the point that modulus value is loaded into counter is the synchronous points (referring to Figure 19) of most convenient.

Select these synchronous points to be because main time base passage (as 285 among Figure 18,304 among Figure 19) has had the required testing circuit that is used for other purposes (as 330 of Figure 18,351 among Figure 19).In addition, the time base in these selected synchronous points is existing or simple generation (as down counter De $0000, the modulus value in count-up counter De $FFFF and the modulus counter) in all auxilliary time base passages.The base passage is used to detect the appearance of synchronous points to produce synchronizing signal when main.Synchronizing signal offers one or more auxilliary time base passages subsequently, wherein synchronizing signal in order to simultaneously with institute sometimes base value be reset to identical value.

In case the counter (320 among Figure 18 and 321,340 among Figure 19 and 341) in each time base passage has been set as identical value, and with same frequency and phase place master timer signal timing, counter should keep all count values fully synchronously.If base value in the time of loses synchronously because of noise or other influence, undertaken again synchronous by synchronizing signal in next synchronous points.

Like this, the time basic passage of the present invention's permission on different I/O control module (IOCM) 281-284 (referring to Figure 16) or different integrated circuit 300-302 (referring to Figure 17) produces and uses a synchronization and consistent time base value.Because the restriction of circuit load, can with same timer bus 71 couplings with from the time work of base passage 80 and 81 base value when receiving and other number of channels have a higher limit.Like this, the present invention allow on different I CM and the different integrated circuit the time base passage to providing synchronization and consistent time base value with different work and other passage of different timer buses couplings.When using the ic pin of minimum number, the performance that increases the timer passage to peripheral hardware integrated circuit (as 301 among Figure 17 and 302) is important.

Referring to Figure 16, notice that in one embodiment of this invention the IOCM 281 in timer system integrated circuit 280 comprises all circuit shown in Fig. 2.Equally, the IOCM in timer system integrated circuit 280 284 comprises the copy of all circuit shown in Fig. 2.Be different from intermodule bus 24 (referring to Fig. 1), overall tunneling traffic bus 200 (referring to Figure 10), master timer signal 328 and synchronizing signal 329, IOCM 281 and IOCM 286 are coupled with transmission information betwixt without any need for other lead.

In the context of attention base passage synchronously the time, term " master " and " assist " basic passage reception synchronizing signal (assisting) when synchronizing signal (master) and which basic passage provide when being used to which is indicated.Term " master " is different with the meaning of master timer bus control channel and auxilliary timer bus control channel with " assisting ", and is also different with the meaning of being responsible for foot control system passage and auxilliary pin control channel.Yet in general, the circuit of more control pointed out to provide in term " master ", and the circuit of pointing out to provide less control or receiving more control signal from main circuit there " assisted " in term.

Pin/status bus structure

Referring to Fig. 1 and Fig. 2, pin/status bus 75-77, with timer bus 71 and 72 similar, be modularizationization, can expand or segmentation to create the independent bus line of delivery unlike signal.The present invention uses one or more pins/status bus 75-77, and these buses can be controlled (PCC) by pin and be divided into different buses and section simply.

The interchannel that pin/status bus 75-77 is used in IOCM 25 transmits information.In some embodiments of the invention, one or more pin/status bus (as 77) in order to from an IOCM (as 25) to another different IOCM (as 26) transmission information.In addition, pin/status bus 75-77 is used for transmitting information at one or more interchannels of ic pin 33 and IOCM 25.Ic pin 31-35 is used to receive and provide the external information of I/O integrated circuit 22.Each IOCM25-29 has one or more pin/status bus with transmission information between a plurality of IOCM interchannels or IOCM passage and one or more ic pin 31-35.

In some embodiments of the invention, pin/status bus 75-77 serves as the passage influence and controls the mode that is coupled to other passage on identical pin/status bus.Pin/status bus 75-77 also serves as the mode of passage influence and control output ic pin logic level, and passage is transfused to the logic level influence of ic pin and the mode of control.

In one embodiment of this invention, each of pin/status bus (as 75-77 among Fig. 2) can be used as four purposes: the logic level of one or more ic pins of (1) indication programming input; (2) logic level of one or more ic pins of decision programming output; (3) serve as the incoming event source of one or more passages; (4) serve as the outgoing event destination of one or more passages.

It is necessary coordinating by CPU 13 (referring to Fig. 1) that data to passage write.Under the situation of using pin/status bus, consistance must be guaranteed.These buses provide interchannel synchro control, so channel operation can the phase mutually synchronization.Because CPU 13 also influences these buses by the control register in the pin control, so channel operation can be synchronous with CPU 13 operations.Consequently, the consistent access of channel data can be guaranteed by the control of 13 pairs of pin/status bus of CPU.

The architecture of IOCM 25-29 and bus structure provide any place along its length with pin/status bus method of the section of being divided into simply.Consequently, passage be divided into can access the different passage blocks of different ic pins.Each passage in a passage block can be to a plurality of, and one, or the ic pin that does not have provides information, or from a plurality of, one, or the ic pin that does not have receives information.Equally, in a passage block, can provide information to same ic pin, or receive information from same ic pin more than a passage.Referring to Fig. 2, note with passage be divided into can the different pins of access/status bus 75-77 different passage blocks with passage is divided the different passage blocks that journey can the different timer buses of access and is had nothing to do.

As an example, referring to Fig. 2, note pin/status bus 75 corresponding to the passage block that is marked with 57, pin/status bus 76 is corresponding to the passage block that is marked with 58.Pin/status bus 75 is used for transmitting pin and/or status information in 57 in passage, and is same, and pin/status bus 76 is used for transmitting pin and/or status information in 58 in passage.

(as 61-64 among Fig. 2) is different with the timer bus control channel, and " master " and " assisting " version is not distinguished in pin control.What replace is that its corresponding pin/status bus of control is responsible in each pin control.For example, in Fig. 2, pin control 51 control pin/status bus 75; Pin control 52 control pin/status bus 76; Pin control 53 control pin/status bus 77.

Yet as shown in Figure 3, pin control shared logic 106 can be in order to optionally to be coupled to one or more leads of pin/status bus 118 one or more leads of pin/status bus 119.Like this, pin/status bus (118,119) of in fact having formed an expansion.For example, pin control shared logic 106 can connect pin/status bus 118 and pin/status bus 119, and like this, bus 118 can transmit identical numerical value or signal with one or more leads of 119.Consequently, pin control shared logic 106 allow pin/status bus 118 with 119 part or all effectively be connected or be extended to a bus, this bus is the identical signal of delivery between the integrated circuit of the passage of twice and twice actually, transmits identical information.

Referring to Fig. 3, IOCM 26 parts shown in Fig. 3 comprise 4 pins/status bus 116-119.Pin/status bus 116 does not transmit any information to any other pin/status bus by pin control 109 controls.Pin/status bus 117 does not transmit any information to any other pin/status bus by pin control 108 controls.Pin/status bus 118 is by pin control 105 controls, and by pin control shared logic 106 to and/or from pin/status bus 119 transmission information.Pin/status bus 119 is by pin control 107 controls, and by pin control shared logic 106 to and/or from pin/status bus 118 transmission information.

In one embodiment of this invention, each pin/status bus (as 118) has 8 leads in order to transmit pin information (as 112), and 8 leads can be programmed separately to transmit 8 pin informations or status information (as 113).Control register stored bits 120 in pin control 105 is used for optionally determining, for each pin/status bus 113, whether this lead transmits pin information between passage 123 and one or more ic pin 110, or this lead is not only at 123 transferring status datas of passage.Equally, control register stored bits 122 in pin control 107 is used for optionally determining, for each pin/status bus 115, whether this lead transmits pin information between passage 125 and one or more ic pin 111, or this lead is not only at 125 transferring status datas of passage.

The part of control register stored bits is used to control lead selectively coupled of the lead of pin/status bus 118 and pin/status bus 119 in pin control shared logic 106.In optional embodiment of the present invention, the part of control register stored bits can be duplicated in the pin control shared logic 106, as the part of pin control (PCC) 105 and 107 physical circuits.Can change the shielding option to activate this part of two control register stored bits of one in the pin control 105 and 107.

For example, change the part that the shielding option can activate the control register stored bits 121 in the pin control 105, and the part of duplicating of control register stored bits 121 keeps unactivated state in the pin control 107.Control register stored bits 121 parts that activate in the pin control 105 and 106 couplings of pin control shared logic, and be used for control tube foot control system shared logic 106, and the part of duplicating of unactivated control register stored bits 121 is not coupled with pin control shared logic 106 in the pin control 107, and pin control shared logic 106 is not had influence.In one embodiment of this invention, pin control 105 with control register stored bits 121 that part activates is considered to the control of " master " pin, and the pin control 107 with the unactivated control register stored bits 121 of part is considered to " assisting " pin and controls.

Referring to Fig. 2, recognize that it is important that pin/status bus 75-77 must use different leads, because they must transmit not pin/state value on the same group simultaneously.Yet pin/status bus 75-77 can be considered as independent bus line from conceptive, perhaps also can be from conceptive different piece or the section of regarding same overall pin/status bus as.In this sense, overall pin/status bus is to point to all necessary passages of integrated circuit 22 and the bus that all essential pins transmit the pin/state value of all requirements.Key point is to each pin that must transmit simultaneously/state value group, must use not pin/status bus lead on the same group.These different leads can be considered to independent bus line, perhaps are considered to the different piece or the section of a global bus.

Attention is in optional embodiment of the present invention, and each passage block can have still less, and more or different passages are coupled to pin/status bus.For example, referring to Fig. 2, passage 57 and 58 can comprise still less, the available channel in the more or different channel pools.

In the timer system that comprises modularization channels configuration piece, the pin of segmentation/status bus structure provides at any place along pin/status bus direction and provides modes a plurality of and different pin/status informations easily to the different piece of timer system, and does not lose resolution ratio.

For example, in a typical timer system (referring to Fig. 2), may need exchange message between the passage 58, and under pin control 52 controls access ic pin (not shown), and may need exchange message between the passage 57, and control access ic pin (not shown) under 51 controls at pin.Referring to Fig. 3, if one or more passages 123 need provide information, or from one or more passage 125 reception information, pin control shared logic 106 must be inserted between pin control 105 and the pin control 107 shares information with permission pin/status bus 118 and pin/state C119, and transmits identical pin/state value simultaneously.The present invention with overall pin/status bus need be to the local segmentation of each IOCM 25-29 output.Consequently, corresponding to the passage (as 75,76 and 77) of each single pin/status bus, receive and provide and carry out the needed pin/status information of function that requires.

Also be in the timer system of pin/status bus that needs may be grown very much, because need to support a large amount of functions, the invention provides mode, have enough driving forces with each part that guarantees pin/status bus with pin/status bus segmentation.

Pin and and or output flexibly

The specific embodiment of the pin/status bus shown in Fig. 3 only is a kind of possible embodiment, also has many other embodiment.The optional embodiment of another of pin/status bus shown in Fig. 4 allows user logic to merge hyperchannel output to judge the state of output pin.

Among the embodiment shown in Figure 4, each free input state bus 143-145 of each of pin among Fig. 1/status bus 75-77 and outgoing event bus 131-133 realize.Each root input state bus 143-145 comprises 8 pin leads 146,148 and 150 separately; And 8 pin/state leads 147,149 and 158.Each outgoing event bus 131-133 comprises 8 set leads 134,137 and 140 separately; 8 zero clearing leads 135,138 and 141, and 8 upset leads 136,139 and 142.

Outgoing event bus 132 is used to judge the output state of pin one 95, corresponding to controlled in pin control channel 52.Different passages in the passage 58 influence the logic state of pin one 95 by the outgoing event bus.Each of pin one 95 is coupled to some in the set lead 137, some in the some and upset lead 139 in the zero clearing lead 138.Like this, the logic state of specific pin 195 is by the logic state decision of these three leads that are coupled to this specific pin, i.e. set, zero clearing and upset.Yet, note set, zero clearing and upset lead do not influence the pin one 95 that is configured to input pin by pin control channel 52.The set that is associated with pin, zero clearing and upset lead only just work when this pin is configured to output pin.

Still referring to Fig. 4, in one embodiment of this invention, each of 24 lead 137-139 all is one and can carries out the line that line connects XOR with other lead and connect the XOR lead.In one embodiment of this invention, all the set leads 137 in the service aisle piece (as 160,161) are that common line connects XOR.Equally, all the zero clearing leads 138 in the service aisle piece (as 160,161) are that common line connects XOR.Similarly, all rollovers lead 139 in the service aisle piece (as 160,161) is that common line connects XOR.

As example, the operation of pin/status bus 76 (referring to Fig. 4) is described below.Fig. 5 shows the part of pin/status bus 76, when pin one 65 is configured to output pin, is used for the output state of control integrated circuit pin one 65.Set lead 157 is in 8 set leads 137 shown in Fig. 4; Zero clearing lead 158 is in 8 zero clearing leads 138 shown in Fig. 4; Upset lead 159 is in 8 upset leads 139 shown in Fig. 4.Each root lead 157-159 is that a line that is precharged to logic level 1 connects the XOR lead.Like this, if the pin control circuit 162 of coupling passage 160 drives logic level 1 on lead 171, and the pin control circuit 163 of coupling passage 161 drives logic level 0 on lead 168, and the logic level of set lead 157 will be a logic level 0.Therefore, line is connect the XOR lead, logic level 0 is main.Optional embodiment also can use line to connect or lead.

Pin control circuit 164 receives set lead 157, zero clearing lead 158, and the line of upset lead 159 meets the XOR result.Pin control circuit 164 also receives the current logic level of pin 165 by lead 174.Pin control circuit 164 uses the logic level result of the logic level of lead 157-159 and 174 with judgement lead 168, and then judges the next output logic level of ic pin 165.

Fig. 6 shows a truth table that embodiment is used by pin control circuit 164, with the logic level result of judgement lead 168, and then the next output logic level of judgement ic pin 165.Lead 168 is used to drive the output logic level of pin 165 as a result.Truth table shown in Fig. 6 has defined an agreement, is used to determine pin one 65 aaset bit, zero clearing and upset lead 157-159 the action might situation taked.For the table of Fig. 6, set, the positive status of zero clearing and upset lead 157-159 is logic level " 0 ", set, the negative state of zero clearing and upset lead 157-159 is logic level " 1 ".This agreement can be presented below: (1) if the upset lead 159 are positive status, the overturning unit merit, pin one 65 is reversed; (2) if all lead 157-159 are negative states, pin one 65 keeps former level; (3) if set lead 157 and zero clearing lead 158 all are positive status, upset lead 159 is negative states, and pin one 65 keeps former level.Optional embodiment can use different agreement and different truth tables.

By having independent set (137), the outgoing event bus 132 of zero clearing (138) and upset (139) lead, the present invention can actuating logic operation in the output of a plurality of passages, and does not need service processor to get involved.This is very powerful and performance flexibly.

For the change of initialization timer output pin logic level with result phase as a plurality of timer passages, prior art necessarily requires service processor (as CPU (central processing unit)) to get involved.Service processor is by interrupting or other mechanism intervention.Service processor is discerned a plurality of timer channel statuses, as response, produces a corresponding logic level at the timer output pin and changes.Whether an example of coupling channel status is to mate to occur.

After the selected channel status of identification, the service processor executing state relatively produces one of following result and uses for specific automation application: (1) if the state of all selected passages be very then the set output pin; (2) if the state of all selected passages be very then the zero clearing output pin; (3) if the state of any one selected passage be very then the set output pin; (4) if the state of any one selected passage be very then the zero clearing output pin.Unfortunately, come the state of the different passages of comparison and cause output pin to be driven to the suitable a large amount of software overhead of output logic level needs by service processor.Because the output pin state of a set and an accurate timing of zero clearing is with the comprehensive state as a plurality of passages, intervention that must service processor, so the stand-by period of service processor can cause in the output of accurate timing, timing error occurring.

The present invention allows to dispose the timer passage to carry out above-mentioned four classes " logic " operation, does not need the intervention of service processor.Consequently, in the output of accurate timing, can not cause occurring timing error because of the stand-by period of service processor.The quantity of the timer passage output that can logic merges only is subject to total number of channels available in this timer system in theory.

The invention provides user-programmable timer passage output pin logical and and or, as the pin one among Fig. 5 65.In one embodiment, the invention provides a kind of system, this system has a plurality of independent timer passages and possesses the ability of selectivity configuration portion of channel, can control pin status and does not need the intervention of service processor.Its algorithm is an one of the following: (1) if the output state of all selected passages is true, then this pin of set; (2) if the output state of all selected passages is true, this pin of zero clearing then; (3) if the output state of arbitrary selected passage is true, this pin of set then; (4) if the output state of arbitrary selected passage is true, this pin of zero clearing then.

Referring to Fig. 5, each pin has one or more control registers.Coupling passage 160 has control register 166, and coupling passage 161 has control register 167, and pin control channel has control register 184.Fig. 7 shows the part of control register 166 among Fig. 5 and the part of control register 167.In one embodiment, control register 166 has four pins to select control bit 180, be used for selecting the some of 16 ic pins, and control register 167 has four pins to select control bit 181, is used for selecting the some of 16 ic pins.In the one embodiment of the invention shown in Fig. 5, pin control

select bit

180 and 181 by user program with base pin selection 165.

In one embodiment of this invention, control register 166 has three pin output drive control bits 182, is used to select to mate the function that passage 160 produces at output pin 165.Equally, control register 167 has three pin output drive control bits 183, is used to select to mate the function that passage 161 produces at output pin 165.Fig. 8 shows in one embodiment of this invention, and the user can be by the function of pin output

drive control bit

182 and 183 programmings.In optional embodiment of the present invention, can use more bits, still less bit or the different control bit of different bits of encoded.

Referring to Fig. 8, the user program function has determined when coupling takes place how each coupling passage 160-161 influences set lead 157, zero clearing lead 158 and upset lead 159.For example, if coupling passage 160 is programmed to function of shielding, when coupling takes place, coupling passage 160 will not exert an influence to lead 157-159.If coupling passage 160 is programmed to the rising function, when coupling takes place, coupling passage 160 will be got timer period of positive set lead 157 (by drive logic level 0 on set lead 157).If coupling passage 160 is programmed to the decline function, when coupling takes place, coupling passage 160 will be got timer period of positive zero clearing lead 158 (by drive logic level 0 on set lead 158).If coupling passage 160 is programmed to turn over function, when coupling takes place, coupling passage 160 will be got timer period of positive tipping line 159 (by drive logic level 0 on set lead 159).

Remaining four functions, promptly with zero clearing, with set, or zero clearing and or set, be user-programmable timer passage output logical and and or.Fig. 9 shows by the logical and of coupling passage 160 and 161 states and or the output result that produces at pin one 65." T " is true, and coupling has taken place in indication, and " F " is false, and the indication coupling did not take place.If coupling passage 160 and 161 all is programmed for and set, when coupling passage 160 with coupling passage 161 coupling took place all, the next logic level of pin one 65 just can be set (that is to say logic level " 1 ").Like this, mean that coupling must be when coupling passage 160 all takes place with coupling passage 161, ability set pin one 65 with set.Equally, mean that coupling must be when coupling passage 160 all takes place with coupling passage 161, ability zero clearing pin one 65 with zero clearing.

If coupling passage 160 and 161 all is programmed for or set, when coupling passage 160 or coupling passage 161 generation couplings, the next logic level of pin one 65 is set (that is to say logic level " 1 ").Like this, or set means when coupling takes place for coupling passage 160 or coupling passage 161, with regard to set pin one 65.Equally, or zero clearing means when coupling takes place for coupling passage 160 or coupling passage 161, with regard to zero clearing pin one 65.Although the example shown in Fig. 9 uses two coupling passages, in fact can use the coupling passage of any amount.

In addition, can merge different logical ands and or function.For example, additional channel as counting channel 185, can be positioned between the coupling passage 160 and pin control channel 52 of Fig. 5.Counting channel 185 can have user program to select bit with the control pin of base pin selection 165 in control register 187.Like this, counting channel 185 can drive lead 157-159.If coupling passage 160 and 161 all is programmed for and set, counting channel 185 is programmed for or set, and when counting channel 185 reaches its count value or coupling passage 160 and coupling passage 161 and all takes place to mate, pin one 65 will be set.The present invention can be used for forming the more complicated Boolean equation that relates to different channel statuses.

Referring to Fig. 5, because set, the toe-in XOR attribute of zero clearing and upset lead itself, in fact they be used for actuating logic and operate with logical OR.How the operation of logical and and logical OR carries out if being described below.In one embodiment of this invention, set lead 157 and zero clearing lead 158 be used for realization and zero clearing and and set function; Upset lead 159 is used for realization or zero clearing and or set function.

If coupling passage 160 is programmed for and set, coupling passage 160 will be got positive zero clearing lead 158 until mating.Notice that set lead 157 and upset lead 159 keep precharge negative state (also being logic level " 1 ").When coupling takes place, coupling passage 160 will be got positive set lead 157 and the logic level that just continues to get until pin one 65 becomes logic level 1 (set just).Notice that coupling passage 160 receives the output logic level (referring to Fig. 4) of pin 165 by input state bus 144.As long as pin one 65 keeps set, coupling passage 160 is no longer got just any lead 157-159.Pin one 65 can be by other lead zero clearing, if coupling passage 160 is reconfigured by software, and also can be by coupling passage 160 to its zero clearing.In case pin one 65 is cleared, coupling passage 160 is got positive zero clearing lead 158 once more until mating.

If coupling passage 160 is programmed for and zero clearing, coupling passage 160 will be got positive set lead 157 until mating.Notice that zero clearing lead 158 and upset lead 159 keep precharge negative state (also being logic level " 1 ").When coupling takes place, coupling passage 160 will be got positive zero clearing lead 158 and the logic level that just continues to get until pin one 65 becomes logic level 1 (zero clearing just).Notice that coupling passage 160 receives the output logic level (referring to Fig. 4) of pin 165 by input state bus 144.As long as pin one 65 keeps zero clearing, coupling passage 160 is no longer got just any lead 157-159.Pin one 65 can be by other lead set, if coupling passage 160 is reconfigured by software, and also can be by coupling passage 160 to its set.In case pin one 65 is set, coupling passage 160 is got positive set lead 157 once more until mating.

If coupling passage 160 is programmed for or set, coupling passage 160 will not got just any lead 157-159 until mating.Notice that lead 157-159 keeps precharge negative state (also being logic level " 1 ").Pin one 65 must be by other passage zero clearing, or coupling passage 160 zero clearings by different configurations.When coupling takes place, coupling passage 160 will be got the logic level of just overturning lead 159 and just continuing to get until pin one 65 and become opposite logic level 1 (set just).Notice that coupling passage 160 receives the output logic level (referring to Fig. 4) of pin 165 by input state bus 144.As long as pin one 65 keeps set, coupling passage 160 is no longer got just any lead 157-159.Pin one 65 can be by other lead zero clearing, if coupling passage 160 is reconfigured by software, and also can be by coupling passage 160 to its zero clearing.In case pin one 65 is cleared, coupling passage 160 is waited for once more until upset lead 159 and being mated.

If coupling passage 160 is programmed for or zero clearing, coupling passage 160 will not got just any lead 157-159 until mating.Notice that lead 157-159 keeps precharge negative state (also being logic level " 1 ").Pin one 65 must be by other passage set, or coupling passage 160 set by different configurations.When coupling takes place, coupling passage 160 will be got the logic level of just overturning lead 159 and just continuing to get until pin one 65 and become opposite logic level 1 (zero clearing just).Notice that coupling passage 160 receives the output logic level (referring to Fig. 4) of pin 165 by input state bus 144.As long as pin one 65 keeps zero clearing, coupling passage 160 is no longer got just any lead 157-159.Pin one 65 can be by other lead set, if coupling passage 160 is reconfigured by software, and also can be by coupling passage 160 to its set.In case pin one 65 is cleared, coupling passage 160 is waited for once more until upset lead 159 and being mated.

The foregoing description of noting circuit operation among Fig. 5 also is applicable to other outgoing event bus conductor 131-133 shown in other passage 57-58 and Fig. 4.

The operation of input state bus 143-145 shown in Figure 4 is described now.In one embodiment, input state bus 143,144 and 145 each comprise 8 pin leads 146,148 and 150 separately, and 8 pin/state leads 147,149 and 151.Like this, each pin/status bus (as 118) has 8 leads to be used to transmit pin information (as 112) and 8 can to programme separately to transmit the lead (as 113) of pin information or status information.

Control register stored bits 192 in pin control channel 52 is used for judging selectively that each pin/state lead 149 is to transmit pin information between passage 58 and one or more ic pin 195, still transferring status data between passage 58 only.Equally, control register stored bits 191 in pin control channel 51 is used for judging selectively that each pin/state lead 151 is to transmit pin information between passage 57 and one or more ic pin 194, still transferring status data between passage 57 only.

Pin/state lead 147,149 and 151 can be used as the state lead, and the state lead does not influence pin, but can inform that incident (as coupling) has taken place on certain special modality other passage.Other lead thereby can be based on event on the special modality is adjusted behavior separately simultaneously.When as the state lead, lead 149 provides the mode of different passages in a kind of hardware bonded channel 58.Equally, when as the state lead, lead 151 provides the mode of different passages in a kind of hardware bonded channel 57.For example, coupling passage 161 can be by an information that provides coupling to take place in the positive conductor 149 be provided.Like this, whether this lead of channel monitoring in the one or more passage 58 mates to judge in the passage 161.

Pin lead 148 is used for the current logic state of ic pin 195 is sent back passage 58, and pin lead 150 is used for the current logic state of ic pin 194 is sent back passage 57.More specifically, each in the pin lead 148 is from the some current logic level of pin to the pairing ic pin 195 of this lead of passage 58 loopbacks.Equally, each in the pin lead 150 is from the some current logic level of pin to the pairing ic pin 194 of this lead of passage 57 loopbacks.

Like this, the present invention allows a plurality of passages (as passage among Fig. 4 58) to provide information to identical pin/status bus lead (as pin/status bus lead 76).Consequently, can influence the logic level of ic pin more than a passage, (as one in the pin one 95), and a plurality of passage can be that hardware connects.Although above-mentioned enforcement actuating logic with and or function, in optional embodiment of the present invention, can carry out any logical operation, comprise the logic XOR, different with, exclusive or and more complicated boolean's function.

Overall situation tunneling traffic bus

Referring to Figure 10, in some embodiments of the invention, transmit information at the interchannel that is coupled to different pins/status bus 216-218 by an overall tunneling traffic bus 200.The purpose of overall situation tunneling traffic bus 200 is the interchannel transmission information at different I CM 25-29 (referring to Fig. 1), and the interchannel transmission information that is coupled to different pin/status bus (as 216 among Figure 10 and 217) in an IOCM.In addition, in some embodiments of the invention, overall tunneling traffic bus 200 can receive information by ic pin 223 from the outside, and provides information to I/O integrated circuit 22 (referring to Fig. 1).Notice that the pin 34 shown in Fig. 1 may comprise the one or more of the pin two 33 shown in pin two 13-215 and Figure 10 in one embodiment of this invention.

With prior art, the local state that produces is communicated by letter with other independent circuits functional block on one or more integrated circuit by service processor with control information.For example, many controls are used and are used the incident (, catching timing or the like as coupling) that is produced by passage to trigger the different disposal on a plurality of independent circuits functional blocks.These independent circuits functional blocks can be distributed on the disparate modules physically, even on different integrated circuit.In realizing at present, require individual event to produce an interruption, require Interrupt Service Routine to trigger the action of on each independent circuits functional block, being taked.In addition, Interrupt Service Routine triggers each action successively.

Interrupt by using overall tunneling traffic bus 200 (referring to Figure 10) to replace, the present invention allows to broadcast state and the control information simultaneously of all passages.Like this, all operations in a plurality of independent circuits functional blocks can synchronous triggering, thereby the consistent mode (referring to Fig. 1) of communication overall signal is provided in whole data handling system 10 inside.

The overall broadcast behavior that is provided by overall tunneling traffic bus 200 (referring to Figure 10) has been eliminated one of each generation required interruption to service processor must be with the incident of the different tunneling traffics that are coupled to different pin/status bus the time.Compare with the existing techniques in realizing mode of using service processor, because the speed of Interrupt Service Routine is usually than the slow order of magnitude of speed of the broadcast behavior of overall tunneling traffic bus 200, so overall tunneling traffic bus 200 has also caused communication and response time faster.

In addition, during software fault, service processor does not normally move.Because service processor does not move, to interrupt just can not producing, the I/O function that many needs intercom mutually must conductively-closed.In the past, if during software fault, require the I/O system to carry out some limited operations, needed the specific hardware of design.Because the independent circuits functional block each other can be by overall tunneling traffic bus 200 direct communications, so broadcast behavior of the present invention has been eliminated the needs to these specific hardware.

Broadcast behavior of the present invention has also been simplified modification and has been increased required design and the realization of data handling system 10 (referring to Fig. 1).In many versions of data handling system 10, an interior passage of IOCM 25-29 is used to carry out a kind of specific function of or limited quantity, for bandwidth or the modification application that increases original application reconfigures some difficulty of hardware to carry out other task.The broadcast behavior that overall situation tunneling traffic bus 200 provides allows a plurality of independent circuits functional blocks (as IOCM 25-29) can communicate by letter each other, realizes difference in functionality thereby increased bandwidth and allowed to stride IOCM.

Referring to Figure 10, overall tunneling traffic bus 200 is used for transmitting information at the interchannel that is coupled to different pins/status bus 216-218.Different pins/status bus 216-217 can be distributed in the same IOCM (as IOCM27), or different pin/status bus 217-218 can be distributed in different I CM upward (as IOCM 26 and IOCM 27).In some embodiments of the invention, overall tunneling traffic bus 200 can be closed with all pins/status bus lotus root on the integrated circuit 22.

In optional embodiment, overall tunneling traffic bus 200 can be only with must close with pin/status bus lotus root that lotus root not is combined in same tunneling traffic on pin/status bus.For example, if do not have passage to receive in the passage 206 or provide information to any other passage except passage 206, pin/status bus 218 just needn't be coupled on the overall tunneling traffic bus 200.

Referring to Fig. 1, modular member bus 24 is used to carry out the read and write operation of C pin U13 to the register of the register that is positioned at external bus interface 23 and the passage that is positioned at IOCM 25-29.Modular member bus 24 is transfer system information also, as interrupting information.Modular member bus 24 is respectively by Bus Interface Unit 3640 and each IOCM interface.In one embodiment of this invention, overall tunneling traffic bus 200 is as just the part of modular member bus 24.

Yet in optional embodiment of the present invention, overall tunneling traffic bus 200 is different from modular member bus 24.The overall situation tunneling traffic bus 200 directly pin control channel (as 201-203) in each IOCM 25-29 is sought route.Overall situation tunneling traffic bus 200 is directly communicated by letter with each pin control channel (as 201-203) rather than is passed through Bus Interface Unit 36-40 indirect communication.

Coupling circuit 220-222 in laying respectively at each pin control channel 201-203 is coupled to one or more control register 224-226 separately.As an example, the control register stored bits in the control register 224 can be coupled on the overall tunneling traffic bus 200 with which root in base pin selection/status bus 216 or which root lead by user program.Like this, which passage the user can select be coupled to which root lead in pin/status bus 216 by control register 229-230 and pin control circuit 227-228, and the user can also be coupled on the overall tunneling traffic bus 200 by which the root lead in control register 224 and the coupling circuit 220 base pin selections/status bus 216.

In one embodiment of this invention, each of overall tunneling traffic bus 200 all is to be connect or lead by the line that pulls into logic level 0 under the weak pull-down device (not shown).Like this, if service aisle 212 is set to logic level 1 by coupling circuit 222 with first lead of overall tunneling traffic bus 200, and service aisle 210 is set to logic level 1 by coupling circuit 221 with same first lead of overall tunneling traffic bus 200, and the logic level of first lead of overall tunneling traffic bus 200 will be a logic level 1.Therefore, line is connect or lead, logic level 1 is main.Optional embodiment can use line to connect the XOR lead.

Referring to Figure 10, in one embodiment of this invention, pin/status bus (as 216-218) is not that line connects or lead or line connect the XOR lead.Therefore, to receiving the passage (as 204-206) of broadcasted values, coupling circuit (as 220-222) receives this broadcasted values from overall tunneling traffic bus 200, drives the selected lead (as 216-218) of pin/status bus then with suitable value.Similarly, to the passage (as 204-206) that broadcasted values is provided, coupling circuit (as 220-222) drives overall tunneling traffic bus 200 with suitable value then from suitable lead (as the 216-218) reading numerical values of pin/status bus.

Consequently, the present invention allows the user program of data handling system 10 (referring to Figure 10) to select in the integrated circuit 22, or which or which passage can provide information to the lead of overall tunneling traffic bus 200 in the different integrated circuit (as integrated circuit 12).The integrated circuit 22 that the information that provides to overall tunneling traffic bus 200 is selected to the user or all passage synchronized broadcasts of different integrated circuit (as integrated circuit 12) do not need the intervention of service processor.

The invention provides the signal of data handling system 10 all passages or the synchronous global communication mode of information.The invention provides the dirigibility of the information of between a plurality of independent circuits functional blocks (as IOCM 25-29), sharing, thereby allow IOCM 25-29 to move jointly, coordinate one or more functions that they are carried out.In addition, the present invention has reduced the number of interruptions that is used for service processor, allows data handling system 10 can carry out more function synchronously.

Figure 11 shows an embodiment of the part of control register 226 among Figure 10.In one embodiment of this invention, overall tunneling traffic bus 200 comprises 8 leads.Each root of 8 leads of overall situation tunneling traffic bus 200 all has SFUN (status function control) the register-stored bit 250 of a correspondence, a SDAT (status data) register-stored bit 251, a GLS (control is selected in the overall situation/this locality) register-stored bit 252 and a GDO (global data output) register-stored bit 253.For example, lead 246 (referring to Figure 12) is corresponding to SFUN bit 254, SDAT bit 255, GLS bit 256 and GDO bit 257.

SDAT bit 251 contains status data, and status data representative is for the communication and the needs of communicating by letter of passage to C pin U of channel-to-channel, by the result of the output state incident of the overall situation or local channel generation.Each SDAT bit 251 is subjected to 250 controls of corresponding SFUN bit.Each SFUN bit 250 has been specified the relevant pattern of a kind of with corresponding SDAT bit 251.The pattern that SDAT bit 251 is composed is " hardware controls " pattern and " software control " pattern.Except SFUN bit 250, SDAT bit 251 is also by 252 configurations of GLS bit.Whether the corresponding SDAT bit 251 of each GLS bit 252 control represents local status data or global state data.

As an example, referring to Figure 10 and Figure 12, if SDAT bit 255 is configured to local mode by corresponding GLS bit 256, and be configured to " hardware controls " by corresponding SFUN bit 254, SDAT bit 255 comprises the result of the passage output state incident that is driven by passage 206 on lead 241.If SDAT bit 255 is configured to global mode by corresponding GLS bit 256, and be configured to " hardware controls " by corresponding SFUN bit 254, SDAT bit 255 comprises the result of the global state incident that the selected passage by any place in the integrated circuit 22 (referring to Fig. 1) drives on lead 246.SDAT bit 255 provides its data to passage 206 by lead 240.Under " hardware controls " mode, SDAT bit 251 can not be write (referring to Fig. 1) by C pin U13.

If SDAT bit 255 is configured to local mode by corresponding GLS bit 256, and be configured to " software control " by corresponding SFUN bit 254, SDAT bit 255 comprises the data that write by C pin U 13 state with emulation lead 241.Yet when being configured to global mode, under the software control mode, SDAT bit 255 can not be written into.The global state of SDAT bit 255 reflection leads 246.SDAT bit 255 guiding lines 240 provide this value.Under the software control mode, only when being configured to local state, SDAT bit 251 could be write (referring to Fig. 1) by C pin U13.In order to write global state, GDO bit 257 must be written into.

When writing SDAT bit 251, can force single SDAT bit to become new state and do not influence other bit.For realizing this purpose, SDAT bit 251 and SFUN bit 250 must be write by C pin U13 simultaneously.Because the SDAT bit 251 of a correspondence of each SFUN bit 250 control influences SDAT bit 251 so this time of the content of SFUN bit 250 decision writes.In order to write to influence some in the SDAT bit 251, corresponding SFUN bit 250 must write %0.Do not influence some in the SDAT bit 251 in order to write, corresponding SFUN bit 250 must write %1.In this way, SFUN bit 250 is used to shield corresponding SDAT bit 251 with the ratio feature of control to specific SDAT bit 251.

Referring to Figure 11 and Figure 12, GDO bit 253 comprises the global data that offers overall tunneling traffic bus 200.The data that are stored in the GDO bit 257 provide by one in two possible sources, i.e. lead 241 and C pin U13.Whether SFUN bit 250 and GLS bit 256 decision leads 241 or C pin U13 provide global data to GDO bit 257.

When GLS bit 256 is configured to global mode, GDO bit 257 is used for guiding line 246 provides a global state value.Under software control mode and hardware controls mode, GDO bit 257 all provides this global state value by drive this global state value on lead 246.If GDO bit 257 is configured to the software control mode by corresponding SFUN bit 254, then C pin U13 can revise the global state value that is stored in the GDO bit 257.If GDO bit 257 is configured to the hardware controls mode by corresponding SFUN bit 254, then have only lead 241 can revise the global state value that is stored in the GD0 bit 257.

When GLS bit 256 is configured to local mode, GDO bit 257 is not used further to guiding line 246 global state is provided.GDO bit 257 can not be write by C pin U13.GDO bit 257 can only be revised by lead 241.

Referring to Fig. 3, attention allows the user to provide passage output from overall tunneling traffic bus 200 to output pin 110 ability that (corresponding to PCC105) of pin one 10 is coupled to (corresponding to other paired PCC107) of pin/status information lead 115.Like this, any passage in the integrated circuit 22 (referring to Fig. 1) can be by overall tunneling traffic bus 200 to any output pin 31-35 outgoing event.In one embodiment of this invention, the not reflection on pin/status information lead 115 of the logic level of input pin 110, like this, the pin input can not be carried out global communication by overall tunneling traffic bus.In an optional embodiment of the present invention, the logic level of an input pin 110 can be reflected on pin/status information lead 115, therefore can come the input of global transmission pin by overall tunneling traffic bus 200.

In one embodiment of the invention, GDO bit 253 can be read at any time by CPU13, when only being set to global state in the software control pattern, just can be write by CPU13.

With reference to Figure 11 and Figure 12, each SFUN bit 250 is used for preference pattern, is called software control pattern or hardware controls pattern, a corresponding respectively SDAT bit 251 and GDO bit 253.CPU13 can read and write SFUN bit 250 at any time.

With reference to Figure 11 and Figure 12, it is the part or overall that each GLS bit 252 is used to select a corresponding SDAT bit 251.The local state value that is stored in SDAT bit 251 only goes up transmission at local pin/status bus (as 218 among Figure 10), this bus by local pin control channel (as 203 among Figure 10) control.Be stored in the global state value in the GDO bit 257, can provide by overall tunneling traffic bus 200 or local pin/status bus (as 218 among Figure 10).CPU13 can read and write GLS bit 252 at any time.

With reference to Figure 12, it is the overall situation or local to notice that SDAT bit 255 can be set to respectively by the GLS bit 256 of correspondence.When being set to the overall situation, lead 241 provides a global state value to GDO bit 257, rather than SDAT bit 255.GDO bit 257 is sources that the global state value is provided to overall tunneling traffic bus 200 by lead 246.The final logic level (being the global state value) of lead-in wire or lead 246 is stored in the SDAT bit 255.This global state value is transferred to lead 240, delivers to the input (see figure 10) of passage 206 again.

Should note in one embodiment of the present of invention, global timing's device bus (not marking) is arranged, each master timer bus control channel (as 61 among Fig. 2 and 62) is given in coupling, be used for when one or more base value be transferred to timer bus on the different integrated circuit 22 (as Fig. 1) (as Fig. 2 71 and 72).Global timing's device bus (not shown) acts on (see figure 10) on the overall tunneling traffic bus 200 with analog form.In an alternative embodiment of the present invention, do not use global timing's device bus.But, if when independently IOCMs25-29 requires when identical base value, produce institute take base the time basic passage (as the degree timer passage 94 among Fig. 2) be replicated to a plurality of IOCMs25-29.

The interchannel data transmission

At " passage silicon storehouse (silicon library of channels) " a plurality of passages, can programme is used to finish data transfer operation.In data transfer operation, data can be transferred to the data register (as 401) of passage itself from the data register of a top adjacency channel (as 400 Figure 20) and be transferred to the data register of bottom adjacency channel (as 402) from the data register of passage (as 401) itself.Programme by control register bit, finish these interchannel data transmission, just can constitute and use stack and first-in first-out (FIFO) structure passage.Support the service aisle of interchannel data transmission to comprise in one embodiment of the invention: (1) coupling passage (2) trap channel; (3) add the counter passage.In one embodiment, the up-down counter passage also allows some data-transformation facilities.

In one embodiment of the invention, can utilize the passage of supporting the interchannel data transmission to constitute the structure of three kinds of fundamental types: (1) stack is a useful structure of collecting base value when many or counting operation value; (2) FIFO, a plurality of coupling outgoing events can be exported to a pin or state lead, wherein utilize to be stored in time base value collected in the fifo structure, (these outgoing events can utilize by other passage or until devices such as I/O integrated circuit); (3) FIFO also can be used for collecting and store up-to-date time base value or the most recent count operation that captures.

This stack and data fifo storage organization can reduce the service frequency of passage requirement, thereby reduce the interruption that needs by the CPU13 response and count (see figure 1).Figure 20 shows an example of data transfer operation between adjacency channel 400-402.

As shown in figure 20, coupling passage 400, trap channel 401, counter passage 402 is controlled the data transmission from they top adjacency channels to their its data registers separately.For control data transmission, the data transfer logic of a passage (as one among the 407-409), communicate with the data transfer logic of top adjacency channel, the data transfer logic of each passage can produce two kinds of output files to status bus 414, being called display channel and top adjacency channel all has a kind of output file of valid data and display channel and top adjacency channel that a kind of output file of invalid data is all arranged.In addition, trap channel 401 can be used to the input file from status bus 414, makes the data in its data register 404 invalid.

In one embodiment of the invention, pin control channel (PCC) (as 52 among Fig. 2) has a 32-bit data path, and through it, the top adjacency channel of PCC can pass PCC transmission data and give its bottom adjacency channel.The data transmission of passing PCC does not influence PCC.(be that PCC does not have Data Transmission Controlling and do not store data by it.)

Figure 21 and circuit shown in Figure 22 comprise control and status register memory circuit, and it is used to support the data transfer operation in the passage (as trap channel 401).Circuit shown in Figure 21 is used for the 16-bit data transfer operation, and circuit shown in Figure 22 is used for the 32-bit data transfer operation.The 32-bit data-transformation facility is used for the register bit position of data transfer operation, the signal of communicating by letter between adjacency channel, and the outgoing event that used incoming event and channel data transmission logic produce all will be in following description.Should note: control and status register memory circuit can be counted as virtual box, because they physically are positioned the part of one or more user-programmable register.Should note: zero clearing DVB incoming event signal only can be captured passage and use.

Coupling passage 400, trap channel 401, counter passage 402 all can be arranged to operate in data-transmission mode, perhaps as two 16 seat passages or as one 32 bit port fully independently.As shown in figure 21, trap channel 401 is configured to 16 bit data transmission operator scheme.As shown in figure 22, trap channel 400 is configured to 32 bit data transmission operator scheme.Coupling passage 400 sum counter passages 402 can be provided with in the same way.

With reference to Figure 21, should note: control the logical block functional similarity of each 16 seat passage but independently of one another.In one embodiment of the invention, two of a passage 16 seat passages needn't run on same operator scheme.For example: the high 16 seat passages of coupling passage 400 are set, mate 16 place values (as the timer bus 71 of Fig. 2) on the timer bus, low 16 seat passages are used for 16 Bit datas transmission operation.

With reference to Figure 21, high 16 the register-stored bit of control channel is by reset, and the register-stored bit that control channel is low 16 is by set (as DTC0 and DTC1).As Figure 22, when being set up, passage (as 401) carries out 32 Bit datas when transmission, and the register storage space of controlling high 16 seat passages is used to control 32 data transmission.

In one embodiment of the invention, support the passage of data transfer operation that three kinds of different register bit fields are arranged, be used for control data transmission and provide status information to CPU13.These three register-bit are respectively data significant bit (DVB), Data Transmission Controlling bit (DTC) and data transmission state bit (DTS).In one embodiment of the invention, trap channel sum counter passage also uses the incoming event edge to select position (IE) to come control event transmission operation.

With reference to Figure 21 and 22, each data effective bit (DVB) 425-426 is used as control and status bits by corresponding data transfer logic 422,429,430.As status bits, in the DVB indication corresponding data register effectively or the appearance of invalid data.As the control bit position, the corresponding data transfer logic of DVB quilt is used for controlling the data transmission from the top adjacency channel.

In one embodiment of the invention, the DVB position is a logical one, represents valid data to occur in this channel data register.For example, in trap channel 401, as long as capture operation one is finished, the DVB position just is changed to logical one.As Figure 20 and shown in Figure 22, when data successor data register 404 (as from top adjacency channel 400), it is logical one that the data transfer logic 430 of trap channel is just put the DVB position.

In addition, fashionable if the CPU13 (see figure 1) is write to any data register that is set as the data channel of data-transmission mode, the DVB position is put logical one automatically, shows that these data are effective.In one embodiment of the invention, when the coupling passage be in match pattern, write to its data register fashionable, the coupling passage the DVB position also put logical one.

In one embodiment of the invention, DVB position logical zero represents to occur in the channel data register invalid data.For example, in coupling passage 400, in case the coupling outgoing event takes place, the DVB position is clearly a logical zero.As Figure 20 and shown in Figure 22, import data register 405 (bottom adjacency channel) when data into from data register 404, the DVB position 425 in the transmission logic 409 zero clearing trap channel 401 is a logical zero.In case data are transmitted, the DVB bit 425 of passage 401 is cleared to logical zero, and video data is no longer valid.

In addition, CPU13 can be a logical zero by the corresponding DVB of zero clearing position 425, makes the data in the data register 404 invalid.For zero clearing DVB position 425, CPU13 must read DVB position 425 in the establishment attitude earlier, must write logical one to it then.DVB position 425 is invalid for the data in the logical one video data register 404.Should note: because the DVB position not only is a mode bit but also be control bit, CPU13 may cause that to the zero clearing action of DVB position valid data are covered by data transfer operation.

To one embodiment of the present of invention, Figure 23 lists the operation of energy set and zero clearing DVB position.Be included under the various operator schemes, to every kind of operation of supporting the passage of data transfer operation.With reference to Figure 20 and Figure 22, when passage 402 is set to data-transmission mode, the DVB position of top adjacency channel (the DVB position of passage 401) is logical one, and the DVB position of passage itself (as the DVB position of passage 402) when being logical zero data transmission takes place.The data transfer logic of passage (as the transmission logic of passage 402), adjacent channel data register 404 at first from the top, copies data is to the data register 405 of this passage.Then the DVB position (the DVB bit of passage 401) of top adjacency channel is cleared to logical zero.The DVB position of this passage is changed to logical one at last.

With reference to Figure 21 and Figure 22, Data Transmission Controlling (DTC) bit 423-424 is used to enable and forbids corresponding data transfer logic 422,429,430.When the data transfer logic of a passage is enabled, the content of the data register of top adjacency channel can be transferred to the data register of this passage.When the DVB position of a passage is a logical zero, and the DVB position of top adjacency channel is when being logical one, and data transmission begins.

Under following two kinds of patterns of data transfer operation, produce outgoing event.(1) if the DVB position of passage and its top adjacency channel is all logical one (showing that valid data all appear in two passages), begins to transmit data and cause an outgoing event.(this outgoing event is called as the efficient neighbor data to (VADP) outgoing event) (2) begin to transmit data and cause an outgoing event if the DVB bit of passage and its top adjacency channel is all logical zero (showing that invalid data all appears in two passages).(this outgoing event is called as invalid adjacent data to (IADP) outgoing event)

In one embodiment of the invention, the type of the purpose (outgoing event lead) of outgoing event and outgoing event under these two kinds of patterns (rise, descend, upset) all be can't help software control.These two kinds of outgoing events all directly link to each other with same status bus 414 (seeing Figure 21,22), and the two all causes a trigger event.

Figure 24 has described the data transfer operation pattern by the Data Transmission Controlling position (DTC) in the passage that can carry out data transfer operation (as Figure 21, the 423-424 in 22) control.

With reference to Figure 21,22, data output state position (DTS) 427-428 is used to indicate that an outgoing event is produced by respective data transfer logic 422,429,430.If DTC=%10, and VADP detects outgoing event and produced by the events corresponding transmission logic, and then the DTS position is changed to logical one.If DTC=%11, and IADP detects outgoing event and produced by the events corresponding transmission logic, and then the DTS position is changed to logical zero.For zero clearing DTS bit 427, CPU13 must read DTS position 427 in the establishment attitude earlier, writes logical one to it then.

Below discussion is used for realizing the control signal of data transfer operation.With reference to Figure 21,22, indicate the great amount of data transmission control signal among the figure, these signals are used for being arranged on (or from) the top adjacency channel of data transfer operation pattern and communicate by letter.Three kinds of approach of two passages contact: 32/16-BIT data line, reading signal lines, reset signal line.The data register (as the data register 404 of Figure 20 passage 401) that the 32/16-BIT data line is used for passage receives data from top adjacency channel (as the passage 400 of Figure 20).

Read signal is used for the data transfer logic of passage, with communicating by letter between the DVB position of top adjacency channel.The information that reads has two purposes.The first, when data transfer operation, be logical one if the DVB of passage itself is the DVB of logical zero and top adjacency channel, begin to transmit data so.The second, when being programmed, passage produces a VADP or an IADP outgoing event, and read signal is with determining whether existing an effective or invalid adjacent data right.

Reset signal is used to the top adjacency channel, at the data register of data from this top adjacency channel, reaches after the data register of passage itself, conditionally the DVB bit of zero clearing passage.

Should note: data transmission channel has three kinds of approach and the contact of bottom adjacency channel among Figure 22.They are already mentioned: data, read the write signal line.When designing integrated circuit, if allow data transmission channel (as the 400-402 of Figure 20) circuit be adjacent to each other, then data are read, and the wiring of write signal line can be pointed to another adjacent passage directly from a passage.In one embodiment of the invention, can allow each data transmission channel, the data transmission of control from adjacency channel to data register own.In optional embodiment of the present invention, use different states and control register bit, different data transfer control signals adopts different circuit to transmit the data (see figure 1) in I/O integrated circuit 22 between adjacency channel.

In one embodiment of the invention, all data transmission channels all produce two types outgoing event: efficient neighbor data are to outgoing event (VADP), an invalid adjacent data outgoing event (IADP).In addition, in some embodiments of the invention, what run on data-transmission mode captures the sum counter passage, can utilize an incoming event zero clearing to capture or the DVB bit (seeing Figure 21,22) of counter passage itself.

With reference to Figure 21,22, in one embodiment of the invention, the efficient neighbor data are to (VADP), or invalid adjacent data is to export condition line 414 to and produce a trigger event to (IADP) outgoing event signal.VADP and IADP outgoing event can be used for showing a stack full or a FIFO (First Input First Output) sky by the CPU13 (see figure 1).Pin control channel (PCC) is monitored condition line 414 (as the condition line of pin/control bus 76), and it can be programmed, and the trigger event on condition line causes interruption when being identified.

The incoming event logic of trap channel or counter passage can be programmed, and when carrying out data transfer operation, uses an incoming event, zero clearing corresponding D VB bit (seeing Figure 21, the zero clearing DVB incoming event signal 431 and 433 in 22).This is extremely useful to the data of forbidding a bottom data transmission channel in the fifo queue, and all data that are positioned at like this on the bottom data passage can be transmitted downwards along a passage.

In timer is used, three kinds of basic data transmission structure are arranged.First kind of data transmission structure is storehouse, and its preserves time base value and the counting operation value capture.The fifo queue of base value when second kind of data transmission structure is produces a series of coupling outgoing events with it.The third data transmission structure be preserve capture recently in a large number the time base value and most recent count operating value fifo queue.The present invention allows that user program is provided with these three kinds basic time base transmission structures, adjusts the operation of data transmission capabilities and one or more passages.

The counting operation controlling features

Many microcontrollers of using based on control need carry out the high-precision measurement that adds up to echo signal.For example: the counter passage 58 among Fig. 2 can carry out the high-precision measurement that adds up to echo signal.Echo signal can be provided by the outside and enter I/O (I/O) integrated circuit 22 (see figure 1)s, also can be provided by inside and send into I/O (I/O) integrated circuit 22.Counter passage 58 (see figure 2)s can be carried out multiple counting operation, and by the one or more user-programmable control register stored bits 67 to it, write prevalue and come the selection operation mode.

As shown in figure 26, as the operation of first selection able to programme, counter passage 58 can increase or reduce count value according to " height " and " low " decision of echo signal level.The second, counter passage 58 increases count value in the time of can arriving on effective edge of each echo signal.Be the rising edge or the negative edge of echo signal effectively along programmable.The 3rd, the counter passage can begin continuous counter when effectively the edge arrives first.The 4th, counter passage 58 reduces count value in the time of can arriving on effective edge of each echo signal.Optional embodiment of the present invention can be used other counting operation.

The second road signal that some control application needs are produced by second passage (as coupling passage 56, trap channel 55, other counter passage in the channel group 87), when decision carries out the counting operation of echo signal.In the prior art, if the counter passage in a time period to the echo signal operation that adds up, the second road signal reply echo signal is carried out gating, perhaps produces an interruption to the break in service processor.The break in service processor will respond interruption, and the gated counter passage is to the counting operation of echo signal.

Equally in the prior art, in order to stop the counting of counter passage to echo signal, the second road signal strain of echo signal gating is invalid, perhaps produces an interruption to the break in service processor.The break in service processor will respond interruption, end the counting operation of counter passage to echo signal.Unfortunately, adopt prior art to cause the mistake that adds up of counting operation often.

As shown in figure 25: in the prior art,, just introduced the mistake that adds up when ending the counting operation of counter passage with the second the tunnel to echo signal.Because it is invalid that the second road signal had become before the echo signal negative edge arrives, promptly the counter passage just stopped to have counted before the one-period of echo signal finishes.The periodic accumulation value that is stored in prior art counter passage like this can be lower than right value, and its difference is the wrong value that adds up just.Should note: Figure 25, the arrow indication counter passage 58 that makes progress in 26 does to increase the number operation, and downward arrow indication counter passage 58 is done the subtrahend operation.

With reference to Figure 25, in a time period, carry out periodic accumulation with prior art, as in " count window ", " count window " established by the count window signal and effectively to begin, be reversed to unavailability End.Usually by first counter passage to the echo signal event count, produce the count window signal by second passage.But first counter passage receiving target signal and receive window signal.As shown in figure 25, the establishment initial state of count window signal is " height " level, and effective edge of echo signal is a negative edge.

Carry out periodic accumulation with reference to employing prior art shown in Figure 25, establish beginning when the count window signal, first counter passage begins counting on effective edge that echo signal is right after, and constantly counts when the count window signal is effective.It is invalid that the count window signal that receives when first counter passage becomes, and first counter passage stops counting at once.Like this, if the count window signal does not become invalid (as shown in figure 25) on the cycle boundary of echo signal, will cause the mistake that adds up.

Yet, the present invention allow the counter passage receive the 3rd passage (in Fig. 2, the coupling passage 56, trap channel 55, other counter passage etc. in the channel group 87) the Third Road signal that provides perhaps is connected to the Third Road signal that the external source of I/O integrated circuit 22 (see figure 1)s provides.Be labeled as the Third Road signal of " count stop signal " among Figure 26, be counted device passage 58 and receive to decide when stop to receive operation.Should note: to any break in service that enables and not needing to forbid processor of counter passage 58.In addition, use the Third Road signal to end counting operation, allow counting operation to stop at the cycle boundary of echo signal, thereby avoided the mistake that adds up.

As the Third Road signal of count stop signal, provide in a time period approach of the accurate echo signal incident that adds up.Should note: in the prior art, have no idea the Third Road signal that provides by outside or other passage is provided, strengthen the termination counting operation.In addition, utilize the Third Road signal to provide not need the break in service response, the effective way of accumulated value that just can accurate one time period of measurement internal object signal.

Should note: in some embodiments of the invention, echo signal also can be used as count stop signal.With reference to Figure 25, the counting stop condition a certain edge type that is set to echo signal able to programme.For example: by the control register bank bit 67 to counter passage 58 (see figure 2)s, writing prevalue, to select count stop signal be the negative edge of echo signal.Be reversed to invalidly when the count window signal like this, and counting is when stopping incident and taking place (as the negative edge of echo signal), and counter passage 58 stops counting.Like this, counter passage 58 is after the count window signal is established beginning, and first negative edge of echo signal begins counting, and first negative edge that is reversed to invalid back echo signal at the count window signal stops counting.As a result, counter passage 58 is measured and has been preserved point-device periodic accumulation value, and the prior art method can't be by comparison.

The present invention allows to utilize the second the tunnel, and the Third Road signal is optimized the counting operation to echo signal: counting operation is by " count window " gating of the second tunnel signal definition, by the second the road or the second the road be used for limiting the second tunnel Third Road signal and end.In some cases, the edge of echo signal can be used as the Third Road signal.In one embodiment, some position of the control register bank bit 67 of counter passage 58 (see figure 2)s is used to determine whether usage count stop signal.And some is used for selecting to end the incident of counting operation, is Third Road signal (being called count stop signal among Figure 26) incident, still echo signal incident shown in Figure 25, or the count window signal event of prior art.In the prior art, the counter-rotating of count window signal always is used to end counting operation.

Figure 27 has provided an embodiment of counter passage 58 (see figure 2) parts.The counter passage comprises a counter circuit 440 and a data register 447.Data register and bus 24 (see figure 1)s directly are coupled.Counter circuit 440 comprises 441, one control circuits 442 of a counter, another control circuit 443.Control circuit 442 receives the receive window signal from circuit 448, from circuit 449 count pick up stop signals, from circuit 450 receiving target signals.Control circuit 442 provides count enable signal by circuit 444 to counter.Control circuit 443 provides the counter inhibit signal by circuit 445 to counter.Counter 441 is receiving target signal from the circuit 450 also.Counter 441 provides count value by circuit 446 to data register 447.

At counter 441, control circuit 442 transmits between the control circuit 443 by lead 451 for control and status information.For example, one in the

control circuit

442 and 443 is passed through lead 451, provides a data transfer control signal to counter 441.After the data transfer control signal that offers counter 441 was established, counter 441 was transferred to data register 447 with present count value by lead 446.Data register 447 can utilize read/write access to visit by bus 24.Counter 441 is accepted a timer signal by lead 452.

Control circuit

442 and 443 is given by lead 453 couplings in control register stored bits position 67.

Figure 28 has shown an embodiment (seeing Fig. 2 and Figure 27) of register 67 parts.Should notice that some register bit positions have different functions according to 58 lectotypes of counter passage.For example, when the count window pattern was invalid, the CZO/WTO/DTO bit was used as and count down to the zero output bit, when the count window pattern is effective, be used as window terminal output bit, when selecting data-transmission mode, be used as data transmission output bit.In one embodiment, control register bit shown in Figure 28 is carried out following function.16/8 and 24/32-16-bits; 8-24-,32-46900-32-01-8-24-1X-16-CCS：4700-1-DTC：4710X-10-w/VADP11-w/IADPCLK：472000-111-0-7SCC：/4730-1-CI：0000-0111-0-71000-1111-0-7CIEL：475CCS＝0X00-X01-X10-X11-CCS＝1000-001-010-011-100-101-110-111-USI/MTI/CDVI：//4760000-0111-0-71000-1111-0-7USIE/MTIE/CDVE：//47700-01-cnt/Xfer mod/Clr DVB10-cnt/Xfer mod/Clr DVB11-cnt/Xfer mod/Clr DVBCZO/WTO/DTO：//4780000-0111-0-71000-1111-0-7CZOEL/WTOEL/DTOE：//479CZOEL/WTOEL000-001-010-011-100-/101-/110-/111-/DTOEX00-X01-X10-X11-

Figure 29 illustrates an embodiment of control register 67 (seeing a Figure 27) part.In one embodiment, control register bit shown in Figure 29 is carried out following function.CM: counter mode bit 4800-subtracts count mode 1-and adds count mode CWE: count window enable bit position 48100-count window is operated invalid 01-and utilized selected state line to enable 1X-to be used to enable and should note from the input of the adjacent double-FIFO passage of low side (as available): if adjacent pair of FIF0 passage of a low side do not exist and select CWE=1X, then the window input is always low.WTOC: it is effective that window terminal output control bit position 48200-count down to zero output,

Window terminal is exported invalid 01-, and to count down to zero output invalid,

It is effective that window terminal output count down to zero output to the effective 10-of first counting operation in the window,

It is effective that window terminal output count down to zero output to the effective 11-of first counting operation in the window,

Window terminal is exported any effective OFC of counting operation in the window: overflow to stop at when control bit position 4830-overflows and continue to increase LCE when zero 1-overflows: logical complement enable bit position 4850-logical complement is exported invalid 1-logical complement and is exported effective CWI: count window input bit position 484000-111-state line 0-state line 7

An embodiment of Figure 30 display register 67 (seeing Figure 27) part.Should notice that in certain embodiments register 67 comprises control register bit and status register bit.In embodiment illustrated in fig. 30, the part of register 67 is used for storaging state information.In one embodiment, status register bit shown in Figure 30 is carried out following function.

WTS: window terminal status bits 490

Single counting operation in the 0-window, or first continuous counter operation is not terminated

Single counting operation in the 1-window, or first continuous counter operation is terminated

USIS/MTS/CDVS: add counting and stop input state/mould transmission state/zero clearing data effective status bit 491

0-stops counter/mould transmission/zero clearing data effectively not to be taken place

1-stops counter/mould transmission/zero clearing data effectively to be taken place

CZS/DTS: count down to zero condition/data transmission state bit 492

0-Inc/Dec does not take place to zero or VADP/IADP

1-Inc/Dec takes place to zero or VADP/IADP

DVB: data effective bit 493

Data are invalid in the 0-data register

Data are effective in the 1-data register

CIS: counting input state bit 494

0-adds/subtract the counting input not to be taken place

1-adds/subtract the counting input to be taken place

Counting operation in Figure 31 display counter 441 (seeing Figure 27), and the relation between some control register bits shown in Figure 28-29.With reference to Figure 31, when CCS=0 and CIEL=X01, after the count window signal was height, counter 441 increased along when input at each rising edge.Should note the count window signal become low after, counter 441 continues to increase.The count window signal become low after, after first count stop signal incident produced, counter 441 stopped.In this point, counting operation is finished, and the adding counting in the control register 67 stops the input state bit and is set, and count value is transferred to data register 447, and the DVB bit in the control register 67 is set.

When CCS=1 and CIEL=111, height when no matter when echo signal is high and count window signal, counter 441 utilize the selected timer of CLK bit field to import to add counting.In addition, the count window signal become low after, when first count stop signal incident produced, counter 441 stopped.As CCS=1 and CIEL=010, counter 441 is used to add counting from the timer signal of lead 452, when count window signal when being high, at first trailing edge of echo signal along the beginning counting operation.Equally, after the counter-rotating of count window signal, counter 441 stops when first count stop signal incident produces.

Figure 32 has shown an optional embodiment of the part of counter passage 58 (see figure 2)s.In this embodiment, counter passage 58 comprises 460, one event registers 461 of a counter register and outgoing event logic 467.In one embodiment, counter register 460 can be divided into two counter portion of energy independent operation.First counter portion response count device steering logic 462 and incoming event logic 464.Second counter portion response count device steering logic 463 and incoming event logic 465.In one embodiment, each counter portion also has a cover independently, as Figure 28 and control register bit shown in Figure 29.

Various control shown in Figure 32 and status bits, although but be positioned at the access read-write register, also influence the behavior of counter passage 58 shown in figure 32.Should note DTC register bit position 471, DVB register bit position 493 and DTS register bit position 492 with as among Figure 20-24 and described the same manner of subsidiary part of this explanation, are used for the interchannel data transmission.

Should note in one embodiment,, then not need count stop signal if when counter (as the counter among Figure 27 441) is a down counter.In some embodiment that used a down counter, a complete count value of zero can be used to refer to and should stop counting operation.For a down counter, a complete count value of zero can be carried out and a function that count stop signal is same that adds in the counter like this.Like this, after the counter-rotating of count window signal, when count value reached zero entirely for the first time, a down counter stopped counting.

Capture window feature

Base value during one of many control application requirements based on microcontroller, this time base value only at the rising edge of an echo signal, negative edge, or capture at both places.For example, based on the time that the edge of a selected echo signal produces, utilize trap channel 55 base value when timer bus 71 is captured among Fig. 2.Echo signal can from outside provide to I/O (I/O) integrated circuit 22 (see figure 1)s, or produce to give interior to I/O integrated circuit 22.Trap channel 55 can be carried out various capture operation, and this operation can be by writing in the trap channel 55 (seeing Fig. 2,5,35 and 36) in advance, and the controlling value of one or more user-programmable control register stored bits position 66 is selected.

One of many control application requirements are used for the time based on a target signal generating by the secondary signal that a second channel produces, base value and base value when when not capturing when stipulating when to capture one.For example, with reference to Fig. 2, this second channel that produces secondary signal can be a passage 54, and it can be a coupling passage, a counter passage, or the service aisle of another other type in the passage 57.Ideally, the time enabling of capturing of base value and forbid should not requiring directly service by a processor (as the CPU13 among Fig. 1), and base value should consistently with the frequency of echo signal have nothing to do when capturing.

Yet, in prior art control is used, require secondary signal to produce an interruption, require to introduce the Interrupt Service Routine that a processor (as the CPU13 among Fig. 1) is carried out, be used in trap channel, enabling capture operation.In addition,, require secondary signal to produce an interruption, require to introduce Interrupt Service Routine, be used in trap channel, forbidding capture operation in trap channel, forbidding capture operation.

In addition, the unanimity of base value when capturing for maintenance, the control of prior art is used and is generally required break in service to handle, and is used for before the triggering edge of next echo signal, and base value was transferred to a latch or storer when each was captured.When if the frequency of echo signal is enough high like this, Interrupt Service Routine always can be in the triggering of next echo signal before do not produce, and base value is transferred to a latch or storer in the time of will capturing, thereby loses the consistance of base value when capturing.

Figure 33 demonstrates a secondary signal, captures window signal for promptly so-called one, is how to be used for regulation base value when a timer bus is captured.As one first selection able to programme, incident last time that trap channel 55 can the based target signal (be triggered last time along) base value when capturing and storing.Trigger along programming and be chosen as the rising edge of echo signal, negative edge or any edge.The second, trap channel 55 is with " N-1 " other trap channel, base value when can capture and store " N ", each the time base value corresponding " N " last echo signal trigger the edge.The 3rd, trap channel 55 is with " N-1 " other trap channel, base value when can capture and store " N ", each the time base value corresponding " N " last echo signal positive edge.In addition, trap channel 55 is with " N-1 " other trap channel, base value when can capture and store " N ", each the time base value corresponding marginal edge of " N " last echo signal.The 4th, trap channel 55 is with " N-1 " other trap channel, base value when can capture and store " N ", each the time base value corresponding one " N " for the first time echo signal trigger the edge.In one embodiment of the invention, used two trap channel, then number " N " is 2." N " that use in this section represents a positive integer.Optional embodiment of the present invention can be used other capture operation.

As mentioned above, capture window feature and eliminated the needs that a processor (as the CPU13 among Fig. 1) service gets involved, and provide data relevant, and with the echo signal frequency-independent.Capture window feature and allow a trap channel directly to receive excitation (promptly capturing window signal), decide base when when capturing, when do not capture.Therefore, the break in service of a processor (as the CPU13 among Fig. 1) is greatly reduced, and the unanimity of base value when keeping capturing, and with the frequency-independent of echo signal.

Capture window feature allow a trap channel to the time the capturing of base value, stipulate that by the logic state of a secondary signal this signal is called one and captures window signal, capturing of base value can be enabled between the window phase that secondary signal defines in the time of like this.

Capture window enable register bit (CWE501 among Figure 35) for one and be used to enable to capture window feature.One is captured window is a period or time/angle " window ", wherein holds the line timebase capture operation.When capturing the window bit when being set, the time base at based target signal edge is captured by the state of a secondary signal and is stipulated, this signal is called captures window signal.The time base that belongs to echo signal is captured, and (logic level 1 among Figure 33-34) is allowed to when capturing the establishment of window signal state, and (logic level 0 among Figure 33-34) is under an embargo when the secondary signal state reverses.

Figure 34 shows and uses the example capture window feature and to use some register controlled bit of the register 66 that is positioned at trap channel 55 (see figure 2)s.In this example, capture window enable bit position (CWE501 among Figure 35) and be set, thereby enable to capture window feature.When trap channel 55 produces at each rising edge of echo signal, be trapped in the time base value on timer bus 71 (see figure 2)s.It should be noted that however trap channel 55 is also only being captured that window signal is established and during the generation of selected echo signal edge, is being trapped in the time base value on the timer bus 71.Therefore, capturing period that window signal is established has defined and has allowed " window " of capturing.When capturing window signal when counter-rotating, further base is captured and is under an embargo during echo signal.

Should note in the example shown in Figure 34, capture window signal, or adjacent double-FIFO passage (as being implemented) is provided for trap channel 55 from the bottom by pin/status bus 75.In one embodiment, a double-FIFO passage is a service aisle, can be used to store numerical value as a double-depth (two-deep) FIFO.For example, with reference to Figure 20, counter passage 402 can be replaced by a double-FIFO passage, is used for trap channel 401 as the adjacent double-FIFO passage in bottom like this.If CWE bit 501 base pin selections/status bus 75 as the source of capturing window signal, then utilize CWI bit 505, come in base pin selection/status bus lead 75 which to be used to provide and capture window signal to trap channel 55.If CWE bit 501 selects the adjacent double-FIFO passage in bottom as the source of capturing window signal, then CWI bit 505 is left in the basket.It should be noted that if the bottom adjacency channel is not a double-FIFO passage, and CWE bit 505 is programmed and selects the adjacent double-FIFO passage in bottom, then capture window and keep invalid.

Still with reference to example shown in Figure 34, utilize the CI bit 506 in the register 66 (seeing Figure 35), come in base pin selection/status bus lead 75 which to be used to provide and capture echo signal to trap channel 55.Utilize CIE bit 507 to come which edge of selective capture echo signal, so-called rising edge, negative edge, or arbitrary edge are used to trigger base value when timer bus 71 is captured.And, utilize CTB bit 503, come selective capture passage 55 base value when which timer bus 71 captures.

Figure 35 has shown an embodiment of the part of register 66 (seeing Fig. 2 and Figure 27).Should note being based upon trap channel 55 selected patterns, can there be a different function some register bit positions.For example, when capturing window scheme when being enabled, CI/CDVI bit 506 is as capturing the input bit position, when selecting data-transmission mode, as the effective input bit of zero clearing data position.In one embodiment, control register bit shown in Figure 35 is carried out following function.

16/32:16-bit or 32-bit function bit 500

The 0-32-bit

1-16-bit CWE:capture window enable bit position 50100-and capture the invalid 01-of window and utilize the selected condition line of CWI bit field to enable to capture window 1x-to utilize the input of the adjacent double-FIFO passage (if available) from the bottom to enable to capture window DTC:Data Transmission Controlling bit 5020x-data transmission is invalid; Capture effective 10-VADP11-IADPCTB: base 0-7SCC during base bit 503000-111 when capturing: single/as to capture continuously the single capture operation CWI of the continuous capture operation 1-of bit 5040-: as to capture window input bit position 505000-111 status bus 0-7CI/CDVI: as to capture the input/effective input bit of zero clearing data position 5060000-0111 pin bus 0-71000-1111 status bus 0-7CIE/CDVE: capture input edge/zero clearing data effective edge and input the arbitrary edge of invalid 01-rising edge 10-trailing edge 11-along bit 50700-

CO/DTO: capture output/data transmission output bit 508

000-111 condition line 07

COE/DTOE: capture output edge/data transmission output edge bit 509

00-output is invalid

The 01-rising edge

The 10-negative edge

The 11-upset

An embodiment of the part of Figure 36 display register 66 (see figure 2)s.Should notice that in certain embodiments register 66 comprises control register bit and status register bit.In embodiment shown in Figure 36, the part of register 66 is used for storaging state information.In one embodiment, status register bit shown in Figure 36 is carried out following function.

CES: capture edge status bits 510

0-detects a negative edge incoming event, produces relevant capture operation

1-detects a rising edge incoming event, produces relevant capture operation

CDVS: zero clearing data effective status bit 511

0-does not detect the regulation incoming event of DVB=1

1-detects the regulation incoming event of DVB=1

COS: capture output state bit 512

The 0-capture operation does not produce or COE bit field=00

The 1-capture operation produces and COE bit field=00

DTS: data transmission output state bit 512

0-does not detect the condition that meets VADP or IADP

1-detects the condition that meets VADP or IADP

DVB: data effective bit 513

Data in the 0-data register are invalid

Data in the 1-data register are effective

CIS: capture input state/zero clearing data effective status bit 514

0-does not produce one and captures

1-produces one and captures

Figure 37 shows an embodiment of the part of trap channel 55 (see figure 2)s.In this embodiment, trap channel 55 comprises a data register 520, captures logic 521, and data transfer logic 522 is single/as to capture logic 523 continuously, outgoing event logic 524, incoming event logic 525 and 16/32 bit logic 526.

Various control shown in Figure 37 and status bits, although but be positioned at the access read-write register, also influence the behavior of trap channel 55 as shown in figure 37.Should note DTC register bit position 502, DVB register bit position 513 and DTS register bit position 512 with as among Figure 20-24 and described the same manner of subsidiary part of this explanation, are used for the interchannel data transmission.

The feature of a single/continued operation timer passage

In an embodiment of I/O integrated circuit 22 (see figure 1)s, each service aisle all has a single operation pattern and a continuous transmission mode.In one embodiment of the invention, each counter passage (as counter passage 58), each trap channel (as trap channel 55) and each coupling passage (as coupling passage 57) all have a user-programmable register bit, allow with single pattern or continuous-mode operation passage.

For example, single/continuous counter operation (SCC) register bit position 473 (seeing Figure 28), decision counter passage 58 (see figure 2)s are in the single operation pattern or at continuous operation mode.Single/continuous capture operation (SCC) register bit position 504 (seeing Figure 35), decision trap channel 55 (see figure 2)s are in the single operation pattern or at continuous operation mode.And single/continuous matching operation (SCM) register bit position 531 (seeing Figure 38), decision coupling passage 57 (see figure 2)s are in the single operation pattern or at continuous operation mode.

When entering the single operation pattern, relevant timer functional status bit is (as counting input state (CIS) bit 494 among Figure 30, capture output state (COS) bit 512 among Figure 36, with matching status (MS) bit 534 among Figure 39) will be cleared, and the state and the control of timer function are provided.When service aisle is provided with for the single operation pattern, if relevant timer functional status bit is set, passage will be under an embargo, if relevant timer functional status bit is cleared, passage is enabled.

Unfortunately however, to a single operation pattern/continuous operation mode service aisle, still have three problems.First problem is to change from a continuous operation mode to the consistent of single operation pattern.Second problem is when the single operation pattern, prevents that the coupling passage from enabling unexpectedly again.The 3rd problem is in continuous operation mode, prevents the multiple output of mating the redundant match event of passage based on from one.

Solve in the following manner from the consistent problem of changing of a continuous operation mode to a single operation pattern.When (promptly " single hitting " mates in the single operation pattern, capture etc.) when carrying out the timer function, the status bits relevant with the timer function, (be the CIS bit 494 among Figure 30, COS bit 512 among Figure 36, with the MS bit 534 among Figure 39), show that the timer function is effectively or invalid.In one embodiment, if status bits is cleared, the timer function is enabled, if status bits is set, the timer function is under an embargo.The result is status bits " control " timer function operations.

When in a continuous operation mode (promptly " continuously " coupling is captured etc.) execution timer function, the same status bits relevant with the timer function shows whether one or more incidents (promptly coupling is captured etc.) produce.Status bits only provides operation information, and influences never in any form or control timer function.

When being transformed into the single operation pattern from continuous operation mode, the same status bits relevant with the timer function must be transformed into " state and control " function from carrying out " state " function.Be very similar to when service aisle be during at continuous operation mode, status bits will be set.When being transformed into the single operation pattern, if status bits keeps set, service aisle will be forbidden oneself immediately, and without timer function of executed.If it is invalid that service aisle becomes when entering the single operation pattern, possible passage will be lost " excitation ", thereby cause an inconsistent conversion from continuous to the single operation pattern.

The feasible relevant status bits of service aisle circuit, zero clearing oneself when entering the single operation pattern allows this status bits to carry out " state and control " function then.The service aisle circuit is all using same status bits continuously and in the single operation pattern, although the method for user mode bit is different according to pattern.In addition, when changing between two-mode, will can not lose the excitation of service aisle, the conversion between two-mode is consistent in this.

When the single operation pattern, prevent that the problem that a coupling passage enables unexpectedly again from solving in the following manner.When a coupling passage (as the coupling passage 57 among Fig. 2 and Figure 40) (only allows to produce true a comparison when being operated in the single operation pattern, forbid mating passage then), when relevant matches status bits (as the MS bit 534 among Figure 39) shows that a coupling does not produce (MS=%0), the coupling passage will be enabled.When the relevant matches status bits shows that a coupling produces (MS=%1), the coupling passage will be under an embargo.

In some cases, need zero clearing matching status bit and no longer enable to mate passage.The coupling channel circuit passes through only zero clearing matching status bit, prevents to mate passage and is enabled.In order to enable to mate passage again, the matching status bit must be cleared, and data register (as the data register among Figure 40 540) must be written into.The mode of a unanimity is provided like this, be used for CPU13 (see figure 1) control coupling passage and (promptly change the control register stored control value, change the data value and the counter-rotating matching status bit of storage in the match registers (as 540 among Figure 40)), and need not enable to mate passage again.This is a useful feature, allows CPU13 (see figure 1) zero clearing matching status bit, and need not enable matching feature again.

Prevent when the time, solve in the following manner based on the problem of the multiple output of redundant match event at continuous operation mode.At continuous operation mode,, may there be multiple ratio by base value when same when coupling passage base during (to be lower than half frequency increase of rate matched) when mating to one " slowly ".At that time base value equal in the data register value and when the middle maintenance of multiple ratio is identical, data register will be carried out one relatively the time each, establish one and really compare.

Need the time value in base value and the match registers when mating, only establish an output, and no matter produced how many " relatively true " signals.The coupling channel circuit only allows following true comparison signal to produce an output: (1) is from relatively first true comparison of back of vacation last time; (2) from match registers after its data register receives new data (promptly write by CPU13 or transmit from an adjacency channel), first really compares.When first true coupling produces, one continuously coupling is relevant is set (forbidding coupling), at base when identical, when last time, first true coupling of true relatively back produced, or when continuous mode (being SCM=%0 and MOD=%000) coupling is under an embargo, this relevant being cleared (enabling coupling).The result will not produce redundant coupling, and irrelevant with the coupling timebase frequency.

An embodiment of the part of register 65 (see figure 2)s shown in Figure 38.In one embodiment, control register bit shown in Figure 38 is carried out following function.

12/16/32:12/ half-word/word select selection of bit position 529

0x-32-bit (word)

The 10-12-bit

The 11-16-bit

MTB: base bit 530 during coupling

Base 0-7 during 000-111

SCM: single/continuous match bit position 531

The continuous matching operation of 0-

The single matching operation of 1-

MO: coupling output bit 532

0000-0111 pin bus 0-7

1000-1111 status bus 0-7

MOE: coupling output edge bit 533

000-exports and equates and relatively is under an embargo

001-exports a rising edge

010-exports a negative edge

011-exports a upset

100-condition and output set pin/state

101-conditioned disjunction output set pin/state

110-condition and output zero clearing pin/state

111-conditioned disjunction output zero clearing pin/state

An embodiment of the part of Figure 39 display register 65 (seeing Figure 27).Should notice that in certain embodiments register 65 comprises control register bit and status register bit.In embodiment shown in Figure 39, the part of register 65 is used to storaging state information.In one embodiment, status register bit shown in Figure 39 is carried out following function.

MS: matching status

0-does not produce a coupling

1-produces a match event

Figure 40 shows an embodiment of the part of coupling passage 57 (see figure 2)s.In this embodiment, coupling passage 57 comprises a data register 540, and

equality comparator logic

541,12/16/32 is selected logic 542, matching logic 543 and outgoing event logic 544.In one embodiment, data register 540 can be divided into two parts, is called a top and a lower part, and both can independent operation.In one embodiment, each compatible portion all has independently a cover as Figure 38 and control and status register bit shown in Figure 39, when the 12/16/32 selection bit 529 that only has a cover control to divide except.First compatible portion is used data register 540, equality comparator logic 541, the first of matching logic 543 and outgoing event logic 544; Second compatible portion is used data register 540, equality comparator logic 541, the second portion of matching logic 543 and outgoing event logic 544.

Various control shown in Figure 40 and status bits, although but be positioned at the access read-write register, also influence the behavior of mating passage 57 as shown in figure 40.Should notice that in embodiment shown in Figure 40 coupling passage 57 does not comprise register bit position and the circuit that is used to carry out data transmission between adjacency channel.Yet, with reference to Figure 40 and Figure 37, in optional embodiment of the present invention, coupling passage 57 can comprise data transfer logic and register bit position DTC, DVB, and DTS, be used for carrying out and trap channel 55 data transfer logics 522 and register bit position DTC471 the function that DVB493 and DTS492 are same.If realize, will with as among Figure 20-24 and described the same manner of subsidiary part of this explanation, produce from or go to a data transmission of mating passage.

Still with reference to Figure 40, coupling passage 57 is supported single and continuous matching operation.When with single or continuous matching operation operation, the value in the data register 540 with compare from one in eight values of timer bus 71.Outgoing event can be programmed to be produced and offer pin/status bus 76.The operation of an embodiment of coupling passage 57 now will be according to the operation purpose, and the control bit position of setting operation and the outgoing event that produces are described.

In single and continuous matching operation, coupling is created in valid data, and between the value (base value when any 32-bit or one 12/16 bit) from timer bus 71.The time base value by MTB register bit position 530 (seeing Figure 38) programming is selected.The time base value bit number by selecting bit 529 programmings to select to 12/16/32.For example, if select the 12-bit operating, the time low 12 bits of base value and data register 540 in low 12 bits of numerical value, will compare by equality comparator 541.

If the value that the MOE bit is not equal in %000 and the data register 540 is not equal to from the time base value on the timer bus 71, at this moment produce a coupling, MS bit 34 (seeing Figure 39) is set.Produce an outgoing event, and offer in pin/status bus lead 76 one.The kind of outgoing event is selected by MOE bit 533 (seeing Figure 38) is programmed.If the MOE bit equals %000, outgoing event logic 544 and equality comparator 541 are under an embargo.The purpose of outgoing event is selected by MO bit 532 (seeing Figure 38) is programmed.

Single/coupling (SCM) bit 531 (seeing Figure 38) is used between the software service of CPU13 (see figure 1) continuously, selects the coupling passage only to produce an outgoing event (being the single operation pattern), still produce more than an outgoing event (being continuous operation mode).

When single/continuously coupling (SCM) bit 531 (seeing Figure 38) is selected single matching operation when being %1.In single matching operation, when base value and the numerical value that is stored in data register 540 equate when from timer bus 71, on pin/status bus 76, produce an outgoing event, and establish single coupling related mechanism and prevent redundant coupling.Follow-up outgoing event only could produce after removing single coupling related mechanism.Need following two operations to remove single coupling related mechanism (can any order carry out this two operations): (1) matching status (MS) bit 534 (seeing Figure 39) are read at establishment state (i.e. logic level 1), and the quilt of the state (being logic level 0) after the counter-rotating is write back MS bit 534; (2) numerical value are written into data register 540.

Should notice that the CPU13 (see figure 1) is used to carry out the read/write access of single coupling related mechanism requirement.In addition, owing to following reason, need operation (2) to remove single coupling related mechanism.If exist to produce the multiple coupling passage of outgoing event, with the interrupt request on identical pin/status bus lead 76, operation (2) allows any coupling passage zero clearing MS bit 534, the state of zero clearing interrupt source like this and need not to enable again passage.

When single/continuously coupling (SCM) bit 531 (seeing Figure 38) is selected continuous matching operation when being %0.In continuous matching operation, when base value and the numerical value that is stored in data register 540 equate when from timer bus 71, on pin/status bus 76, produce an outgoing event, and establish continuously that the coupling related mechanism prevents redundant coupling.Follow-up outgoing event only could produce after removing continuous coupling related mechanism.Unequally relatively produce or after MOE bit 533 is cleared to %000, just removes continuously coupling and be correlated with at one.After first coupling produced, MS bit 534 was set, and did not produce follow-up coupling zero clearing MS bit 534 but be not required to be.

The present invention carries out diagram and description with reference to certain embodiments, and those skilled in the art will expect further revising and improving.Therefore should be appreciated that the present invention is not limited only to illustrated particular form, and as in additional claim as indicated in, the form behind the covering all modifications, they do not exceed the spirit and scope of the present invention.

Claims

1. a timer processor (22) is characterized in that:

One first timer bus (71);

One second timer bus (72);

Base is selected signal (50) when a plurality of;

First o'clock base passage (in 80) is used to produce first o'clock base value, described first o'clock base passage (in 80) be coupled to described when a plurality of base select signal (50);

Second o'clock base passage (in 81) is used to produce second o'clock base value, described second o'clock base passage (in 81) be coupled to described when a plurality of base select signal;

One first timer bus control channel (61), corresponding to described first o'clock base passage (in 80), be used to select described first and second o'clock base passages (80,81) in one, if with described first o'clock the base passage (in 80 one) selected, be used for driving the described first timer bus (71) with first o'clock base value, the described first timer bus control channel (61) is coupled to the described first timer bus (71) and described a plurality of time base is selected signal (50);

One second timer bus control channel (62), corresponding to described second o'clock base passage (in 81), if described second o'clock the base passage (in 81 one) selected, be used for driving the described first timer bus (71) with second o'clock base value, the described second timer bus control channel (in 81) be coupled to the described first timer bus (71) and described when a plurality of base select signal (50);

A pin/status bus is used to provide pin and status information;

A pin control channel (52) is used to be controlled at described pin/status bus, the transmission of pin and status information;

One first service aisle (57) is coupled to the described first timer bus (71), is used to receive first o'clock base value and is coupled to described pin/status bus be used to receive pin and status information; With

One second service aisle (56) is coupled to the described second timer bus (72), is used to receive the 3rd an o'clock base value and is coupled to described pin/status bus be used to receive pin and status information;

2. an integrated circuit timer (22) is characterized in that:

One first timer bus (71);

First o'clock base passage (in 80) is used to produce first o'clock base value;

Second o'clock base passage (in 81) is used to produce second o'clock base value;

One first timer bus control channel (61), corresponding to described first o'clock base passage (in 80), be used to select described first and second o'clock base passages (80,81) in one, if with described first o'clock the base passage (in 80 one) selected, be used for first o'clock base value drive the described first timer bus (71) and

One second timer bus control channel (62) corresponding to described second o'clock base passage (in 81), if described second o'clock base passage (in 81) is selected, is used for driving the described first timer bus (71) with second o'clock base value.

3. an integrated circuit timer (22) is characterized in that:

A plurality of data conductor (435);

One first timer passage (400) is characterized in that:

One first data storage circuitry (403) is used to store one first data value;

One second timer passage (404) is characterized in that:

One second data storage circuitry (404);

A transmission circuit (408) is used for control from described first data storage circuitry, to described second data storage circuitry, a transmission of first data value, first data value is by described a plurality of leads transmission;

The wherein said first and second timer passages (400,404) first in, execution relates to a timer function of first data value, with the wherein said first and second timer passages (400,404) in second, store first data value, and do not carry out any timer function that relates to first data value.

4. a timer processor (22) is characterized in that:

One first integrated circuit land (in 110 one);

One second integrated circuit land (in 111 one);

One first service aisle (101);

One second service aisle (102);

One the 3rd service aisle (103);

A first pin/status bus is characterized in that:

One first pin information lead (in 112 one); With

First pin/status information lead (in 113 one);

A second pin/status bus is characterized in that:

One second pin information lead (in 114 one); With

Second pin/status information lead (in 115 one); With

Control device (105,106,107), be used for by the described first pin information lead (112 one), information transmitted between described first service aisle (101) and the described first integrated circuit land (in 110 one) selectively, be used for by described first pin/status information lead (113 one), transmission information between described first service aisle (101) and the described second integrated circuit land (in 111 one) selectively, be used for by described first pin/status information lead (113 one), selectively at described first service aisle (101), and transmission information between described second service aisle (102), with be used for by described first and second pins/status information lead (113,115), selectively at described first service aisle (101), and transmission information between described second service aisle (103), described control device (105,106,107) be coupled to the described first and second integrated circuit lands (110,111), the described first and second and the 3rd service aisle (101,102,103) and described first and second pins/status bus.

5. an integrated circuit timer (22) is characterized in that:

A plurality of first service aisles (206);

One first local bus (218) is coupled to each described more than first service aisle (206);

A plurality of second service aisles (205);

One second local bus (217) is coupled to each described more than second service aisle (205); With

A global communication bus (200), selectively be coupled at least one described more than first service aisle (206), selectively be coupled at least one described more than second service aisle (205), described global communication bus (200), receive a timing signal and at least one to described more than second service aisle (205) of this timing signal is provided from described more than first service aisle at least one (206).

6. an integrated circuit timer (22) is characterized in that:

One first service aisle (160);

One second service aisle (161);

Set wire installation (157), be used for receiving one first set value from described first service aisle (160), be used for receiving one second set value from described second service aisle (161), with be used to provide a set value as a result, described set wire installation (157) is coupled to described first and second service aisles (160,161);

Zero clearing wire installation (158), be used for receiving one first clear value from described first service aisle (160), be used for receiving one second clear value from described second service aisle (161), with be used to provide a clear value as a result, described zero clearing wire installation (158) is coupled to described first and second service aisles (160,161);

Trigger wire installation (159), be used for receiving one first trigger value from described first service aisle (160), be used for receiving one second trigger value from described second service aisle (161), with be used to provide a trigger value as a result, described triggering wire installation (159) is coupled to described first and second service aisles (160,161);

Control device (64), be used for reception result set value, clear value and trigger value as a result as a result, described control device (64) is used to provide an output signal (168), output signal logic state can be by set value as a result like this, clear value as a result, trigger value is determined as a result, described control device (64) is coupled to described set lead (157), described zero clearing lead (158) and described triggering lead (159).

7. an integrated circuit timer (280) is characterized in that:

One first timer module (281), have one first o'clock the base bus (71, or 271) be used to transmit first o'clock base value;

One second timer module (282) has second o'clock base bus, is used to transmit second o'clock base value;

A clock lead (328), be used to transmit a clock signal, this clock signal is by a generation in described first and second counter modules (281,282), described clock module (328) is coupled to described first and second counter modules (281,282); With

A synchronous lead (329) is used to transmit a synchronizing signal, and this synchronizing signal is by an establishment in described first and second counter modules (281,282), and described synchronous lead is coupled to described first and second counter modules (281,282);

The wherein said first timer module (281) is characterised in that:

One first time base counter (320) is used to produce first o'clock base value, and described first time base counter (320) is increased or reduces by clock signal, and when synchronizing signal was established, described first time base counter (320) was loaded into a predetermined value; With

The wherein said second timer module (282) is characterised in that:

One second time base counter (320) is used to produce second o'clock base value, and described second time base counter (321) is increased or reduces by clock signal, and when synchronizing signal was established, described second time base counter (321) was loaded into a predetermined value.

8. an integrated circuit timer (22) is characterized in that:

One first timer passage (55);

One second timer passage (57);

Timer bus conductor device (71), be used for first o'clock base value of transmission in a period 1, transmit second o'clock base value with being used in a second round, described timer bus conductor device (71) is coupled to the described first and second timer passages (55,57); With

Sign wire installation (50), be used to transmit one first value of statistical indicant corresponding to first o'clock base value, with one second value of statistical indicant that is used to transmit corresponding to second o'clock base value, described sign wire installation (50) is coupled to the described first and second timer passages (55,57).