CN115954024B

CN115954024B - Decoder and decoding method thereof

Info

Publication number: CN115954024B
Application number: CN202310238658.5A
Authority: CN
Inventors: 王琳
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-03-14
Filing date: 2023-03-14
Publication date: 2023-06-02
Anticipated expiration: 2043-03-14
Also published as: CN115954024A

Abstract

The embodiment of the disclosure provides a decoder and a decoding method thereof. The decoding method is used for decoding to obtain an address of a target storage unit, wherein the address comprises a row indicator and a column indicator, and the decoding method comprises the following steps: receiving target data, wherein the target data is positioned at an Nth bit in a target data set; determining a row indicator and a column indicator of a target storage unit to which target data is to be written according to the number M of columns of the storage unit array and the number N of bits corresponding to the target data in the target data set; wherein N is any positive integer greater than or equal to 1, and M is any positive integer greater than 1. The decoding method provided by the embodiment of the disclosure can decode to obtain the row indicator and the column indicator of the memory cell to be written by any write data (i.e., target data) according to the number of columns M of the memory cell array and the number of bits N corresponding to the target data in the target data set.

Description

Decoder and decoding method thereof

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a decoder and a decoding method thereof.

Background

Writing data to the memory cell array requires determining an address to which the data is to be written, the address indicating which memory cell of the memory cell array the data is to be written. The address to which the data is to be written is decoded using a decoder to obtain a row indicator and a column indicator of the memory cell to which the data is to be written, i.e. to determine which memory cell of the memory cell array the data is to be written to, and subsequently the data can be written to the corresponding memory cell.

Therefore, there is a need for a decoding method that can decode the row indicator and the column indicator of the memory cell to which the data is to be written.

Disclosure of Invention

In view of this, the embodiments of the present disclosure provide a decoder and a decoding method thereof.

In order to achieve the above purpose, the technical scheme of the present disclosure is realized as follows:

in a first aspect, an embodiment of the present disclosure provides a decoding method for decoding an address of a target memory cell to which target data is to be written in a memory cell array, the address including a row indicator and a column indicator, the decoding method including:

receiving target data, wherein the target data is positioned at an Nth bit in a target data set;

determining the row indicator and the column indicator of a target storage unit to which the target data is to be written according to the number M of columns of the storage unit array and the number N of bits corresponding to the target data in the target data set; wherein N is any positive integer greater than or equal to 1, and M is any positive integer greater than 1.

In some embodiments, the determining the row indicator and the column indicator of the target memory cell to which the target data is to be written according to the number of columns M of the memory cell array and the number of bits N corresponding to the target data in the target data set includes:

Determining the corresponding bit number of the line head data of the line head storage unit of each line to be written into the storage unit array in the target data set according to the column number M of the storage unit array;

respectively carrying out subtraction operation on the bit number N corresponding to the target data in the target data set and the bit number corresponding to the line head data in the target data set, and obtaining a plurality of first parameters and second parameters according to the subtraction operation result;

sequentially carrying out logic operation on the first parameters corresponding to the adjacent rows to obtain a logic operation set;

and determining the row indicator of the target storage unit to which the target data is to be written according to the logic operation set.

In some embodiments, the determining a plurality of first parameters and second parameters from the result of the subtracting operation includes:

if the most significant bit in the subtraction operation generates a carry, determining that the first parameter is 1;

and if the most significant bit in the subtraction operation does not generate carry, determining that the first parameter is 0.

In some embodiments, the set of logical operations includes a valid operation value and an invalid operation value; the logic operation is sequentially performed on the first parameters corresponding to the adjacent rows to obtain a logic operation set, which comprises the following steps:

After carrying out logic operation on the first parameters corresponding to the 1 and the first row, sequentially carrying out logic operation on the first parameters corresponding to the adjacent rows until the effective operation value is obtained;

and obtaining a logic operation set according to the effective operation value and the ineffective operation value.

In some embodiments, said determining said row indicator of a target storage unit to which said target data is to be written according to said set of logical operations comprises:

and decoding according to the two first parameters corresponding to the effective operation value to obtain the row indicator of the target storage unit to which the target data is to be written.

In some embodiments, after obtaining the plurality of first parameters and the plurality of second parameters according to the result of the subtraction operation, the decoding method further includes:

determining a preset range according to the number M of columns of the memory cell array; wherein the preset range is greater than or equal to 0 and less than the column number M;

determining a target second parameter from the second parameters according to the second parameters and the preset range;

and decoding to obtain the column indicator of the target storage unit to which the target data is to be written according to the target second parameter.

determining a target second parameter from a plurality of second parameters according to the row indicator of the target storage unit;

In some embodiments, the total number of bits of the column indicator of the target memory cell is the same as the number of columns M of the memory cell array, and the column indicator corresponding to the column of column number C in the memory cell array comprises

0 and 1, wherein the columns of column number C correspond toThe column indicator of (2) is obtained by decoding the column sequence number C according to the target second parameter, wherein the C bit in the lowest bit to the highest bit is 1.

In a second aspect, embodiments of the present disclosure provide a decoder for decoding an address of a target memory cell to which target data is to be written in a memory cell array, the address including a row indicator and a column indicator, the decoder comprising:

the receiving module is used for receiving target data, and the target data is positioned at the Nth bit in the target data set;

A decoding module, configured to determine the row indicator and the column indicator of a target memory cell to which the target data is to be written according to a column number M of the memory cell array and a bit number N corresponding to the target data in the target data set; wherein N is any positive integer greater than or equal to 1, and M is any positive integer greater than 1.

In some embodiments, the decoder further comprises:

a preparation module, configured to determine, according to the number M of columns of the storage unit array, a number of bits corresponding to line header data of a line header storage unit of each line to be written into the storage unit array in the target data set;

the subtraction operation module is used for respectively carrying out subtraction operation on the bit number N corresponding to the target data in the target data set and the bit number corresponding to the line head data in the target data set, and obtaining a plurality of first parameters and second parameters according to the subtraction operation result;

the logic operation module is used for sequentially carrying out logic operation on the first parameters corresponding to the adjacent rows to obtain a logic operation set;

the decoding module comprises a row decoding submodule and a column decoding submodule, and the row decoding submodule is used for determining the row indicator of a target storage unit to which the target data is to be written according to the logic operation set.

In some embodiments, the subtracting module is specifically configured to determine that the first parameter is 1 if a carry is generated by a most significant bit in the subtracting module; and if the most significant bit in the subtraction operation does not generate carry, determining that the first parameter is 0.

In some embodiments, the set of logical operations includes a valid operation value and an invalid operation value; the logic operation module is specifically configured to perform logic operation on the first parameters corresponding to the 1 and the first row, and then sequentially perform logic operation on the first parameters corresponding to the adjacent rows until the effective operation value is obtained;

In some embodiments, the row decoding submodule is specifically configured to decode the row indicator of the target storage unit to which the target data is to be written according to the two first parameters corresponding to the valid operation value.

In some embodiments, the decoder further comprises: the combination logic module comprises a determining module and a screening module; the determining module is used for determining a preset range according to the number M of columns of the storage unit array; wherein the preset range is greater than or equal to 0 and less than the column number M;

The screening module is used for determining a target second parameter from the second parameters according to the second parameters and the preset range;

the column decoding submodule is specifically configured to decode, according to the target second parameter, the column indicator of the target storage unit to which the target data is to be written.

In some embodiments, the decoder further comprises:

the data selection module is used for determining a target second parameter from a plurality of second parameters according to the row indicator of the target storage unit;

The embodiment of the disclosure provides a decoder and a decoding method thereof. The decoding method is used for decoding to obtain an address of a target storage unit, wherein the address comprises a row indicator and a column indicator, and the target data is to be written into the storage unit array, and the decoding method comprises the following steps: receiving target data, wherein the target data is positioned at an Nth bit in a target data set; determining the row indicator and the column indicator of a target storage unit to which the target data is to be written according to the number M of columns of the storage unit array and the number N of bits corresponding to the target data in the target data set; wherein N is any positive integer greater than or equal to 1, and M is any positive integer greater than 1. For a memory cell array having any number of rows and any number of columns, a plurality of data in a target data set is sequentially written into the memory cell array, and the decoding method provided by the embodiment of the present disclosure may decode according to the number of columns of the memory cell array to obtain a row indicator and a column indicator of a memory cell to which any write data (i.e., target data) is to be written, so as to determine which memory cell the any write data is to be written into.

Drawings

Fig. 1 is a schematic flow chart of a decoding method according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of a target data set and memory cell array provided by an embodiment of the present disclosure;

FIG. 3 is a flow chart of decoding a row indicator provided by an embodiment of the present disclosure;

FIG. 4 is a flow chart of decoding a column indicator provided by an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a memory cell array according to one embodiment;

FIG. 6 is a schematic diagram of a decoded row indicator provided by a specific example;

FIG. 7 is a schematic diagram of a decoded column indicator provided by a specific example;

FIG. 8 is a schematic diagram of a decoder provided by an embodiment of the present disclosure;

the drawings include: 100. a decoder; 110. a receiving module; 120. a subtraction module; 130. a logic operation module; 140. a decoding module; 141. a row decode sub-module; 142. a column decode submodule; 150. a combinational logic module; 151. a determining module; 152. a screening module; 160. and a data selection module.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the embodiments of the present disclosure and the accompanying drawings, it being apparent that the described embodiments are only some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.

In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.

For a thorough understanding of the present disclosure, detailed steps and detailed structures will be presented in the following description in order to illustrate the technical aspects of the present disclosure. Preferred embodiments of the present disclosure are described in detail below, however, the present disclosure may have other implementations in addition to these detailed descriptions.

Referring to fig. 1, fig. 1 is a flow chart illustrating a decoding method according to an embodiment of the disclosure. As shown in fig. 1, an embodiment of the present disclosure provides a decoding method for decoding an address of a target memory cell to be written to a memory cell array by target data, the address including a row indicator and a column indicator, the decoding method including the steps of:

step S101: receiving target data, wherein the target data is positioned at an Nth bit in a target data set;

step S102: determining a row indicator and a column indicator of a target storage unit to which target data is to be written according to the number M of columns of the storage unit array and the number N of bits corresponding to the target data in the target data set; wherein N is any positive integer greater than or equal to 1, and M is any positive integer greater than 1.

Here, for a memory cell array having an arbitrary number of rows and an arbitrary number of columns, a plurality of data in a target data set needs to be sequentially written into the memory cell array, the decoding method provided in the embodiments of the present disclosure may decode, according to the number of columns of the memory cell array, an address of a memory cell to which arbitrary write data (i.e., target data) is to be written into the memory cell array, where the address includes a Row address and a Column address, where the Row address refers to a Row Indicator (Row Indicator), and the Column address refers to a Column Indicator (Column Indicator), so as to determine which memory cell to which arbitrary write data is to be written.

In the embodiment of the present disclosure, in step S101, target data is received, where the target data is located at an nth bit in the target data set.

Here, the target data refers to data to be written to a target memory cell within the memory cell array; the target data set refers to a set of all data to be written into the memory cell array; wherein any data within the target data set may be selected as target data. The target data set provided by the embodiment of the disclosure comprises a plurality of data, and the plurality of data in the target data set can be sequentially ordered, so that each data in the target data set corresponds to the number of bits (namely, the ordering number) one by one. Wherein the number of digits is a consecutive number (consecutive numbers), the consecutive number being a consecutive integer, the consecutive integer referring to the difference between any two adjacent digits being 1. For example, the target data set may include 5 data, with the number of bits of the 5 data within the target data set corresponding to 1, 2, 3, 4, and 5, respectively. For another example, the target data set may include 100 data, with the number of bits of the 100 data within the target data set corresponding to 1, 2, … …, 99, and 100, respectively.

The embodiments of the present disclosure are not particularly limited to specific data within the target data set.

It should be noted that, the number of bits N corresponding to the target data in the target data set may be represented by a binary number. For example, the number of bits N corresponding to the target data in the target data set may be 21, and the decimal number 21 may be represented as a binary number 010_101. For another example, the number of bits N corresponding to the target data in the target data set may be 42, and the decimal number 42 may be represented as a binary number 101_010. The embodiment of the present disclosure is not particularly limited in terms of the representation of the number of bits N corresponding to each data in the target data set. For example, the number of bits corresponding to each data in the target data set may be expressed as a decimal number or as a binary number. Of course, currently computers operate on binary numbers.

Here, the number of rows of the memory cell array may be any number of rows, and the number of columns of the memory cell array may be any number of columns. According to the decoding method provided by the embodiment of the disclosure, the row indicator and the column indicator of the target storage unit to be written in by the target data can be obtained by decoding according to the number M of columns of the storage unit array and the number N of bits corresponding to the target data in the target data set.

Referring to fig. 2, fig. 2 is a schematic diagram of a target data set and a memory cell array according to an embodiment of the present disclosure. As shown in fig. 2, the target data set includes data 1, data 2, … …, data

And data N, N total data. Wherein the plurality of data in the target data set may be sequentially ordered, and each data in the target data set may be in one-to-one correspondence with the number of bits. For example, data 1 is located at bit 1 in the target data set, and then the number of bits corresponding to data 1 in the target data set is 1. For another example, the data N is located at the nth bit in the target data set, and then the number of bits corresponding to the data N in the target data set is N.

The memory cell array provided by the embodiment of the disclosure has any number of rows and any number of columns. For example, the number of columns of the memory cell array illustrated in fig. 2 is 12. And sequentially writing a plurality of data in the target data set into the memory cell array, wherein the data 1 is to be written into the 1 st row and 1 st column memory cells of the memory cell array, and the data 2 is to be written into the 1 st row and 2 nd column memory cells of the memory cell array until the data 12 is to be written into the 1 st row and 12 th column memory cells of the memory cell array. Thus, after each data to be written into the 1 st row of the memory cell array in the target data set is determined, each data to be written into the 2 nd row of the memory cell array in the target data set is determined until the addresses of all data to be written into the memory cells of the memory cell array in the target data set are determined.

In the embodiment of the disclosure, a plurality of data in a target data set are sequentially written into a memory cell array, and if the number of columns of the memory cell array is M, then the 1 st bit to the M bit data in the target data set are sequentially written into each memory cell of the 1 st row of the memory cell array, and the (m+1) th bit to the 2 nd bit data in the target data set are sequentially written into each memory cell of the 2 nd row of the memory cell array until the writing of all data in the target data set is completed.

Fig. 2 illustrates a correspondence relationship between the number of bits of each data in the target data set and each memory cell after all of the plurality of data in the target data set are written into the memory cell array. The embodiments of the present disclosure do not limit the relationship between the number of bits of each data and the order of writing each data within the target data set. That is, the number of bits of each data in the target data set and the writing order of each data may be the same or different. The order of writing each data in the target data set into the memory cell array is not particularly limited in the embodiments of the present disclosure, as long as the address of the memory cell into which each data is to be written can be decoded. For example, the data is located at the 8 th bit in the target data set, the data may be the data written to the 8 th memory cell array in the target data set, and the data may be the data written to the 1 st memory cell array in the target data set.

In other words, in the embodiment of the present disclosure, after writing to a row of memory cells is completed, writing to a next row of memory cells may be performed; writing to a next row of memory cells after writing to a row of memory cells is completed; any target data may also be randomly selected and written to the target storage unit. For example,

data

8, 14, and 5 may be received sequentially, data 8 (i.e., bit number 8) may be written to the memory cells of row 1 and column 8 illustrated in fig. 2, data 14 (i.e., bit number 14) may be written to the memory cells of row 2 and column 2 illustrated in fig. 2, and data 5 (i.e., bit number 5) may be written to the memory cells of row 1 and column 5 illustrated in fig. 2.

Before each data in the target data set is written to the memory cell array, an address to which the data is to be written is determined, and the address is used to indicate which memory cell of the memory cell array the data is to be written to. For example, before writing data 3 into the memory cell array, the address of the memory cell to which data 3 is to be written needs to be determined, that is, the row indicator and the column indicator of the memory cell to which data 3 is to be written need to be determined.

In the embodiment of the disclosure, the memory cell Array may be an antifuse Array (Anti-fuse Array), and the number of bits of each data in the target data set may also be represented by a binary number, where any data in the target data set (i.e., the target data) is written into the antifuse Array, where it is necessary to determine in advance the address of the memory cell into which the data is to be written, and blow the corresponding antifuse cell, so as to store the data into the corresponding antifuse cell.

In the embodiment of the present disclosure, in step S102, a row indicator and a column indicator of a target memory cell to which target data is to be written are determined according to a column number M of the memory cell array and a bit number N corresponding to the target data in the target data set; wherein N is any positive integer greater than or equal to 1, and M is any positive integer greater than 1.

Here, the decoding method provided by the embodiment of the present disclosure may be applied to a memory cell array having an arbitrary number of rows and an arbitrary number of columns. For example, the number of columns M of the memory cell array may be input as a test parameter of the decoding method. In other words, regardless of the number of rows and the number of columns of the memory cell array, once the number of columns of the memory cell array is determined, the row indicator and the column indicator of the target memory cell in the target data set to which any data (i.e., target data) is to be written, that is, the address of the target memory cell in the target data set to which any data is to be written, can be determined based on the number of columns M of the memory cell array and the number of bits N of the target data in the target data set.

N is any positive integer greater than or equal to 1. Specifically, the minimum value of N is 1, which indicates that the target data is located at bit 1 in the target data set at this time; the maximum value of N is the same as the total amount of data included in the target data set, indicating that the target data is located at the last 1 bit in the target data set at this time. The number of columns M of the memory cell array is any positive integer greater than 1, and the number of columns M of the memory cell array is greater than or equal to 2, because the column indicator of the target memory cell is unique and determined during writing of the target data into the target memory cell of the memory cell array in the case that the number of columns M of the memory cell array is 1, and the column indicator of the target memory cell is not determined by using the decoding method.

In some embodiments, determining the row indicator and the column indicator of the target memory cell to which the target data is to be written according to the number of columns M of the memory cell array and the number of bits N corresponding to the target data in the target data set includes:

Respectively carrying out subtraction operation on bit numbers N corresponding to target data in a target data set and bit numbers corresponding to line head data in the target data set, and obtaining a plurality of first parameters and second parameters according to the subtraction operation result;

sequentially carrying out logic operation on first parameters corresponding to adjacent rows to obtain a logic operation set;

according to the set of logical operations, a row indicator of a target memory cell to which target data is to be written is determined.

In the embodiment of the disclosure, a plurality of data in a target data set are sequentially written into a memory cell array, and if the number of columns of the memory cell array is M, a number of bits corresponding to the first data of the first memory cell of each row to be written into the memory cell array in the target data set can be determined according to the number of columns of the memory cell array M. For example, data having a bit number of 1 in the target data is written into the head-of-line memory cell of the 1 st row of the memory cell array, data having a bit number of (m+1) in the target data is written into the head-of-line memory cell of the 2 nd row of the memory cell array, and the bit number in the target data is

The data of the kth row of the memory cell array is written into the head of line memory cell of the kth row of the memory cell array.

It should be noted that, for a plurality of data in the target data set sequentially written into the memory cell arrayAnd writing a plurality of data of the storage units of each row of the storage unit array, wherein the bit number corresponding to the head data of the head storage unit in the target data set is minimum. In other words, as the row number of the memory cell array increases, the number of bits corresponding to the head of row data in the target data set also increases. For example, the head of line data of the kth line corresponds to a greater number of bits in the target dataset than the kth line

The line head data of the line corresponds to the number of bits in the target data set.

In the embodiment of the disclosure, one data is arbitrarily selected from a plurality of data in a target data set as target data, a bit number N corresponding to the target data in the target data set is subtracted from a bit number corresponding to line head data of each line of the memory cell array in the target data set, and a plurality of first parameters and second parameters are obtained according to the result of the subtraction.

Referring to fig. 3, fig. 3 is a schematic flow chart of decoding the row indicator according to an embodiment of the disclosure. As shown in fig. 3, the bit number corresponding to the target data in the target data set and the line head data of each line of the memory cell array are input to the subtraction module 120 for subtraction, and a plurality of first parameters and second parameters are obtained according to the result of the subtraction.

Specifically, the bit number corresponding to the target data in the target data set and the bit number corresponding to the line head data of the 1 st line of the memory cell array in the target data set are input into the subtraction operation module 120, and the first parameter carry1< N > and the second parameter sum1< N:0> are output; the bit number corresponding to the target data in the target data set and the bit number corresponding to the line head data of the 2 nd line of the storage unit array in the target data set are input into the subtraction operation module 120, and a first parameter carry2< N > and a second parameter sum2< N:0> are output; the number of bits corresponding to the target data in the target data set and the number of bits corresponding to the head data of the kth row of the memory cell array in the target data set are input into the subtraction module 120, and the first parameter carryk < N > and the second parameter sumk < N:0> are output.

Since the second parameter is derived from the result of the subtraction, the second parameter sumk < N:0> is actually the difference (remainders). The addition (Add) and the Subtraction (Subtraction) are complementary operations, and the Subtraction may be referred to as complementary addition (Complementary Add). The user may perform addition or subtraction. However, since the computer is provided with only an addition module, the computer can perform only addition, and thus the computer needs to convert subtraction operation into addition operation.

Here, the number of bits corresponding to the target data received at the input of the subtraction module in the target data set is denoted as X, the number of bits corresponding to the head of line data received at the input of the subtraction module in the target data set is denoted as Y, the subtraction module performs subtraction on X and Y, that is,

can be converted into the complement of X +.>

Is added to the complement of (c). In this way, the subtraction operation module can be used for subtracting X and Y into the complement sum of the subtraction operation module to X

And (3) performing addition operation by using the complement code. In binary operation, the complement and the original code are the same for positive numbers; for negative numbers, the complement is to invert the original code except the sign bit, and then add 1 to the least significant bit.

For convenience of explanation, the process of performing the subtraction using the complement in decimal will be discussed first, and the process of performing the subtraction using the complement in binary will be discussed later. Here, to

For example, the subtraction is performed using the complement.

First, assume that the digital bit width is 4 bits, the highest bit isThe sign bit, the original code and the complement of 28 are both represented as 0028,

the original code of (a) is indicated as 1022. The nature of the inverse is the number of poles in the bin minus the original number. The pole number is the maximum number that can be represented by the system, for example, the maximum number that can be represented by a 4-bit decimal system is 9999. That is to say + >

Is expressed as the complement of

。

Next to this, the process is carried out,

the complement subtraction of (2) can be converted into a complement equal to 28 plus +.>

Is added to the code of the complement of (c), 28 is still indicated as 0028, ">

The complement of->

I.e. ] a +>

The complement of (2) is 9978. Thus (I)>

The complement subtraction of (2) can be expressed as +.>

Namely +.>

. At this time, the most significant bit in the subtraction operation generates a carry, and the most significant bit carry is truncated because the digital bit width is 4 bits, resulting in the result of the subtraction operation being 0006.

Finally, use of complement in the binary discussionAnd (5) performing row subtraction operation. Assuming that the digital bit width is 6 bits, the most significant bit is the sign bit, the original and complement of 28 are both represented as 011_100,

the original code of (1) is denoted as 110_110, (-)>

The complement of (c) is denoted 101_010./>

The complement subtraction can be converted into 28 complements plus +.>

The complement of (1) is (011_100+101_010). At this time, the most significant bit in the subtraction generates a carry, and the most significant bit carry is truncated due to the 6 bits of digital bit width, resulting in the subtraction result of 000_110.

As can be seen from the above analysis, the subtraction module performs a subtraction operation on the bit number (i.e., X) corresponding to the target data in the target data set and the bit number (i.e., Y) corresponding to the line head data in the target data set, and when Y is less than or equal to X, the highest bit in the subtraction operation generates a carry; when Y is greater than X, the most significant bits of the subtraction result in no carry.

In some embodiments, deriving the plurality of first parameters and the second parameters from the result of the subtraction operation includes:

if the highest bit in the subtraction operation generates a carry, determining that the first parameter is 1;

if the most significant bit in the subtraction operation does not generate a carry, the first parameter is determined to be 0.

Here, the number of bits corresponding to the target data in the target data set is subtracted from the number of bits corresponding to the head of line data to be written into the head of line memory cell of each line of the memory cell array, and the first parameter is determined according to whether the highest bit in the subtraction generates a carry.

Specifically, for a row whose row sequence number is smaller than or equal to the row sequence number of the target storage unit, the number of bits corresponding to the row header data in the target data set is smaller than or equal to the number of bits corresponding to the target data in the target data set, and then the number of bits corresponding to the target data in the target data set and the number of bits corresponding to the row header data in the target data set are subtracted, the highest bit generates a carry, so that the first parameter is determined to be 1. For a row with a row sequence number greater than that of the target storage unit, the number of bits corresponding to the row head data in the target data set is greater than that of the target data in the target data set, and then the number of bits corresponding to the target data in the target data set and the number of bits corresponding to the row head data in the target data set are subtracted, so that the highest bit does not generate a carry, and the first parameter is determined to be 0.

The number of rows of the memory cell array is not particularly limited in the embodiments of the present disclosure. In an embodiment of the present disclosure, if the number of columns of the memory cell array is M, the total amount of data in the target data set can be written into the kth row of the memory cell array, where the total amount of data in the target data set is at least greater than or equal to

. Meanwhile, if the target data is to be written into the R-th row of the memory cell array (i.e., the row number of the target memory cell is R), where R is less than or equal to k. For the 1 st row to the R (i.e., the row serial number is less than or equal to the row serial number of the target memory cell) of the memory cell array, the number of bits corresponding to the first data of the 1 st row to the R in the target data set is less than or equal to the number of bits corresponding to the target data in the target data set, then the highest bit generates a carry in the subtraction operation of the number of bits corresponding to the target data in the target data set and the number of bits corresponding to the first data in the target data set, thereby determining ∈>

. For the (R+1) -th row to the kth row of the memory cell array (i.e. the row sequence number is greater than the row sequence number of the target memory cell), the corresponding bit number of the row head data of the (R+1) -th row in the target data set is greater than the corresponding bit number of the target data in the target data set, and then the target data is in the target In the subtraction of the bit number corresponding to the data set and the bit number corresponding to the line head data in the target data set, the highest bit will not generate carry, thereby determining +.>

。

For example, if the total amount of data in the target data set can be written to row 7 of the memory cell array, the target data is to be written to row 4 of the memory cell array. The target data is to be written into the 4 th row of the memory cell array (i.e. the row serial number of the target memory cell is 4), for the 1 st row to the 4 th row of the memory cell array (i.e. the row serial number is smaller than or equal to the row serial number of the target memory cell), the bit number corresponding to the first data of the 1 st row to the 4 th row in the target data set is smaller than or equal to the bit number corresponding to the target data in the target data set, then the subtraction operation is carried out on the bit number corresponding to the target data in the target data set and the bit number corresponding to the first data of the row in the target data set, the highest bit will generate a carry, thereby determining

. For the 5 th to 7 th rows of the memory cell array (i.e., the row sequence number is greater than the row sequence number of the target memory cell), the number of bits corresponding to the head data of the 5 th to 7 th rows in the target data set is greater than the number of bits corresponding to the target data in the target data set, then the number of bits corresponding to the target data in the target data set and the number of bits corresponding to the head data in the target data set are subtracted, the highest bit does not generate a carry, thereby determining- >

。

In the embodiment of the disclosure, logic operation is sequentially performed on the first parameters corresponding to the adjacent rows to obtain a logic operation set. Here, the logical operation may be a logical exclusive or operation, and the logical operation set may be a logical exclusive or operation set.

Here, referring to fig. 3, the first parameters corresponding to the adjacent rows are sequentially logically xored using the logical operation module 130, more specifically, using the logical exclusive-or operation module. Wherein the first parameter comprises 1 and 0. If the first parameters corresponding to the adjacent rows are 0 and 1 respectively, performing logical exclusive OR operation to obtain a result of 1; if the first parameters corresponding to the adjacent rows are all 0, the result after the logical exclusive OR operation is 0; if the first parameters corresponding to the adjacent rows are all 1, the result is 0 after the logical exclusive-or operation is performed.

In some embodiments, the set of logical operations includes a valid operation value and an invalid operation value; sequentially performing logic operation on first parameters corresponding to adjacent rows to obtain a logic operation set, wherein the logic operation set comprises:

after carrying out logic operation on the first parameters corresponding to the 1 and the first row, sequentially carrying out logic operation on the first parameters corresponding to the adjacent rows until an effective operation value is obtained;

and obtaining a logical operation set according to the valid operation value and the invalid operation value.

Here, the logical operation set includes a valid operation value and an invalid operation value, wherein the valid operation value may be 1 and the invalid operation value may be 0.

Here, the logic operation is performed on the first parameter corresponding to the row (i.e., the 1 st row) with the smallest number of bits corresponding to the first data in the target data set, and at this time, the logic operation value is obtained as the invalid operation value, so that the logic operation process continues, and the logic operation of the adjacent rows is sequentially performed from the row with the smallest number of bits corresponding to the first data in the target data set to the row with the largest number of bits corresponding to the first data in the target data set until the logic operation value is the valid operation value, so that the logic operation process ends. And logic operation is not required to be carried out on the bit number corresponding to the subsequent line head data in the target data set. In other words, the logical operation set includes only 1 valid operation value, and the other valid operation values. Therefore, the method is beneficial to reducing the times of logic operation and saving decoding time.

In an embodiment of the present disclosure, if the number of columns of the memory cell array is M, the total amount of data in the target data set can be written into the kth row of the memory cell array, where the total amount of data in the target data set is at least greater than or equal to

. The first parameters corresponding to

lines

1 and 1 are logically exclusive-ored, i.e. XOR (carry 1<N>1) a step of; performing a logical exclusive-or operation on the first parameter corresponding to line 1 and the first parameter corresponding to line 2, i.e. XOR (carry 2)<N>，carry1<N>) The method comprises the steps of carrying out a first treatment on the surface of the And sequentially carrying out logic operation on the first parameters corresponding to the adjacent rows until an effective operation value is obtained. If the first is

First parameter and +.>

The first parameters corresponding to the rows are logically exclusive-ored, i.e.,

for a valid operand, then the logical exclusive-or operation process ends. No longer need to follow-up->

The first parameters corresponding to the rows and the first parameters corresponding to the kth row are logically exclusive-ored, i.e.,

. At this time, the logical exclusive-or operation set includes +.>

The logical operand values, more specifically, the set of logical exclusive-or operations, comprises +.>

An invalid operand and 1 valid operand. In other words, the set of logical exclusive-or operations includes at least 2 logical operation values and at most k logical operation values.

In the embodiment of the disclosure, if the total amount of data in the target data set can be written to the kth row of the memory cell array, the target data is to be written to the (R) row of the memory cell array (i.e., the row number of the target memory cell is R), where R is less than or equal to k. Pair 1 and First parameter (carry 1) corresponding to line 1<N>=1) performing a logical exclusive-or operation, i.e. XOR (carry 1)<N>1) =0. For the first parameter (carry 1)<N>=1) performing a logical exclusive-or operation on the first parameter corresponding to line 2, if r=1, carry2<N>=0, then XOR (carry 2<N>，carry1<N>) =1, at which time a valid logical value is obtained, and the logical exclusive-or operation process ends. If it is

，carry2<N>=1, then XOR (carry 2<N>，carry1<N>) =0, and at this time, an invalid logical value is obtained, and the logical exclusive-or operation process proceeds.

For example, if the total amount of data in the target data set can be written to row 7 of the memory cell array, the target data is to be written to row 4 of the memory cell array. The logical operation result for the first parameter corresponding to 1 and 1 st line (i.e., carry1< N > =1) is 0, i.e., XOR (carry 1< N >, 1) =0. Similarly, XOR (carry 2< N >, carry1< N >) =0, XOR (carry 3< N >, carry2< N >) =0, XOR (carry 4< N >, carry3< N >) =0. The result of the logical operation on the first parameter corresponding to the 4 th line (i.e., carry4< N > =1) and the first parameter corresponding to the 5 th line (i.e., carry5< N > =0) is 1, i.e., XOR (carry 5< N >, carry4< N >) =1. At this time, a valid operation value is obtained, and the logical operation process ends. The set of logical operations includes 5 logical operation values, of which 4 invalid operation values (i.e., 0) and 1 valid operation value (i.e., 1).

In some embodiments, determining a row indicator of a target memory cell to which target data is to be written according to a set of logical operations includes:

and decoding to obtain the row indicator of the target storage unit to which the target data is to be written according to the two first parameters corresponding to the effective operation value.

Here, the set of logical operations may be a set of logical exclusive or operations. As shown in fig. 3, the row decoding submodule 141 decodes, according to the valid operation values in the logical exclusive or operation set, which two rows of the logical operation result of the first parameter corresponding to which row is 1, so as to determine which row of the memory cell array the target memory cell is located in, so that which row of the memory cell array the target data is to be written into can be decoded by the row decoding submodule.

FIG. 3 illustrates travel indicators

The total number of bits of the row indicator is the same as the number k of rows of the memory cell array. The row indicator corresponding to the row of the row number R in the memory cell array comprises +.>

0 and 1, wherein the row indicator corresponding to the row of the row sequence number R points from the lowest bit to the R-th bit in the highest bit as 1, and the other bits are all 0.

For example, if the number of rows of the memory cell array is 3, the target data is to be written into the 2 nd row of the memory cell array, then the total number of bits of the row indicator of the 2 nd row is 3, the row indicator includes 2 0 s and 1 s, and the 2 nd bit of the row indicator of the 2 nd row is 1 from the lowest bit to the 2 nd bit of the highest bit, that is, 010.

Referring to fig. 4, fig. 4 is a schematic flow chart of decoding a column indicator according to an embodiment of the disclosure. Two methods for decoding to obtain the column indicator will be described in detail with reference to fig. 4, in which, in the first method, a target second parameter is determined from a plurality of second parameters according to a preset range, so that the column indicator is determined according to the target second parameter; in a second method, a target second parameter is determined from a plurality of second parameters based on the row indicator, thereby determining the column indicator based on the target second parameter.

Referring to fig. 4 (a) and fig. 4 (c), in some embodiments, after obtaining the plurality of first parameters and the plurality of second parameters according to the result of the subtraction operation, the decoding method further includes:

determining a preset range according to the number M of columns of the memory cell array; wherein, the preset range is more than or equal to 0 and less than the number M of columns;

determining a target second parameter from the plurality of second parameters according to the plurality of second parameters and the preset range;

Here, the combinational logic (Combinational Logic) module 150 includes a determination module 151 and a screening module 152. The determination module 151 may determine the preset range according to the number M of columns of the memory cell array. For example, the number M of columns of the memory cell array is 21, then the preset range is greater than or equal to 0 and less than 21, the minimum value of the preset range is 0, and the maximum value of the preset range is 20. The screening module 152 may also be used to determine a target second parameter from a plurality of second parameters according to a preset range. In other words, the second parameter (i.e. the difference value) within the preset range is found by the filtering module 152, which is the target second parameter. The second parameter is obtained by subtracting the bit number corresponding to the target data in the target data set from the bit number corresponding to the head-of-line data to be written into the head-of-line memory cells of each line of the memory cell array. More specifically, the target second parameter is obtained by subtracting the number of bits corresponding to the target data in the target data set from the number of bits corresponding to the head of line data located in the same line as the target data in the target data set.

Here, the difference between the column in which the target storage unit to which the target data is to be written and the column in which the head-of-line storage unit of the head-of-line data located in the same line as the target data is located (i.e., the 1 st column) may be determined according to the target second parameter using the column decoding sub-module 142; based on the difference, a column indicator of the target memory location to which the target data is to be written can be decoded. For example, after the number of bits N corresponding to the target data in the target data set and the number of bits corresponding to the head data of the same row as the target data in the target data set are subtracted, the second target parameter of 6 is obtained, and at this time, the head data of the same row as the target data is located in column 1, and the target data is located in column 7.

Referring to fig. 4 (b) and fig. 4 (c), in other embodiments, after obtaining the plurality of first parameters and the plurality of second parameters according to the result of the subtraction operation, the decoding method further includes:

determining a target second parameter from the plurality of second parameters according to the row indicator of the target storage unit;

Here, a data selection Module (MUX) 160 may be used to determine a target second parameter among a plurality of second parameters according to a line indicator of a target memory cell, that is, to determine a second parameter (that is, a target second parameter) corresponding to line head data of the target memory cell located in the same line.

Here, the column indicator of the target memory location to which the target data is to be written may be decoded according to the target second parameter using the column decoding sub-module 142. Wherein the target second parameter refers to a difference between a column in which the target memory cell is located and a column (i.e., 1 st column) in which the head-of-line memory cell of head-of-line data that is located in the same row as the target data is located. For example, after the number of bits corresponding to the target data in the target data set and the number of bits corresponding to the head data of the same row as the target data in the target data set are subtracted, the second target parameter is 6, and at this time, the head data of the same row as the target data is located in column 1, and the target data is located in column 7.

In some embodiments, the total number of bits of the column indicator of the target memory cell is the same as the number M of columns of the memory cell array, and the column indicator corresponding to the column of the column number C in the memory cell array comprises

And 0 and 1, wherein the column indicator corresponding to the column of the column sequence number C is obtained by decoding the column sequence number C according to the target second parameter, wherein the C bit from the lowest bit to the highest bit is 1.

For the column decoding submodule, a binary code is input to the column decoding submodule, and the total bit number of the binary code is Z+1, and the binary code with Z+1 bits is shared

The seed combination, therefore, the column decode submodule output is identical to the +.>

Seed combination corresponding->

And output signals. According to->

Greater than or equal to the number M of columns of the memory cell array, i.e.)>

The minimum value of Z satisfying the inequality condition is determined. Wherein Z is any integer greater than or equal to 0. For example, the column number m=9 of the memory cell array, then z=3; for another example, the number of columns of the memory cell array m=16, then z=3.

Here, the total number of bits of the column indicator is the same as the number M of columns of the memory cell array. The column indicator corresponding to the column of the column number C in the memory cell array comprises

0 and 1, wherein the column indicator corresponding to the column of the column sequence number C points from the lowest bit to the C bit in the highest bit to be 1, and the other bits are 0; and the column sequence number C is obtained by decoding according to the target second parameter.

For example, if the number of columns of the memory cell array is 21, and the target data is to be written into the 7 th column of the memory cell array, the total number of bits of the column indicator is 21, the column indicator includes 20 0 s and 1 s, and the 7 th bit of the column indicator from the lowest bit to the highest bit is 1, that is,

。

With reference to fig. 5, 6 and 7, how to decode the row indicator and column indicator of the target memory cell to which the target data is to be written is described in detail.

As shown in fig. 5, the number M of columns of the memory cell array is 21. The 1 row of the memory cell array may store 21 data, the 2 rows of the memory cell array may store 42 data, and the 3 rows of the memory cell array may store 63 data. The target data set includes 50 data, the 50 data within the target data set being sequentially ordered, the number of bits of each data within the target data set being in

turn

1, 2, 3, … …, 49 and 50. The number of bits of each data within the target data may be represented using a binary number. Sequentially writing the 1 st to 21 st data in the target data set into the 1 st to 21 st columns of the 1 st row of the memory cell array; sequentially writing 22 nd to 42 nd data in the target data set into 1 st to 21 st columns of the 2 nd row of the memory cell array; and writing the 43 rd bit to the 50 th bit data in the target data set in sequence in the 1 st column to the 8 th column of the 3 rd row of the memory cell array.

The number of rows of the memory cell array is not particularly limited in the embodiment of the present disclosure, and only 3 rows of the memory cell array are illustrated in fig. 5. This is because the data in the target data set is written to the memory cell array in sequence, and the total amount of data in the target data set can be written only to row 3 of the memory cell array.

Here, one data is arbitrarily selected as target data in the target data set, for example, 28 th bit data in the target data set is selected as target data, the number of bits corresponding to the target data in the target data set is 28, or 011_100 th bit data in the target data set is selected as target data, and the number of bits corresponding to the target data in the target data set is 011_100. Therein, the decimal number 28 may be converted into a binary number 011_100. According to the decoding method provided by the embodiment of the disclosure, the row indicator and the column indicator of the target storage unit to which the target data is to be written can be decoded, and the address of the target storage unit to which the target data is to be written can be determined.

Still referring to fig. 5, according to the number of columns M of the memory cell array being 21, the number of bits corresponding to the head of line data of the head of line memory cell of each line to be written into the memory cell array in the target data set is determined in the target data set. The bit number corresponding to the head of line data to be written to the head of line memory cell of the 1 st row of the memory cell array in the target data set is 1 (i.e., binary number 000_001); the bit number corresponding to the head of line data to be written to the head of line memory cell of the 2 nd row of the memory cell array in the target data set is 22 (i.e., binary number 010_110); the head of line data to be written to the head of line memory cell of the 3 rd row of the memory cell array corresponds to a number of bits of 43 (i.e., binary number 101_011) in the target data set.

As shown in fig. 6, the bit number 011_100 corresponding to the target data in the target data set and the bit number 000_001 corresponding to the 1 st row of the memory cell array are input into the subtraction module 120, after subtraction, carry is generated according to the highest bit in the subtraction to obtain a first parameter carry1< N > =1, and according to the result of the subtraction, a second parameter sum1< n:0> =011_011 is obtained; inputting the bit number 011_100 corresponding to the target data in the target data set and the line head data of the 2 nd line of the memory cell array into a subtraction operation module 120, performing subtraction operation, generating a carry according to the highest bit in the subtraction operation to obtain a first parameter carry2< N > =1, and obtaining a second parameter sum2< N:0> =000_110 according to the result of the subtraction operation; the bit number 011_100 corresponding to the target data in the target data set and the line head data of the 3 rd line of the memory cell array are input into the subtraction operation module 120, after subtraction operation, no carry is generated according to the highest bit in the subtraction operation, a first parameter carry3< N > =0 is obtained, and according to the result of the subtraction operation, a second parameter sum3< N:0> =110_001 is obtained.

The subtraction procedure is described in detail below. Will be

The subtraction is scaled to (+)>

Complementary to) 28 is 011_100, < ->

The complement of (2) is 111_111, then (+)>

The complement of (2) in the arithmetic process, the most significant bit generates a carry to obtain a first parameter carry1<N>=1, and the result of the operation is 011_011, resulting in the second parameter sum1<N:0>011_011 (i.e., decimal number 27 converted to a binary number).

Will be

The subtraction is scaled to (+)>

Complementary to) 28 is 011_100, < ->

The complement of (2) is 101_010, then (/ -)>

The complement of) to generate a carry from the most significant bit during the operation to obtain a first parameter carry2<N>=1, and the result of the operation is 000_110, resulting in a second parameter sum2<N:0>=000_110 (i.e., decimal number 6 converted to a binary number).

Will be

The complement subtraction is scaled to (+)>

Complementary to) 28 is 011_100, < ->

The complement of (2) is 010_101, then (/ -)>

The complement of (2) in the operation process, the most significant bit does not generate carry, thereby obtaining a first parameter carry2<N>=1, and the result is 110_001, resulting in a second parameter sum2<N:0>=110_001 (i.e., decimal number

Complement converted to binary numbers).

Still referring to fig. 6, the first parameter corresponding to the 1 st row and 1 are logically xored with a logical operation module 130, more specifically, a logical exclusive-or operation module, XOR (carry 1< N >, 1) =xor (1, 1) =0; performing a logical exclusive-or operation on the first parameters corresponding to the 1 st and 2 nd rows, wherein XOR (carry 2< N >, carry1< N >) =xor (1, 1) =0; the first parameters corresponding to the 2 nd and 3 rd rows are logically exclusive-ored, XOR (carry 3< N >, carry2< N >) =xor (0, 1) =1. Thus, a set of logical exclusive-or operations is obtained as {0, 1}. According to the first parameters corresponding to the line head data with the effective operation values of the 3 rd line and the 2 nd line in the logical exclusive-or operation set, the 2 nd line of the memory cell array to be written with the target data is determined, so that the row decoding submodule 141 is utilized to decode to obtain the row indicator of the target memory cell to be written with the target data with the bit number of 011_100 corresponding to the target data set as 010.

The total number of bits of the row indicator is the same as the number k of rows of the memory cell array. In the case where the target memory cell is located in the R-th row, the lowest bit of the row indicator is directed to the highest bit of the row indicator, the R-th bit of the row indicator is 1 and the other bits of the row indicator are 0. As an example, in the case where the number of rows is 3, the total number of bits of the row indicator is 3; wherein, the row indicator of the 1 st row is 001, the row indicator of the 2 nd row is 010, and the row indicator of the 3 rd row is 100.

Referring to fig. 7 (a) and 7 (c), the combinational logic module 150 includes a determining module 151 and a filtering module 152, and determines a preset range of [0, 20 ] according to the number M of columns of the memory cell array being 21 by the determining module 151]I.e. [000_000, 010_100 ]]The method comprises the steps of carrying out a first treatment on the surface of the Based on a plurality of second parameters (including sum1 using the filtering module 152<N:0>、sum2<N:0>And sum3<N:0>) And a preset range, determining a second parameter sum2 within the preset range<N:0>=000_110 (i.e., decimal number 6) is the target second parameter; benefit (benefit)By the column decoding sub-module 142, according to the second parameter of the target, the difference between the number of bits corresponding to the target data in the target data set and the number of bits corresponding to the head-of-line data located in the same line as the target data in the target data set can be determined, so as to determine that the target memory cell to which the target data is to be written is located in the 7 th column, and the column indicator of the target memory cell is

。

Referring to fig. 7 (b) and 7 (c), a data selection module 160 is used to determine a target second parameter among a plurality of second parameters, that is, to determine a second parameter corresponding to line head data of a target memory cell located in the same line, that is, to determine a second parameter sum2 located within a preset range, based on a line indicator 010 of the target memory cell<N:0>=000_110 (i.e., decimal number 6) is the target second parameter; by using the column decoding sub-module 142, according to the second parameter of the target, the difference between the number of bits corresponding to the target data in the target data set and the number of bits corresponding to the head-of-line data located in the same line as the target data in the target data set can be determined, and further the target memory cell in which the target data is to be written is located in the 7 th column, and the column indicator of the target memory cell is

。

The number of columns M of the memory cell array is 21, and Z+1 to Z+1 are used

The column decoding submodule decodes a column indicator of the target memory cell, when z=3,/-and>

the need to decode the column indicators of the memory cell array cannot be satisfied; when z=4, _>

The need to decode the column indicator of the memory cell array can be satisfied. Thus, can To use 5 to->

The column decoding submodule decodes a column indicator of the memory cell array.

The total number of bits of the column indicator is the same as the number of columns M of the memory cell array. For example, in the case where the number of columns is M, the total number of bits of the column indicator is M. In addition, in the case of the column number C of the target memory cell, the most significant bit of the column indicator is pointed to by the least significant bit of the column indicator, the C-th bit of the column indicator is 1 and the other bits of the column indicator are 0. As an example, in the case where the number of columns is 21, the total number of bits of the column indicator is 21; wherein the column indicator of column 1 is

Column indicator of column 2 is +.>

Column indicator of column 21 is +.>

。

Here, for a memory cell array having an arbitrary number of rows and an arbitrary number of columns, a plurality of data in a target data set is sequentially written into the memory cell array, and the decoding method provided in the embodiments of the present disclosure may decode according to the number of columns of the memory cell array to obtain a row indicator and a column indicator of a memory cell to which arbitrary data (i.e., target data) is to be written, so as to determine a row address and a column address of the target memory cell to which arbitrary data is to be written.

Referring to fig. 8, fig. 8 is a schematic diagram of a decoder provided in an embodiment of the present disclosure. As shown in fig. 8, the embodiment of the present disclosure further provides a decoder 100, where the decoder 100 is configured to decode an address of a target memory cell in a memory cell array to which target data is to be written, the address including a row indicator and a column indicator, and the decoder 100 includes:

a receiving module 110, configured to receive target data, where the target data is located at an nth bit in the target data set;

a decoding module 140, configured to determine a row indicator and a column indicator of a target memory cell to which target data is to be written according to a column number M of the memory cell array and a bit number N corresponding to the target data in the target data set; wherein N is any positive integer greater than or equal to 1, and M is any positive integer greater than 1.

Here, the decoding module 140 may include a row decoding sub-module 141 and a column decoding sub-module 142; wherein the row decoding submodule 141 is used for decoding to obtain a row indicator of a target memory cell to which target data is to be written, and the column decoding submodule 142 is used for decoding to obtain a column indicator of the target memory cell to which the target data is to be written.

In the embodiment of the disclosure, for a memory cell array having any number of rows and any number of columns, a plurality of data in a target data set is to be written into the memory cell array in sequence, a receiving module is configured to receive target data, the target data is located at an nth bit in the target data set, and a decoding module is configured to decode to obtain a row indicator and a column indicator, i.e., a row address and a column address, of a target memory cell to which any write data (i.e., target data) is to be written according to a column number M of the memory cell array and a bit number N corresponding to the target data in the target data set.

In some embodiments, the decoder further comprises:

the preparation module is used for determining the corresponding bit number of the line head data of the line head storage unit of each line to be written into the storage unit array in the target data set according to the column number M of the storage unit array;

the row decoding module comprises a row decoding submodule and a column decoding submodule, and the row decoding submodule is used for determining a row indicator of a target storage unit to which target data is to be written according to a logic operation set.

In one particular example, the logical operation module may be a logical exclusive-or operation module.

In some embodiments, the subtracting module is specifically configured to determine the first parameter as 1 if the most significant bit in the subtracting generates a carry; if the most significant bit in the subtraction operation does not generate a carry, the first parameter is determined to be 0.

In some embodiments, the set of logical operations includes a valid operation value and an invalid operation value; the logic operation module is specifically configured to perform logic operation on the first parameters corresponding to the 1 and the first row, and then sequentially perform logic operation on the first parameters corresponding to the adjacent rows until an effective operation value is obtained;

In some embodiments, the row decoding submodule is specifically configured to decode to obtain a row indicator of a target storage unit to which the target data is to be written according to two first parameters corresponding to the valid operation value.

In some embodiments, the decoder further comprises: the combination logic module comprises a determining module and a screening module; the determining module is used for determining a preset range according to the number M of columns of the memory cell array; wherein, the preset range is more than or equal to 0 and less than the number M of columns;

the screening module is used for determining a target second parameter from the plurality of second parameters according to the plurality of second parameters and the preset range;

the column decoding submodule is specifically configured to decode, according to the second parameter of the target, a column indicator of a target storage unit to which the target data is to be written.

In some embodiments, the decoder further comprises:

the column decoding submodule is specifically configured to decode, according to the second parameter, a column indicator of a target storage unit to which target data is to be written.

It should be noted that, the description of the decoder is similar to the description of the decoding method embodiment, and has similar beneficial effects as the decoding method embodiment, so that a detailed description is omitted. For technical details not disclosed in the decoding method according to the embodiments of the present disclosure, please refer to the description of the decoder according to the embodiments of the present disclosure.

The embodiment of the disclosure also provides a storage device, including: the decoder.

In some embodiments, the memory device is a dynamic random access memory (Dynamic Random Access Memory, DRAM).

In some embodiments, the DRAM memory meets the second generation double data rate synchronous DRAM (Double Data Rate Synchronous Dynamic Random Access Memory, DDR 2) memory specifications.

In some embodiments, the memory of the DRAM complies with DDR3 memory specifications.

In some embodiments, the memory of the DRAM conforms to DDR4 memory specifications.

In some embodiments, the memory of the DRAM complies with DDR5 memory specifications.

In some embodiments, the DRAM memory meets the fourth generation low power double data rate synchronous DRAM (Low Power Double Data Rate SDRAM, LPDDR 4) memory specification.

In some embodiments, the memory of the DRAM complies with the LPDDR5 memory specification.

The embodiment of the disclosure also provides a storage system, including: the memory device and a controller coupled to the memory device.

In DDR antifuse arrays, there is a case where it is necessary to transfer target data within a target data set to any row and any column to indicate a particular location in the antifuse array, thereby blowing the corresponding antifuse cell. Since the number of rows and columns of the antifuse array depends on its density in the antifuse array, the density is different in different cases, and thus the number of rows and columns of the antifuse array may be different in different cases. Thus, there is a need for a generic method to implement a decoder that can decode arbitrary data to obtain row indicators and column indicators. For expansion, if a test pattern is added to the algorithm to control the complement number (complementary number), the memory matrix can be dynamically changed, with the number of rows and columns of the memory matrix being dynamic. The decoder and decoding method provided by the embodiments of the present disclosure may be applicable to different situations.

In the embodiment of the disclosure, the bit number corresponding to the target data in the target data set and the bit number corresponding to the line head data of each line in the target data set may be input to the subtraction module, so as to obtain a first parameter carryk < N > and a second parameter sumk < N:0>. Here, the number of bits of the line head data of each line corresponding to the target data set may also be referred to as a comparison number (compare data) or a complementary number. If a test mode is used, the value of the complementary number will also change, since the complementary number is related to the number of columns of the memory matrix, i.e. in the test mode the number of columns of the memory matrix changes, so will the number of bits corresponding to the head of line data of each row of the memory matrix in the target data set.

In the embodiment of the disclosure, a logic operation module may sequentially perform a logic exclusive-or operation on first parameters corresponding to adjacent rows to obtain a logic exclusive-or operation set; and decoding by utilizing a row decoding submodule to obtain a row indicator of a target storage unit to which target data is to be written. Here, too, the logic operation module and the row decoding submodule need to be controlled using a test mode.

In the embodiment of the disclosure, the second parameter (i.e., the target second parameter) within the preset range can be found by using the combinational logic module; alternatively, the data selection module may also be utilized to find, according to the line indicator, a second parameter (i.e., a target second parameter) corresponding to line head data of the same line as the target data from among the plurality of second parameters; and decoding by utilizing a column decoding submodule to obtain a column indicator of a target storage unit to which target data is to be written. The combinational logic module may include a determination module and a screening module. Here, it is also necessary to control the combinational logic module, the data selection module, and the column decoding submodule using a test mode.

If the test mode is used to dynamically change the value of the complement, it should also be used to control the corresponding other functional modules, which are combined together to complete the decoding function. Of course, the decoding method is the same as described above.

The embodiment of the disclosure provides a decoder and a decoding method thereof. The decoding method is used for decoding and obtaining the address of a target storage unit in a storage unit array to which target data is to be written, wherein the address comprises a row indicator and a column indicator, and the decoding method comprises the following steps: receiving target data, wherein the target data is positioned at an Nth bit in a target data set; determining the row indicator and the column indicator of a target storage unit to which the target data is to be written according to the number M of columns of the storage unit array and the number N of bits corresponding to the target data in the target data set; wherein N is any positive integer greater than or equal to 1, and M is any positive integer greater than 1. For a memory cell array having any number of rows and any number of columns, a plurality of data in a target data set is sequentially written into the memory cell array, and the decoding method provided by the embodiment of the present disclosure may decode according to the number of columns of the memory cell array to obtain a row indicator and a column indicator of a memory cell to which any write data (i.e., target data) is to be written, so as to determine which memory cell the any write data is to be written into.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

The foregoing description is only of the preferred embodiments of the present disclosure, and is not intended to limit the scope of the present disclosure, but rather, the equivalent structural changes made by the present disclosure and the accompanying drawings under the inventive concept of the present disclosure, or the direct/indirect application in other related technical fields are included in the scope of the present disclosure.

Claims

1. A decoding method for decoding an address of a target memory cell in an array of memory cells to which target data is to be written, the address including a row indicator and a column indicator, the decoding method comprising:

determining the row indicator and the column indicator of the target memory cell to which the target data is to be written according to the number of columns M of the memory cell array and the number of bits N corresponding to the target data in the target data set, including:

respectively carrying out subtraction operation on the bit number N corresponding to the target data in the target data set and the bit number corresponding to the line head data in the target data set, and obtaining a plurality of first parameters and second parameters according to the subtraction operation result; the first parameter is obtained by determining whether a carry is generated by the highest bit in the subtraction operation or not; the second parameter is obtained by determining the difference value in the subtraction operation;

Determining the row indicator of the target storage unit to which the target data is to be written according to the first parameter; and determining the column indicator of the target storage unit to which the target data is to be written according to the second parameter; wherein N is any positive integer greater than or equal to 1, and M is any positive integer greater than 1.

2. The decoding method of claim 1, wherein the determining the row indicator of the target storage unit to which the target data is to be written according to the first parameter comprises:

3. The decoding method according to claim 2, wherein the obtaining a plurality of first parameters and second parameters from the result of the subtraction operation includes:

4. The decoding method of claim 3, wherein the set of logical operations includes a valid operation value and an invalid operation value; the logic operation is sequentially performed on the first parameters corresponding to the adjacent rows to obtain a logic operation set, which comprises the following steps:

5. The decoding method of claim 4, wherein the determining the row indicator of the target storage unit to which the target data is to be written according to the set of logical operations comprises:

6. The decoding method according to claim 1, wherein after obtaining a plurality of first parameters and second parameters from the result of the subtraction operation, the decoding method further comprises:

7. The decoding method according to claim 1, wherein after obtaining a plurality of first parameters and second parameters from the result of the subtraction operation, the decoding method further comprises:

8. The decoding method according to claim 6 or 7, wherein the total number of bits of the column indicator of the target memory cell is the same as the number of columns M of the memory cell array, the column indicator corresponding to the column of the column number C in the memory cell array includes (M-1) 0 s and 1 s, wherein the column indicator corresponding to the column of the column number C is decoded according to the target second parameter from the lowest bit to the C-th bit in the highest bit being 1.

9. A decoder for decoding an address of a target memory cell in an array of memory cells to which target data is to be written, the address comprising a row indicator and a column indicator, the decoder comprising:

a decoding module, configured to determine the row indicator and the column indicator of a target memory cell to which the target data is to be written according to a column number M of the memory cell array and a bit number N corresponding to the target data in the target data set;

the decoding module comprises a preparation module, a subtraction operation module, a row decoding sub-module and a column decoding sub-module; the preparation module is configured to determine, according to the number M of columns of the storage unit array, a number of bits corresponding to line head data of line head storage units of each line to be written into the storage unit array in the target data set;

the subtraction module is configured to perform subtraction on a bit number N corresponding to the target data in the target data set and a bit number corresponding to the line head data in the target data set, and obtain a plurality of first parameters and second parameters according to a result of the subtraction; the first parameter is obtained by determining whether a carry is generated by the highest bit in the subtraction operation or not; the second parameter is obtained by determining the difference value in the subtraction operation;

The row decoding submodule is used for determining the row indicator of a target storage unit to which the target data is to be written according to the first parameter; the column decoding submodule is used for determining the column indicator of a target storage unit to which the target data is to be written according to the second parameter; wherein N is any positive integer greater than or equal to 1, and M is any positive integer greater than 1.

10. The decoder of claim 9, wherein the row decoding submodule is specifically configured to sequentially perform a logic operation on the first parameters corresponding to adjacent rows to obtain a logic operation set;

11. The decoder according to claim 10, wherein the subtracting module is specifically configured to determine the first parameter as 1 if a most significant bit of the subtracting operation generates a carry; and if the most significant bit in the subtraction operation does not generate carry, determining that the first parameter is 0.

12. The decoder of claim 11, wherein the set of logical operations includes a valid operation value and an invalid operation value; the logic operation module is specifically configured to perform logic operation on the first parameters corresponding to the 1 and the first row, and then sequentially perform logic operation on the first parameters corresponding to the adjacent rows until the effective operation value is obtained;

13. The decoder according to claim 12, wherein the row decoding submodule is specifically configured to decode the row indicator of the target storage unit to which the target data is to be written according to two first parameters corresponding to the valid operation values.

14. The decoder according to claim 9, wherein the column decoding submodule is specifically configured to determine a preset range according to a column number M of the memory cell array; wherein the preset range is greater than or equal to 0 and less than the column number M;

15. The decoder according to claim 9, wherein the column decoding submodule is configured to determine a target second parameter from a plurality of the second parameters based on the row indicator of the target memory location;