CN115952755B - ATPG library model generation system of synchronizer standard unit - Google Patents
ATPG library model generation system of synchronizer standard unit Download PDFInfo
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Abstract
The invention relates to an ATPG library model generation system of a synchronizer standard unit, which is used for realizing the steps E1, acquiring the synchronizer standard unit to be processed and a fourth liberty file; step E2, extracting K s State table of (2); step E3, extracting K s Timing information of (a), third logic information, and a register sequence; e4, generating a third target ATPG library model with the same logic as the third logic information; step E5, setting each register unit RF u RF is to u Is connected to RF u+1 Connecting a third target ATPG library model to RF 1 Based on K s Corresponding timing information connects the clock signal to each RF u And (3) generating a target ATPG library model. The invention simplifies the generation process of the ATPG library model of the standard unit of the synchronizer and improves the generation efficiency of the ATPG library model of the standard unit of the synchronizer.
Description
Technical Field
The invention relates to the technical field of computers, in particular to an ATPG library model generation system of a synchronizer standard unit.
Background
Automatic test vector generation (Automatic Test Pattern Generation, ATPG for short) is a process in which test vectors used in semiconductor chip testing are automatically generated by a program. The test vectors are sequentially loaded onto the input ports of the device, and the output signals are collected and compared with the budgeted test vectors to determine the test results. ATPG effectiveness is an important indicator for measuring test error coverage. The foundation for realizing the ATPG is to construct an ATPG library model corresponding to the standard unit, and generate a chip based on the ATPG library model; and designing an ATPG model corresponding to the gate-level netlist, so that a test vector is automatically generated by an ATPG tool to test the chip.
The conventional ATPG library model is generated based on the Verilog model corresponding to the standard unit, and the Verilog model corresponding to the standard unit is developed for accurate simulation and verification and is not suitable for the purpose of ATPG. For example, to accurately describe the simulated behavior, the Verilog model corresponding to the standard cells of the IO pad type is very complex. For another example, standard cells of Integrated Clock Gating (ICG) are designed for clock gating, and the corresponding Verilog model is also very complex. However, ATPG only focuses on the logic behavior of the digital circuit, and generates an ATPG library model based on these complex Verilog models, so that the ATPG library model is complex to generate, and further, the ATPG model corresponding to the generated design gate level netlist is not simplified enough, and the test efficiency is reduced.
In addition, the prior art typically displays the design gate level netlist through a graphical user interface (Graphical User Interface, GUI for short) to debug the design gate level netlist and the ATPG process. In the prior art, standard cells in a design gate level netlist, connection relations among the standard cells, and input and output values generated by the standard cells based on an ATPG model are usually directly shown. However, some standard units occupy larger area, and can not directly display the composition details in the standard units, so that the readability is poor, if the composition detail information needs to be acquired, the corresponding standard units need to be clicked one by one to display the composition details, and the area occupied by the expanded standard units can be further increased, so that the debugging efficiency is low, and the user experience is poor.
Disclosure of Invention
The invention aims to provide an ATPG library model generation system of a synchronizer standard unit, which simplifies the generation process of the ATPG library model of the synchronizer standard unit and improves the generation efficiency of the ATPG library model of the synchronizer standard unit.
The invention provides an ATPG library model generation system of a synchronizer standard unit, comprising a pre-constructed ATPG basic cell library { A } 1 ，A 2 ，…A M A memory storing a computer program and a processor,A m the M-th ATPG basic unit in the ATPG basic unit library has the value range of M from 1 to M, wherein M is the total number of the ATPG basic units in the ATPG basic unit library, and when the processor executes the computer program, the following steps are realized:
step E1, obtaining a synchronizer standard unit set { K ] to be processed 1 ,K 2 ,…K S And fourth liberty file, K s The value range of S is 1 to S, S is the total number of the synchronizer standard units to be processed, K 1 ,K 2 ,…K S Belongs to the same standard cell library to be processed;
step E2, extracting each K from the fourth liberty file s Corresponding state table, K s The corresponding state table comprises a plurality of second state records, wherein the second state records comprise L(s) input fields and T(s) output fields, and the L(s) input fields comprise a second enabling input field, a selection signal field and L(s) -2 data input fields; the second enabling input field is used for storing a first edge trigger state and a second edge trigger state, the selection signal field, other L(s) -2 data input fields and T(s) output fields are used for storing corresponding level states, and the level states comprise a first level state and a second level state; when the second enable input field is in the first edge trigger state, T(s) output fields are determined based on the logical relationship of the selection signal field and the L(s) -2 data input fields; when the second enabling input field is in a second edge triggering state, the T(s) output fields keep the current state unchanged; the j-th output field corresponds to K s Output state of jth register, K s Includes T(s) registers;
step E3, slave K s Extracting K from the corresponding state table s Corresponding timing information, third logic information, and a register sequence (RE) having T(s) registers arranged in connection order 1 ，RE 2 ，…RE T(s) ),RE u For K s The value range of u is 1 to T(s);
step E4, from { A ] 1 ，A 2 ，…A M At least one A is selected from } m Combination of generation and K s A third target ATPG library model corresponding to the third logic information and having the same logic;
step E5, setting K s Each RE of (2) u Corresponding register unit RF u Each RF u Including an active signal port, a data input port and an output port, to be RF u Is connected to RF u+1 Connecting the third target ATPG library model to RF 1 Based on K s Corresponding timing information connects the clock signal to each RF u Is effective signal port of (1) to generate K s A corresponding target ATPG library model.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the ATPG library model generation system of the synchronizer standard unit provided by the invention can achieve quite technical progress and practicality, has wide industrial utilization value, and has at least the following advantages:
The system generates the ATPG library model aiming at the logic information based on the ATPG basic unit library by extracting the time sequence information, the logic information and the connection relation between the registers in the state table of the synchronizer standard unit, and then generates the ATPG library model of the synchronizer standard unit by combining the clock information and the connection relation between the registers, thereby simplifying the generation process of the ATPG library model of the synchronizer standard unit and improving the generation efficiency of the ATPG library model of the synchronizer standard unit.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention, as well as the preferred embodiments thereof, together with the following detailed description of the invention, given by way of illustration only, together with the accompanying drawings.
Drawings
FIG. 1 is a flowchart of generating an ATPG library model according to a first embodiment of the present invention;
fig. 2 is a flowchart of generating an ATPG library model of a combinational logic standard cell according to a second embodiment of the present invention;
fig. 3 is a schematic diagram of an ATPG library model generation flow of an integrated clock gating standard cell according to a third embodiment of the present invention;
FIG. 4 is a schematic diagram of a state representation of an integrated clock gating cell according to a third embodiment of the present application;
fig. 5 is a schematic diagram of an ATPG library model generation flow of a synchronizer standard unit according to a fourth embodiment of the present application;
FIG. 6 is a diagram showing the status of a standard cell of a synchronizer according to a fourth embodiment of the present application;
fig. 7 is a schematic diagram of generating a target display structure according to a fifth embodiment of the present application;
fig. 8 is a schematic diagram of converting a gate level netlist of a chip design to be tested into a display based on a target display structure according to a fifth embodiment of the present application.
Detailed Description
In order to further describe the technical means and effects adopted by the application to achieve the preset aim, the following detailed description refers to the specific implementation and effects of an ATPG library model generation system of a synchronizer standard unit according to the application with reference to the accompanying drawings and the preferred embodiment.
Aiming at the technical problems that the traditional ATPG library model is generated based on the Verilog model corresponding to the standard unit, the ATPG only focuses on the logic behavior of the digital circuit, and the ATPG library model is generated based on the complex Verilog models, so that the efficiency of generating the ATPG library model is low, the ATPG library model is complex, the ATPG model corresponding to the generated design gate level netlist is not simplified enough, and the testing efficiency is reduced.
Embodiment 1,
An embodiment one provides an ATPG library model generation system, which comprises a pre-constructed ATPG basic unit library { A 1 ，A 2 ，…A M Memory and processor storing computer programs, A m The M-th ATPG basic unit in the ATPG basic unit library has the value range of M from 1 to M, and M is in the ATPG basic unit libraryTotal number of ATPG basic units, A m ＝(A1 m ,A2 m ,A3 m ),A1 m Is A m Is composed of A2 m Is A m Logic information of A3 m Is A m Weight value of A m Weight value sum a of (2) m Inversely proportional to the cost of ATPG, the more easily handled the ATPG the higher the weight value of the base unit, when the processor executes the computer program, as shown in fig. 1, the following steps are implemented:
step S1, obtaining a standard cell library { B }, which is to be processed 1 ，B 2 ，…B N And the first liberty file, B n For the nth standard unit in the standard unit library to be processed, the value range of N is 1 to N, N>>M, each B is stored in the first liberty file n Corresponding logic information and timing information therein.
Step S1 is to obtain a standard cell library { B { to be processed from preset process design information 1 ，B 2 ，…B N And a first liberty file.
Standard cell libraries include plate libraries, symbol libraries, circuit logic libraries, and the like. The integrated circuit chip comprises combinational logic, sequential logic, functional units and special types of units, and is a basic part in the design process of the back end of the integrated circuit chip. The design efficiency can be greatly improved by utilizing the optimized library units designed in advance to perform automatic logic synthesis and layout and wiring. Typically each process manufacturer will provide a corresponding standard cell under each process. For example, a 7nm standard cell library provided by a process manufacturer, a 10nm standard cell library, and the like. Each standard cell library may include thousands of standard cells, some standard cells are very complex, for example, one 7nm standard cell library may include tens of thousands of standard cells, the gate netlist of the chip design to be tested is generated based on the standard cell library, and since ATPG cannot directly and effectively process the final gate netlist of the chip design to be tested, an ATPG library model of each standard cell needs to be abstracted to generate an ATPG model corresponding to the chip design to be tested. Each ATPG library model is based on an ATPG basic unit library { A } 1 ，A 2 ，…A M It is common to have the generation, i.e., so that thousands of standard cells in the same or different libraries of standard cells are all generated based on the same small number of ATPG basic cells. Preferably, N is on the order of 10 1 For example, 30 ATPG basic units may be provided.
The first liberty file is a file including standard unit time sequence information and logic information, and the first liberty file and the standard unit library can be directly obtained from preset process design information (Process Design Kit, abbreviated as PDK) and are not described herein.
Step S2, extracting B from the first liberty file n Corresponding logic information to be processed.
Wherein the first liberty file stores B n Corresponding Boolean function or truth table can directly convert B n The corresponding boolean function or truth table is used as the logic information to be processed, and the truth table can be converted into the boolean function to be used as the logic information to be processed.
Step S3, based on at least one A m Is formed by combining logical information and composition structure of (C) with B n And constructing a candidate ATPG library model set by using the corresponding candidate ATPG library models with the same logic of the logic information to be processed.
Step S4, based on A corresponding to each candidate ATPG library model m Selecting the candidate ATPG library model with the largest total weight from the candidate ATPG library model set as B n And a corresponding ATPG library model to be processed.
It should be noted that, based on the ATPG basic unit library, multiple AND B can be generated n The candidate ATPG library models with the same logic corresponding to the logic information to be processed are based on A corresponding to each candidate ATPG library model m The candidate ATPG library model with the largest total weight, i.e. the most favorable for the ATPG process, is selected from the weight values of (a) as the combinational logic standard unit.
Step S5, based on B n Corresponding to-be-processed ATPG library model and/or B n Corresponding time sequence information generates each B n A corresponding target ATPG library model.
It should be noted thatThe standard cell may be a combinational logic cell or a sequential logic cell, if B n Is a combinational logic standard cell, then directly B n The corresponding ATPG library model to be processed is determined as B n Corresponding target ATPG library model, if B n Is a sequential logic standard unit, B is also needed n Corresponding to-be-processed ATPG library model and B n Corresponding time sequence information is combined to generate B n A corresponding target ATPG library model.
The traditional ATPG library model generation method is based on Verilog generation of a standard unit, if test related information needs to be extracted, the information needs to be extracted from a first liberty file, and the information needs to be annotated into an ATPG model, the method is realized in two steps, and the method can extract B from the first liberty file only through one step n And corresponding logic information to be processed is simultaneously and directly extracted to test related information, so that the generation efficiency of the ATPG library model is further improved.
As an example, the test related information may specifically be scan chain related information, specifically, if B n Including a register having a scanning function, the step S2 further includes:
and S21, extracting scanning chain access information and scanning chain control information from the first liberty file.
The step S5 includes:
step S51, based on the scan chain linking information, linking the B n The data input end and the scanning enabling end of the corresponding target ATPG library model are marked into the corresponding ATPG library model and used for realizing the automatic insertion of the subsequent scanning chain.
More specifically, in order to efficiently support automatic insertion and generation of a test circuit, a register library unit with a scan function needs to be provided in a liberty file of a standard cell library, and related information is passed through a test_cell structure. The following is illustrated by one specific example:
in the above example, the register bank unit explicitly defines how this bank unit is accessed into the scan chain, in particular with pin 'SI' as data access into the scan chain and pin 'SE' as data input for controlling the scan chain. This information needs to be extracted from the first liberty file and then inserted into the ATPG library model to ensure that the tool on the back end that performs the scan chain can correctly identify and use these register library elements to correctly insert the scan chain required for the test in the circuit.
As one embodiment, the ATPG basic cell library comprises basic logic ATPG basic cells, combinational logic ATPG basic cells, basic sequential logic ATPG basic cells and ATPG basic cells for processing tri-state logic, pull-up resistor and pull-down resistor; the basic logic ATPG basic unit comprises a Buffer (Buffer), an Inverter (Inverter), an AND gate (AND), an OR gate (OR), a NAND gate (NAND) AND a NOR gate (NOR); the combinational logic ATPG basic unit comprises a multi-input and-nor gate (AOI), an exclusive-OR gate (XOR), an exclusive-OR gate (XNOR), a selector (MUX) and the like; the basic sequential logic ATPG basic unit comprises a Latch (Latch) and a register (Flip-flop). Based on the ATPG basic unit library, the ATPG library model can be simplified as much as possible for a given standard unit. That is, the ATPG library model is constructed by using as few ATPG basic units as possible, so that the correctness and the high efficiency of the result of the ATPG are ensured.
As an embodiment, each ATPG basic unit is generated based on Verilog language description, such as a 4-input nor gate:
and as a two-input MUX:
it will be appreciated that the above is only a list of some of the ATPG basic units and is not limited thereto.
The ATPG basic units are each generated based on the Verilog language description such that each B n The corresponding target ATPG library model is a model based on Verilog language. And the subsequent verification of the ATPG library model is facilitated. Specifically, the first liberty file further includes B n The corresponding Verilog model, after step S5, further includes:
step S6, B n Corresponding target ATPG library model and B n Inputting the corresponding Verilog model into a preset verification tool for verification, and if the verification is passed, B n The corresponding target ATPG library model is added into a preset target ATPG library model library.
It should be noted that, because the target ATPG library model is a model based on Verilog language, the target ATPG library model can be directly connected with B n The corresponding Verilog model is verified through a preset verification tool without other conversion, so that the test efficiency of the target ATPG library model is improved, and B n The corresponding Verilog model is also directly available from the preset process design information. The preset checking tool can be a standard form checking tool in industry.
The step S1-step S6 can generate an ATPG library model corresponding to each standard unit in the standard unit library to be processed, and on the basis, the ATPG model of the chip design to be tested can be generated based on the gate-level netlist of the chip design to be tested, and as an embodiment, the step S6 further comprises:
S7, obtaining a chip design gate-level netlist to be tested, wherein the chip design gate-level netlist to be tested is based on the standard cell library { B to be processed 1 ，B 2 ，…B N And (3) generating.
And S8, replacing each standard unit in the chip design gate netlist to be tested with a corresponding target ATPG library model in a preset target ATPG library model library to generate an ATPG model corresponding to the chip design gate netlist to be tested.
It should be noted that, after the ATPG model corresponding to the gate level netlist of the chip to be tested is generated, a test vector can be generated by an ATPG tool based on the ATPG model, and the chip to be tested is tested.
The ATPG base unit library is flexibly configurable according to specific application requirements, and as an embodiment, when the processor executes the computer program, the following steps are further implemented:
step S9, updating the ATPG basic unit library, wherein the updating comprises adding, deleting or modifying the ATPG basic unit.
And S10, obtaining a standard cell library corresponding to the updated ATPG basic cell, reconstructing the standard cell library to be processed, and re-obtaining a corresponding ATPG library model through steps S1-S5.
According to the system, logic information corresponding to standard units can be directly extracted from the liberty file, an ATPG library model corresponding to each standard unit is generated based on the logic information and a preset ATPG basic unit library, a Verilog model corresponding to the standard unit does not need to be concerned, the generation process of the ATPG library model is simplified, and the generation efficiency and quality of the ATPG library model are improved.
Embodiment II,
A second embodiment provides an ATPG library model generation system for combining logical standard cells, which comprises a pre-constructed ATPG basic cell library { a 1 ，A 2 ，…A M Memory and processor storing computer programs, A m The value range of M is 1 to M, M is the total number of ATPG basic units in the ATPG basic unit library, A m ＝(A1 m ,A2 m ,A3 m ),A1 m Is A m Is composed of A2 m Is A m Logic information of A3 m Is A m Weight value of A m Weight value sum a of (2) m Inversely proportional to the cost of ATPG, the easier it is for ATPG to be locatedThe higher the weight value of the base unit of the theory. When the processor executes the computer program, as shown in fig. 2, the following steps are implemented:
step C1, obtaining a to-be-processed combination logic standard unit set { D } 1 ，D 2 ，…D P And a second liberty file, D p The P-th to-be-processed combinational logic standard unit has the value range of P from 1 to P, wherein P is the total number of to-be-processed combinational logic standard units, and D 1 ，D 2 ，…D P Belongs to the same standard cell library to be processed, and each D is stored in the second liberty file p A corresponding boolean function or truth table.
Step C2, taking the total weight value of the ATPG library model as a logic optimization target and based on { A } 1 ，A 2 ，…A M Pair D p Logically optimizing a corresponding Boolean function or truth table to generate f (p) values of at least one A m Is formed by combining the composition structure of (C) with D p Logically identical set of candidate ATPG library models { E for logical information 1 p ,E 2 p ,…E f(p) p },E x p For the xth candidate ATPG library model, the value range of x is 1 to f (p), E x p Consists of g (xp) ATPG basic units.
It should be noted that, the truth table may be converted into a boolean function and then logically optimized. The logical synthesis algorithm is used to find the optimal ATPG library model. The ATPG algorithm is sensitive to the number of basic cells of the ATPG in the chip gate level netlist, and the goal of the optimization is typically to find an equivalent ATPG library model with the least basic library cells. However, it is understood that if other factors are required to be considered in the application scenario, other factors may be set in the application scenario, but the weight corresponding to the number of the basic library units is set to be the highest.
Step C3, obtaining each E x p Is a total weight value G of (2) x p ：
Wherein,and the weight value corresponding to the ith ATPG basic unit in the xth candidate ATPG library model.
Step C4, will { E ] 1 p ,E 2 p ,…E f(p) p E with the largest total weight value x p Is determined as D p A corresponding target ATPG library model.
It should be noted that, based on the ATPG basic unit library, multiple AND D may be generated p The candidate ATPG library models with the same logic corresponding to the logic information to be processed are based on A corresponding to each candidate ATPG library model m The weight value of (2) selects the candidate ATPG library model with the largest total weight, namely the candidate ATPG library model which is most beneficial to the ATPG process as D p A corresponding target ATPG library model.
As an embodiment, the step C1 includes:
and step C11, acquiring a standard cell library to be processed and a first liberty file from preset process design information, wherein logic information and time sequence information corresponding to each standard cell in the standard cell library to be processed are stored in the first liberty file.
The first liberty file is a file including standard unit timing information and logic information, and the first liberty file and the standard unit library can be directly obtained from preset process design information (Process Design Kit, abbreviated as PDK) and are not described herein.
Step C12, extracting a combined logic standard unit set { D { comprising only logic information from the standard unit library to be processed and the first liberty file 1 ，D 2 ，…D P And a second liberty file.
As one embodiment, the ATPG basic cell library comprises basic logic ATPG basic cells, combinational logic ATPG basic cells, basic sequential logic ATPG basic cells and ATPG basic cells for processing tri-state logic, pull-up resistor and pull-down resistor; the basic logic ATPG basic unit comprises a Buffer (Buffer), an Inverter (Inverter), an AND gate (AND), an OR gate (OR), a NAND gate (NAND) AND a NOR gate (NOR); the combinational logic ATPG basic unit includes a multi-input nor gate, an exclusive or gate (XOR), an exclusive nor gate (XNOR), and a selector (MUX); the basic sequential logic ATPG basic unit comprises a Latch (Latch) and a register (Flip-flop). Based on the ATPG basic unit library, the ATPG library model can be simplified as much as possible for a given standard unit. That is, the ATPG library model is constructed by using as few ATPG basic units as possible, so that the correctness and the high efficiency of the result of the ATPG are ensured.
As one embodiment, each ATPG basic unit is generated based on a Verilog language description, such that each B n The corresponding target ATPG library model is a model based on Verilog language. The verification of the ATPG library model is convenient to follow, and specifically, the second liberty file further comprises D p The corresponding Verilog model, after the step C4, further includes:
step C5, D p Corresponding target ATPG library model and D p Inputting the corresponding Verilog model into a preset verification tool for verification, and if the verification is passed, D p The corresponding target ATPG library model is added into a preset target ATPG library model library.
It should be noted that, because the target ATPG library model is a model based on Verilog language, the model can be directly combined with D p The corresponding Verilog model is verified through a preset verification tool without other conversion, so that the test efficiency of the target ATPG library model is improved, and D p The corresponding Verilog model is also directly available from the preset process design information. The preset checking tool can be a standard form checking tool in industry.
The above process is not only applicable to the combinational logic standard cell, but also applicable to the construction process of the target ATPG library model of the sequential logic standard cell after extracting the sequential information. As an embodiment, when the processor executes the computer program, the following steps are also implemented:
And step C10, acquiring a to-be-processed sequential logic standard unit set and a third liberty file, and extracting a state table corresponding to each sequential logic standard unit from the third liberty file.
And step C20, acquiring corresponding time sequence information and logic information from a state table corresponding to each time sequence logic standard unit to be processed, wherein the logic information is a truth table or a Boolean function.
And C30, generating a target ATPG library model corresponding to the logic information through steps C2-C4 based on the logic information corresponding to the to-be-processed sequential logic standard unit.
And step C40, combining the target ATPG library model corresponding to the logic information with the time sequence information to generate a target ATPG library model corresponding to each time sequence logic standard unit to be processed.
As an embodiment, the to-be-processed sequential logic standard unit is an integrated clock gating standard unit, and technical details for specifically constructing a target ATPG library model corresponding to the integrated clock gating standard unit are specifically described in the third embodiment, and are not described herein again.
As an embodiment, the to-be-processed sequential logic standard unit is a synchronizer standard unit, and technical details for specifically constructing a target ATPG library model corresponding to the synchronizer standard unit are specifically described in the fourth embodiment and are not described herein.
In the second embodiment, the system performs logic optimization on each combinational logic standard unit to obtain a candidate ATPG library model set of each combinational logic standard unit, and selects a target ATPG library model from the candidate ATPG library model set based on the corresponding weight value set of each standard unit, so that the generation process of the ATPG library model of the combinational logic standard unit is simplified, and the generation efficiency of the ATPG library model of the combinational logic standard unit is improved.
Third embodiment,
An ATPG library model generation system integrating clock gating (integrated clock gating, ICG) standard units comprises a pre-constructed ATPG basic unit library { A } 1 ，A 2 ，…A M Memory and processor storing computer programs, A m Is the mth ATPG basic unit, m in the ATPG basic unit libraryThe value range is 1 to M, and M is the total number of ATPG basic units in the ATPG basic unit library. When the processor executes the computer program, as shown in fig. 3, the following steps are implemented:
step D1, obtaining an integrated clock gating standard cell set { F }, which is to be processed 1 ，F 2 ，…F R And third liberty file, F r For the R-th integrated clock gating standard unit to be processed, the value range of R is 1 to R, R is the total number of the integrated clock gating standard units to be processed, F 1 ，F 2 ，…F R Belonging to the same standard cell library to be processed.
Step D2, extracting each F from the third liberty file r Corresponding state table F r The corresponding state table comprises a plurality of first state records, the first state records comprise h (r) input fields and an output field, the h (r) input fields comprise a first enabled input field and h (r) -1 data input fields, the first enabled input field is used for storing a first state or a second state, the h (r) -1 data input field and the output field are used for storing corresponding level states, the level states comprise a first level state and a second level state, when the first enabled input field is in the first state, the output field is determined based on the logic relation of the h (r) -1 data input field, and when the first enabled input field is in the second state, the output field keeps the current state unchanged.
Step D3, from F r Extracting F from the corresponding state table r Corresponding time sequence information and first logic information, and from F r The output of the medium acquisition state table is connected to F r F at the output end r Corresponding second logic information.
It should be noted that, the first logic information is more complex than the second logic information, and still taking the state table shown in fig. 4 as an example, the extracted first logic information is iq= (fe|te), and the second logic information is generally simpler, for example, may be gck=iq=ck, gck= l! Iq+ck or gck=iq|ck, GCK is the final output of the integrated clock gating standard cell.
Step D4, slave{A 1 ，A 2 ，…A M At least one A is selected from } m Combining the generation and F r A first target ATPG library model corresponding to the first logic information and having the same logic as F r A second target ATPG library model corresponding to the second logic information and having the same logic;
step D5, setting F r Corresponding memory cell, said F r The corresponding memory unit comprises an effective signal port, a data input port and an output port, and is based on F r Corresponding time sequence information connects a clock signal to the effective signal port, connects the first target ATPG library model to a data input port, connects the second target ATPG library model to an output port, and generates F r A corresponding target ATPG library model.
As an embodiment, the step D3 includes:
step D31, F r Deleting the record with the first enabling input field in the second state in the corresponding state table, deleting the column where the first enabling input field is located, and obtaining F r A corresponding truth table.
Step D32, based on F r And the corresponding truth table acquires the first logic information.
Wherein F can be specifically selected from r The corresponding truth table is converted into a Boolean function as the first logic information.
As an example, A m ＝(A1 m ,A2 m ,A3 m ),A1 m Is A m Is composed of A2 m Is A m Logic information of A3 m Is A m Weight value of A m Weight value sum a of (2) m Inversely proportional to the cost of ATPG, the D4 comprises:
step D41, taking the total weight value of the ATPG library model as a logic optimization target and based on { A } 1 ，A 2 ，…A M Pair F r Performing logic optimization on the corresponding first logic information to generate k (r) pieces of information consisting of at least one A m Is formed by combining the composition structure of (C) with F r Corresponding candidate ATPG library models with the same logic of the first logic information, and forming candidatesSelecting an ATPG library model set { Ey } 1 r ,Ey 2 r ,…Ey k(r) r },Ey z r For the z candidate ATPG library model, the value range of z is 1 to k (r), ey z r Consists of V (r) ATPG basic units.
It should be noted that the logic synthesis algorithm is used to find the optimal ATPG library model. The ATPG algorithm is sensitive to the number of basic cells of the ATPG in the chip gate level netlist, and the goal of the optimization is typically to find an equivalent ATPG library model with the least basic library cells. However, it is understood that if other factors are required to be considered in the application scenario, other factors may be set in the application scenario, but the weight corresponding to the number of the basic library units is set to be the highest.
Step D42, obtaining each Ey z r Is a total weight value G of (2) z r ：
Wherein,and in the r candidate ATPG library model, the weight value corresponding to the i ATPG basic unit is obtained.
Step D43, will { Ey } 1 r ,Ey 2 r ,…Ey k(r) r Ey with the largest total weight value in } z r Is determined as F r A corresponding first target ATPG library model.
It should be noted that, based on the ATPG basic unit library, multiple AND F can be generated r The candidate ATPG library models with the same logic of the logic information to be processed corresponding to the corresponding first logic information are based on A corresponding to each candidate ATPG library model m The weight value of (2) selects the candidate ATPG library model with the largest total weight, namely the candidate ATPG library model which is most beneficial to the ATPG process as F r A corresponding first target ATPG library model.
As an embodiment, the D4 includes:
step D41', from { A ] 1 ，A 2 ，…A M Acquisition and F r Corresponding second logic information is logically the same A m As the second target ATPG library model.
It should be noted that due to F r The corresponding second logic information is usually relatively simple and can therefore be derived directly from { A } 1 ，A 2 ，…A M Acquisition and F r Corresponding second logic information is logically the same A m As the second target ATPG library model, a screening step is not required to be performed.
As an embodiment, the step D1 includes:
step D11, acquiring a standard cell library to be processed and a first liberty file from preset process design information, wherein logic information and time sequence information corresponding to each standard cell in the standard cell library to be processed are stored in the first liberty file.
The first liberty file is a file including standard unit timing information and logic information, and the first liberty file and the standard unit library can be directly obtained from preset process design information (Process Design Kit, abbreviated as PDK) and are not described herein.
Step D12, traversing standard cells in a standard cell library to be processed, determining standard cells with at least any pin 'clock_gate_clock_pin' item set as 'true' as integrated clock gating standard cells to be processed, and generating the integrated clock gating standard cell set { F } 1 ，F 2 ，…F R And acquiring a third liberty file from the first liberty file.
It should be noted that "clock_gate_clock_pin" is an attribute item of a pin, and when "true" is set, the corresponding standard cell is described as an integrated clock gating standard cell.
As one embodiment, the ATPG basic cell library comprises basic logic ATPG basic cells, combinational logic ATPG basic cells, basic sequential logic ATPG basic cells and ATPG basic cells for processing tri-state logic, pull-up resistor and pull-down resistor; the basic logic ATPG basic unit comprises a Buffer (Buffer), an Inverter (Inverter), an AND gate (AND), an OR gate (OR), a NAND gate (NAND) AND a NOR gate (NOR); the combinational logic ATPG basic unit includes a multi-input nor gate, an exclusive or gate (XOR), an exclusive nor gate (XNOR), and a selector (MUX); the basic sequential logic ATPG basic unit comprises a Latch (Latch) and a register (Flip-flop). Based on the ATPG basic unit library, the ATPG library model can be simplified as much as possible for a given standard unit. That is, the ATPG library model is constructed by using as few ATPG basic units as possible, so that the correctness and the high efficiency of the result of the ATPG are ensured.
As one embodiment, each ATPG basic unit is generated based on a Verilog language description, such that each B n The corresponding target ATPG library model is a model based on Verilog language. The verification of the ATPG library model is convenient to follow, and specifically, the second liberty file further comprises D p The corresponding Verilog model, after the step D5, further includes:
step D6, F r Corresponding target ATPG library model and F r Inputting the corresponding Verilog model into a preset verification tool for verification, and if the verification is passed, F r The corresponding target ATPG library model is added into a preset target ATPG library model library.
It should be noted that, because the target ATPG library model is a model based on Verilog language, the target ATPG library model can be directly matched with F r The corresponding Verilog model is verified through a preset verification tool without other conversion, so that the test efficiency of the target ATPG library model is improved, and F r The corresponding Verilog model is also directly available from the preset process design information. The preset checking tool can be a standard form checking tool in industry.
As an example, if F r Integrated clock-gating standard cell for latch formation, then F r The first state and the second state in the corresponding state table are the first level state or the second level state, and the storage unit corresponding to the step D5 is a latch.
Specifically, the first level state is a high level state, the second level state is a low level state, or the first level state is a low level state, and the second level state is a high level state.
As an embodiment, if the second electrical state is a high state, in the step D5, further includes: an inverter is inserted at the active signal port of the memory cell.
The state table of an integrated clock gating standard cell is shown in fig. 4, wherein "CK" is an enable input field, "FE" is a first data input field, "TE" is a second data input field, and "IQ" is an output field. "L" indicates a first state and a first level state, specifically, a low level. H represents a second state and a second level state, specifically a high level. "N" means that it remains unchanged and "-" means that the corresponding field is ignored, i.e., any state will not have an effect on the result.
As an example, if F r Integrated clock-gating standard cell for register formation, then F r The corresponding first state and second state are a first edge trigger state and a second edge trigger state.
Specifically, the first edge triggering state is a rising edge, the second edge triggering state is a falling edge, or the first edge triggering state is a falling edge, and the second edge triggering state is a rising edge.
As an embodiment, if the second electrical state is a rising edge, in the step D5, the method further includes: an inverter is inserted at the active signal port of the memory cell.
In the third embodiment, the system generates the ATPG library model for the logic information based on the ATPG basic unit library by extracting the time sequence information and the logic information in the state table of the integrated clock gating standard unit, and then generates the ATPG library model of the integrated clock gating standard unit by combining the clock information, thereby simplifying the generation process of the ATPG library model of the integrated clock gating standard unit and improving the generation efficiency of the ATPG library model of the integrated clock gating standard unit.
Fourth embodiment,
ExamplesFourth, an ATPG library model generation system of synchronizer standard unit is provided, which comprises a pre-constructed ATPG basic unit library { A } 1 ，A 2 ，…A M Memory and processor storing computer programs, A m And M is the M-th ATPG basic unit in the ATPG basic unit library, the value range of M is 1 to M, and M is the total number of the ATPG basic units in the ATPG basic unit library, and when the processor executes the computer program. As shown in fig. 5, the following steps are implemented:
step E1, obtaining a synchronizer standard unit set { K ] to be processed 1 ,K 2 ,…K S And fourth liberty file, K s The value range of S is 1 to S, S is the total number of the synchronizer standard units to be processed, K 1 ,K 2 ,…K S Belonging to the same standard cell library to be processed.
Step E2, extracting each K from the fourth liberty file s Corresponding state table, K s The corresponding state table comprises a plurality of second state records, wherein the second state records comprise L(s) input fields and T(s) output fields, and the L(s) input fields comprise a second enabling input field, a selection signal field and L(s) -2 data input fields; the second enabling input field is used for storing a first edge trigger state and a second edge trigger state, the selection signal field, other L(s) -2 data input fields and T(s) output fields are used for storing corresponding level states, and the level states comprise a first level state and a second level state; when the second enable input field is in the first edge trigger state, T(s) output fields are determined based on the logical relationship of the selection signal field and the L(s) -2 data input fields; when the second enabling input field is in a second edge triggering state, the T(s) output fields keep the current state unchanged; the j-th output field corresponds to K s Output state of jth register, K s Including T(s) registers.
As shown in the state table of one synchronizer standard cell in fig. 6, in this example, there are two registers, and the corresponding output fields are "IQ1" and "IQ2", respectively; "CLK" represents the second enable input field, "se" represents the select signal field, "d" represents the first data input field of the synchronizer standard cell, and "si" represents the second data input field of the synchronizer standard cell. "R" represents a first state, "-R" represents a second state, "L" represents a first level state, specifically a low level, and "H" represents a second level state, specifically a high level. "N" means remaining unchanged, "H/L" means either the first level state or the second level state, and "-" means that the corresponding field is ignored, i.e., neither state has an effect on the result.
Step E3, slave K s Extracting K from the corresponding state table s Corresponding timing information, third logic information, and a register sequence (RE) having T(s) registers arranged in connection order 1 ，RE 2 ，…RE T(s) ),RE u For K s The value range of u is 1 to T(s) in the registers of the u row.
Still referring to the example shown in fig. 6, the register corresponding to "IQ1" is arranged before the register corresponding to "IQ2", i.e., the output terminal of the register corresponding to "IQ1" is connected to the input terminal of the register corresponding to "IQ 2".
Step E4, from { A ] 1 ，A 2 ，…A M At least one A is selected from } m Combination of generation and K s And a third target ATPG library model with the same logic of the corresponding third logic information.
Step E5, setting K s Each RE of (2) u Corresponding register unit RF u Each RF u Including an active signal port, a data input port and an output port, to be RF u Is connected to RF u+1 Connecting the third target ATPG library model to RF 1 Based on K s Corresponding timing information connects the clock signal to each RF u Is effective signal port of (1) to generate K s A corresponding target ATPG library model.
As an embodiment, the step E1 includes:
and E11, acquiring a standard cell library to be processed and a first liberty file from preset process design information, wherein logic information and time sequence information corresponding to each standard cell in the standard cell library to be processed are stored in the first liberty file.
The first liberty file is a file including standard unit timing information and logic information, and the first liberty file and the standard unit library can be directly obtained from preset process design information (Process Design Kit, abbreviated as PDK) and are not described herein.
Step E12, traversing standard cells in a standard cell library to be processed, determining time sequence standard cells comprising more than two registers as synchronizer standard cells to be processed, and generating a synchronizer standard cell set { K to be processed 1 ,K 2 ,…K S And acquiring a fourth liberty file from the first liberty file.
As one embodiment, the ATPG basic cell library comprises basic logic ATPG basic cells, combinational logic ATPG basic cells, basic sequential logic ATPG basic cells and ATPG basic cells for processing tri-state logic, pull-up resistor and pull-down resistor; the basic logic ATPG basic unit comprises a Buffer (Buffer), an Inverter (Inverter), an AND gate (AND), an OR gate (OR), a NAND gate (NAND) AND a NOR gate (NOR); the combinational logic ATPG basic unit includes a multi-input nor gate, an exclusive or gate (XOR), an exclusive nor gate (XNOR), and a selector (MUX); the basic sequential logic ATPG basic unit comprises a Latch (Latch) and a register (Flip-flop). Based on the ATPG basic unit library, the ATPG library model can be simplified as much as possible for a given standard unit. That is, the ATPG library model is constructed by using as few ATPG basic units as possible, so that the correctness and the high efficiency of the result of the ATPG are ensured.
As one embodiment, each ATPG basic unit is generated based on a Verilog language description, such that each B n The corresponding target ATPG library model is a model based on Verilog language. The verification of the ATPG library model is convenient to follow, and specifically, the second liberty file further comprises D p The corresponding Verilog model, after the step E5, further includes:
step E6, K s Corresponding target ATPG library model and K s The corresponding Verilog model is input into a preset verification tool for verification, and if the verification is passed, K is calculated s The corresponding target ATPG library model is added into a preset target ATPG library model library.
It should be noted that, because the target ATPG library model is a model based on Verilog language, the target ATPG library model can be directly combined with K s The corresponding Verilog model is verified through a preset verification tool without other conversion, so that the test efficiency of the target ATPG library model is improved, and K is increased s The corresponding Verilog model is also directly available from the preset process design information. The preset checking tool can be a standard form checking tool in industry.
As an embodiment, the step E3 includes:
step E31, K s Deleting the record of which the second enabling input field is in the second edge triggering state in the corresponding state table, and deleting the column in which the second enabling input field is positioned to obtain K s A corresponding truth table.
Step E32, based on K s And the corresponding truth table acquires the third logic information.
Wherein, specifically, K can be s The corresponding truth table is converted into a Boolean function as the first logic information.
As an example, A m ＝(A1 m ,A2 m ,A3 m ),A1 m Is A m Is composed of A2 m Is A m Logic information of A3 m Is A m Weight value of A m Weight value sum a of (2) m Inversely proportional to the cost of ATPG, the more easily handled the ATPG, the higher the weight value of the base unit, the E4 comprising:
step E41, taking the total weight value of the ATPG library model as a logic optimization target and based on { A } 1 ，A 2 ，…A M Pair K s Performing logic optimization on the corresponding third logic information to generate I(s) groups of logic information consisting of at least one A m Is combined with K s Corresponding third logic informationLogically identical set of candidate ATPG library models { Ec 1 s ,Ec 2 s ,…Ec I(s) s },Ec w s For the w candidate ATPG library model, the value range of w is 1 to I(s), ec w s Consists of J(s) ATPG basic units.
It should be noted that the logic synthesis algorithm is used to find the optimal ATPG library model. The ATPG algorithm is sensitive to the number of basic cells of the ATPG in the chip gate level netlist, and the goal of the optimization is typically to find an equivalent ATPG library model with the least basic library cells. However, it is understood that if other factors are required to be considered in the application scenario, other factors may be set in the application scenario, but the weight corresponding to the number of the basic library units is set to be the highest.
Step E42, obtaining each Ec w s Is a total weight value G of (2) w s ：
Wherein,and in the w candidate ATPG library model, the weight value corresponding to the i ATPG basic unit is obtained.
Step E43, adding { Ec } 1 s ,Ec 2 s ,…Ec I(s) s Ec with the largest total weight value in } w s Is determined as K s And a corresponding third target ATPG library model.
It should be noted that, based on the ATPG basic unit library, multiple AND K can be generated s The candidate ATPG library models with the same logic of the logic information to be processed corresponding to the corresponding first logic information are based on A corresponding to each candidate ATPG library model m The weight value of (2) selects the candidate ATPG library model with the largest total weight, namely the candidate ATPG library model which is most beneficial to the ATPG process as K s And a corresponding third target ATPG library model.
As an embodiment, the first edge trigger state is a rising edge, the second edge trigger state is a falling edge, or the first edge trigger state is a falling edge, and the second edge trigger state is a rising edge.
As an embodiment, if the second electrical state is a rising edge, then in the step E5, an inverter is inserted into the valid signal port of each register.
In the fourth embodiment, the system generates the ATPG library model for the logic information based on the ATPG basic unit library by extracting the time sequence information, the logic information and the connection relation between the registers in the state table of the synchronizer standard unit, and then generates the ATPG library model of the synchronizer standard unit by combining the clock information and the connection relation between the registers, thereby simplifying the generation process of the ATPG library model of the synchronizer standard unit and improving the generation efficiency of the ATPG library model of the synchronizer standard unit.
Fifth embodiment (V),
The method aims at the prior art that standard cells in a design gate level netlist, connection relations among the standard cells and input and output values generated by the standard cells based on an ATPG model are usually directly shown. However, some standard units occupy larger area, the composition details in the standard units cannot be directly displayed, the readability is poor, if the composition detail information needs to be acquired, the corresponding standard units need to be clicked one by one to display the composition details, the area occupied by the expanded standard units is further increased, and therefore the technical problems of low debugging efficiency and poor user experience are caused.
A fifth embodiment provides a data processing system for generating a standard cell target display structure, including a standard cell library { B to be processed 1 ，B 2 ，…B N First liberty file, memory and processor storing computer program, B n For the nth standard unit in the standard unit library to be processed, the value range of N is 1 to N, and each B is stored in the first liberty file n Corresponding logic information and timing information. When the processor executes the computer program, as shown in fig. 7, the following steps are implemented:
Step F1 based on B n The corresponding logic information and timing information obtain the corresponding boolean function Q (n).
Step F2, inverting Q (n) to obtain-! Q (n).
Step F3, respectively comparing Q (n) with-! Q (n) is logically optimized to generate candidate functions Q1 (n) in the form of the sum SOP (Sum Of Product) of products corresponding to Q (n) and candidate functions Q2 (n) in the form of the sum POS (Product Of Sum) of products corresponding to Q (n), ++! Candidate function in the form of sum SOP of products corresponding to Q (n)! Q3 (n), ≡! Candidate function in the form of product POS of the sum of Q (n) ++! Q4 (n).
SOP represents the sum of the products, i.e., the form of the min term, and POS represents the sum of the products, i.e., the form of the max term. Existing generation of Q (n) and-! The implementation of candidate functions in the form of SOPs and POS for Q (n) are all within the scope of the present invention.
Step F4, from Q1 (n), Q2 (n), ++! Q3 (n) and-! Selecting the simplest candidate function from Q4 (n) as an objective function corresponding to Q (n);
and F5, generating a target display structure corresponding to the Q (n) based on a target function corresponding to the Q (n), wherein the target display structure comprises an input port, an output port, a composition module and a connection relation among the composition modules.
Step F4 is implemented in two embodiments:
Embodiment one,
The step F4 includes:
step F41, if Q1 (n), Q2 (n), ++! Q3 (n) and-! Q4 (n) has a candidate function with the minimum variable number, and the candidate function with the minimum variable number is determined as an objective function corresponding to Q (n), wherein WX and-! WX is regarded as a variable, WX represents any one variable, and if there are a plurality of candidate functions with the smallest number of variables, step F42 is performed.
And step F42, if the candidate function with the minimum variable number has a candidate function with the minimum number of gates, determining the candidate function with the minimum number of gates as an objective function corresponding to Q (n), wherein each bracket in the candidate function corresponds to one gate, and if the candidate function with the minimum number of gates has a plurality of candidate functions, executing step F43.
And F43, determining the candidate function with the least inverse number from the candidate functions with the least number of gates as an objective function corresponding to Q (n).
Wherein, the step F43 includes:
and F431, if one candidate function with the minimum number of the gates exists in the candidate functions with the minimum number of the gates, determining the candidate function with the minimum number of the gates as an objective function corresponding to Q (n), and if the candidate function with the minimum number of the gates exists, randomly selecting the candidate function with the minimum number of the gates as the objective function corresponding to Q (n).
The target display structure corresponding to the Q (n) obtained based on the constraint condition optimization can enable the displayed schematic diagram to be convenient to understand and analyze, improve the readability of a user and improve the debugging efficiency.
Embodiment II,
The step F4 includes:
step F41 ’ Setting variable quantity weight We 1 Door quantity weight We 2 And taking the inverse number weight We 3 ,We 1 、We 2 、We 3 Satisfy We 1 >We 2 >We 3 ，We 1 -We 2 >WZ 1 ,We 2 -We 3 >WZ 2 ,WZ 1 >WZ 2 ，WZ 1 For the first level difference threshold, WZ 2 Is the second level difference threshold.
Step F42 ’ Obtaining SX d Number of medium variables a d Number of gates b d And taking the inverse number c d ，SX d Is { Q1 (n), Q2 (n), +.! Q3 (n) and-! A function of Q4 (n) }, d has a value ranging from 1 to 4, wherein a preset constraint condition is satisfied: WX and-! WX is considered a variable, and WX represents any one variable; one for each bracket.
Step F43', obtain SX d Corresponding total weight SY d :
SY d ＝We 3 *a d +We 2 *b d +We 3 *c d ；
Step F44', SY d Maximum SX d Is determined as an objective function corresponding to Q (n).
The target display structure corresponding to the Q (n) obtained based on the constraint condition optimization can enable the displayed schematic diagram to be convenient to understand and analyze, improve the readability of a user and improve the debugging efficiency.
As an embodiment, the system further comprises a display interface, and after step F5, further comprises:
Step F6, obtaining a chip design gate-level netlist to be tested, wherein the chip design gate-level netlist to be tested is based on the standard cell library { B to be processed 1 ，B 2 ，…B N And (3) generating.
And F7, based on the target display structure, replacing each standard unit in the chip design gate-level netlist to be tested with a corresponding target display structure, and displaying on the display interface.
It can be understood that the structure displayed in the step F7 is directly replaced by a standard unit with a corresponding target display structure, and the structure which is logically correct and optimally displayed is displayed, so that the specific composition of the gate-level netlist of the whole chip design to be tested can be intuitively presented, no additional clicking is needed, and the debugging is convenient.
As an embodiment, the system further includes an ATPG model corresponding to the pre-generated gate level netlist of the chip design to be tested, and the step F7 further includes:
and F71, generating an input parameter value and an output parameter value corresponding to each target display structure based on an ATPG model corresponding to the chip design gate level netlist to be tested, and displaying an input end and an output end corresponding to each target display structure on the interface.
The debugging efficiency is further improved by intuitively displaying the input parameter values and the output parameter values.
Fig. 8 shows the original display interface (the part above the arrow) of the gate-level netlist of the original chip design to be tested to the display interface (the part below the arrow) based on the target display structure, and as can be seen from the figure, the display interface based on the target display structure enables the same units to be obviously reduced in size, and detailed components and connection relations of each component unit are clearly shown.
It should be noted that, the specific generation details of the ATPG model corresponding to the gate level netlist of the chip to be tested may be implemented by any one of the technical details of the first embodiment, the second embodiment, the third embodiment and the fourth embodiment, which are not described herein.
It will be appreciated that some of the technical details of the above embodiments are equally applicable to another embodiment and will not be fully described.
In the fifth embodiment, the system can logically optimize each standard cell and generate a corresponding target display structure, so that when the gate-level netlist of the chip design is displayed, the target display structure corresponding to each standard cell is directly displayed, the specific composition structure of the gate-level netlist can be clearly displayed, the readability is high, the display area of the gate-level netlist of the chip design can be reduced, the debugging is convenient for a user, and the debugging efficiency is improved.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (7)
1. An ATPG library model generation system of a synchronizer standard unit is characterized in that,
comprising a pre-constructed ATPG basic cell library { A } 1 ，A 2 ，…A M Memory and processor storing computer programs, A m The M-th ATPG basic unit in the ATPG basic unit library has the value range of M from 1 to M, wherein M is the total number of the ATPG basic units in the ATPG basic unit library, and when the processor executes the computer program, the following steps are realized:
step E1, obtaining a synchronizer standard unit set { K ] to be processed 1 ,K 2 ,…K S And fourth liberty file, K s The value range of S is 1 to S, S is the total number of the synchronizer standard units to be processed, K 1 ,K 2 ,…K S Belongs to the same standard cell library to be processed;
step E2, extracting each K from the fourth liberty file s Corresponding state table, K s The corresponding state table comprises a plurality of second state records, wherein the second state records comprise L(s) input fields and T(s) output fields, and the L(s) input fields comprise a second enabling input field, a selection signal field and L(s) -2 data input fields; the second enabling input field is used for storing a first edge trigger state and a second edge trigger state, the selection signal field, other L(s) -2 data input fields and T(s) output fields are used for storing corresponding level states, and the level states comprise a first level state and a second level state; when the second enable input field is in the first edge trigger state, T(s) output fields are determined based on the logical relationship of the selection signal field and the L(s) -2 data input fields; when the second enabling input field is in a second edge triggering state, the T(s) output fields keep the current state unchanged; the j-th output field corresponds to K s Output state of jth register, K s Includes T(s) registers;
step E3, slave K s Corresponding toExtracting K from state table s Corresponding timing information, third logic information, and a register sequence (RE) having T(s) registers arranged in connection order 1 ，RE 2 ，…RE T(s) ),RE u For K s The value range of u is 1 to T(s);
step E4, from { A ] 1 ，A 2 ，…A M At least one A is selected from } m Combination of generation and K s A third target ATPG library model corresponding to the third logic information and having the same logic;
A m ＝(A1 m ,A2 m ,A3 m ),A1 m is A m Is composed of A2 m Is A m Logic information of A3 m Is A m Weight value of A m Weight value sum a of (2) m Inversely proportional to the cost of ATPG, said step E4 comprises:
step E41, taking the total weight value of the ATPG library model as a logic optimization target and based on { A } 1 ，A 2 ，…A M Pair K s Performing logic optimization on the corresponding third logic information to generate I(s) groups of logic information consisting of at least one A m Is combined with K s Set of logically identical candidate ATPG library models { Ec for corresponding third logical information 1 s ,Ec 2 s ,…Ec I(s) s },Ec w s For the w candidate ATPG library model, the value range of w is 1 to I(s), ec w s Consists of J(s) ATPG basic units;
step E42, obtaining each Ec w s Is a total weight value G of (2) w s ：
Wherein,in the w candidate ATPG library model, the i ATPG basic unit pair A weight value to be applied;
step E43, adding { Ec } 1 s ,Ec 2 s ,…Ec I(s) s Ec with the largest total weight value in } w s Is determined as K s A corresponding third target ATPG library model;
step E5, setting K s Each RE of (2) u Corresponding register unit RF u Each RF u Including an active signal port, a data input port and an output port, to be RF u Is connected to RF u+1 Connecting the third target ATPG library model to RF 1 Based on K s Corresponding timing information connects the clock signal to each RF u Is effective signal port of (1) to generate K s A corresponding target ATPG library model.
2. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
the step E1 includes:
step E11, acquiring a standard cell library to be processed and a first liberty file from preset process design information, wherein logic information and time sequence information corresponding to each standard cell in the standard cell library to be processed are stored in the first liberty file;
step E12, traversing standard cells in a standard cell library to be processed, determining time sequence standard cells comprising more than two registers as synchronizer standard cells to be processed, and generating a synchronizer standard cell set { K to be processed 1 ,K 2 ,…K S And acquiring a fourth liberty file from the first liberty file.
3. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
the step E3 includes:
step E31, K s Deleting the record of which the second enabling input field is in the second edge triggering state in the corresponding state table, and deleting the column in which the second enabling input field is positioned to obtain K s A corresponding truth table;
step E32, based on K s And the corresponding truth table acquires the third logic information.
4. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
the first edge triggering state is a rising edge, the second edge triggering state is a falling edge, or the first edge triggering state is a falling edge, and the second edge triggering state is a rising edge.
5. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
if the second electrical state is a rising edge, then inserting an inverter at the active signal port of each register is also included in step E5.
6. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
the ATPG basic unit library comprises basic logic ATPG basic units, combination logic ATPG basic units, basic time sequence logic ATPG basic units and ATPG basic units for processing tristate logic, pull-up resistor and pull-down resistor; the basic logic ATPG basic unit comprises a buffer, an inverter, an AND gate, an OR gate, a NAND gate and a NOR gate; the combined logic ATPG basic unit comprises a multi-input exclusive OR gate, an exclusive OR gate and a selector; the basic sequential logic ATPG basic unit comprises a latch and a register.
7. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
each ATPG basic unit is generated based on Verilog language description, each B n The corresponding target ATPG library model is a model based on Verilog language.
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