CN115940628B - Charge pump, chip, main board and electronic equipment - Google Patents
Charge pump, chip, main board and electronic equipment Download PDFInfo
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Abstract
The embodiment of the application provides a charge pump, a chip, a main board and electronic equipment, wherein the charge pump comprises: an adjustable voltage output circuit, an output switching circuit and a clock signal generating circuit; the adjustable voltage output circuit is used for transmitting a first voltage signal to the source voltage input end under the control of the control signal input by the control signal input end; the clock signal generating circuit is used for transmitting at least two clock signals to the clock signal input end so as to control the output switching circuit to step down the first voltage signal and output the obtained target voltage signal through the target voltage output end. The charge pump only comprises a clock signal generating circuit, a switching tube, a resistor and other components, does not comprise an amplifier, a measuring circuit, an integrator, a differentiator, an adder and the like, has a simple structure and small area cost, and does not have the risk of structural stability of a loop mechanism.
Description
Technical Field
The present application relates to the field of power conversion circuits, and in particular, to a charge pump, a chip, a motherboard, and an electronic device.
Background
The multiple of the output voltage and the input supply voltage of a conventional charge pump is fixed, i.e. the output voltage of the charge pump is the same for the same input supply voltage. However, for load modules with different supply voltage requirements, the charge pump can only supply power to the load modules with fixed supply voltage requirements under the condition that the input supply voltage is fixed, and for load modules with different supply voltage requirements, the charge pump is required to regulate the output voltage.
In the technical scheme of adjusting the output voltage of the charge pump by utilizing the controllable current source to adjust the supply voltage of the charge pump in the related technology, because the whole analog control loop comprises auxiliary circuit modules such as a measuring circuit, an amplifier module circuit and the like, the circuit structure is complex, the layout area cost is large, and the loop stability is at risk.
In the technical scheme of adjusting the output voltage of the charge pump by introducing a proportional integral derivative (Proportion Integration Differentiation, PID) closed-loop control technology, the PID control module comprises a proportional amplifier, an integrator, a differentiator and an adder, so that the structure is complex, the area overhead is large, and the loop structure has stability risks.
Disclosure of Invention
In view of the foregoing, embodiments of the present application have been developed to provide a charge pump that overcomes the foregoing problems to reduce the complexity and area overhead of the circuit structure while also avoiding loop stability risks.
To solve the above-mentioned problems, in a first aspect, an embodiment of the present application discloses a charge pump, including: an adjustable voltage output circuit, an output switching circuit and a clock signal generating circuit;
The adjustable voltage output circuit comprises a first power supply voltage input end, a first grounding end, a control signal input end, a voltage signal output end and an array adjusting circuit electrically connected with each end; the array adjusting circuit comprises at least one switch tube and a resistor; the control electrode of each switching tube in the array regulating circuit is electrically connected with the control signal input end;
The output switching circuit comprises a pump capacitor, a switching switch component, a second power supply voltage input end, a clock signal input end, a second grounding end and a target voltage output end;
the voltage signal output end of the adjustable voltage output circuit is electrically connected with the second power supply voltage input end of the output switching circuit, and the adjustable voltage output circuit is used for transmitting a first voltage signal to the second power supply voltage input end under the control of a control signal input by the control signal input end;
the clock signal generating circuit generates at least two clock signals for controlling a change-over switch component in the output switching circuit;
The output switching circuit reduces the first voltage signal under the control of the at least two clock signals, and outputs the obtained target voltage signal through the target voltage output end.
In a second aspect, an embodiment of the present application further discloses a chip, including the charge pump according to the first aspect of the embodiment of the present application.
In a third aspect, an embodiment of the present application further provides a motherboard, including the chip according to the second aspect of the embodiment of the present application.
In a fourth aspect, an embodiment of the present application further provides an electronic device, including a motherboard according to the third aspect of the embodiment of the present application.
The embodiment of the application has the following advantages:
In the embodiment of the application, a first voltage signal is transmitted to an output switching circuit through an adjustable voltage output circuit under the control of a control signal input by a control signal input end; and transmitting at least two clock signals to the output switching circuit through the clock signal generating circuit, so that the output switching circuit steps down the first voltage signal under the control of the at least two clock signals to obtain a target voltage signal. Since the control signal input from the control signal input terminal corresponds to the target voltage signal, the first voltage signal corresponds to the target voltage signal. That is, different first voltage signals correspond to different target voltage signals. Furthermore, for different first voltage signals, after the output switching circuit steps down the different first voltage signals, different target voltage signals can be obtained, and the output voltage of the charge pump can be adjusted.
Meanwhile, the charge pump comprises an adjustable voltage output circuit, an output switching circuit and a clock signal generating circuit; the adjustable voltage output circuit comprises a first power supply voltage input end, a first grounding end, a control signal input end, a voltage signal output end and an array adjusting circuit electrically connected with each end; the array regulating circuit comprises at least one switch tube and a resistor, namely, the charge pump only comprises a clock signal generating circuit, a pump capacitor, the switch tube, the resistor and other components, and does not comprise an amplifier, a measuring circuit, an integrator, a differentiator, an adder and the like, so that the structure is simple, the area cost is small, and the risk of loop structural stability is avoided.
Drawings
Fig. 1 is a schematic diagram of a composition structure of a charge pump according to an embodiment of the present application;
FIG. 2 is a schematic diagram of another charge pump according to an embodiment of the present application;
Fig. 3 is a schematic diagram of a composition structure of a charge pump with an adjustable voltage output circuit for realizing a voltage step-down function according to an embodiment of the present application;
fig. 4 is a schematic diagram of a composition structure of an adjustable voltage output circuit according to an embodiment of the present application;
fig. 5 is a schematic diagram of a composition structure of a low-power charge pump according to an embodiment of the present application;
Fig. 6 is a schematic diagram of a composition structure of an adjustable voltage output circuit in a low-power charge pump according to an embodiment of the present application;
fig. 7 is a schematic diagram of a specific composition structure of a charge pump according to an embodiment of the present application;
FIG. 8 is a schematic diagram of a specific structure of an adjustable voltage output circuit according to an embodiment of the present application;
FIG. 9 is a schematic diagram of a transient simulation result of a charge pump according to an embodiment of the present application;
Fig. 10 is a schematic diagram of a specific composition structure of another low-power charge pump according to an embodiment of the present application;
FIG. 11 is a schematic diagram of a specific structure of another low-power charge pump according to an embodiment of the present application;
FIG. 12 is a schematic diagram of a charge pump according to an embodiment of the present application;
FIG. 13 is a schematic diagram showing a structure of another adjustable voltage output circuit according to an embodiment of the present application;
Fig. 14 is a schematic diagram of a composition structure of a charge pump circuit for implementing a boosting function of an adjustable voltage output circuit according to an embodiment of the present application;
Fig. 15 is a schematic diagram of a composition structure of an adjustable voltage output circuit for implementing a boosting function according to an embodiment of the present application;
Fig. 16 is a schematic diagram of a specific composition structure of a charge pump circuit for implementing a boosting function by an adjustable voltage output circuit according to an embodiment of the present application;
Fig. 17 is a schematic diagram of a specific composition structure of an adjustable voltage output circuit for implementing a boosting function according to an embodiment of the present application;
Fig. 18 is a schematic diagram of a composition structure of a low-power charge pump according to an embodiment of the present application;
Fig. 19 is a schematic diagram of a specific composition structure of a further adjustable voltage output circuit according to an embodiment of the present application.
Detailed Description
In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description.
In an electronic circuit, when a submodule which is lower than the voltage of a system power supply needs to be supplied with power, the power supply voltage of the system needs to be reduced to obtain the voltage lower than the system power supply.
Currently, the scheme that can step down the supply voltage of the system includes: a conventional Direct Current-Direct Current (DC-DC) converter using an inductor as an energy transfer device, a low dropout linear regulator (Low Dropout Regulator, LDO) and a charge pump.
Wherein the charge pump has lower electromagnetic interference (Electromagnetic Interference, EMI)/or ripple, smaller area and lower cost than a conventional DC-DC converter with inductance as the energy transfer device; compared with LDO, the charge pump has higher efficiency; as a result, charge pumps are increasingly being used by portable devices.
The charge pump is a power supply conversion circuit, belongs to a kind of DC-DC converter, but unlike the traditional converter which uses magnetic elements such as inductance/transformer as energy transfer device, the charge pump uses capacitance as energy transfer element, and is realized by switching power storage and discharging by switching period.
The multiple of the output voltage of the conventional charge pump and the voltage of the input power supply is fixed, and for the load modules requiring different power supply voltages, the output voltage of the charge pump can be adjusted according to the requirements. However, the existing step-down charge pump circuit with adjustable output voltage has the problems of poor environmental stability, complex structure, large design difficulty, large area overhead, high cost, limited adjustable range of the output voltage, low adjustment fineness and the like, so that the application requirement in an electronic device is difficult to meet.
For example, in the technical scheme of adjusting the power supply voltage of the charge pump by using the controllable current source so as to adjust the output voltage of the charge pump, the whole analog control loop comprises auxiliary circuit modules such as a measuring circuit, an amplifier module circuit and the like, the structure is complex, the layout area overhead is large, and the loop stability is at risk; meanwhile, the auxiliary circuit module also generates additional static power consumption, so that the energy conversion efficiency of the whole circuit is reduced; in addition, because the temperature coefficient of the current is poor, the method for adjusting the voltage by controlling the current in the scheme has the problem that the current value greatly drifts along with environmental factors such as temperature, process angle and the like.
In the technical scheme that the output voltage is regulated by changing the number of charge pumps connected in parallel through a controller, the whole circuit comprises a charge pump array, and the charge pump array consists of a plurality of charge pumps, and has the advantages of complex structure and larger area; and only the boosting function can be realized, and the depressurization function can not be realized; furthermore, when a plurality of charge pumps are operated simultaneously, the power consumption of the circuit is large.
In the technical scheme that the variable frequency clock signals with different duty ratios are generated by controlling the voltage-controlled oscillator and sent to the charge pump to regulate the output voltage of the charge pump, the control signals with different frequencies can enable the output voltage of the charge pump to generate ripples with different amplitudes, if the tolerance of a load device to the power supply ripples is not high enough, the output voltage of the scheme can possibly generate the risk of abnormal operation of the load module/component caused by larger output voltage ripples.
In the technical scheme of adjusting the output voltage of the charge pump by introducing the PID closed-loop control technology, the PID control module comprises a proportional amplifier, an integrator, a differentiator and an adder, the structure of the PID control module is complex, the area cost is large, and the loop structure has stability risk.
In the scheme of adjusting the output voltage of the charge pump by changing the connection state and the quantity of the capacitors and the charge source, the circuit structure for controlling whether the passive device is enabled (switched on or off) is relatively complex, and excessive capacitor array accumulation can cause additional parasitic capacitance, so that the influence on circuit precision is larger.
The scheme of changing the circuit structure and then adjusting the output voltage of the charge pump by controlling the switching device can only realize 1/2 and 2/3 of the voltage reduction, the adjustable range of the output voltage is limited, and the adjusting fineness is low.
In the scheme of adjusting the output voltage of the charge pump by introducing the variable resistor, the variable resistor lacks the feasibility of on-chip adjustment, and the scheme does not relate to a corresponding adjusting circuit structure, and further does not relate to the scheme of how to adjust the resistance value of the variable resistor after the circuit is made into a chip finished product.
Based on the above technical problems, an embodiment of the present application provides a charge pump, as shown in fig. 1, including: an adjustable voltage output circuit 10, an output switching circuit 11, and a clock signal generation circuit 12;
The adjustable voltage output circuit 10 includes a first power supply voltage input terminal, a first ground terminal, a control signal input terminal, a voltage signal output terminal, and an array adjustment circuit 101 electrically connected to each terminal; the array regulating circuit 101 comprises at least one switching tube and a resistor; the control electrode of each switching tube of the array regulating circuit is electrically connected with the control signal input end;
the output switching circuit 11 comprises a pump capacitor, a switching switch component, a second power supply voltage input end, a clock signal input end, a second grounding end and a target voltage output end;
The voltage signal output end of the adjustable voltage output circuit 10 is electrically connected with the second power supply voltage input end of the output switching circuit 11, and the adjustable voltage output circuit 10 is used for transmitting a first voltage signal to the second power supply voltage input end under the control of the control signal input by the control signal input end;
The clock signal generation circuit 12 generates at least two clock signals for controlling a change-over switch component in the output switching circuit; the output switching circuit 11 steps down the first voltage signal under the control of the at least two clock signals, and outputs the obtained target voltage signal through the target voltage output terminal.
In some possible embodiments, the control signal may be a degenerate control signal; the degenerate control signal may be a plurality of parallel 0 or 1 signals; here, 0 or 1 corresponds to a low level or a high level, respectively.
In some embodiments, the output switching circuit 11 steps down the first voltage signal, which may be that the output switching circuit 11 reduces the voltage amplitude of the first voltage signal by 1/2, that is, the constant voltage amplitude of the target voltage signal is equal to 1/2 of the voltage amplitude of the first voltage signal.
In the embodiment of the application, a first voltage signal is transmitted to an output switching circuit through an adjustable voltage output circuit under the control of a control signal input by a control signal input end; and transmitting at least two clock signals to the output switching circuit through the clock signal generating circuit, so that the output switching circuit steps down the first voltage signal under the control of the at least two clock signals to obtain a target voltage signal. In some embodiments, the at least two clock signals may be non-overlapping signals. Since the control signal input from the control signal input terminal corresponds to the target voltage signal, the first voltage signal corresponds to the target voltage signal. That is, different first voltage signals correspond to different target voltage signals. Furthermore, for different first voltage signals, after the output switching circuit steps down the different first voltage signals, different target voltage signals can be obtained, and the output voltage of the charge pump can be adjusted.
Meanwhile, the charge pump comprises an adjustable voltage output circuit, an output switching circuit and a clock signal generating circuit; the adjustable voltage output circuit comprises a first power supply voltage input end, a first grounding end, a control signal input end, a voltage signal output end and an array adjusting circuit electrically connected with each end; the array regulating circuit comprises at least one switch tube and a resistor, namely, the charge pump only comprises a clock signal generating circuit, a pump capacitor, the switch tube, the resistor and other components, and does not comprise an amplifier, a measuring circuit, an integrator, a differentiator, an adder and the like, so that the structure is simple, the area cost is small, and the risk of loop structural stability is avoided.
In some embodiments of the application, the switch assembly comprises first to fourth switch assemblies; the control electrodes of the first to fourth transfer switch components are connected with the clock signal input end; the second change-over switch component is connected between the second power supply voltage input end and the upper polar plate of the pump capacitor; the first switch component is connected between a lower polar plate of the pump capacitor and the second grounding end; the third change-over switch component is connected between the lower polar plate of the pump capacitor and the target voltage output end; the fourth change-over switch component is connected between the upper polar plate of the pump capacitor and the target voltage output end;
the clock signals include a first clock signal and a second clock signal that are non-overlapping; charging the pump capacitor through the first voltage signal under the condition that the first clock signal controls the second and the third transfer switch assemblies to be both on and the second clock signal controls the first and the fourth transfer switch assemblies to be both off; discharging the pump capacitor under the condition that the first clock signal controls the second switching switch assembly and the third switching switch assembly to be disconnected and the second clock signal controls the first switching switch assembly and the fourth switching switch assembly to be conducted;
And under the condition of charging and discharging the pump capacitor, the first voltage signal is reduced to the target voltage signal and is output through the target voltage output end.
In some embodiments of the present application, referring to FIG. 2, the clock signal generation circuit 12 may be CLK_0, CLK_0 being configured to generate two non-overlapping clock signals Φ1 and Φ2 under control of an input power source; the output switching circuit 11 is composed of a first controlled switching module sw_1, a second controlled switching module sw_2, third and fourth controlled switching modules sw_3 and sw_4, and a pump capacitor c_1; SW_1 is connected between the lower plate of C_1 and GND, and SW_2 is connected between V_bias and the upper plate of C_1; sw_3 is connected between the voltage signal output terminal of the adjustable voltage output circuit 10 and the lower plate of c_1; sw_4 is connected between the target voltage output terminal of the output switching circuit 11 and the upper plate of c_1.
Φ1 as an enable signal controlling the opening and closing of sw_2 and sw_3; and Φ2 controls the opening and closing of sw_1 and sw_4 as an enable signal.
It can be understood that when the first voltage signal output by the voltage signal output end of the adjustable voltage output circuit 10 is V1, and Φ1 controls sw_2 and sw_3 to be closed, and accordingly Φ2 controls sw_1 and sw_4 to be opened, at this time, the voltage difference between the two plates of c_1 is V1 and the voltage difference between the two plates of c_1 is (V1-Vout); while when Φ2 controls sw_1 and sw_4 to be closed, correspondingly Φ1 controls sw_2 and sw_3 to be opened, at this time, the voltage difference between the plates c_1 is Vout. In an ideal case, the output voltage value should be vout=v1/2 according to the law of conservation of charge.
Here, sw_1 to sw_4 may select P-type Metal-Oxide-Semiconductor (PMOS) tubes, N-type Metal-Oxide-Semiconductor (NMOS) tubes, transfer gates, and the like according to circumstances.
In some embodiments of the present application, referring to fig. 3, the adjustable voltage output circuit ctrl_1 corresponds to the adjustable voltage output circuit 10 of fig. 1 or 2; CTRL_1 is a three-input single-output module, three input ends (a first power voltage input end, a first grounding end and a control signal input end) are correspondingly connected with a power voltage Vin, a ground voltage GND and (N+M+1) degenerate control signals v_ctrl_1<0:N+M >, and one output end (a voltage signal output end) outputs v_bias_1 to be connected with one end of SW_2.
It will be appreciated that CTRL_1 functions to convert Vin to αvin (0 < α.ltoreq.1), and to output αvin to one end of SW_2 as v_bias_1 output from the voltage signal output terminal of CTRL_1. Correspondingly, vout= (alpha/2) Vin, i.e. power supply voltage (alpha/2), is multiplied by 0< (alpha/2). Ltoreq.1/2 in the scheme, so that Vin can be reduced by any multiple of more than 0 and less than or equal to 1/2 by the scheme.
In some embodiments of the application, the array conditioning circuit includes at least one parallel branch connected in series; each of the parallel branches comprises at least one series branch electrically connected in parallel; each of the series branches comprises at least one switching tube and at least one resistor electrically connected in series; the control electrode of each switching tube is electrically connected with the control signal input end.
In some embodiments of the application, the array conditioning circuit includes a first parallel branch and a second parallel branch connected in series; the first parallel branch comprises 1 st to N th serial branches connected in parallel; the second parallel branch comprises an n+1th to n+Mth series branch connected in parallel; the ith serial branch circuit correspondingly comprises an ith switching tube and an ith resistor which are connected in series; i is any positive integer from 1 to n+m; the control electrode of the ith switching tube is electrically connected with the control signal input end; the first parallel branch and the second parallel branch are connected in series to form the array adjusting circuit, and the array adjusting circuit is connected between the first power supply voltage input end and the first grounding end in a bridging manner; the first connecting point of the first parallel branch and the second parallel branch is electrically connected with the voltage signal output end;
the array adjusting circuit is used for accessing or removing the ith serial branch under the control of a control signal input by the control signal input end to obtain a target serial branch, and transmitting a first voltage signal with a first amplitude to the output switching circuit based on the voltage division of the power supply voltage by the resistor in the target serial branch.
The first parallel branch further comprises an n+m+1-th switching tube connected in parallel with the 1 st to N-th serial branches; the control electrode of the (N+M+1) th switching tube is electrically connected with the control signal input end;
The n+M+1 switching tube is used for conducting or disconnecting the electric connection between the first power supply voltage input end and the voltage signal output end under the action of a control signal input by the control signal input end;
Correspondingly, the array adjusting circuit is configured to output, as the first voltage signal, a signal input by the first power supply voltage input end to the output switching circuit, where the first power supply voltage input end is electrically connected to the voltage signal output end; and under the condition that the first power supply voltage input end is disconnected from the voltage signal output end, outputting the first voltage signal with the first amplitude value to the output switching circuit.
In the embodiment of the present application, referring to fig. 4, the 1 st to nth switching tubes and the n+m+1th switching tubes correspond to the 1 st controlled switching modules sw1_u_0 to (n+1) th controlled switching modules sw1_u_n, the n+1 th to n+m switching tubes correspond to the (n+2) th controlled switching modules sw1_d_0 to (n+m+1) th controlled switching modules sw1_d_m_1, the 1 st to N resistors correspond to the 1 st high-order resistors ru_0 to N high-order resistors ru_n_1, and the n+1 st to n+m resistors correspond to the 1 st low-order resistors rd_0 to M low-order resistors rd_m_1, respectively;
Wherein, sb1_u_0 is connected between the input power voltage Vin and the upper level of Ru_0, sb1_u_1 is connected between Vin and the upper level of Ru_1, and so on, sb1_u_N-1 is connected between Vin and the upper level of Ru_N-1; in particular, sw1_u_n is connected between Vin and v_bias_1; sw1_d_0 is connected between the lower stage of rd_0 and GND, sw1_d_1 is connected between the lower stage of rd_1 and GND, and so on, sw1_d_m-1 is connected between the lower stage of rd_m-1 and GND; the lower stages of Ru_0, ru_1 through Ru_N-1 and the upper stages of Rd_0, rd_1 through Rd_M-1 are all connected to v_bias_1;
v_ctrl_1<0:n+m > as control signals control the opening and closing of sw1_u_0 to sw1_u_ N, SW1_d_0 to sw1_d_m-1, respectively, i.e. a first control signal v_ctrl_1<0> controls the opening and closing of sw1_u_0, a second control signal v_ctrl_1<1> controls the opening and closing of sw1_u_1, and so on, an (n+m+1) th control signal v_ctrl_1< n+m > controls the opening and closing of sw1_d_m-1.
In some embodiments of the present application, the 1 st to n+m resistances are equal in resistance; the first amplitude is equal to the amplitude of the power supply voltage by a first multiple; the first multiple is equal to a quotient of the first number and the first total number; the first total number represents a sum of the first number and a second number; the first number represents the number of series branches belonging to the 1 st to nth series branches in the target series branch; the second number represents the number of series branches belonging to the n+1th to n+mth series branches in the target series branch.
It will be appreciated that the first multiple corresponds to a.
As can be seen from an analysis of fig. 4, the values of α are shown in table 1 below.
TABLE 1
Here, in order to facilitate calculation and display rules, the values of all resistors are deduced to be consistent, but the values of the resistors can be selected according to specific situations when the actual design is applied.
As can be seen from table 1, the finer degree of adjustment of the output voltage by ctrl_1 is higher as the value of N or M increases (the number of upper and lower resistors increases). But the increase in the number of resistors at the high and low positions also increases the area overhead. However, the area overhead of the charge pump circuit structure provided by the embodiments of the present application is still relatively small compared to the charge pump circuit structure of the same precision.
In a word, the technical scheme of the embodiment of the application can solve the technical problem of low output adjustable voltage regulation fineness of the charge pump to a certain extent.
In some embodiments of the application, the array adjustment circuit further comprises an n+m+2-th switching tube; the control electrode of the n+M+2 switching tube is connected with the output end of the clock signal generating circuit; the n+M+2 switching tube is connected in series between the second parallel branch and the first grounding end;
The n+m+2 switching tube is configured to disconnect the electrical connection between the second parallel branch and the first ground terminal under the condition that the clock signal output by the clock signal generating circuit controls the capacitor in the charge pump assembly to discharge, so that the array adjusting circuit stops working; under the condition that the clock signal output by the clock signal generating circuit controls the capacitor in the charge pump assembly to charge, the electric connection between the second parallel branch and the first grounding end is conducted, so that the array adjusting circuit is connected into or removed from the ith serial branch under the control of the control signal input by the control signal input end, and the target serial branch is obtained.
In the embodiment of the present application, referring to fig. 5, the adjustable voltage output circuit ctrl_1_pr corresponds to the adjustable voltage output circuit 10 in fig. 1 or fig. 2; CTRL_1_PR is a four-input single-output module, and three input terminals (a first power supply voltage input terminal, a first ground terminal, a control signal input terminal) are connected and have unchanged functions, one clock signal input terminal connected with the output clock signal phi 1 of CLK_0 is added, and one output terminal is added, compared with FIG. 3.
In the embodiment of the present application, as shown in fig. 6, compared with fig. 4, in the adjustable voltage output circuit ctrl_1_pr, the controlled switch modules sw1_pr are connected in series between the ends of sw1_d_0 to sw1_d_m_1 near GND and GND, the control input terminal of sw1_pr is connected Φ1, and the opening and closing of sw1_pr is controlled by Φ1.
As can be seen from fig. 6, ctrl_1_pr operates only when sw1_pr is closed and outputs a voltage signal via v_bias_1, and ctrl_1_pr does not operate when sw1_pr is open. Since Φ1 simultaneously controls the opening and closing of sw1_pr, sw_2, and sw_3, and charges the capacitor c_1 with Φ1 controlling the closing of sw_2 and sw_3, ctrl_1_pr operates only with the capacitor charged, and thus, power consumption of ctrl_1_pr can be reduced, thereby reducing power consumption of the charge pump circuit.
Fig. 7 corresponds to fig. 3, and the charge pump includes clk_0, ctrl_1, and an output switching circuit 11. The structure of ctrl_1 is identical to that of fig. 3, and clk_0 and output switching circuit 11 are actually specific circuits.
Here, clk_0 generates three clock control signals clk_1, clk_2, and clk_1b; clk_1 and clk_2 are two non-overlapping clock signals, clk_1b is the inverse of clk_1. The output switching circuit 11 is a specific switching transistor circuit selected according to characteristics of the NMOS switching transistor and the PMOS switching transistor, which are ideal sw_1 to sw_4 in fig. 2.
It can be understood that the NMOS switch is turned on at a high level and turned off at a low level; conduction to low levels is better, conduction to higher levels is worse, and there is a threshold penalty if the VDD level is transmitted. The PMOS switch is turned on at a low level and turned off at a high level; conduction to high level is better, conduction to lower level is worse, if 0 level is transmitted, there is a threshold loss.
As shown in fig. 7, sw_1 is composed of an NMOS transistor MN1, and the drain, gate and source of MN1 are respectively connected to the lower plate of c_1, clock control signals clk_2 and GND; the SW_2 consists of a PMOS transistor MP2 and an NMOS transistor MN2, and the source electrode and the grid electrode of the MP2 are correspondingly connected with the drain electrodes of the v_bias_1 and the MN2 respectively; the drain electrode and the substrate of MP2 are connected with the upper polar plate of C_1; the gate and source of MN2 are connected to clk_1 and GND, respectively. Here, the effect of connecting the drain electrode of MP2 and the substrate to the upper plate of c_1 is to regulate the PMOS threshold voltage by using the liner bias effect, and reduce the transmission threshold loss when the switch is turned on and the leakage current when the switch is turned off.
SW_3 is a transmission gate switch structure and consists of a PMOS transistor MP3 and an NMOS transistor MN3, wherein the source electrode of the MP3 and the source electrode of the MN3 are both connected with the lower polar plate of the C_1, the drain electrode of the MP3 and the drain electrode of the MN3 are both connected with Vout, the gate electrode of the MN3 is connected with clk_1, and the gate electrode of the MP3 is connected with clk_1b;
The structure of SW_4 is the same as that of SW_2, SW_4 is composed of a PMOS transistor MP4 and an NMOS transistor MN4, and the source electrode and the grid electrode of MP4 are correspondingly connected with the upper polar plate of C_1 and the drain electrode of MN4 respectively; the drain electrode and the substrate of MP4 are connected with Vout, and the grid electrode and the source electrode of MN4 are correspondingly connected with clk_2 and GND respectively;
Wherein, the resistor R_1 is connected between the grid electrode of MP2 and the upper polar plate of C_1 in a bridging way; resistor R_2 is connected across the gate of MP4 and Vout. Here, when the working principle of r_1 is CLK1 is high, the MP2 gate is at 0 level, MP2 is turned on, if CLK1 becomes low, the MP2 gate needs to be turned high to turn MP2 off, but if no R1 exists, the MP2 gate has no charge source to charge it to high level, at this time, MP2 is not turned off, CLK2 becomes high, which may cause circuit operation disorder, if R1 exists, the path of R1 will pump part of the charge of the plate on C1 to the MP2 gate, and charge the MP2 gate to high level, thereby achieving the purpose of turning MP2 off. The principle of operation of R_2 is similar to that of R_1.
Fig. 8 corresponds to fig. 4, with the only difference that: the Sw1_u_0 to Sw1_u_N are respectively and correspondingly composed of (N+1) PMOS transistors Mp1_0 to Mp1_N, the sources of Mp1_0 to Mp1_N are respectively connected with Vin, the drains of Mp1_0 to Mp1_N-1 are respectively and correspondingly connected with the upper stages of Ru_0 to Ru_N-1, the drains of Mp1_N are respectively connected with v_bias_1, and the gates of Mp1_0 to Mp1_N are respectively and correspondingly connected with v_ctrl_1<0> to v_ctrl_1<N >; the SW1_d_0 to SW1_d_M-1 are respectively composed of M NMOS transistors M1_0 to M1_M-1, the sources of M1_0 to M1_M-1 are respectively connected with GND, the drains of M1_0 to M1_M-1 are respectively connected with the lower stages of Rd_0 to Rd_M-1, and the gates of M1_0 to M1_M-1 are respectively connected with v_ctrl_1< N+1> to v_ctrl_1< N+M >.
Wherein the control logic of (n+m+1) degenerate control signals v_ctrl_1<0:n+m > and the above (n+m+1) controlled switch modules (sw1_u_0 to sw1_u_n and sw1_d_0 to sw1_d_m-1) are shown in table 2.
TABLE 2
As shown in fig. 9, the simulation results of the circuit transient simulation of the charge pump shown in fig. 7 show that waveforms 901 to 903 respectively generate clk_1, clk_1b and clk_2 for clk_0; waveform 904 is a voltage waveform output by the low power consumption charge pump circuit with an adjustable output voltage that can implement a step-down function. The input voltage (power supply voltage Vin) corresponding to waveform 904 is 1.0V, and the target output voltage of the charge pump circuit is set to 330mV. As can be seen from fig. 9, the output voltage of the actual charge pump circuit is stabilized at 330mV at about 2 microseconds, so that the expected function can be correctly realized.
Fig. 10 corresponds to fig. 5, and compared with fig. 7, the embodiment of the present application improves ctrl_1 in fig. 7 to ctrl_1_pr (see fig. 5), wherein the connection and the function of the three input terminals (Vin, GND and v_ctrl_1<0:n+m >) are maintained unchanged, and the added input terminal is one clock signal input port, and the clock signal input port is connected to clk_1 of the output of clk_0.
Fig. 11 differs from fig. 8 only in that ctrl_1_pr connects one NMOS transistor mn1_m in series between one end of mn1_0 to mn1_m-1 near GND and GND. The drain of Mn1_M is connected to the sources of Mn1_0 through Mn1_M-1, the source of Mn1_M is connected to GND, and the gate chain of Mn1_M is connected to clk_1.
In some embodiments of the present application, the adjustable voltage output circuit 10 further includes a bias current input terminal, and as shown with reference to fig. 12, the adjustable voltage output circuit ctrl_2 corresponds to the adjustable voltage output circuit 10 in fig. 1 or 2; CTRL_2 is a four-input single-output module, four input ends (a first power supply voltage input end, a first grounding end, a control signal input end and a bias current input end) are correspondingly connected with a power supply voltage Vin, a ground voltage GND, and (P+Q+1) degenerate control signals v_ctrl_2<0:P+Q > and bias currents I_bias respectively, and one output end (a voltage signal output end) outputs v_bias_2 to be connected with one end of SW_2;
It can be appreciated that CTRL_2 functions to convert Vin to βVin (2. Gtoreq.βgtoreq.1) and to output βVin as v_bias_2 output from the voltage signal output terminal of CTRL_2 to one terminal of SW_2. Correspondingly, vout= (beta/2) Vin, namely (beta/2) times the power supply voltage, and 1 is more than or equal to beta/2 is more than or equal to 1/2, so that Vin can be reduced by any multiple of more than or equal to 1/2 and less than or equal to 1 through the scheme.
In some embodiments of the application, the array conditioning circuit includes a third parallel branch and a fourth parallel branch connected in series; the third parallel branch includes 1 st to P-th series branches connected in parallel; the fourth parallel branch comprises a P+1st to P+Q series branch connected in parallel; the jth series branch correspondingly comprises a jth switching tube and a jth resistor which are connected in series; j is any positive integer from 1 to P+Q;
The third parallel branch and the fourth parallel branch are connected in series to form an array regulating circuit, and the array regulating circuit is connected between the bias current input end and the first grounding end in a bridging way; the second common connection point of the third parallel branch and the fourth parallel branch is electrically connected with the first power supply voltage input end; the bias current input end is electrically connected with the voltage signal output end;
the array adjusting circuit is used for accessing or removing the j-th serial branch under the control of the control signal input by the control signal input end to obtain a target serial branch, and transmitting a first voltage signal with a second amplitude to the output switching circuit based on the voltage division of the power supply voltage by the resistor in the target serial branch.
In some embodiments of the application, the third parallel branch further comprises a p+q+1-th switching tube connected in parallel with the 1 st to P-th series branches; the control electrode of the P+Q+1 switching tube is electrically connected with the control signal input end; the P+Q+1 switching tube is used for conducting or disconnecting the electric connection between the first power supply voltage input end and the voltage signal output end under the action of a control signal input by the control signal input end;
Correspondingly, the array adjusting circuit is configured to output, as the first voltage signal, a signal input by the first power supply voltage input end to the output switching circuit, where the first power supply voltage input end is electrically connected to the voltage signal output end; and under the condition that the first power supply voltage input end is disconnected from the voltage signal output end, outputting the first voltage signal with the second amplitude to the output switching circuit.
In the embodiment of the present application, referring to fig. 13, the 1 st to P-th switching tubes and the p+q+1 st switching tubes correspond to the 1 st controlled switching modules sw2_u_0 to (p+1) th controlled switching modules sw2_u_p, the p+1 st to p+q switching tubes correspond to the (p+2) th controlled switching modules sw2_d_0 to (p+q+1) th controlled switching modules sw2_d_q-1, the 1 st to P-th resistors correspond to the 1 st high-order resistors ru_0 to ru_p-1, and the p+1 st to p+q resistors correspond to the 1 st low-order resistors rd_0 to Q low-order resistors rd_q-1, respectively;
Wherein the first controlled switch module sw2_u_0 is connected between v_bias_2 and the upper stage of the first high-order resistor ru_0, the second controlled switch module sw2_u_1 is connected between v_bias_2 and the upper stage of the second high-order resistor ru_1, and so on, the P-th controlled switch module sw2_u_p-1 is connected between v_bias_2 and the upper stage of the P-th high-order resistor ru_p-1;
In particular, the (p+1) -th controlled switching module sw2_u_p is connected between the output voltages v_bias_2 and Vin; the (P+2) -th controlled switching module SW2_d_0 is connected between the lower stage of the first low-level resistor Rd_0 and GND, the (P+3) -th controlled switching module SW1_d_1 is connected between the lower stage of the second low-level resistor Rd_1 and GND, and so on, the (P+Q+1) -th controlled switching module SW1_d_Q-1 is connected between the lower stage of the Q-th low-level resistor Rd_Q-1 and GND;
The lower stages of the first high-order resistor Ru_0, the second high-order resistor Ru_1 and the P-th high-order resistor Ru_P-1 and the upper stages of the first low-order resistor Rd_0, the second low-order resistor Rd_1 and the Q-th low-order resistor Rd_Q-1 are connected to Vin; the third input voltage, i.e., (P+Q+1) degenerate control signals v_ctrl_2<0:P+Q >, are used as control signals to control the opening and closing of the (P+Q+1) controlled switch modules respectively, i.e., the first control signal v_ctrl_2<0> controls the opening and closing of SW2_u_0, the second control signal v_ctrl_2<1> controls the opening and closing of SW2_u_1, and so on, the (P+Q+1) th control signal v_ctrl_2< P+Q > controls the opening and closing of SW 2_d_Q-1; the fourth input is i_bias, which acts to inject current into the v_bias_2 node.
In some embodiments of the present application, the 1 st to p+q resistances are equal in resistance; the second amplitude is equal to a second multiple of the amplitude of the supply voltage; the second multiple is equal to a quotient of a second total number and a third number; the second total number represents a sum of the third number and a fourth number; the third number is greater than the fourth number; the third number represents the number of series branches belonging to the 1 st to P th series branches in the target series branch; the fourth number represents the number of series branches belonging to the p+1st to p+q series branches in the target series branch.
It will be appreciated that the second multiple corresponds to β.
From an analysis of fig. 13, it can be seen that β has a value as shown in table 3 below.
TABLE 3 Table 3
Here, in order to facilitate calculation and display rules, the values of all resistors are deduced to be consistent, but the values of the resistors can be selected according to specific situations when the actual design is applied.
As can be seen from table 3, as the P or Q value increases (the number of upper and lower resistors increases), the finer degree of adjustment of the output voltage by ctrl_2 is higher. But the increase in the number of resistors at the high and low positions also increases the area overhead. However, the area overhead of the charge pump circuit structure provided by the embodiments of the present application is still relatively small compared to the charge pump circuit structure of the same precision.
In a word, the technical scheme of the embodiment of the application can solve the technical problem of low output adjustable voltage regulation fineness of the charge pump to a certain extent.
In some embodiments of the application, the array conditioning circuit further comprises a p+q+2-th switching tube; the control electrode of the P+Q+2 switching tube is connected with the output end of the clock signal generating circuit; the P+Q+2 switching tube is connected in series between a fourth parallel branch and the first grounding end;
The p+q+2 switching tube is configured to disconnect the electrical connection between the fourth parallel branch and the first ground terminal under the condition that the clock signal output by the clock signal generating circuit controls the capacitor in the charge pump assembly to discharge, so that the array adjusting circuit stops working; under the condition that the clock signal output by the clock signal generating circuit controls the capacitor in the charge pump assembly to charge, the electric connection between the second parallel branch and the first grounding end is conducted, so that the j-th serial branch is connected or removed by the array adjusting circuit under the control of the control signal input by the control signal input end, and the target serial branch is obtained.
In the embodiment of the present application, referring to fig. 14, the adjustable voltage output circuit ctrl_2_pr corresponds to the adjustable voltage output circuit 10 in fig. 1 or fig. 2; ctrl_2_pr is a four-input single-output module, and four inputs (a first power supply voltage input terminal, a first ground terminal, a control signal input terminal, and a bias current input terminal) are connected and function is unchanged, and a clock signal input terminal connected to an output clock signal Φ1 of clk_0 is added, as compared with fig. 12.
In the embodiment of the present application, as shown in fig. 15, compared with fig. 13, in the adjustable voltage output circuit ctrl_2_pr, sw2_d_0 to sw2_d_q_1 are connected in series between one end close to GND and GND of the controlled switch module sw2_pr, the control input terminal of sw2_pr is connected Φ1, and the opening and closing of sw2_pr is controlled by Φ1.
As can be seen from fig. 15, ctrl_2_pr operates only with sw2_pr closed and outputs a voltage signal via v_bias_2, and ctrl_2_pr does not operate with sw2_pr open. Since Φ1 simultaneously controls the opening and closing of sw2_pr, sw_2, and sw_3, and charges the capacitor c_1 with Φ1 controlling the sw_2 and sw_3 to be closed, ctrl_2_pr operates only with the capacitor charged, and thus, power consumption of ctrl_2_pr can be reduced, thereby reducing power consumption of the charge pump circuit.
Compared with fig. 12, fig. 16 corresponds to fig. 7, in the embodiment of the present application, only ctrl_1 in fig. 7 is replaced by ctrl_2, four input terminals of ctrl_2 are respectively connected to Vin, GND, v _ctrl2 <0:p+q > and i_bias, and output terminals are connected to v_bias_2.
FIG. 17 corresponds to FIG. 13, and compared with FIG. 13, the Sb2_u_0 to Sb2_u_P are respectively composed of (P+1) PMOS transistors Mp2_0 to Mp2_P, the sources of Mp2_0 to Mp2_P are respectively connected with v_bias_2, the drains of Mp2_0 to Mp2_P-1 are respectively correspondingly connected with the upper stages of Ru_0 to Ru_P-1, and the drains of Mp2_P are connected with Vin; the gates of Mp2_0 to Mp2_P are respectively connected with v_ctrl_2<0> to v_ctrl_2<P >;
The SW2_d_0 to SW2_d_Q-1 are composed of Q NMOS transistors MN2_0 to MN2_Q-1, respectively, the sources of the MN2_0 to MN2_Q-1 are connected with GND, the drains of the MN2_0 to MN2_Q-1 are correspondingly connected with the lower stages of the Rd_0 to Rd_Q-1, respectively, and the gates of the MN2_0 to MN2_Q-1 are correspondingly connected with v_ctrl_2< P+1> to v_ctrl_2< P+Q >.
Wherein v_ctrl_2<0:p+q > and sw2_u_0 to sw2_u_ P, SW2_d_0 to sw2_d_q-1 are described in table 4.
TABLE 4 Table 4
Fig. 18 corresponds to fig. 16, and compared with fig. 7, the embodiment of the present application improves ctrl_2 in fig. 7 to ctrl_2_pr (see 16), wherein the connection and the function of four inputs (Vin, GND, v _ctrl_1<0:p+q > and i_bias) remain unchanged, and the added input is one clock signal input port, which is connected to clk_1 of the output of clk_0.
In fig. 19, compared with fig. 17, the difference is only that ctrl_2_pr connects an NMOS transistor mn2_q in series between one end of mn2_0 to mn2_q-1 near GND and GND, the drain of mn2_q is connected to the sources of mn2_0 to mn2_q-1, the source of mn2_q is connected to GND, and the gate of mn2_q is connected to clk_1.
On the basis of the above embodiments, the embodiments of the present application provide a chip, where the chip includes any one of the charge pumps described above.
The embodiment of the application also provides a main board, which comprises the chip. The chip can be used as a carrier by using a circuit board, and a processor, a power circuit and the like are fixed on the circuit board in a welding mode to manufacture an expansion main board. The main board is simple in structure, small in area overhead and free of risk of loop structural stability.
The embodiment of the application also provides electronic equipment, which comprises the charge pump circuit structure, the chip or the main board. The charge pump circuit structure, the chip or the main board can be applied to a general-purpose computer or an industrial control computer so as to reduce the complexity of structural design and the area overhead and achieve the effect of saving the cost.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or terminal device that comprises the element.
The charge pump, the chip, the main board and the computer equipment provided by the application are described in detail, and specific examples are applied to the principle and the implementation of the application, and the description of the examples is only used for helping to understand the method and the core idea of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (12)
1. A charge pump, comprising: an adjustable voltage output circuit, an output switching circuit and a clock signal generating circuit;
The adjustable voltage output circuit comprises a first power supply voltage input end, a first grounding end, a control signal input end, a voltage signal output end and an array adjusting circuit electrically connected with each end; the array adjusting circuit comprises at least one switch tube and a resistor; the control electrode of each switching tube in the array regulating circuit is electrically connected with the control signal input end;
The output switching circuit comprises a pump capacitor, a switching switch component, a second power supply voltage input end, a clock signal input end, a second grounding end and a target voltage output end;
the voltage signal output end of the adjustable voltage output circuit is electrically connected with the second power supply voltage input end of the output switching circuit, and the adjustable voltage output circuit is used for transmitting a first voltage signal to the second power supply voltage input end under the control of a control signal input by the control signal input end;
the clock signal generating circuit generates at least two clock signals for controlling a change-over switch component in the output switching circuit;
The output switching circuit reduces the voltage of the first voltage signal under the control of the at least two clock signals, and outputs an obtained target voltage signal through the target voltage output end;
The array conditioning circuit includes at least one parallel branch connected in series; each of the parallel branches comprises at least one series branch electrically connected in parallel; each of the series branches comprises at least one switching tube and at least one resistor electrically connected in series; the control electrode of each switching tube is electrically connected with the control signal input end; the switch assembly includes first to fourth switch assemblies; the control electrodes of the first to fourth transfer switch components are connected with the clock signal input end; the second change-over switch component is connected between the second power supply voltage input end and the upper polar plate of the pump capacitor; the first switch component is connected between a lower polar plate of the pump capacitor and the second grounding end; the third change-over switch component is connected between the lower polar plate of the pump capacitor and the target voltage output end; the fourth change-over switch component is connected between the upper polar plate of the pump capacitor and the target voltage output end;
the clock signals include a first clock signal and a second clock signal that are non-overlapping; charging the pump capacitor through the first voltage signal under the condition that the first clock signal controls the second and the third transfer switch assemblies to be both on and the second clock signal controls the first and the fourth transfer switch assemblies to be both off; discharging the pump capacitor under the condition that the first clock signal controls the second switching switch assembly and the third switching switch assembly to be disconnected and the second clock signal controls the first switching switch assembly and the fourth switching switch assembly to be conducted;
And under the condition of charging and discharging the pump capacitor, the first voltage signal is reduced to the target voltage signal and is output through the target voltage output end.
2. The charge pump of claim 1, wherein the array conditioning circuit comprises a first parallel branch and a second parallel branch connected in series; the first parallel branch comprises 1 st to N th serial branches connected in parallel; the second parallel branch comprises an n+1th to n+Mth series branch connected in parallel; the ith serial branch circuit correspondingly comprises an ith switching tube and an ith resistor which are connected in series; i is any positive integer from 1 to n+m; the control electrode of the ith switching tube is electrically connected with the control signal input end;
The first parallel branch and the second parallel branch are connected in series to form the array adjusting circuit, and the array adjusting circuit is connected between the first power supply voltage input end and the first grounding end in a bridging manner; the first connecting point of the first parallel branch and the second parallel branch is electrically connected with the voltage signal output end;
the array adjusting circuit is used for accessing or removing the ith serial branch under the control of a control signal input by the control signal input end to obtain a target serial branch, and transmitting a first voltage signal with a first amplitude to the output switching circuit based on the voltage division of the power supply voltage by the resistor in the target serial branch.
3. The charge pump of claim 2, wherein the 1 st to n+m resistances are equal in resistance; the first amplitude is equal to the amplitude of the power supply voltage by a first multiple; the first multiple is equal to a quotient of the first number and the first total number; the first total number represents a sum of the first number and a second number; the first number represents the number of series branches belonging to the 1 st to nth series branches in the target series branch; the second number represents the number of series branches belonging to the n+1th to n+mth series branches in the target series branch.
4. The charge pump of claim 1, wherein the adjustable voltage output circuit further comprises a bias current input; the array regulating circuit comprises a third parallel branch and a fourth parallel branch which are connected in series; the third parallel branch includes 1 st to P-th series branches connected in parallel; the fourth parallel branch comprises a P+1st to P+Q series branch connected in parallel; the jth series branch correspondingly comprises a jth switching tube and a jth resistor which are connected in series; j is any positive integer from 1 to P+Q; the control electrode of the j-th switching tube is electrically connected with the control signal input end;
The third parallel branch and the fourth parallel branch are connected in series to form the array adjusting circuit, and the array adjusting circuit is connected between the bias current input end and the first grounding end in a bridging way; the second common connection point of the third parallel branch and the fourth parallel branch is electrically connected with the first power supply voltage input end; the bias current input end is electrically connected with the voltage signal output end;
the array adjusting circuit is used for accessing or removing the j-th serial branch under the control of the control signal input by the control signal input end to obtain a target serial branch, and transmitting a first voltage signal with a second amplitude to the output switching circuit based on the voltage division of the power supply voltage by the resistor in the target serial branch.
5. The charge pump of claim 4, wherein the resistances of the 1 st to p+q resistances are equal; the second amplitude is equal to a second multiple of the amplitude of the supply voltage; the second multiple is equal to a quotient of a second total number and a third number; the second total number represents a sum of the third number and a fourth number; the third number is greater than the fourth number; the third number represents the number of series branches belonging to the 1 st to P th series branches in the target series branch; the fourth number represents the number of series branches belonging to the p+1st to p+q series branches in the target series branch.
6. The charge pump of claim 2, wherein the first parallel branch further comprises an n+m+1-th switching tube connected in parallel with the 1 st to N-th series branches; the control electrode of the (N+M+1) th switching tube is electrically connected with the control signal input end;
The n+M+1 switching tube is used for conducting or disconnecting the electric connection between the first power supply voltage input end and the voltage signal output end under the action of a control signal input by the control signal input end;
Correspondingly, the array adjusting circuit is configured to output, as the first voltage signal, a signal input by the first power supply voltage input end to the output switching circuit, where the first power supply voltage input end is electrically connected to the voltage signal output end; and under the condition that the first power supply voltage input end is disconnected from the voltage signal output end, outputting the first voltage signal with the first amplitude value to the output switching circuit.
7. The charge pump of claim 2, wherein the array conditioning circuit further comprises an n+m+2 switch tube; the control electrode of the n+M+2 switching tube is connected with the output end of the clock signal generating circuit; the n+M+2 switching tube is connected in series between the second parallel branch and the first grounding end;
The n+m+2 switching tube is configured to disconnect the electrical connection between the second parallel branch and the first ground terminal when the clock signal output by the clock signal generating circuit controls the pump capacitor in the charge pump to discharge, so that the array adjusting circuit stops working; under the condition that the clock signal output by the clock signal generating circuit controls the pump capacitor in the charge pump to charge, the electric connection between the second parallel branch and the first grounding end is conducted, so that the array adjusting circuit is connected into or removed from the ith serial branch under the control of the control signal input by the control signal input end, and the target serial branch is obtained.
8. The charge pump of claim 4, wherein the third parallel branch further comprises a p+q+1-th switching tube connected in parallel with the 1 st to P-th series branches; the control electrode of the P+Q+1 switching tube is electrically connected with the control signal input end; the P+Q+1 switching tube is used for conducting or disconnecting the electric connection between the first power supply voltage input end and the voltage signal output end under the action of a control signal input by the control signal input end;
Correspondingly, the array adjusting circuit is configured to output, as the first voltage signal, a signal input by the first power supply voltage input end to the output switching circuit, where the first power supply voltage input end is electrically connected to the voltage signal output end; and under the condition that the first power supply voltage input end is disconnected from the voltage signal output end, outputting the first voltage signal with the second amplitude to the output switching circuit.
9. The charge pump of claim 4, wherein the array conditioning circuit further comprises a p+q+2-th switching tube; the control electrode of the P+Q+2 switching tube is connected with the output end of the clock signal generating circuit; the P+Q+2 switching tube is connected in series between a fourth parallel branch and the first grounding end;
The p+q+2 switching tube is configured to disconnect the electrical connection between the fourth parallel branch and the first ground terminal when the clock signal output by the clock signal generating circuit controls the pump capacitor in the charge pump to discharge, so that the array adjusting circuit stops working; and under the condition that the clock signal output by the clock signal generating circuit controls the pump capacitor in the charge pump to charge, the electrical connection between the fourth parallel branch and the first grounding end is conducted, so that the j-th serial branch is connected or removed by the array regulating circuit under the control of the control signal input by the control signal input end, and the target serial branch is obtained.
10. A chip comprising a charge pump as claimed in any one of claims 1 to 9.
11. A motherboard comprising the chip of claim 10.
12. An electronic device comprising the motherboard of claim 11.
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| CN102594130A (en) * | 2011-01-10 | 2012-07-18 | 中兴通讯股份有限公司 | Method for outputting constant difference voltage and charge pump circuit |
| CN112165250A (en) * | 2020-10-12 | 2021-01-01 | 唯捷创芯(天津)电子技术股份有限公司 | Charge pump circuit, chip and communication terminal |
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| US8462578B2 (en) * | 2011-05-23 | 2013-06-11 | Freescale Semiconductor, Inc. | Charge pump circuit with fast start-up |
| US9190903B2 (en) * | 2013-12-20 | 2015-11-17 | Infineon Technologies, Ag | System and method for a controlled feedback charge pump |
| CN104518663B (en) * | 2014-07-18 | 2017-03-29 | 上海华虹宏力半导体制造有限公司 | Negative pressure charge pump feedback circuit |
| US9553572B2 (en) * | 2014-11-18 | 2017-01-24 | Silicon Laboratories Inc. | Self clocking comparator for a charge pump |
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| CN102594130A (en) * | 2011-01-10 | 2012-07-18 | 中兴通讯股份有限公司 | Method for outputting constant difference voltage and charge pump circuit |
| CN112165250A (en) * | 2020-10-12 | 2021-01-01 | 唯捷创芯(天津)电子技术股份有限公司 | Charge pump circuit, chip and communication terminal |
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