CN115939033B - Method for making metal bumps and flip chip interconnection method - Google Patents

Abstract

The present application relates to a method for making metal bumps and a flip chip interconnection method. The method for making metal bumps includes: forming a seed layer on a substrate; forming a first photoresist pattern on the seed layer, wherein the first photoresist pattern exposes a portion of the seed layer; etching to remove the seed layer exposed outside the first photoresist pattern, and then removing the remaining first photoresist pattern; forming a second photoresist pattern, wherein the second photoresist pattern exposes the seed layer; electroplating the seed layer to form an under-bump metal and a metal bump using an electrochemical deposition process; and removing the second photoresist pattern. In one embodiment, the material of the second photoresist pattern is SU8 photoresist. The above-mentioned method for making metal bumps and the above-mentioned metal bumps obtained can be well applied to the ultra-fine pitch and height-adjustable flip chip interconnection process.

Description

Method for making metal bumps and flip chip interconnection method

Technical Field

The present application belongs to the field of semiconductor processing, and in particular relates to a method for manufacturing metal bumps and a flip chip interconnection method.

Background technique

With the rapid development of the semiconductor industry, chip packaging is developing towards the trend of increasing the number of pins and reducing the package volume, and the key technology is the bump flip-chip process. Therefore, it is inevitable that the flip-chip technology is also facing the pressure of the bumps becoming smaller and the bump density becoming larger. The chip flip-chip technology process includes the main processes such as the preparation of the metallization layer under the bump, the preparation of the bump, and the reflow soldering. Among them, the preparation of the bump is the key technology for the realization of the entire packaging method, which has a decisive influence on other process steps. Usually, the main methods for preparing bumps are: electrochemical deposition, nail head bump method, metal mask evaporation method, screen printing, ball planting method, and solder jetting method.

Taking into account the size, shape control, bump spacing, production efficiency and cost advantages of the bumps, with the help of advanced photolithography technology, the electrochemical deposition process is the bump preparation technology that can flexibly control the size and spacing of the bumps and has extremely low cost. It can also meet the current ultra-high density (ball diameter below 100μm) bump preparation requirements and has great application value.

However, the trend toward high integration and high density results in low yield, complex process and low efficiency of the above-mentioned bump preparation process.

Summary of the invention

According to a first aspect of the present application, a method for manufacturing a metal bump is provided, comprising:

forming a seed layer on a substrate;

forming a first photoresist pattern on the seed layer, wherein the first photoresist pattern exposes a portion of the seed layer;

Etching and removing the seed layer exposed outside the first photoresist pattern, and then removing the remaining first photoresist pattern;

forming a second photoresist pattern, wherein the second photoresist pattern exposes the seed layer;

Electroplating the seed layer to form under-bump metal and metal bumps using an electrochemical deposition process;

The second photoresist pattern is removed.

The above-mentioned method for making metal bumps can use a thicker (75-85 microns) second photoresist pattern as a dielectric layer/sacrificial layer to limit the direction and morphology of the metal bumps formed by subsequent electroplating, so that the metal bump solder with a height of less than 150 microns (μm) can be regulated to grow, solving the problem of adjustable solder height. In addition, the metal under the bump and the metal bump formed by the electrochemical deposition process have strong directionality, high quality and good uniformity, thus solving the problem of difficult laser ball planting.

In the above-mentioned method for making metal bumps, the seed layer in a part of the area is first etched away, and then the under-bump metal and the metal bump are formed by electroplating using an electrochemical deposition process, which is beneficial to reducing the process steps and improving the quality rate of the obtained structure.

Furthermore, before forming the seed layer, an oxidized insulating layer is first grown on the surface of the substrate by a thermal oxidation method. The oxidized insulating layer formed by thermal oxidation can prevent unnecessary electrical interconnection of the pads or electrical structures below.

Furthermore, before thermal oxidation, the surface of the substrate is provided with an electrode strip, a plurality of pads and a plurality of connecting wires, one electrode strip is connected to a plurality of pads, and each pad is electrically connected to the electrode strip through the connecting wire. In the subsequent electrochemical deposition process, by applying a voltage to the electrode strip, the voltage can be applied to the plurality of pads at the same time.

Furthermore, the electrode strips are arranged on the peripheral side of the substrate. The electrode strips arranged on the peripheral side of the substrate do not affect the arrangement of the chips in the middle area, and are also convenient for cutting off the electrode strips later.

Furthermore, the formed seed layer includes a first seed layer and a second seed layer.

Furthermore, the material of the first seed layer includes titanium, and the material of the second seed layer includes gold or copper.

Furthermore, the first seed layer and the second seed layer are formed by magnetron sputtering or electron beam evaporation process.

Further, the step of forming the second photoresist pattern includes:

spin coating a second photoresist layer;

The second photoresist layer above the seed layer is removed by a photolithography process, and the second photoresist layer located at the periphery of the seed layer is retained to form a second photoresist pattern.

Furthermore, the material of the second photoresist layer and the second photoresist pattern is SU8 photoresist.

Furthermore, the thickness of the second photoresist pattern is 75 micrometers to 85 micrometers.

Furthermore, the height of the second photoresist pattern is greater than the height of the seed layer, so as to form an accommodating space above the seed layer.

Furthermore, the under-bump metal formed by electroplating using an electrochemical deposition process is completely located in the accommodation space above the seed layer; a portion of the metal bump formed by electroplating using an electrochemical deposition process is located in the accommodation space above the seed layer, and another portion is exposed from the accommodation space.

Furthermore, the under bump metal includes a nickel layer.

Furthermore, the thickness of the nickel layer is 2.5-3.5 microns.

Furthermore, the metal bumps include a gold layer or a copper layer at the bottom and a tin layer at the top.

Furthermore, the thickness of the gold layer or copper layer is 300-500 nanometers, and the thickness of the tin layer is 90-110 micrometers.

Furthermore, before the step of removing the second photoresist pattern, a reflow process is performed;

Through the reflow process, the metal protrusion portion exposed from the accommodating space will form an arc-shaped protrusion portion.

Furthermore, the arc-shaped convex point portion is spherical or hemispherical.

Furthermore, the temperature of the reflow process is controlled between 130-140° C., and the duration of the reflow process is 50-70 minutes.

According to a second aspect of the present application, a flip chip interconnection method is provided, comprising:

Making metal bumps using the method described above;

Cutting the substrate to form multiple independent chips;

The flip chip is welded to complete the package.

The above flip chip interconnection method can use a thicker (75-85 microns) second photoresist pattern as a dielectric layer/sacrificial layer to limit the direction and morphology of the metal bumps formed by subsequent electroplating, so that the metal bump solder with a height of less than 150 microns (μm) can be regulated to grow, solving the problem of adjustable solder height. In addition, the metal under bump and metal bumps formed by the electrochemical deposition process have strong directionality, high quality and good uniformity, thus solving the problem of difficult laser ball planting.

In the above flip chip interconnection method, the seed layer in a part of the area is first etched away, and then the under bump metal and metal bumps are formed by electroplating using an electrochemical deposition process, which is conducive to reducing process steps and improving the quality rate of the obtained structure.

Furthermore, during the welding process, the pressure is 400-600 Newtons and the temperature is controlled at 105-115°C.

It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

FIG. 1 is a flow chart of a method for manufacturing a metal bump according to an embodiment of the present application.

2 to 10 are schematic diagrams of various intermediate structures obtained in the process of manufacturing metal bumps according to embodiments of the present application.

Implementation

Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "one" or "one" and the like used in this application specification and claims do not indicate a quantitative limitation, but indicate the existence of at least one. "Multiple" means two or more. "Including" or "including" and the like mean that the elements or objects appearing in front of "including" or "including" include the elements or objects listed after "including" or "including" and their equivalents, and do not exclude other elements or objects. "Connected" or "connected" and the like are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect. "On" and/or "below" and the like are only for the convenience of explanation, and are not limited to a position or a spatial orientation. The singular forms of "one", "said" and "the" used in this application specification and the attached claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The present application provides a method for manufacturing a metal bump, as shown in FIG1 , comprising:

Step S10: forming a seed layer on the substrate;

Step S20: forming a first photoresist pattern on the seed layer, wherein the first photoresist pattern exposes a portion of the seed layer;

Step S30: etching and removing the seed layer exposed outside the first photoresist pattern, and then removing the remaining first photoresist pattern;

Step S40: forming a second photoresist pattern, wherein the second photoresist pattern exposes the seed layer;

Step S50: electroplating the seed layer to form an under-bump metal and a metal bump by using an electrochemical deposition process;

Step S60: removing the second photoresist pattern.

The above-mentioned method for making metal bumps can use a thicker (75-85 microns) second photoresist pattern (SU-8 photoresist) as a dielectric layer/sacrificial layer to limit the direction and morphology of the metal bumps formed by subsequent electroplating, so that the metal bump solder with a height of less than 150 microns (μm) can be regulated to grow, solving the problem of adjustable solder height. In addition, the metal under the bump and the metal bump formed by the electrochemical deposition process have strong directionality, high quality and good uniformity, thus solving the problem of difficult laser ball implantation.

In the above-mentioned method for making metal bumps, the seed layer in a part of the area is first etched away, and then the under-bump metal and the metal bump are formed by electroplating using an electrochemical deposition process, which is beneficial to reducing the process steps and improving the quality rate of the obtained structure.

The method for manufacturing the metal bumps and the metal bumps prepared are well suited for use in a flip chip interconnection process with ultra-fine spacing and adjustable height.

The method for manufacturing the above-mentioned metal bumps will be described in detail below in conjunction with specific embodiments and drawings.

Referring to FIG. 2 , before step S10 , step S05 may be performed first: growing an oxide insulating layer 30 on the surface of the substrate 20 by a thermal oxidation method.

The substrate 20 may be a silicon-based wafer, the grown oxidized insulating layer 30 may be silicon dioxide, and the thickness of the grown oxidized insulating layer 30 may be 2 micrometers (μm).

Before thermal oxidation, the surface of the substrate 20 may be provided with a plurality of pads 82, as shown in FIG3. During the thermal oxidation process, the area where the pads are located will not be oxidized, so the pads are still exposed to the outside and can be electrically connected to the bumps formed subsequently. That is, the grown oxidized insulating layer 30 does not have to cover the entire surface of the substrate 20.

The surface of the substrate 20 may also be provided with long strips of electrode strips 84, and the number of electrode strips 84 may be one or more. One electrode strip 84 is connected to multiple pads 82 at the same time. In the electrochemical deposition process, by applying a voltage to the electrode strip 84, the voltage can be applied to multiple pads 82 at the same time. Each pad 82 is connected to the electrode strip 84 through a connecting wire 86. The electrode strip 84 can be arranged on the peripheral side of the substrate 20, so as not to affect the arrangement of the pads 82 and the chip in the middle area. During subsequent cutting, the electrode strip 84 and the connecting wire 86 are cut off and are not part of the chip.

The oxidized insulating layer 30 formed by thermal oxidation can prevent unnecessary electrical interconnection of the pads or electrical structures therebelow.

In step S10 , the seed layer formed may be a single layer or multiple layers.

2 , the formed seed layer includes a first seed layer 40 and a second seed layer 50. The first seed layer 40 may be titanium (Ti), and the second seed layer 50 may be gold (Au) or copper (Cu). The thickness of the first seed layer 40 may be 20 nanometers (nm), and the thickness of the second seed layer 50 may be 50 nanometers (nm).

The first seed layer 40 and the second seed layer 50 may be formed by magnetron sputtering or electron beam (thermal) evaporation process.

4, in step S20, the formed first photoresist pattern P1 exposes a portion of the second seed layer 50 below. The position of the first photoresist pattern P1 corresponds to the position of the metal bump to be formed, and also corresponds to the position of the pad below.

In specific implementation, a first photoresist layer may be formed by spin coating on the second seed layer 50, and the first photoresist layer covers the entire surface. The material of the first photoresist layer may be AZ6130 photoresist. Then, a mask is used for exposure, and the first photoresist pattern P1 may be obtained after photolithography and development.

In step S30, the second seed layer 50 and the first seed layer 40 not covered by the first photoresist pattern P1 may be removed by ion beam etching (IBE). Due to the shielding protection of the first photoresist pattern P1, the second seed layer 50 and the first seed layer 40 under the first photoresist pattern P1 are retained.

Then, the remaining first photoresist pattern P1 may be removed. The formed structure is shown in FIG.

In the step S40, the step of forming a second photoresist pattern may include:

Spin-coat a whole second photoresist layer P22, wherein the thickness of the second photoresist layer P22 is greater than the thickness of the seed layer, and the formed structure is shown in FIG6 ;

The second photoresist layer P22 above the seed layer is removed by photolithography, and the second photoresist layer P22 around the seed layer is retained to form a second photoresist pattern P2, the structure formed is shown in Figure 7. The opening area in the second photoresist pattern P2 is the area where the metal bump is to be formed.

In one embodiment, the material of the second photoresist layer P22 and the second photoresist pattern P2 may be SU8-2038 photoresist. In one embodiment, the thickness of the second photoresist pattern P2 is 75 micrometers (μm) to 85 micrometers (μm).

In one embodiment, as shown in FIG. 7 , the height of the second photoresist pattern P2 is greater than the height of the seed layer, so as to form an accommodation space R above the seed layer for accommodating the metal bump to be formed.

The second photoresist layer P22 may be processed by ultraviolet lithography to obtain a second photoresist pattern P2. In one embodiment, the second photoresist layer P22 may be processed by ultraviolet lithography, comprising:

Step S41 - pretreatment: using an oven (such as a HDMS oven) to pretreat the surface of the substrate 20 and the surface of the seed layer to increase the surface hydrophobicity, thereby increasing the adhesion between the substrate, the seed layer and the photoresist;

Step S42 - evenly spread the photoresist: After the photoresist is applied, the rotation of the substrate 20 can be controlled in three stages. The set rotation speed of the first stage is 450-550rad/min, such as 500rad/min. The duration of the first stage is 8-12s, such as 10s; the duration includes the time for acceleration from zero to the set rotation speed, and the acceleration may be 500rad/s2. The set rotation speed of the second stage is 950-1050rad/min, such as 1000rad/min. The duration of the second stage is 35-45s, such as 40s; the duration includes the time for acceleration from the set speed of the first stage to the set rotation speed of the second stage, and the acceleration may be 500rad/s2. The third stage is a stage of gradually decelerating to zero. The duration of the third stage may be 4-8s, such as 6s;

Step S43 - soft baking: the temperature is controlled within the range of 0-60°C and the duration is 5 minutes;

Step S44 - exposure: includes three stages, and the energy per unit area is controlled at: (1) 280 mj/cm ² ; (2) 250 mj/cm ² ; (3) 240 mj/cm ² ;

Step S45 - medium baking: includes four stages, wherein the temperature of the first stage is set at 65°C-95°C, and the duration is 3-5 minutes; the temperature of the second stage is set at 95°C, and the duration is 40 minutes; the temperature of the third stage is set at 95°C-65°C, and the duration is 15 minutes; the fourth stage is natural cooling;

Step S46 - Development: using 1500 Thinner diluent, development time 5 minutes;

Step S47 - plasma cleaning: the power is set at 400 W and the cleaning time is 5 minutes.

In the above step S42, the thickness of the second photoresist layer P22 (SU-8 photoresist) can be easily controlled by switching different rotation speeds between multiple stages.

Please refer to Figure 8. In step S50, the under-bump metal 60 formed by electroplating using an electrochemical deposition process is completely located in the accommodating space R above the seed layer, a portion of the metal bump 70 formed by electroplating using an electrochemical deposition process is located in the accommodating space R above the seed layer, and another portion (the upper portion) of the metal bump 70 is exposed from the accommodating space R.

In one embodiment, the under-bump metal 60 includes a nickel layer (Ni). The thickness of the nickel layer may be 2.5-3.5 micrometers (μm), such as 3 micrometers. In one embodiment, the metal bump 70 includes a gold layer (Au) or a copper layer (Cu) located at the lower layer and a tin layer (Sn) located at the upper layer. The thickness of the gold layer or the copper layer may be 300-500 nanometers (nm), such as 400 nanometers; the thickness of the tin layer may be 90-110 micrometers (μm), such as 100 micrometers. The thickness of the gold layer or the copper layer and the thickness of the tin layer in the metal bump 70 can be well controlled by the second photoresist pattern P2, and the height difference of the flip-chip bonding between the chip and the substrate can be adjusted at will according to different usage scenarios.

In one embodiment, during the electrochemical deposition process, low current and low rate electroplating is used to form the under-bump metal and the metal bump, so as to further improve the quality, uniformity and adhesion of the coating. Thus, defects such as micro-holes and cracks inside the metal bump can be avoided, and subsequent problems such as bump breakage and insufficient adhesion can be prevented.

After step S50 and before step S60, step S55 - reflow process may be performed. Through the reflow process, the portion of the metal bump 70 exposed from the accommodation space R forms an arc-shaped bump portion 75, as shown in Fig. 9. The arc-shaped bump portion 75 may be spherical or hemispherical.

In one embodiment, the temperature of the reflow process is controlled between 130-140° C., such as 135° C., and the duration of the reflow process is 50-70 minutes, such as 1 hour.

In step S60 , the second photoresist pattern P2 can be removed by washing with acetone, ethanol and deionized water in sequence. The obtained structure is shown in FIG. 10 .

After step S60, step S70 may be performed: cutting the substrate 20 to form a plurality of independent chips. After cutting, the relative integrity and adaptability of each chip circuit must be ensured. During the cutting process, each metal bump structure is also cut to form a whole with the corresponding chip.

In one embodiment, the cutting may be accomplished using a hard knife.

After step S70, step S80 may be performed: flipping the chip for welding to complete the packaging. In one embodiment, during the welding process, the pressure between the chip and the substrate is maintained at 400-600 Newtons (N), such as 500 Newtons; the temperature is controlled at 105-115°C, such as 110°C; and the duration is 18-22 minutes, such as 20 minutes.

In the embodiment of the present application, a thicker (75-85 microns) second photoresist pattern (SU-8 photoresist) is used as a dielectric layer/sacrificial layer to limit the direction and morphology of the metal bumps formed by subsequent electroplating, so that the metal bump solder with a height of less than 150 microns (μm) can be regulated to grow, solving the problem of adjustable solder height. In addition, the metal under the bump and the metal bump formed by the electrochemical deposition process have strong directionality, high quality, and good uniformity, thereby solving the problem of difficult laser ball implantation.

In the embodiment of the present application, the seed layer of a part of the area is first etched away, and then the under-bump metal and the metal bump are formed by electroplating using an electrochemical deposition process, which helps to reduce the process steps and improve the yield of the resulting structure.

In the present application, various embodiments can complement each other if there is no conflict.

In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The terms "plurality" and "several" refer to two or more than two, unless otherwise clearly defined.

Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims (19)

1. A method for making a metal bump used in a flip chip process, comprising: forming a seed layer on a substrate; forming a first photoresist pattern on the seed layer, wherein the first photoresist pattern exposes a portion of the seed layer; Etching and removing the seed layer exposed outside the first photoresist pattern, and then removing the remaining first photoresist pattern; forming a second photoresist pattern, wherein the second photoresist pattern does not cover the seed layer and completely exposes the seed layer, and the thickness of the second photoresist pattern is 75 micrometers to 85 micrometers; Electroplating the seed layer to form under-bump metal and metal bumps using an electrochemical deposition process; removing the second photoresist pattern; Wherein, the height of the second photoresist pattern is greater than the height of the seed layer, so as to form an accommodating space above the seed layer. 2. The method for manufacturing a metal bump as claimed in claim 1, wherein before forming the seed layer, an oxide insulating layer is first grown on the surface of the substrate by a thermal oxidation method. 3. The method for manufacturing metal bumps as described in claim 2 is characterized in that before thermal oxidation, an electrode strip, a plurality of pads and a plurality of connecting wires are provided on the surface of the substrate, one electrode strip is connected to a plurality of pads, and each of the pads is electrically connected to the electrode strip via the connecting wire. 4 . The method for manufacturing a metal bump as claimed in claim 3 , wherein the electrode strips are arranged on the peripheral side of the substrate. 5 . The method for manufacturing a metal bump as claimed in claim 1 , wherein the formed seed layer comprises a first seed layer and a second seed layer. 6 . The method for manufacturing a metal bump as claimed in claim 5 , wherein the material of the first seed layer comprises titanium, and the material of the second seed layer comprises gold or copper. 7 . The method for manufacturing a metal bump according to claim 6 , wherein the first seed layer and the second seed layer are formed by magnetron sputtering or electron beam evaporation. 8. The method for making a metal bump according to claim 1, wherein the step of forming a second photoresist pattern comprises: spin coating a second photoresist layer; The second photoresist layer above the seed layer is removed by a photolithography process, and the second photoresist layer located at the periphery of the seed layer is retained to form a second photoresist pattern. 9. The method for manufacturing a metal bump as claimed in claim 8, wherein the material of the second photoresist layer and the second photoresist pattern is SU8 photoresist. 10. The method for manufacturing a metal bump as described in claim 8 is characterized in that the metal under bump formed by electroplating using an electrochemical deposition process is completely located in the accommodating space above the seed layer; a portion of the metal bump formed by electroplating using an electrochemical deposition process is located in the accommodating space above the seed layer, and another portion is exposed from the accommodating space. 11. The method for manufacturing a metal bump according to claim 10, wherein the under bump metal comprises a nickel layer. 12. The method for making a metal bump as claimed in claim 11, wherein the thickness of the nickel layer is 2.5-3.5 microns. 13. The method for manufacturing a metal bump according to claim 10, wherein the metal bump comprises a gold layer or a copper layer at a lower layer and a tin layer at an upper layer. 14. The method for manufacturing a metal bump according to claim 13, wherein the thickness of the gold layer or the copper layer is 300-500 nanometers, and the thickness of the tin layer is 90-110 micrometers. 15. The method for manufacturing a metal bump according to claim 10, wherein a reflow process is performed before removing the second photoresist pattern; Through the reflow process, the metal protrusion portion exposed from the accommodating space will form an arc-shaped protrusion portion. 16 . The method for manufacturing a metal bump according to claim 15 , wherein the arc-shaped bump portion is spherical or hemispherical. 17 . The method for manufacturing a metal bump according to claim 15 , wherein the temperature of the reflow process is controlled between 130° C. and 140° C., and the duration of the reflow process is 50 to 70 minutes. 18. A flip chip interconnection method, comprising: Making a metal bump using the method according to any one of claims 1 to 17; Cutting the substrate to form multiple independent chips; The flip chip is welded to complete the package. 19. The flip chip interconnection method according to claim 18, characterized in that during the welding process, the pressure is 400-600 Newtons and the temperature is controlled at 105-115°C.