CN115938439B - Nor Flash without sense expansion, sensing circuit and electronic equipment - Google Patents
Nor Flash without sense expansion, sensing circuit and electronic equipment Download PDFInfo
- Publication number
- CN115938439B CN115938439B CN202310016992.6A CN202310016992A CN115938439B CN 115938439 B CN115938439 B CN 115938439B CN 202310016992 A CN202310016992 A CN 202310016992A CN 115938439 B CN115938439 B CN 115938439B
- Authority
- CN
- China
- Prior art keywords
- flash
- sensing circuit
- selector
- rising edge
- input end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Read Only Memory (AREA)
Abstract
The invention relates to the technical field of integrated circuits, and particularly discloses a Nor Flash with non-inductive capacity expansion, a sensing circuit and electronic equipment, wherein the sensing circuit comprises: a plurality of open drain pads respectively connected with different sub-chips; the first ends of the pull-up resistors are connected with the output ends of all the open drain pads, and the second ends of the pull-up resistors are connected with the power supply voltage; the first end of the transistor is connected with the first end of the pull-up resistor, the second end of the transistor is grounded, and the third end of the transistor is connected with the main chip; the input end of the NOT gate is connected with the first end of the pull-up resistor; the first selector, its selection control end is connected with NAND gate output end, its one input end inputs the high level signal; the trigger input end of the register is connected with the output end of the first selector, and the output end of the register is connected with the other input end of the first selector; the sensing circuit can realize on-line monitoring of the running states of all the memory chips without actively returning each memory chip to the state.
Description
Technical Field
The application relates to the technical field of integrated circuits, in particular to a Nor Flash with noninductive capacity expansion, a sensing circuit and electronic equipment.
Background
The serial interface Nor Flash memory is a commonly used data storage component, and when a large capacity and a small package size are required, multiple Flash chips are generally stacked and packaged to expand the capacity, for example, two chips with a size of 256M can be changed into a Flash package with a size of 512M. The three-dimensional stacking and sealing scheme can reduce the packaging area to meet the miniaturization requirement.
In order to solve the problem of accurately accessing different chips during stacking, the existing Flash memory generally adopts a noninductive capacity expansion mode to perform Nor Flash stacking so as to form a packaging sheet, the whole packaging sheet has no difference with a large-capacity chip in view from the outside, and has only one chip selection signal input end, and the application function is also different from that of a general capacity expansion chip.
In the case of Nor Flash erase or program commands, the external host needs to read the status register to see if it is erased or programmed, whereas for these existing Nor Flash with no sense-amplifier, the status register needs to be returned to this state by the memory chip being programmed and erased. However, if the Suspend command is received and the program command is received by the memory chip that originally performs the erase operation in the read process, the memory chip cannot return to the state of the status register, so that the external host cannot accurately know whether the Nor Flash has completed the erase or program operation.
In view of the above problems, no effective technical solution is currently available.
Disclosure of Invention
The application aims to provide a Nor Flash with no sense expansion, a sensing circuit and electronic equipment, so as to realize on-line monitoring of the running states of all memory chips under the condition that each memory chip does not need to actively return to the state.
In a first aspect, the present application provides a sensing circuit of a non-inductive capacity-expansion Nor Flash, where the non-inductive capacity-expansion Nor Flash includes a main chip and a plurality of sub-chips that are stacked and sealed, and the sensing circuit includes:
the plurality of open drain pads are respectively connected with different sub-chips and are respectively used for outputting low-level signals when the corresponding sub-chip is in an erasing or programming state;
the first ends of the pull-up resistors are connected with the output ends of all the open drain pads, and the second ends of the pull-up resistors are connected with the power supply voltage;
the first end of the transistor is connected with the first end of the pull-up resistor, the second end of the transistor is grounded, and the third end of the transistor is connected with the main chip and is used for monitoring erasing state signals of the main chip;
the input end of the NOT gate is connected with the first end of the pull-up resistor;
the selection control end of the first selector is connected with the NOT gate output end, and one input end of the first selector inputs a high-level signal;
and the trigger input end of the register is connected with the output end of the first selector, and the output end of the register is used for outputting a busy state signal of Nor Flash and is connected with the other input end of the first selector.
The sensing circuit of the Nor Flash without the sense expansion monitors the execution states of the auxiliary chip and the main chip on line based on the open drain pad and the transistor, and when the main chip or the auxiliary chip executes erasing or programming actions, the sensing circuit can input low level into the NOT gate so that the first selector outputs high level to trigger the register to generate corresponding busy state signals.
The sensing circuit of the Nor Flash without the sense expansion further comprises a follower, and the first end of the pull-up resistor is connected with the input end of the NOT gate through the follower.
The follower can buffer (buf) the input signal, can prevent the change process of the level signal, can perform preliminary filtration on the signal, and improves the anti-interference capability of the whole sensing circuit.
The sensing circuit of the Nor Flash without the sense expansion further comprises a filter, and the follower is connected with the input end of the NOT gate through the filter.
The sensing circuit of the Nor Flash without sense expansion further comprises a first rising edge detection circuit, a second rising edge detection circuit and a second selector, wherein the output end of the first selector is connected with one input end of the second selector so as to be connected with the trigger input end of the register through the output end of the second selector, and the other input end of the second selector inputs a low-level signal;
the input end of the first rising edge detection circuit is connected with the filter, the output end of the first rising edge detection circuit is connected with the input end of the second rising edge detection circuit, and the output end of the second rising edge detection circuit is connected with the selection control end of the second selector.
The sensing circuit of the Nor Flash without the sense expansion further comprises a judging circuit, wherein the input end of the judging circuit is connected with the output end of the second rising edge detecting circuit, and the output end of the judging circuit is used for outputting an error state signal.
The sensing circuit of Nor Flash without sense expansion, wherein the first rising edge detection circuit and the second rising edge detection circuit are both delay signal generation circuits based on rising edge triggering.
The sensing circuit of Nor Flash without sense expansion, wherein the register is a D trigger.
The sensing circuit of Nor Flash without sense expansion, wherein the transistor is an NMOS tube.
In a second aspect, the present application further provides a non-inductive capacity-expansion Nor Flash, where the non-inductive capacity-expansion Nor Flash includes a main chip and a plurality of auxiliary chips that are stacked and sealed, and the main chip is provided with the sensing circuit of the non-inductive capacity-expansion Nor Flash provided in the first aspect.
According to the Nor Flash without sense expansion, the sensing circuit of the Nor Flash without sense expansion provided by the first aspect is installed in the main chip, so that an external host can accurately know whether a memory chip which is executing erasing or programming actions exists in the Nor Flash based on a busy state signal output by the main chip.
In a third aspect, the present application further provides an electronic device, where the electronic device includes the Nor Flash with no sense-of-expansion provided in the second aspect.
As can be seen from the above, the present application provides a non-inductive capacity-expansion Nor Flash, a sensing circuit and an electronic device, wherein the sensing circuit monitors the execution states of a secondary chip and a primary chip on line based on an open drain pad and a transistor, when the primary chip or the secondary chip executes an erasing or programming action, both the sensing circuit can input a low level to a NOT gate so that a first selector outputs a high level to trigger a register to generate a corresponding busy state signal, and the on-line monitoring of the operation states of all memory chips can be realized without actively returning to the state of each memory chip, so that the state checking efficiency can be effectively improved, and the problem that the return state of the memory chip fails due to the need of switching the state is avoided.
Drawings
Fig. 1 is a schematic structural diagram of a sensing circuit of a Nor Flash with no sense expansion according to some embodiments of the present application.
Fig. 2 is a schematic structural diagram of a sensing circuit of Nor Flash without sense expansion according to still other embodiments of the present application.
Fig. 3 is a schematic structural diagram of a sensing circuit of a Nor Flash without sense expansion according to other embodiments of the present application.
Fig. 4 is a schematic structural diagram of a sensing circuit of Nor Flash without sense expansion according to still other embodiments of the present application.
Fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Reference numerals: 1. opening and leaking pad; 2. a pull-up resistor; 3. a transistor; 4. a NOT gate; 5. a first selector; 6. a register; 7. a follower; 8. a filter; 9. a first rising edge detection circuit; 10. a second rising edge detection circuit; 11. a second selector; 12. a judgment circuit; 301. a processor; 302. a memory; 303. a communication bus.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.
Referring to fig. 1, some embodiments of the present application provide a sensing circuit of a non-inductive expansion Nor Flash, where the non-inductive expansion Nor Flash includes a main chip and a plurality of sub-chips that are stacked and sealed, and the sensing circuit includes:
the plurality of open drain pad1 are respectively connected with different sub-chips and are respectively used for outputting low-level signals when the corresponding sub-chip is in an erasing or programming state;
the first ends of the pull-up resistors 2 are connected with the output ends of all the open drain pad1, and the second ends of the pull-up resistors are connected with the power supply voltage;
the first end of the transistor 3 is connected with the first end of the pull-up resistor 2, the second end of the transistor is grounded, and the third end of the transistor is connected with the main chip and is used for monitoring the erasing state signal of the main chip;
the input end of the NOT gate 4 is connected with the first end of the pull-up resistor 2;
the first selector 5, its selection control end is connected with output end of NAND gate 4, its one input end inputs the high level signal;
and a trigger input end of the register 6 is connected with an output end of the first selector 5, and an output end of the register is used for outputting a busy state signal of Nor Flash and is connected with the other input end of the first selector 5.
It should be understood that, the sensing circuit of the Nor Flash with no sense-expansion in the embodiment of the present application is installed in the main chip, and is used for comprehensively reflecting whether all the memory chips (including the main chip and the sub-chip) have the memory chips in the erasing state, but meanwhile, the embodiment of the present application does not limit the setting positions of the main chip and the sub-chip, so that the memory chip with the sensing circuit installed can be considered as the main chip, and the rest of the memory chips are the sub-chips.
Specifically, the Nor Flash without sense expansion is integrated into an integral chip, the PAD is a pin of a silicon chip, and is packaged in the Nor Flash, and the open drain refers to open drain output, and can switch the level state according to the running state of a corresponding memory chip (mainly referred to as a secondary chip in the embodiment of the application); in the embodiment of the application, the open drain PAD1 refers to a PAD end connected with one open drain output of the secondary chip; in this embodiment, when the sub-chip performs the erase or program operation, the corresponding open drain pad1 is at a low level (i.e., 0), otherwise, at a high level (i.e., 1).
More specifically, the third terminal of the transistor 3 is used for monitoring the erasing status signal of the main chip, so that the conducting state between the first terminal and the second terminal is controlled based on the erasing status signal of the main chip, in this embodiment, when the main chip performs the erasing or programming action, the first terminal and the second terminal of the transistor 3 are conducted, so the transistor 3 can be regarded as a switching transistor for automatically switching the conducting state based on the running state of the main chip; in the embodiment of the present application, the transistor 3, the pull-up resistor 2, and the power supply voltage correspond to constitute an open drain output with respect to the main chip.
More specifically, the output terminal of the not gate 4 is connected to the selection control terminal of the first selector 5, and the two input terminals of the first selector 5 are connected to the output terminal of the register 6 and the high level signal (i.e., 1' b1 in the drawing), respectively, i.e., the output state of the first selector 5 is changed by changing the output state of the not gate 4; in the embodiment of the present application, the 1 input terminal of the first selector 5 is connected to the high level signal, so that when the not gate 4 outputs the high level, the first selector 5 also outputs the high level.
More specifically, in the embodiment of the present application, the number of sub-chips is one or more, and only one schematic structure of the open drain pad1 is shown in the drawings, it should be understood that if there are multiple sub-chips, the output ends of the open drain pad1 of the multiple sub-chips are connected in parallel.
More specifically, when the main chip performs an erase or program operation, the transistor 3 is turned on so that the point a in fig. 1 is pulled down to a low level; similarly, when the main chip performs the erase or program operation, the open drain pad1 can pull down the point a in fig. 1 to be low level, so that in the whole non-inductive capacity-expansion Nor Flash, as long as the memory chip is performing the erase or program operation, the voltage at the point a is in a low level state, so that the NOT gate 4 outputs a high level, and the first selector 5 outputs a high level to trigger the register 6 to output a corresponding busy state signal.
More specifically, when all the memory chips are not performing the erase and program operations, the transistor 3 and the open drain pad1 are turned off, and the voltage at a in fig. 1 is pulled up to be high by the pull-up resistor 2 and the supply voltage, so that the output of the not gate 4 is low, and the first selector 5 is further enabled to switch the output to trigger the register 6 to output the corresponding busy state signal, and since the 0 end of the first selector 5 is connected to the output end of the register 6, the output of the first selector 5 is gradually pulled down to be low to change the output of the register 6.
More specifically, the Busy status signal (hereinafter abbreviated as Busy) is used to reflect whether the whole nors Flash has a memory chip that is performing an erase or program operation, in this embodiment, busy=1 (high level) indicates that the nors Flash has a memory chip that is performing an erase or program operation, and busy=0 (low level) indicates that the nors Flash does not have a memory chip that is performing an erase or program operation, so that the sensing circuit does not increase power consumption when the nors Flash is in an idle state.
More specifically, in the Nor Flash without sense expansion, only one memory chip is generally executing erasing or programming actions at the same time, so that the embodiment of the application can realize the sense of the whole Nor Flash erasing action by adopting one sensing circuit.
The sensing circuit of Nor Flash without sense expansion monitors the execution states of the secondary chip and the primary chip on line based on the open drain pad1 and the transistor 3, when the primary chip or the secondary chip executes erasing or programming actions, the sensing circuit can input low level to the NOT gate 4 so that the first selector 5 outputs high level to trigger the register 6 to generate corresponding busy state signals, the on-line monitoring of the running states of all the memory chips can be realized without actively returning the states of each memory chip, the state checking efficiency can be effectively improved, and the problem that the return states of the memory chips fail due to the need of switching the states is avoided.
In some preferred embodiments, referring to fig. 2, the sensing circuit of the Nor Flash with no sense expansion further includes a follower 7, and the first end of the pull-up resistor 2 is connected to the input end of the nand gate 4 through the follower 7.
Specifically, the follower 7 is an in-phase buffer, which can perform buffering (buf) on an input signal, so that the level signal can be prevented from changing too fast, and meanwhile, the signal can be subjected to preliminary filtration, so that the anti-interference capability of the whole sensing circuit is improved.
In some preferred embodiments, referring to fig. 2, the sensing circuit of Nor Flash without sense expansion further includes a filter 8, and the follower 7 is connected to the input terminal of the nand gate 4 through the filter 8.
Specifically, as shown in fig. 2, in the embodiment of the present application, the output end of the filter 8 is connected to the output end of the follower 7, the output end of the filter 8 is connected to the output end of the nand gate 4, and the filter 8 is used for filtering burrs in a period lower than a certain period of time, so as to improve the stability of the whole sensing circuit, and the output accuracy of the busy state signal can be effectively ensured when the filter 8 is used in cooperation with the follower 7.
In some preferred embodiments, referring to fig. 3, the sensing circuit of Nor Flash without sense expansion further includes a first rising edge detection circuit 9, a second rising edge detection circuit 10, and a second selector 11, wherein an output end of the first selector 5 is connected to an input end of the second selector 11 to be connected to a trigger input end of the register 6 through an output end of the second selector 11, and another input end of the second selector 11 inputs a low level signal;
the input end of the first rising edge detection circuit 9 is connected with the filter 8, the output end of the first rising edge detection circuit 9 is connected with the input end of the second rising edge detection circuit 10, and the output end of the second rising edge detection circuit 10 is connected with the selection control end of the second selector 11.
Specifically, the memory chip may also generate an unexpected termination condition when performing an erasing or programming action, and the sensing circuit in the embodiment of the present application adds the first rising edge detection circuit 9 and the second rising edge detection circuit 10 to perform error information collection; after the storage chip in the Nor Flash finishes the erasing or programming operation, a high level signal appears at a (the sub chip is represented as an open drain pad1 outputting a high voltage briefly, the main chip is represented as a transistor 3 turning off briefly), the Nor Flash needs to wait for a certain time to perform the next erasing or programming operation, during which the sensing circuit in the embodiment of the present application uses the first rising edge detection circuit 9, the second rising edge detection circuit 10 and the second selector 11 to collect the error information, and the process is as follows: when the memory chip completes the erasing or programming action, the signal at the point a generates a rising edge to enter a high level signal, the first rising edge detection circuit 9 detects the rising edge and triggers the second rising edge detection circuit 10 to detect the signal at the point a, if in a certain time (before the first rising edge detection circuit 9 is cut off), the signal at the point a generates a square wave signal or drops to a low level and rises to a high level (the execution action with errors), the second rising edge detection circuit 10 triggers the second selector 11 to switch the input low level signal (1' b0 in the drawing) based on the rising edge at the point a to lock the output of the register 6, so that Busy output by the register 6 is locked to 0, and when the next memory chip executes the erasing or programming action, the Busy is locked to 0, the error information acquisition of the Nor Flash can be known.
More specifically, the input end of the first rising edge detecting circuit 9 is connected to the filter 8, so that the rising edge detecting process is a process of detecting based on the buffered and filtered input signal, and the rising edge capturing accuracy is ensured.
In some preferred embodiments, referring to fig. 4, the sensing circuit of Nor Flash without sense expansion further includes a determining circuit 12, an input end of the determining circuit 12 is connected to an output end of the second rising edge detecting circuit 10, and an output end of the determining circuit 12 is configured to output an error status signal.
Specifically, in order to make the external host more directly know that the Error information occurs in the Nor Flash, the sensing circuit in this embodiment of the present application adds a determining circuit 12 at the output end of the second rising edge detecting circuit 10, where the determining circuit 12 is configured to determine whether the difference between the occurrence intervals of the rising edges detected by the first rising edge detecting circuit 9 and the second rising edge detecting circuit 10 is smaller than a preset time window, if the difference is smaller than the time window, the Error state signal Error is output as 1, otherwise, the Error state signal Error is output as 0, so that the external host can sense whether the Error or the programming action of the Nor Flash occurs accidentally according to the Error.
More specifically, in some other embodiments, the determining circuit 12 may further determine whether a problem occurs in the programming or erasing operation according to whether the time interval between two rising edges is greater than a preset value when the Nor Flash performs the continuous programming or erasing operation, and switch Error to 1 when the problem occurs.
In some preferred embodiments, the first rising edge detection circuit 9 and the second rising edge detection circuit 10 are both rising edge trigger based delay signal generation circuits.
Specifically, the delay signal generating circuit is generally configured to generate a delay signal according to a clock rising edge trigger, and in this embodiment of the present application, the delay signal generating circuit is configured to generate a delay signal according to a level change condition output by the filter 8, where a timing of generating the delay signal is a timing at which a rising edge occurs.
In some preferred embodiments, register 6 is a D flip-flop.
Specifically, in the embodiment of the present application, the output end of the second selector 11 is connected to the D end of the D flip-flop, and the Q end of the D flip-flop outputs the Busy signal.
More specifically, the CP terminal of the D flip-flop may be connected to the cs# signal input from the external host.
In some preferred embodiments, the transistor 3 is an NMOS transistor.
Specifically, the first end of the transistor 3 is the drain electrode of the NMOS transistor, the second end of the transistor 3 is the source electrode of the NMOS transistor, and the third end of the transistor 3 is the gate electrode of the NMOS transistor; when the main chip is executing erasing or programming action, the grid electrode of the NMOS tube inputs high level, so that the source drain of the NMOS tube is conducted to pull down the point a to low level.
In a second aspect, some embodiments of the present application further provide a non-inductive expansion Nor Flash, where the non-inductive expansion Nor Flash includes a main chip and a plurality of sub-chips that are stacked and arranged, and a sensing circuit of the non-inductive expansion Nor Flash provided in the first aspect is disposed in the main chip.
According to the Nor Flash with the non-inductive capacity expansion, the sensing circuit of the Nor Flash with the non-inductive capacity expansion, which is provided by the first aspect, is installed in the main chip, so that an external host can accurately know whether a memory chip which is executing erasing or programming actions exists in the Nor Flash based on a busy state signal output by the main chip.
In a third aspect, some embodiments of the present application further provide an electronic device, where the electronic device includes the Nor Flash with no sense-of-expansion provided in the second aspect.
Specifically, as shown in fig. 5, the electronic device of the embodiment of the present application includes: processor 301 and memory 302, processor 301 and memory 302 being interconnected and in communication with each other by a communication bus 303 and/or other form of connection mechanism (not shown), memory 302 being a Nor Flash of non-inductive expansion provided by the second aspect.
The processor 301 in the electronic device provided in the embodiment of the present application can obtain the Busy signal from the main chip in the memory 302 to determine whether there is a memory chip in the Nor Flash that is executing the erasing or programming action.
In summary, the embodiment of the application provides a Nor Flash, a sensing circuit and an electronic device with no sense expansion, wherein the sensing circuit monitors the execution states of a secondary chip and a primary chip on line based on an open drain pad1 and a transistor 3, when the primary chip or the secondary chip executes erasing or programming actions, a low level can be input to a NOT gate 4 so that a first selector 5 outputs a high level to trigger a register 6 to generate a corresponding busy state signal, and the on-line monitoring of the operation states of all memory chips can be realized without actively returning to the state of each memory chip, so that the state checking efficiency can be effectively improved, and the problem that the return state of the memory chip fails due to the need of switching the state is avoided.
In the description of the present specification, reference to the terms "one embodiment," "certain embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
What has been described above is merely some embodiments of the present invention. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit of the invention.
Claims (10)
1. The sensing circuit of the Nor Flash without sense expansion comprises a main chip and a plurality of auxiliary chips which are overlapped and sealed, and is characterized in that the sensing circuit comprises:
the plurality of open drain pads are respectively connected with different sub-chips and are respectively used for outputting low-level signals when the corresponding sub-chip is in an erasing or programming state;
the first ends of the pull-up resistors are connected with the output ends of all the open drain pads, and the second ends of the pull-up resistors are connected with the power supply voltage;
the first end of the transistor is connected with the first end of the pull-up resistor, the second end of the transistor is grounded, and the third end of the transistor is connected with the main chip and is used for monitoring erasing state signals of the main chip;
the input end of the NOT gate is connected with the first end of the pull-up resistor;
the selection control end of the first selector is connected with the NOT gate output end, and one input end of the first selector inputs a high-level signal;
and the trigger input end of the register is connected with the output end of the first selector, and the output end of the register is used for outputting a busy state signal of Nor Flash and is connected with the other input end of the first selector.
2. The sense amplifier-free Nor Flash sensing circuit of claim 1, further comprising a follower, wherein the first terminal of the pull-up resistor is connected to the input terminal of the not gate through the follower.
3. The sense-less Flash Nor sensing circuit of claim 2, further comprising a filter, wherein the follower is coupled to the input of the not gate through the filter.
4. The sensing circuit of non-inductive capacity-expansion Nor Flash according to claim 3, wherein the sensing circuit of non-inductive capacity-expansion Nor Flash further comprises a first rising edge detection circuit, a second rising edge detection circuit and a second selector, wherein the output end of the first selector is connected with one input end of the second selector so as to be connected with the trigger input end of the register through the output end of the second selector, and the other input end of the second selector inputs a low-level signal;
the input end of the first rising edge detection circuit is connected with the filter, the output end of the first rising edge detection circuit is connected with the input end of the second rising edge detection circuit, and the output end of the second rising edge detection circuit is connected with the selection control end of the second selector.
5. The sensing circuit of non-inductive capacity-expansion Nor Flash according to claim 4, further comprising a judging circuit, wherein an input end of the judging circuit is connected with an output end of the second rising edge detecting circuit, and an output end of the judging circuit is used for outputting an error state signal.
6. The sense amplifier Nor Flash sensing circuit of claim 4 or 5, wherein the first rising edge detection circuit and the second rising edge detection circuit are both rising edge trigger based delay signal generation circuits.
7. The sense amplifier-free Nor Flash sensing circuit of claim 1, wherein the register is a D flip-flop.
8. The sense amplifier-free Nor Flash sensing circuit of claim 1, wherein the transistor is an NMOS transistor.
9. The Nor Flash without sense expansion comprises a main chip and a plurality of auxiliary chips which are arranged in a stacked mode, and is characterized in that a sensing circuit of the Nor Flash without sense expansion according to any one of claims 1-8 is arranged in the main chip.
10. An electronic device comprising the noninductive Flash of claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310016992.6A CN115938439B (en) | 2023-01-06 | 2023-01-06 | Nor Flash without sense expansion, sensing circuit and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310016992.6A CN115938439B (en) | 2023-01-06 | 2023-01-06 | Nor Flash without sense expansion, sensing circuit and electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115938439A CN115938439A (en) | 2023-04-07 |
| CN115938439B true CN115938439B (en) | 2023-05-09 |
Family
ID=85830633
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310016992.6A Active CN115938439B (en) | 2023-01-06 | 2023-01-06 | Nor Flash without sense expansion, sensing circuit and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115938439B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1534684A (en) * | 2003-02-07 | 2004-10-06 | ��ʽ���������Ƽ� | non-volatile memory |
| CN111294036A (en) * | 2019-07-17 | 2020-06-16 | 锐迪科创微电子（北京）有限公司 | Pad multiplexing device and electronic equipment |
| CN111459419A (en) * | 2020-06-17 | 2020-07-28 | 深圳市芯天下技术有限公司 | Non-inductive capacity expansion method, system, storage medium and terminal for F L ASH |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140008745A (en) * | 2012-07-11 | 2014-01-22 | 삼성전자주식회사 | Magenetic random access memory |
| KR20160005942A (en) * | 2014-07-08 | 2016-01-18 | 에스케이하이닉스 주식회사 | Inverter and electronic device with the same |
| CN105912483B (en) * | 2015-02-23 | 2019-06-21 | 东芝存储器株式会社 | Storage System |
| WO2020073300A1 (en) * | 2018-10-12 | 2020-04-16 | Intel Corporation | Techniques to calibrate impedance level |
-
2023
- 2023-01-06 CN CN202310016992.6A patent/CN115938439B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1534684A (en) * | 2003-02-07 | 2004-10-06 | ��ʽ���������Ƽ� | non-volatile memory |
| CN111294036A (en) * | 2019-07-17 | 2020-06-16 | 锐迪科创微电子（北京）有限公司 | Pad multiplexing device and electronic equipment |
| CN111459419A (en) * | 2020-06-17 | 2020-07-28 | 深圳市芯天下技术有限公司 | Non-inductive capacity expansion method, system, storage medium and terminal for F L ASH |
Non-Patent Citations (1)
| Title |
|---|
| "基于FPGA的NorFlash控制器的设计与实现";钟天明;《中国优秀硕士学位论文全文数据库》;正文第1-60页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115938439A (en) | 2023-04-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US12164454B2 (en) | NAND switch | |
| WO2009107443A1 (en) | Memory system | |
| US6061282A (en) | Semiconductor memory having an improved test circuit | |
| CN104361909A (en) | On-chip RAM built-in self-testing method and circuit | |
| CN111459419B (en) | Non-inductive capacity expansion method, system, storage medium and terminal for FLASH | |
| CN108511029B (en) | Built-in self-test and repair system and method for dual-port SRAM array in FPGA | |
| US20120173798A1 (en) | Memory controller, memory device and method for determining type of memory device | |
| TW201017675A (en) | Multi-chip module | |
| CN201017277Y (en) | Action testing combine group buffer of embedded system | |
| CN103208314A (en) | Internal memory test method of embedded system and embedded system | |
| CN115938439B (en) | Nor Flash without sense expansion, sensing circuit and electronic equipment | |
| CN102915209A (en) | Storage control chip, storage equipment and system data writing method | |
| US5077690A (en) | Memory input data test arrangement | |
| CN116386711B (en) | A test device and test method for data transmission of a storage device | |
| US20230229337A1 (en) | Instruction and data recording apparatus embedded in a host controller | |
| CN110942793B (en) | Memory device | |
| CN114371385A (en) | Design method of port multiplexing test circuit | |
| JPS63250759A (en) | Integrated circuit device | |
| US9633718B1 (en) | Nonvolatile memory device | |
| CN105679377A (en) | Self-adaptive testing method and device of CPU cache memory | |
| CN106205692A (en) | Memory Controller and Memory Module | |
| CN118152197B (en) | Chip testing method, system, device and storage medium | |
| CN117054858B (en) | Three-state configuration pin implementation method and IO device in chip | |
| CN115831198B (en) | Chip selection enabling control device, reading device, erasing device and flash memory | |
| CN119252314B (en) | Method and device for testing single-particle effects of large-capacity solid-state hard disks based on high-energy particles |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |