CN115936128A - Vector processor supporting multi-precision calculation and dynamic configuration and processing method - Google Patents

Abstract

In the vector processor and the data processing method provided by the present invention, a systolic array acceleration unit is added in the processor channel to realize calculation between vectors. The storage unit on the original architecture is fully utilized, the data throughput is increased, and the calculation between more vector data is realized, so that the acceleration effect of the systolic array accelerator is fully utilized, and the calculation utilization rate is greatly improved. The systolic array accelerator can support multi-precision and ultra-low bit quantized calculations to improve the efficiency of vector calculations. At the same time, the parallelism and scalability of vector processors can greatly increase the data calculation density, thereby effectively improving the computing power.

Description

A vector processor and processing method supporting multi-precision calculation and dynamic configuration

technical field

The present application relates to the field of integrated circuits and communication technologies, in particular to a vector processor and processing method supporting multi-precision calculation and dynamic configuration.

Background technique

A neural network model usually includes a large number of network layers, and each network layer has a convolution operation between a weight matrix and an activation matrix, wherein the weight matrix contains a large amount of weight data, and the activation matrix contains a large amount of activation data. When performing a convolution operation, the convolution operation is generally converted into a matrix multiplication, and then the matrix multiplication processor is used for calculation to obtain the result of the convolution operation.

A matrix multiplication processor usually includes a plurality of basic operation units arranged in a systolic array, multiple weight data and activation data are broadcast to the systolic array under the control of a clock signal, and the entire matrix multiplication operation process is controlled by a control signal Each basic operation unit continuously performs multiplication and accumulation operations on the received weight data and activation data.

With the development of deep neural networks, matrix multiplication and addition calculations have gradually become the calculation part that processors focus on. Most of today's matrix multiplication and addition calculations are implemented by arithmetic logic operation units. The arithmetic logic unit can only perform calculations on a single fixed-width data per cycle, and cannot make full use of the computing power of matrix multiplication and addition calculations. As a result, the existing matrix multiplication and addition calculation algorithm implemented by the arithmetic logic unit has low calculation efficiency and low data utilization rate. Judging from the existing solutions, the bottleneck is that the current hardware architecture can only realize the calculation between serial vectors and scalars, and its essence is the calculation of scalars and scalars, which leads to the fact that the calculation utilization of the computing architecture cannot reach the ideal level. Therefore, How to use limited resources to better design hardware units for matrix multiplication and addition calculations has become an urgent problem to be solved.

Contents of the invention

The application provides a vector processor and processing method supporting multi-precision calculation and dynamic configuration, which can be used to solve the technical problem of low calculation utilization.

In the first aspect, the embodiment of the present application provides a vector processor supporting multi-precision calculation and dynamic configuration, including:

A control module, the control module is used to receive an external incoming operation instruction, and analyze the operation instruction to obtain a vector calculation instruction and a vector storage load instruction, and determine the functional unit sent by the vector calculation instruction;

A load-storage module, configured to load data to be processed from the outside according to the vector storage load instruction;

An extended channel module, the extended channel module includes a channel storage unit and a systolic array acceleration unit, the channel storage unit is used to store the data to be processed, and the systolic array acceleration unit is used to calculate the vector from the The corresponding data is acquired in the channel storage unit to perform calculation between vectors, and the calculation result is returned to the channel storage unit for storage; the calculation result stored in the channel storage unit is transmitted to the outside through the load storage module.

With reference to the first aspect, in an implementable manner of the first aspect, the control module includes an instruction distribution unit and a main sequencing unit, and the instruction distribution unit receives an externally incoming operation instruction, and after processing the operation instruction, Identify the type of operation instruction and the corresponding functional unit and send the operation instruction to the main sequencing unit, and the main sequencing unit broadcasts the instruction to all functional units and monitors the running status of the instruction.

With reference to the first aspect, in an implementable manner of the first aspect, the extended channel module includes a channel instruction sequencing unit, the channel storage unit, and several calculation processing units, and the calculation processing unit includes the systolic array acceleration unit.

With reference to the first aspect, in an implementable manner of the first aspect, the channel storage unit includes a vector register file and an operand queue, and the vector register file is used to provide the operand of the functional unit and absorb its result, so The operand queue connects the calculation processing unit and the vector register file, and is used for allocating operands of each calculation processing unit.

With reference to the first aspect, in an implementable manner of the first aspect, the vector register file includes several storage banks and arbitration units, the storage banks are single-port, and the bit width is set to 64 bits, and each of the vector register files There are 8 memory banks in the register file for loading and delivering data to be processed and calculation results, and the arbitration unit is used for allocating the priority of each operation instruction.

With reference to the first aspect, in an implementable manner of the first aspect, the channel instruction sequencing unit is configured to send operation instructions to each functional unit in the extended channel module, and initiate a read from the vector register file A request to fetch an operand.

With reference to the first aspect, in an implementable manner of the first aspect, after the systolic array acceleration unit receives the request to read data from the vector register file, it automatically inputs the data to be processed into the cache in order, and loads After the end, it is judged according to the input mode whether to start the calculation, the calculation result is automatically stored in the output buffer, and the result is output back to the vector register file by the waiting instruction.

With reference to the first aspect, in an implementable manner of the first aspect, the operation instruction is a custom instruction, and the custom instruction is a vector instruction, including the vector calculation instruction, vector load instruction and vector storage instruction , the self-defined instruction includes target address information and action information; the self-defined instruction is input from an external vector processor for processing.

In conjunction with the first aspect, in a possible implementation of the first aspect, the load storage module data loading unit and the data storage unit, the data loading unit loads data through the AXI AR bus, and the data storage unit uses the AXIAW bus for storing data.

In the second aspect, the embodiment of the present application provides a data processing method supporting multi-precision calculation and dynamic configuration, including:

The control module receives external input operation instructions;

The control module parses the operation instruction, obtains the vector calculation instruction and the vector storage load instruction, and determines the functional unit sent by the vector calculation instruction;

The load storage module loads the data to be processed from the outside according to the vector storage load instruction;

The systolic array acceleration unit in the extended channel module acquires corresponding data from the channel storage unit to perform calculation between vectors according to the vector calculation instruction, and returns the calculation result to the channel storage unit for storage; the stored in the channel storage unit The calculation result is transmitted to the outside through the load storage module.

In the vector processor and the data processing method provided by the present invention, a systolic array acceleration unit is added in the processor channel to realize calculation between vectors. The storage unit on the original architecture is fully utilized, the data throughput is increased, and the calculation between more vector data is realized, so that the acceleration effect of the systolic array accelerator is fully utilized, and the calculation utilization rate is greatly improved. The systolic array accelerator can support multi-precision and ultra-low bit quantized calculations to improve the efficiency of vector calculations. At the same time, the parallelism and scalability of vector processors can greatly increase the data calculation density, thereby effectively improving the computing power.

Description of drawings

Fig. 1 is the vector processor frame structure schematic diagram in embodiment 1;

Fig. 2 is the vector processor frame structure schematic diagram in embodiment 2;

Fig. 3 is the frame diagram of the expansion channel module in embodiment 2;

Fig. 4 is the working principle diagram of the pulse array acceleration unit;

Figure 5 is a schematic diagram of the comparison of storage bandwidth utilization between the traditional multiplication tree architecture and the systolic array;

6 is a schematic diagram of the composition of vector calculation instructions;

Fig. 7 is a schematic diagram of the composition of vector storage and loading instructions;

Fig. 8 is the flow chart of data processing during the instruction running process in embodiment 2;

FIG. 9 is a flowchart of the method in Embodiment 3.

100. Control module; 200. Expansion channel module; 300. Loading and storage module;

101. Instruction distribution unit; 102. Main sequencing unit;

201. Channel storage unit; 202. Calculation processing unit; 203. Channel instruction sequencing unit;

201a, vector register file; 201b, operand queue;

202a, a systolic array acceleration unit; 202b, an arithmetic logic unit; 202c, a multiplication calculation unit; 202d, a floating-point number processing unit;

201a-1, storage body; 201a-2, arbitration unit;

301. A data loading unit; 302. A data storage unit.

Detailed ways

In order to make the purpose, technical solution and advantages of the present application clearer, the implementation manners of the present application will be further described in detail below in conjunction with the accompanying drawings.

Example 1

A possible system architecture applicable to this embodiment of the present application is firstly introduced below with reference to FIG. 1 .

Please refer to FIG. 1 , which exemplarily shows a schematic structural diagram of a vector processor applicable to the embodiment of the present application, which includes an expansion channel module 200 , a control module 100 and a load-store module 300 .

A control module 100, the control module 100 is used to receive an operation instruction input from the outside, and analyze the operation instruction to obtain a vector calculation instruction and a vector storage load instruction, and determine the functional unit sent by the vector calculation instruction;

A load-storage module 300, configured to load data to be processed from the outside according to the vector storage load instruction;

An extended channel module 200, the extended channel module 200 includes a channel storage unit 201 and a systolic array acceleration unit 202a, the channel storage unit 201 is used to store the data to be processed, and the systolic array acceleration unit 202a is used to The vector calculation instruction obtains corresponding data from the channel storage unit 201 to perform calculation between vectors, and returns the calculation result to the channel storage unit 201 for storage; the calculation result stored in the channel storage unit 201 is passed through the load The storage module 300 is transmitted to the outside.

The vector processor provided in this embodiment adds a systolic array acceleration unit 202a to the processor channel, and designes a special vector instruction to call the systolic array acceleration unit 202a to realize vector-to-vector calculations. Compared with the original arithmetic logic unit 202b, which can only perform calculations on a single fixed-width data per cycle, the systolic array acceleration unit 202a makes full use of the storage units on the original architecture, increases the data throughput, and achieves more The calculation between the vector data makes full use of the acceleration effect of the systolic array accelerator, and the calculation utilization rate is greatly improved. The systolic array accelerator can support multi-precision and ultra-low bit quantized calculations to improve the efficiency of vector calculations. At the same time, the parallelism and scalability of vector processors can greatly increase the data calculation density, thereby effectively improving the computing power.

Example 2

This embodiment provides a vector processor supporting multi-precision calculation and dynamic configuration, the architecture of which is shown in FIG. 2 .

Wherein, the control module 100 includes an instruction distribution unit 101 and a main sequencer unit 102. The instruction distribution unit 101 receives an operation instruction input from the outside, and after processing the operation instruction, identifies the type of the operation instruction and the corresponding functional unit. And the operation instruction is sent to the main sequencing unit 102, and the main sequencing unit 102 broadcasts the instruction to all functional units, and monitors the running state of the instruction.

Specifically, the instruction distribution unit 101 is the decoder of the vector processor, responsible for receiving the operation instructions from the outside (that is, the first-level instruction decoding unit), so as to identify the vector functional unit corresponding to the vector instruction, the type of the operation instruction, and other information . After the instruction recognition is completed, the instruction distribution unit 101 transmits the operation instruction and the decoded information to the main sequencing unit 102 for subsequent processing. The instruction distribution unit 101 can also screen the types of instructions and give feedback to the first-level instruction decoder. For example, when a scalar instruction is received, an error message will be returned.

The main sequencer unit 102 is responsible for tracking the operation instructions running on the expansion channel module 200, dispatching them to different functional units, and confirming them through the external processing unit. The main sequencing unit 102 is able to grasp the execution progress of instructions on all expansion channel modules 200 . The main sequencing unit 102 also stores information about which vector instruction is accessing which vector register. This information is used to determine data hazards between instructions in order to determine the priority of execution of individual instructions.

As shown in FIG. 2 , in the extended channel module 200, it includes a channel instruction sequencing unit 203, a channel storage unit 201 and several calculation processing units 202, wherein the channel instruction sequencing unit 203 is used to The functional unit sends an operation instruction, the channel storage unit 201 is used to store the data to be processed and the calculation result, and the calculation processing unit 202 is used to receive the vector calculation instruction, read the data to be processed in the channel storage unit 201 for calculation, and then The calculation result is returned to the channel storage unit 201.

As shown in FIG. 2 , there are several other expansion channel modules 200 in the vector processor, namely channel 1 . Each extended channel module 200 has the following channel structure, that is, each channel has its own channel instruction sequencing unit 203 responsible for tracking up to 8 parallel vector instructions. Each channel also has a set of channel storage units 201 including register files to coordinate its access operation queues, and a calculation processing unit 202 including an integer arithmetic logic unit 202b, an integer multiplier and a floating point calculation unit. Each lane contains the entire register file and a portion of the computational processing unit 202 . However, in this embodiment, a systolic array acceleration unit 202a is added to the channel structure for processing operations between vectors,

The specific structure in the expansion channel module 200 will be analyzed below in conjunction with FIG. 3 .

The channel instruction sequencing unit 203 is configured to send operation instructions to each functional unit in the expansion channel module 200, and control them to be executed within the range of a single channel. Different from the main sequencer unit 102, the channel instruction sequencer unit 203 does not store the state of the running instruction, which avoids data duplication between channels. They also initiate requests to read operands from the vector register file 201 a in the channel storage unit 201 .

The channel storage unit 201 in this embodiment includes a vector register file 201a and an operand queue 201b, the vector register file 201a is used to provide the operand of the functional unit and absorb its result, and the operand queue 201b is connected to the calculation process The unit 202 and the vector register file 201a are used to allocate operands of each of the calculation processing units 202 .

The vector register file 201a includes several memory banks 201a-1 and arbitration units 201a-2, the memory bank 201a-1 is a single port, the bit width is set to 64 bits, and each of the vector register files 201a is provided with 8 storage The body 201a-1 is used to load and deliver data to be processed and calculation results, and the arbitration unit 201a-2 is used to allocate the priority of each operation instruction.

The vector register file 201aVRF (Vector Register Files) is the core of each vector processor. Because several instructions can run in parallel, the vector register file 201a must be able to support sufficient throughput to provide operands to functional units and to absorb their results. The VRF of the vector processor is composed of a group of single-port memory banks 201a-1 (bank). The width of each memory bank 201a-1 is limited to the data path width of each channel, ie, 64 bits, to avoid subword selection logic errors. Therefore, in a steady state, the five memory banks 201a-1 can be accessed simultaneously to maintain the predetermined maximum throughput of multiply-add instructions. The vector register file 201a of the vector processor is configured with eight banks per channel, providing some margin for access.

Bank conflicts result when several functional units try to access operands of the same bank. Each expansion channel module 200 has a set of operand queues 201b between the VRF and each functional unit to absorb such bank conflicts. There are 12 operand queues 201b in this embodiment: 4 of them are used exclusively for FPU/MUL (floating-point number processing unit 202d/multiplication calculation unit 202c), 3 are used for ALU (arithmetic logic unit 202b), and the other 3 are used for In a VLSU (vector load/store unit), 2 queues are used for the systolic array acceleration unit 202a. The width of each queue is 64 bits wide, and their depth is selected by simulation, depending on the delay and throughput of the functional unit.

As shown in FIG. 3, an integer ALU (arithmetic logic unit 202b), an integer MUL (multiplication calculation unit 202c) and an FPU (floating point number processing unit 202d) are included in the calculation processing unit 202, which are all in a 64-bit It operates on the data path and is used to meet basic scalar operation functions. The MUL and the FPU share the operand queue 201b, but they cannot be used at the same time. Adequate support for multi-precision operations exists in vector processors, allowing data conversion from 8-bit to 16-bit, from 16-bit to 32-bit, and from 32-bit to 64-bit. The FPU is configured to support FMAs (floating-point multiply-accumulate), addition, multiplication, division, square root, and comparison.

The systolic array unit is specially used to handle operations between vectors, thus greatly improving the vector operation capability of the vector processor. Fig. 4 shows the working principle of the systolic array acceleration unit 202a. The systolic array acceleration unit 202a is composed of multiple computing units (PE, Processing Element) with the same structure, and works in a manner similar to a pipeline. Each computing unit will calculate the incoming data and temporarily store part of the sum, and the next The clock cycle should broadcast the specified data to the adjacent computing units in the specified direction. In a systolic array of adaptive matrix multiplication calculations, a computing unit may choose to broadcast input data to adjacent computing units.

Since in many cases, the processing power of the overall system is limited by memory access bandwidth rather than computing power, as can be seen from Figure 5, this enables systolic arrays to better utilize limited memory accesses compared to traditional multiply tree architectures bandwidth without wasting computing power. Through systolic transmission and data broadcasting, the systolic array fully multiplexes data, which enables the systolic array to achieve high computing throughput without a large increase in storage space.

In this embodiment, when the systolic array acceleration unit 202a receives a request from the VRF in the channel to input data into the systolic array, the control unit inside the systolic array acceleration unit 202a will automatically input the data into cache A and cache B in sequence. middle. When the data loading is finished, the unit will decide whether to start calculation according to the input mode. After the calculation, the data is automatically stored in the output buffer, waiting for the command to output the calculation result to the VRF.

As shown in FIG. 2 , the load-storage module 300 in this embodiment includes a data loading unit 301 and a data storage unit 302 . They are respectively used to load the data to be processed from the outside and store the calculation results from the VRF into the external memory. After the first address in the operation instruction is transmitted to the data loading unit 301, the unit condenses the memory operation of the unit row into a burst request, avoiding the need to request a single element from the memory. The burst start address and burst length are then sent to the load or store unit, which are responsible for initiating the data transfer through the Advanced Extensible Interface (AXI) interface of the vector processing unit. The data loading unit 301 loads data through the AXI AR bus, and the data storage unit 302 AXI AW bus is used for storing data.

The operation instructions in this embodiment are self-defined instructions, and the self-defined instructions are all vector instructions, including the vector calculation instruction, vector load instruction and vector storage instruction, and the self-defined instructions include target address information and action information ; The custom instruction is input from the outside to the processing module for processing.

Among them, the vector calculation instruction is a custom VMSAM instruction, the vector load instruction VL*E and the vector storage instruction VS*E are both RISC-V instructions, and both support customization.

The RISC-V instruction set is an open instruction set architecture (ISA) based on the principle of reduced instruction set computing (RISC). RISC-V is a new instruction system established on the basis of the continuous development and maturity of the instruction set. The RISC-V instruction set is completely open source, simple in design, easy to port to Unix systems, modular design, complete tool chain, and there are a large number of open source implementations and tape-out cases.

RISC-V is a modular reduced instruction set architecture, which consists of the basic integer instruction set represented by the letter I and the extended instruction set of the letters M, A, F, D, and C. The only instruction set that must be implemented is the I-type basic integer instruction set, so that a complete software compilation tool chain can be realized. The extended instruction set adds functions such as multiplication and division, memory atomic operations, and floating-point number operations. All of the above instruction sets can be configured as needed.

Although RISC-V is not the first open-source instruction set (ISA), it is the first instruction set architecture designed to be properly selected according to specific scenarios. Based on the RISC-V instruction set architecture, processors for various application scenarios such as server CPUs, household appliance CPUs, and sensor CPUs can be designed.

As shown in Figure 6, the custom VMSAM instruction belongs to the vector processing instruction; after entering the vector processing unit, the state input and calculation accuracy of the systolic array accelerator can be obtained by decoding the value of rs1 to drive the module to start running; the instruction will not end until the calculation is completed .

As shown in Figure 7, the VL*E instruction belongs to the vector loading instruction; after entering the vector processing unit, the target functional unit is the VRF in the expansion channel module 200; Address; rs2 is the identification of how the data will be fetched from the memory, and rd is the first address of the data stored in the VRF.

The VS*E instruction belongs to the vector storage instruction; after entering the vector processing unit, the target functional unit is the VRF in the channel; the value of vs1 is decoded externally as the first address transmitted to the AW line in the AXI bus; rs2 is the data to be taken out from the VRF rd is the first address where the data is stored in the memory.

Figure 8 shows the process of running instructions in the vector processor for data processing:

1. After the vector processor gets the decoded VLE instruction, the data is read from the AR line of the AXI bus according to the order of the first address. When the data reading is completed, it is loaded into the VRF in the channel. When the data transmission is over, the command execution ends.

2. After the start of the VMSAM instruction, the decoded rs1 specifies the first address to read data from the VRF, rs2 specifies the operating mode of the systolic array acceleration unit 202a and the quantized data precision of the systolic array acceleration unit 202a, and rd specifies the result stored in The first address of the VRF. When the systolic array acceleration unit 202a receives a signal to start calculation, data is sent into the systolic array. After the calculation is completed, the instruction execution ends.

3. After the VSE command starts, the data is loaded from the VRF in the channel to the AW line of the AXI bus. When a transmission of a specific length is completed, the command ends.

As an alternative implementation manner, since the design of the user-defined instruction has a certain degree of flexibility, it is possible to use three specific instructions different from those proposed in this embodiment to guide and control each functional unit in the processor.

Example 3

Referring to FIG. 9, it exemplarily shows a schematic flow chart of a data processing method applicable to the embodiment of the present application, which mainly includes the following steps:

The control module 100 receives external incoming operation instructions;

The control module 100 parses the operation instruction, obtains the vector calculation instruction and the vector storage load instruction, and determines the functional unit sent by the vector calculation instruction;

The load storage module 300 loads the data to be processed from the outside according to the vector store load instruction;

The systolic array acceleration unit 202a in the extended channel module 200 obtains corresponding data from the channel storage unit 201 to perform calculation between vectors according to the vector calculation instruction, and returns the calculation result to the channel storage unit 201 for storage; The calculation results stored in the unit 201 are transmitted to the outside through the load and store module 300 .

Specifically, this embodiment takes the instruction type as a standard R-type instruction for operating the target register and the source register as an example, and shows that the workflow of various instructions after entering the vector processor is as follows:

Among them, the VL*E instruction runs the data flow:

1. Input instructions to the external decoder: 32’h 0000 1101 1010 0111 1111 1001 0101 0111

Obtained by one-level decoding, this is a vector instruction, which should be passed to the vector processor for processing. At the same time, the value of rs1 is 0F,

It is decoded externally to get the stored value of the address as 32’h 8000 0004, and the value of rd is 12, and this information is also passed into the vector.

2. When the vector receives the instruction and other information, it will be sent to the instruction distribution unit 101 for secondary decoding. The instruction distribution unit 101 recognizes that this is a data load instruction VLE according to the opcode of the instruction. At the same time, the values of rs1 and rs2 and the decoded address value are loaded, and these data and instructions are sent to the main sequence unit 102 . There is no error feedback to the external decoder.

3. After checking that there is no hazard between the instruction and other instructions, the main sequence unit 102 broadcasts the instruction and information to all functional units, but only the data loading unit 301 receives it. The data loading unit 301 sends a data loading request to the AR line of the AXI bus according to the first address information and the transmission length information. After the data loading is completed, the loading unit transfers the data to the VRF in Lane, and the storage address is the rd value. When the data is fully loaded into the VRF, the VLE instruction finishes running.

VMSAM instruction operation data flow diagram:

4. Input instructions to the external decoder: 32’h 1010 1010 1001 0001 1010 0000 0101 0111

Obtained by one-level decoding, this is a vector instruction, which should be passed to the vector processor for processing.

5. When the vector processor receives the instruction and other information, send it to the instruction distribution unit 101 for secondary decoding. The instruction distribution unit 101 recognizes that the instruction is a data processing instruction VMSAM according to the opcode of the instruction. At the same time, the values of rs1, rs2, and rd are loaded, and these data and instructions are sent to the main sequencing unit 102 . There is no error feedback to the external decoder.

6. After checking that there is no hazard between the instruction and other instructions, the main sequencer unit 102 broadcasts the instruction and information to all functional units, but only each channel and the systolic array acceleration unit 202a in the channel receive it. According to the first address in rs1 and the input of the mode state contained in rs2, the input precision of rs2 value decoding is 64bit. The functional unit starts to fetch data from the VRF, and judges whether to start calculation according to the state of the input. After the calculation, the result is stored in the output buffer. With rd as the first address, store the value of the output buffer into VRF. When the data is fully loaded into the VRF, the VMSAM instruction finishes running.

VS*E command running data flow diagram:

7. Input instructions to the external decoder: 32’h 0000 0010 0000 1101 1111 0000 0010 0111

Obtained by one-level decoding, this is a vector instruction, which should be passed to the vector for processing. At the same time, the value of rs1 is 1B, and the stored value of this address is 32’h 80042380, and the value of rd is 00 after decoding in the external decoder. Pass this information into the vector as well.

8. When the vector processor receives the instruction and other information, send it to the instruction distribution unit 101 for secondary decoding. The instruction distribution unit 101 recognizes that this is a data storage instruction VSE according to the opcode of the instruction. Simultaneously load the values of rs1 and rd and the decoded address value, and send these data and instructions into the main sequence unit 102 . There is no error feedback to the external decoder.

9. After checking that there is no hazard between the instruction and other instructions, the main sequence unit 102 broadcasts the instruction and information to all functional units, but only the data storage unit 302 receives it. The data storage unit 302 sends a data storage request to the AW line of the AXI bus according to the decoded first address information and transmission length information. After the data storage ends, the AW line will return an end signal to the instruction sequencing unit. When the data is fully loaded into the AXI AW line, the VSE instruction ends.

Those skilled in the art can clearly understand that the technologies in the embodiments of the present application can be implemented by means of software plus a necessary general-purpose hardware platform. Based on this understanding, the technical solution in the embodiment of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a storage medium, such as ROM/RAM , magnetic disk, optical disk, etc., including several instructions to enable a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of the present application.

For the same and similar parts among the various embodiments in this specification, refer to each other. In particular, for the embodiments of the service constructing device and the service loading device, since they are basically similar to the method embodiments, the description is relatively simple, and for relevant parts, please refer to the description in the method embodiments.

The embodiments of the present application described above are not intended to limit the scope of protection of the present application.

Claims (10)

1. A vector processor supporting multi-precision calculation and dynamic configuration, characterized in that, comprising: A control module (100), the control module (100) is used to receive an external incoming operation instruction, and analyze the operation instruction, obtain a vector calculation instruction and a vector storage load instruction, and determine the function sent by the vector calculation instruction unit; A load-storage module (300), the load-storage module (300) is used to load data to be processed from the outside according to the vector storage load instruction; An extended channel module (200), the extended channel module (200) includes a channel storage unit (201) and a systolic array acceleration unit (202a), the channel storage unit (201) is used to store the data to be processed, the The systolic array acceleration unit (202a) is used to obtain corresponding data from the channel storage unit (201) according to the vector calculation instruction to perform calculation between vectors, and return the calculation result to the channel storage unit (201) for storage ; The calculation result stored in the channel storage unit (201) is transmitted to the outside through the load storage module (300). 2. The vector processor supporting multi-precision calculation and dynamic configuration according to claim 1, characterized in that: the control module (100) includes an instruction distribution unit (101) and a main sequencing unit (102), the The instruction distribution unit (101) receives the operation instruction incoming from the outside, recognizes the type of the operation instruction and the corresponding functional unit after processing the operation instruction, and transmits the operation instruction to the main sequencing unit (102), and the main sequence unit (102) The sequence unit (102) broadcasts instructions to all functional units and monitors the running status of the instructions. 3. The vector processor supporting multi-precision calculation and dynamic configuration according to claim 1, characterized in that: the extended channel module (200) includes a channel instruction sequencing unit (203), the channel storage unit (201 ) and several calculation processing units (202), the calculation processing unit (202) includes the systolic array acceleration unit (202a). 4. The vector processor supporting multi-precision calculation and dynamic configuration according to claim 3, characterized in that: the channel storage unit (201) includes a vector register file (201a) and an operand queue (201b), and the The vector register file (201a) is used to provide the operand of the functional unit and absorb its result, and the operand queue (201b) is connected to the calculation processing unit (202) and the vector register file (201a), and is used to allocate each The operand of the calculation processing unit (202). 5. The vector processor supporting multi-precision calculation and dynamic configuration according to claim 4, characterized in that: said vector register file (201a) comprises some memory banks and arbitration units (201a-2), said memory bank It is a single port, and the bit width is set to 64 bits. Each of the vector register files (201a) is provided with 8 memory banks (201a-1) for loading and delivering data to be processed and calculation results, and the arbitration unit ( 201a-2) For allocating the priority of each operation instruction. 6. The vector processor supporting multi-precision calculation and dynamic configuration according to claim 4, characterized in that: the channel instruction sequencing unit (203) is used to provide each functional unit in the expansion channel module (200) An operation instruction is sent, and a request for reading an operand from the vector register file (201a) is initiated. 7. The vector processor supporting multi-precision calculation and dynamic configuration according to claim 4 or 5, characterized in that: the systolic array acceleration unit (202a) receives data read from the vector register file (201a) After the request, automatically input the data to be processed into the cache in order, and judge whether to start calculation according to the input mode after loading, and automatically store the calculation result in the output buffer, and wait for the instruction to output the result back to the vector register file (201a) middle. 8. According to the vector processor supporting multi-precision calculation and dynamic configuration according to any one of claims 1-6, it is characterized in that: the operation instructions are self-defined instructions, and the self-defined instructions are all vector instructions, including all The vector calculation instructions, vector load instructions and vector storage instructions, the self-defined instructions include target address information and action information; the self-defined instructions are input from the external vector processor for processing. 9. The vector processor supporting multi-precision calculation and dynamic configuration according to any one of claims 1-6, characterized in that: the load storage module (300) data loading unit (301) and data storage unit (302) , the data loading unit (301) loads data through the AXI AR bus, and the data storage unit (302) AXI AW bus is used to store data. 10. A processing method supporting multi-precision calculation and dynamic configuration, applied to the vector processor described in any one of rights 1 to 9, characterized in that: comprising, The control module (100) receives external input operation instructions; The control module (100) analyzes the operation instruction, obtains the vector calculation instruction and the vector storage load instruction, and determines the functional unit for sending the vector calculation instruction; The load storage module (300) loads data to be processed from the outside according to the vector storage load instruction; The systolic array acceleration unit (202a) in the extended channel module (200) obtains the corresponding data from the channel storage unit (201) to perform calculation between vectors according to the vector calculation instruction, and returns the calculation result to the channel storage unit (201 ) for storage; the calculation results stored in the channel storage unit (201) are transmitted to the outside through the load storage module (300).

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