CN115912904A - Substrate switching circuit and semiconductor structure - Google Patents
Substrate switching circuit and semiconductor structure Download PDFInfo
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- CN115912904A CN115912904A CN202211353911.3A CN202211353911A CN115912904A CN 115912904 A CN115912904 A CN 115912904A CN 202211353911 A CN202211353911 A CN 202211353911A CN 115912904 A CN115912904 A CN 115912904A
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Abstract
The application discloses a substrate switching circuit and a semiconductor structure, wherein the circuit comprises a comparator module, a first voltage and a second voltage, wherein the comparator module is used for generating a high level or a low level according to a voltage difference between the first voltage and the second voltage; a level shifter for converting the high level or the low level into an input analog signal of the driving stage inverter; the driving stage inverter is used for converting the input analog signal into a first control signal or a second control signal of the power switch module; and the power switch module is used for outputting the first voltage or the second voltage according to the first control signal and the second control signal so as to enable the voltage of the substrate to be higher. The method can convert different input voltages of the input substrate switching circuit into the voltage of the substrate through the comparator module, the level converter, the driving level inverter and the power switch module, and can save cost. The method can be widely applied to the technical field of semiconductor circuit design.
Description
Technical Field
The present application relates to the field of semiconductor circuit design technologies, and in particular, to a substrate switching circuit and a semiconductor structure.
Background
In a CMOS process, a substrate of a PMOS device is usually the highest voltage in a certain voltage domain in a design circuit, a voltage difference between the substrate and a source terminal of the PMOS device, that is, a substrate bias voltage, may affect a threshold voltage of the PMOS device, and in an off state or an anti-leakage state of the PMOS device, it is also necessary to ensure that the substrate voltage and the voltage of a gate terminal are sufficiently high. Therefore, in designs with different power supply voltages, if switching of the PMOS substrate voltage and the gate terminal voltage is ensured, the design is a vital part in low power consumption design and booster circuit design.
One of the common methods in the prior art is to use a simple 2-diode as shown in fig. 1. The characteristic of this technique is that it cannot be ensured that the substrate voltage of the PMOS is the highest of 2 voltages, and the gate-side control terminal voltage of the PMOS is also not the highest. In this case, the PMOS substrate voltage may be VIN minus a diode voltage, or the battery voltage minus a diode voltage, both of which may not properly control the PMOS to turn off;
in addition, according to another prior implementation scheme described in CN202111161432.7, with reference to fig. 2, it is characterized by including: the circuit comprises a hysteresis comparator, a phase inverter, a 2-layer NMOS and cross-coupling PMOS3/PMOS4, a resistor and a BJT tube, 2 diodes and a high-power switch tube PMOS1/PMOS2. Which in principle can achieve a maximum voltage of both VIN and VBAT. According to the principle analysis, the important disadvantage is that the driving current needs to be provided for the important PMOS1/PMOS2 gate terminal by the cross connection of the two MOS of PMOS3/PMOS 4. In practical design, the size of the PMOS1/PMOS2 device is relatively large, on one hand, for electrostatic protection, and on the other hand, for providing a sufficient current for VCC, although the diode D1/D2 can enhance the current driving to some extent, the path will fail when the voltage difference is smaller than that of the diode; and the gate terminal of the PMOS1/PMOS2 can not be changed too slowly when being turned off for faster control, and the scheme two mode can not provide faster gate terminal voltage control change on the principle structure, or the size of the PMOS3/PMOS4 is required to be larger, so that the area cost is also larger. In the scheme, a resistor R0 and a BJT1 exist, the fixed current exists, and the voltage of VBE is the gate end control voltage of NMOS1/NMOS 2; in such a structure, in a low power consumption design, a large resistor is required, for example, when VBAT =6V, assuming that a bias current of 50nA is required, R0= (6-0.6)/50n =108mohm resistor, and in a chip design, the area cost of the resistor with such a large resistance is very large; therefore, a new substrate switching circuit is needed.
Disclosure of Invention
The present application aims to solve at least to some extent one of the technical problems existing in the prior art.
Therefore, it is an object of the embodiments of the present application to provide a substrate switching circuit and a semiconductor structure, which can complete voltage switching of a PMOS substrate, thereby achieving cost saving while driving and preventing leakage.
In order to achieve the technical purpose, the technical scheme adopted by the embodiment of the application comprises the following steps: the comparator module is used for generating a high level or a low level according to a voltage difference between the input first voltage and the input second voltage;
a level shifter for converting the high level or the low level into an input analog signal of the driving stage inverter;
the driving stage inverter is used for converting the input analog signal into a first control signal or a second control signal of the power switch module;
and the power switch module is used for outputting the first voltage or the second voltage according to the first control signal and the second control signal so as to enable the voltage of the substrate to be increased.
In addition, according to the substrate switching circuit of the above embodiment of the present invention, the following additional features may be provided:
further, in the embodiment of the present application, the apparatus further includes a filtering module; the first output end of the filtering module is externally connected with the output end of the substrate switching circuit; and the second output end of the filtering module is externally connected with a low level.
Further, in this embodiment of the application, the power switch module includes a fifth MOS transistor and a sixth MOS transistor; the drain electrode of the fifth MOS tube is externally connected with the input end of the first voltage, the grid electrode of the fifth MOS tube is connected with the fourth output end of the driving-stage phase inverter, and the source electrode of the fifth MOS tube is externally connected with the output end of the substrate switching circuit; the drain electrode of the sixth MOS tube is externally connected with the input end of the second voltage, the grid electrode of the sixth MOS tube is connected with the third output end of the driving-stage phase inverter, and the source electrode of the sixth MOS tube is externally connected with the output end of the substrate switching circuit.
Further, the driving stage inverter in the embodiment of the present application includes: the MOS transistor comprises a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor; the source electrode of the first MOS tube is connected with the drain electrode of the second MOS tube in series; the grid electrode of the first MOS tube is connected with the grid electrode of the second MOS tube in series and then is used as the input end of the driving-stage inverter; the drain electrode of the first MOS tube is connected with the drain electrode of the third MOS tube and then is used as a first output end of the driving-stage phase inverter; a source electrode of the second MOS tube is connected with a source electrode of the fourth MOS tube in parallel and then serves as a second output end of the driving phase inverter, and the second output end is externally connected with a low level; a source electrode of the third MOS tube is connected with a drain electrode of the fourth MOS tube in series to serve as a third output end, and the third output end is connected with the source electrode of the first MOS tube and a grid electrode of the sixth MOS tube; and the source electrode of the third MOS tube is connected with the grid electrode of the fifth MOS tube, and the source electrode of the third MOS tube is the fourth output end of the driving-stage phase inverter.
Further, in the embodiment of the present application, the filtering module includes one or more capacitors.
Further, in the embodiment of the present application, the fifth MOS transistor and the sixth MOS transistor are both PMOS transistors.
Further, in this embodiment of the application, when the filtering module includes a plurality of capacitors, the plurality of capacitors are connected in parallel with each other.
On the other hand, embodiments of the present application further provide a semiconductor structure including a substrate switching circuit according to any one of the above embodiments.
Advantages and benefits of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application:
the voltage switching of the PMOS substrate can be completed by converting different input voltages of the input substrate switching circuit into the voltage of the substrate through the comparator module, the level converter, the driving level inverter and the power switch module, so that the driving and the electric leakage prevention are realized, and the circuit structure is simple, and the cost is saved.
Drawings
FIG. 1 is a schematic diagram of a substrate switching circuit according to the prior art;
FIG. 2 is a schematic diagram of a substrate switching circuit in an embodiment of the present invention;
FIG. 3 is a schematic diagram of another substrate switching circuit in an embodiment of the invention.
Detailed Description
The principles and processes of substrate switching circuits, systems, devices, and storage media in embodiments of the present invention are described in detail below with reference to the following drawings.
Referring to fig. 1, a substrate switching circuit of the present invention includes a comparator module connected to a level shifter; the level shifter is connected with the driving inverter; the power switch module is connected with the driving inverter;
the comparator module can generate a high level or a low level according to a voltage difference between an input first voltage and an input second voltage; specifically, the first voltage may be a driving voltage of a semiconductor such as 3.3v,5v, or the like, or may be other values; the second voltage is any voltage value different from the first voltage, and the second voltage value cannot be larger than the rated voltage of other devices of the circuit; the comparator can be integrated by an operational amplifier and other NMOS transistors, or can be a comparator in the prior art, the comparator is the only current consumption power consumption circuit in the embodiment of the application, the current of the comparator is provided by the input first voltage, the first voltage in the actual design is the external power supply voltage and changes within the range of the established requirement, namely the first voltage belongs to the voltage range required by the actual design, therefore, the current of the comparator is more effectively controllable and cannot be influenced by the boost voltage or the second voltage, and the comparator has better controllability and reliability design.
The level shifter may convert the high level or the low level into an input analog signal of the driving stage inverter; in the embodiment of the present application, the practical application circuit of the level shifter is relatively simple, and the requirement is that the logic signal transmission can be performed normally according to the voltage ranges of the first input voltage and the output voltage, so that in practice, the level shifter can be realized by a small number of MOS transistors, the consumed area cost is very small, and meanwhile, no static current exists to realize low power consumption.
The driving stage inverter can convert the input analog signal into a first control signal or a second control signal of the power switch module; in this embodiment, the power switch module may be composed of two field effect transistors, the first control signal is an electrical signal for driving one of the field effect transistors of the power switch module, and the second control signal is an electrical signal for driving the other field effect transistor of the power switch module; the driving stage inverter can increase the output logic level of the level shifter by a sufficient driving capability, and according to the foregoing description, since the scheme needs to consider a certain driving capability, the power switch module has a PMOS with a relatively large size, and therefore the purpose of enhancing the driving capability here is to drive the PMOS in a faster flip, and the faster flip is also to reduce the power consumption to a certain extent. Since the inverter operates in the output voltage domain, whether the high-voltage MOS transistor is used or not needs to be selected by considering the output voltage under certain conditions.
A power switch module capable of outputting the first voltage or the second voltage according to the first control signal and the second control signal; in the embodiment of the application, the PMOS transistor of the power switch module is characterized in that the substrate is an output voltage, the voltage state of the PMOS transistor is the highest voltage of the first voltage and the second voltage, if the second voltage is lower than the first voltage in the starting process, the output voltage can be switched to the voltage of the first voltage well, and the PMOS transistor of the power switch module has certain driving capability, so that the PMOS transistor can be well applied to other circuits and modules, and can be conveniently applied to low-power design of a system level in a low-power chip.
Further, in this embodiment of the application, referring to fig. 2, the power switch module may include a fifth MOS transistor M5 and a sixth MOS transistor M6; the drain of the fifth MOS transistor M5 is externally connected to the input terminal VDD1 of the first voltage, the gate of the fifth MOS transistor M5 is connected to the fourth output terminal of the driving-stage inverter, and the source of the fifth MOS transistor M5 is externally connected to the output terminal VSUB of the substrate switching circuit; the drain of the sixth MOS transistor M6 is externally connected to an input terminal VDD2 of a second voltage, the gate of the sixth MOS transistor M6 is connected to a third output terminal of the driving-stage inverter, and the source of the sixth MOS transistor M6 is externally connected to an output terminal VSUB of the substrate switching circuit;
further, referring to fig. 2, in the embodiment of the present application, the driving stage inverter may include: the MOS transistor comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3 and a fourth MOS transistor M4; the source electrode of the first MOS tube M1 is connected with the drain electrode of the first MOS tube M2 in series; the grid electrode of the first MOS tube M1 is connected with the grid electrode of the second MOS tube M2 in series and then is used as the input end of the driving-stage inverter; the drain electrode of the first MOS tube M1 is connected with the drain electrode of the third MOS tube M3 and then is used as the first output end of the driving-stage phase inverter; the source electrode of the second MOS tube M2 and the source electrode of the fourth MOS tube M4 are connected in parallel and then serve as a second output end of the driving phase inverter, and the second output end is externally connected with a low level VSS1; the source electrode of the third MOS tube M3 is connected with the drain electrode of the fourth MOS tube M4 in series to serve as a third output end, and the third output end is connected with the source electrode of the first MOS tube M1 and the grid electrode of the sixth MOS tube M6; the source electrode of the third MOS transistor M3 is connected to the gate electrode of the fifth MOS transistor M5, and the source electrode of the third MOS transistor M3 is the fourth output end of the driving-stage inverter.
Further, in the embodiment of the present application, referring to fig. 2, the substrate switching circuit may further include a filtering module; the first output end of the filtering module is externally connected with the output end VSUB of the substrate switching circuit, and the output end VSUB of the substrate switching circuit is also the source electrode of the fifth MOS tube M5 and the sixth MOS tube M6 in the power switch module; the second output end of the filtering module may be externally connected to a low level VSS1.
Further, in the embodiment of the present application, the filtering module includes one or more capacitors; when the capacitors are multiple, the capacitors can comprise multiple same capacitors or different capacitors, and the specific setting can be carried out according to the requirement; the purpose of the filtering module is that VSUB can be better driven to other module circuits, and if transient switching current and static current do not need to be provided for other modules according to practical application, the capacitance here can be reduced as much as possible or any capacitance is not needed, because the static driving circuit and large dynamic driving current do not exist in the switching module here.
Further, in the embodiment of the present application, the fifth MOS transistor M5 and the sixth MOS transistor M6 are both PMOS transistors.
Further, in this embodiment of the application, when the filtering module includes a plurality of capacitors, the plurality of capacitors are connected in parallel with each other.
Referring to fig. 3, the working principle of the substrate switching circuit of the present application is explained below with reference to specific embodiments:
when VDD2 is larger than VDD1, VDD1 is 5V, when VDD2 is 6V, the output of the level shifter is high level, at the moment, the output end connected with M6 outputs high level through level shifting and a driving level inverter, M6 is conducted under the high level, and VSUB outputs the same voltage as VDD2 after M6 is conducted;
when VDD1 is larger than VDD1, VDD1 is 5V, when VDD2 is 4V, the output of the level shifter is low level, at the moment, the output end connected with M5 outputs high level through level shifting and a driving level inverter, M5 is conducted under the high level, and after M5 is conducted, VSUB outputs the same voltage as VDD 1.
In addition, embodiments of the present application further provide a semiconductor structure, which may include at least one substrate switching circuit as described in any of the above embodiments, and the semiconductor structure has an advantage of low cost due to the substrate switching circuit.
In the foregoing description of the specification, reference to the description of "one embodiment/example," "another embodiment/example," or "certain embodiments/examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: numerous changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the application, the scope of which is defined by the claims and their equivalents.
While the present application has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A substrate switching circuit, comprising:
the comparator module is used for generating a high level or a low level according to a voltage difference between the input first voltage and the input second voltage;
a level shifter for converting the high level or the low level into an input analog signal of the driving stage inverter;
the driving stage inverter is used for converting the input analog signal into a first control signal or a second control signal of the power switch module;
and the power switch module is used for outputting the first voltage or the second voltage according to the first control signal and the second control signal so as to enable the voltage of the substrate to be increased.
2. The substrate switching circuit of claim 1, further comprising a filtering module; the first output end of the filtering module is externally connected with the output end of the substrate switching circuit; and the second output end of the filtering module is externally connected with a low level.
3. The substrate switching circuit according to claim 1, wherein the power switch module comprises a fifth MOS transistor and a sixth MOS transistor; the drain electrode of the fifth MOS tube is externally connected with the input end of the first voltage, the grid electrode of the fifth MOS tube is connected with the fourth output end of the driving-stage phase inverter, and the source electrode of the fifth MOS tube is externally connected with the output end of the substrate switching circuit; the drain electrode of the sixth MOS tube is externally connected with the input end of the second voltage, the grid electrode of the sixth MOS tube is connected with the third output end of the driving-stage phase inverter, and the source electrode of the sixth MOS tube is externally connected with the output end of the substrate switching circuit.
4. The substrate switching circuit of claim 3, wherein the driver stage inverter comprises:
the MOS transistor comprises a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor; the source electrode of the first MOS tube is connected with the drain electrode of the second MOS tube in series; the grid electrode of the first MOS tube is connected with the grid electrode of the second MOS tube in series and then is used as the input end of the driving-stage inverter; the drain electrode of the first MOS tube is connected with the drain electrode of the third MOS tube and then is used as a first output end of the driving-stage phase inverter; a source electrode of the second MOS tube is connected with a source electrode of the fourth MOS tube in parallel and then serves as a second output end of the driving phase inverter, and the second output end is externally connected with a low level; a source electrode of the third MOS tube is connected with a drain electrode of the fourth MOS tube in series to serve as a third output end, and the third output end is connected with a source electrode of the first MOS tube and a grid electrode of the sixth MOS tube; and the source electrode of the third MOS tube is connected with the grid electrode of the fifth MOS tube, and the source electrode of the third MOS tube is the fourth output end of the driving-stage phase inverter.
5. The substrate switching circuit of claim 2, wherein the filtering module comprises one or more capacitors.
6. The substrate switching circuit of claim 3, wherein the fifth MOS transistor and the sixth MOS transistor are both PMOS transistors.
7. The substrate switching circuit of claim 5, wherein when the filtering module comprises a plurality of capacitors, the plurality of capacitors are connected in parallel with each other.
8. A semiconductor structure comprising a substrate switching circuit as claimed in any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211353911.3A CN115912904A (en) | 2022-11-01 | 2022-11-01 | Substrate switching circuit and semiconductor structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211353911.3A CN115912904A (en) | 2022-11-01 | 2022-11-01 | Substrate switching circuit and semiconductor structure |
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| CN115912904A true CN115912904A (en) | 2023-04-04 |
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| CN202211353911.3A Pending CN115912904A (en) | 2022-11-01 | 2022-11-01 | Substrate switching circuit and semiconductor structure |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202134953U (en) * | 2011-02-15 | 2012-02-01 | 深圳市锐能微科技有限公司 | power switching circuit |
| US20120030494A1 (en) * | 2010-07-31 | 2012-02-02 | Huawei Technologies Co., Ltd. | Power supply selector and power supply selection method |
| CN109756220A (en) * | 2019-03-07 | 2019-05-14 | 上海长园维安电子线路保护有限公司 | A substrate potential selection circuit |
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2022
- 2022-11-01 CN CN202211353911.3A patent/CN115912904A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120030494A1 (en) * | 2010-07-31 | 2012-02-02 | Huawei Technologies Co., Ltd. | Power supply selector and power supply selection method |
| CN202134953U (en) * | 2011-02-15 | 2012-02-01 | 深圳市锐能微科技有限公司 | power switching circuit |
| CN109756220A (en) * | 2019-03-07 | 2019-05-14 | 上海长园维安电子线路保护有限公司 | A substrate potential selection circuit |
Non-Patent Citations (1)
| Title |
|---|
| 陈阳光;张扬;李琦;: "一种基于电荷泵的衬底电位选择器设计", 桂林电子科技大学学报, no. 04, pages 272 - 274 * |
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