CN115911147B - Selective emitter and preparation method thereof, solar cell and solar module - Google Patents

Abstract

The invention discloses a selective emitter, a preparation method thereof, a solar cell and a solar module, relates to the field of solar cells, and aims to solve the problems of complex process and high manufacturing difficulty of the selective emitter. The preparation method comprises the following steps: texturing at least one surface of the silicon substrate to obtain a textured structure; doping treatment is carried out on the surface of the suede structure so as to form a low-concentration doped layer covering the suede structure and a high-concentration doped layer covering the low-concentration doped layer; the thickness of the high-concentration doped layer positioned at the top of the suede structure is larger than that of the high-concentration doped layers positioned at the other positions; and etching the whole surface of the high-concentration doped layer, wherein the etching thickness is greater than or equal to the thickness of the high-concentration doped layer positioned at the other positions so as to remove the high-concentration doped layer positioned at the other positions and keep the residual high-concentration doped layer positioned at the top position. The method does not need a mask process, simplifies the process, does not need the overlapping of the high-concentration doped layer pattern and the metal electrode pattern, and reduces the manufacturing difficulty.

Description

Selective emitter and preparation method thereof, solar cell and solar module

Technical Field

The invention relates to the technical field of solar cells, and in particular to a selective emitter and a preparation method thereof, a solar cell and a solar module.

Background Art

The selective emitter of a solar cell refers to a high-concentration doping area formed under and near the metal electrode, and a low-concentration doping area in other areas. The doping concentration of the high-concentration doping area is greater than the doping concentration of the low-concentration doping area. This can reduce the recombination of minority carriers between the cell emitter and the surface, increase the minority carrier lifetime of the emitter, form a high-low junction with the low-concentration doping area, and increase the open-circuit voltage of the cell. At the same time, the doping concentration of different areas of the selective emitter can not only reduce the Auger recombination caused by impurity doping in the solar cell, but also ensure that the metal electrode and the silicon substrate form an ohmic contact through the high-concentration doping area, thereby improving the cell conversion efficiency.

However, when preparing high-concentration doping areas and low-concentration doping areas, the pattern of the high-concentration doping area needs to overlap and match the pattern of the metal electrode. This requires high processing accuracy and is difficult to manufacture. A mask process is usually required, which is not only cumbersome, but also the high processing accuracy will affect the product yield.

Summary of the invention

The object of the present invention is to provide a selective emitter and a preparation method thereof, a solar cell and a solar module, so as to simplify the process and reduce the difficulty of manufacturing.

In a first aspect, the present invention provides a method for preparing a selective emitter, comprising the steps of:

Forming a velvet surface on at least one side of the silicon substrate to obtain a velvet surface structure;

Performing a doping treatment on the surface of the velvet structure to form a low-concentration doping layer covering the velvet structure and a high-concentration doping layer covering the low-concentration doping layer; wherein the thickness of the high-concentration doping layer located at the top of the velvet structure is greater than the thickness of the high-concentration doping layer located at other positions of the velvet structure;

The entire surface of the high-concentration doped layer is etched, and the etching thickness of the etching treatment is greater than or equal to the thickness of the high-concentration doped layer located at the rest of the velvet structure, so as to remove the high-concentration doped layer located at the rest of the velvet structure and retain the remaining high-concentration doped layer located at the top of the velvet structure.

When adopting the above technical solution, the surface of the velvet structure is first doped as a whole to obtain a low-concentration doping layer covering the entire velvet structure and a high-concentration doping layer covering the entire low-concentration doping layer, that is, the doping concentration of the surface layer close to the velvet structure is larger, and the doping concentration of the surface layer far from the velvet structure is smaller. Since the top of the velvet structure has a smaller cross-section than the bottom, when the high-concentration doping layer is formed, the doping atoms entering the top position of the velvet structure are more concentrated, and more doping atoms will reach the top position, making the doping concentration of this position higher than that of other areas under the same doping conditions. Based on Fick's first law, the doping speed at the top position is higher, so the doping depth is deeper, so that the thickness of the high-concentration doping layer located at the top position of the velvet structure is greater than the thickness of the high-concentration doping layer located at the rest of the velvet structure. Afterwards, the entire surface of the high-concentration doped layer is etched, and the etching thickness of each area of the entire surface of the high-concentration doped layer is basically the same, but the thickness of the high-concentration doped layer at the top position of the velvet structure is thicker, and the etching thickness is greater than or equal to the thickness of the high-concentration doped layer at the rest of the velvet structure. Therefore, after etching away the high-concentration doped layer of the same thickness, the high-concentration doped layer at the rest of the velvet structure is removed to expose the underlying low-concentration doped layer, and after etching away part of the high-concentration doped layer at the top position of the velvet structure, the remaining high-concentration doped layer is still retained. Finally, a selective emitter is formed on all the velvet structures of the entire silicon substrate, with only the high-concentration doped layer at the top position and the low-concentration doped layer at the rest of the position. Compared with the existing preparation of high-concentration doping regions and low-concentration doping regions, the present application can obtain a selective emitter only through the doping process and etching process that exist in the existing schemes. The process of forming the high-concentration doping layer and the low-concentration doping layer does not require a mask process, thereby simplifying the process. The high-concentration doping layer in the present application is formed along the position of the velvet structure on the silicon substrate, and there is no need to overlap and match the pattern of the high-concentration doping layer with the pattern of the metal electrode. Therefore, high processing accuracy is not required, which reduces the manufacturing difficulty and improves the product yield.

In addition, when the selective emitter obtained by the preparation method of the present application is in conductive contact with the metal electrode, no matter what the pattern of the metal electrode is, as long as the metal electrode can be conductively contacted with the high-concentration doped layer at the top position of the velvet structure below it, the conditions for forming an ohmic contact can be met. Although the high-concentration doped layer in the present application is discretely distributed on the entire silicon substrate, it only exists at the top position of the velvet structure. The sum of the projected areas of all the high-concentration doped layers on the silicon substrate accounts for an area equivalent to the top position of the velvet structure on the entire silicon substrate, which can reach 2% to 4%. Compared with the prior art, in order to ensure that the metal electrode printing falls within the high-concentration doped area, the area of the high-concentration doped area accounts for 6%-10%. The proportion of the high-concentration doped layer in the present application is relatively small, which reduces Auger recombination, thereby improving the photoelectric conversion efficiency of the solar cell.

In some possible implementations, the maximum temperature of the doping treatment is a value within the range of 760°C to 800°C. When the doping treatment is performed at this maximum temperature, a doping structure can be formed on the velvet structure of the silicon substrate, with a high-concentration doping layer close to the surface and a low-concentration doping layer away from the surface, and the thickness of the high-concentration doping layer and the low-concentration doping layer meet the requirements of subsequent etching treatment. If the temperature is lower than this temperature range, a doping structure with a high-concentration doping layer on the surface may not be formed. If the temperature is higher than this temperature range, the thickness of the high-concentration doping layer in the doping structure may be too deep, which is not conducive to subsequent etching removal.

In some possible implementations, the doping process is a thermal diffusion doping process, an ion implantation doping process, or a doping source coating and advancing process. Regardless of the doping method used, as long as a doping structure with a high-concentration doping layer on the surface and a low-concentration doping layer away from the surface can be formed on the silicon substrate.

In some possible implementations, when the doping treatment is a thermal diffusion doping process, the doping treatment of the surface of the velvet structure includes: introducing the doping source gas into the diffusion doping equipment, the maximum temperature of the thermal diffusion doping process is a value in the range of 760°C to 800°C, and the doping source gas includes nitrogen, oxygen and dopants.

When adopting the above technical solution, nitrogen carrying oxygen and dopants is introduced into the diffusion doping equipment, and the velvet structure is thermally diffused doped within the maximum diffusion temperature range of 760°C to 800°C. The dopants are doped into the surface of the silicon substrate at this temperature to form a high-concentration doping layer on the surface and a low-concentration doping layer away from the surface.

In some possible implementations, after the doping treatment, the thickness of the high-concentration doping layer formed on the remaining positions of the velvet structure is in the range of 5nm to 10nm, and the thickness of the low-concentration doping layer formed on the velvet structure is in the range of 120nm to 150nm.

In some possible implementations, the etching thickness of the entire surface of the high-concentration doping layer is within a range of 5 nm to 10 nm.

In some possible implementations, after etching, the sum of the projected areas of the remaining high-concentration doped layers remaining at the top of the velvet structure on the silicon substrate accounts for 2% to 4% of the area of one side of the silicon substrate. Although the high-concentration doped layers in the present application are discretely distributed on the entire silicon substrate, they only exist at the top of the velvet structure. The sum of the projected areas of all the high-concentration doped layers on the silicon substrate accounts for an area equivalent to the top of the velvet structure on the entire silicon substrate, which can reach 2% to 4%. Compared with the prior art, in order to ensure that the metal electrode printing falls within the high-concentration doped area, the area of the high-concentration doped area accounts for 6%-10%. The proportion of the high-concentration doped layer in the present application is small, which reduces Auger recombination, thereby improving the photoelectric conversion efficiency of the solar cell.

In some possible implementations, etching the entire surface of the high-concentration doped layer includes: etching the entire surface of the high-concentration doped layer using a potassium hydroxide solution with a concentration of 1.5% to 4%. Under this concentration of potassium hydroxide solution, it can be ensured that the high-concentration doped layer is removed, and only the high-concentration doped layer at the top of the velvet structure is retained. If the concentration is small, the high-concentration doped layer may remain at other positions during the etching process, which is not conducive to reducing Auger recombination. If the concentration is too high, the high-concentration doped layer at the top of the velvet structure may also be removed, which is not conducive to the formation of ohmic contact between the metal electrode and the silicon substrate, and there may be excessive etching and polishing, resulting in an unclear velvet structure, weakened light trapping, and increased reflectivity.

In some possible implementations, the shape of the suede structure is selected from one or more of a columnar shape, a cone shape, a terrace shape, an arc-shaped groove, or an arc-shaped protrusion.

In some possible implementations, the velvet structure is a pyramid structure, and the length of the bottom side of the pyramid structure is 50nm to 400nm. After etching, the remaining high-concentration doping layer in the top area of the pyramid structure is retained. Since the pyramid structure has a top area, it is easier to form a high-concentration doping layer with higher concentration and deeper depth in the top area than in the rest of the pyramid structure during doping, which is conducive to retaining the high-concentration doping layer in the top area when the high-concentration doping layer of the same thickness is subsequently etched. For a pyramid structure of this size, the spacing of the high-concentration doping layer obtained after etching can achieve a tunneling spacing of 0.1μm to 0.6μm, and the total area of the high-concentration doping layer accounts for about 2% to 4%, which can maintain the resistance between the metal electrode and silicon at an extremely low level, the series resistance increases less, and the open circuit voltage is greatly improved. Compared with the entire surface diffused high-concentration doping layer, the photoelectric conversion efficiency can be increased by about 0.25% to 0.3%. If the bottom side length of the pyramid structure is less than 50nm, the pyramid structure is too small and can be easily completely etched away, making it difficult to control. If the bottom side length of the pyramid structure is greater than 400nm, the spacing between high-concentration doped layers is too large, the metal electrode ohmic contact tunneling spacing is too large, and the contact resistance is too high.

In a second aspect, the present invention also provides a selective emitter, comprising a silicon substrate, at least one side of the silicon substrate being a velvet structure, the top of the velvet structure being covered with a high-concentration doping layer, and the rest of the velvet structure being covered with a low-concentration doping layer, wherein the doping concentration of the high-concentration doping layer is greater than the doping concentration of the low-concentration doping layer.

When the above technical solution is adopted, the high-concentration doped layer in the present application is formed along with the position of the velvet structure on the silicon substrate, and there is no need to overlap and match the pattern of the high-concentration doped area with the pattern of the metal electrode, so high processing accuracy is not required, which reduces the manufacturing difficulty and improves the yield of the product. In addition, when the selective emitter in the present application is in conductive contact with the metal electrode, no matter what the pattern of the metal electrode is, as long as the metal electrode can be in conductive contact with the high-concentration doped layer at the top position of the velvet structure below it, the conditions for forming an ohmic contact can be met.

In some possible implementations, the sum of the projected areas of the high-concentration doping layers on the silicon substrate accounts for 2% to 4% of the area of one side of the silicon substrate. Although the high-concentration doping layers in the present application are discretely distributed on the entire silicon substrate, they only exist at the top of the velvet structure. The sum of the projected areas of all the high-concentration doping layers on the silicon substrate accounts for an area equivalent to the top of the velvet structure on the entire silicon substrate, which can reach 2% to 4%. Compared with the prior art, in order to ensure that the metal electrode printing falls within the high-concentration doping area, the area of the high-concentration doping area accounts for 6% to 10%. The proportion of the high-concentration doping layer in the present application is relatively small, which reduces Auger recombination, thereby improving the photoelectric conversion efficiency of the solar cell.

In some possible implementations, the maximum thickness of the high-concentration doping layer is 10 nm to 25 nm, and the thickness of the low-concentration doping layer is 120 nm to 150 nm.

In some possible implementations, the velvet structure is a pyramid structure, the bottom side length of the pyramid structure is 50nm to 400nm, and only the top area of the pyramid structure is covered with a high-concentration doping layer. For a pyramid structure of this size, the spacing of the high-concentration doping layer on the top area can achieve a tunneling spacing of 0.1μm to 0.6μm, and the total area of the high-concentration doping layer accounts for about 2% to 4%, which can maintain the resistance between the metal electrode and silicon at an extremely low level, the series resistance increases less, and the open circuit voltage is greatly improved. Compared with the entire surface diffused high-concentration doping layer, the photoelectric conversion efficiency can be improved by about 0.25% to 0.3%. If the bottom side length of the pyramid structure is less than 50nm, the size of the pyramid structure is too small, it is easy to be completely etched, and it is difficult to control. If the bottom side length of the pyramid structure is greater than 400nm, the spacing of the high-concentration doping layer is too large, the tunneling spacing of the metal electrode ohmic contact is too large, and the contact resistance is too high.

In a third aspect, the present invention further provides a solar cell comprising a selective emitter and a metal electrode, wherein the selective emitter is any one of the selective emitters described above, and the metal electrode is in conductive contact with a high-concentration doping layer on a partial velvet structure of the selective emitter.

Since the solar cell adopts the selective emitter in the second aspect of the present application, the solar cell has the same technical effect as the selective emitter in the second aspect, which will not be described in detail here.

In a fourth aspect, the present invention further provides a solar cell assembly, comprising a solar cell, a connection structure and a packaging structure, wherein the connection structure is used to enable the solar cell to form a direct current output, and the packaging structure is used to package the solar cell; the solar cell is the solar cell described in the third aspect.

Since the solar cell module adopts the solar cell in the present application, it has the same technical effect as the solar cell, which will not be described in detail here.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

FIG1 is a schematic diagram of a texturing process in a method for preparing a selective emitter provided by an embodiment of the present invention;

FIG2 is a schematic diagram of a doping process in a method for preparing a selective emitter provided by an embodiment of the present invention;

FIG3 is a schematic diagram of an etching process in a method for preparing a selective emitter provided in an embodiment of the present invention;

FIG4 is a schematic diagram showing the principle of a method for preparing a selective emitter provided in an embodiment of the present invention;

FIG5 is a schematic top view of a selective emitter provided by an embodiment of the present invention;

FIG. 6 is a schematic diagram showing the relationship between doping concentrations at different depths of a textured structure of a selective emitter provided by an embodiment of the present invention.

Reference numerals: 1 is a suede structure, 11 is a high-concentration doping layer, 12 is a low-concentration doping layer, and 2 is a silicon substrate.

DETAILED DESCRIPTION

In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by the terms "up", "down", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

An embodiment of the present invention provides a method for preparing a selective emitter, comprising the following steps:

Step S100, as shown in FIG1, is to perform texturing on at least one side of a silicon substrate 2 to obtain a textured structure 1. The silicon substrate 2 may be a P-type single crystal silicon wafer or an N-type single crystal silicon wafer. For example, the silicon substrate 2 is a boron-doped single crystal silicon wafer. Before texturing, the silicon substrate 2 may be cleaned to remove impurities adsorbed on the surface of the silicon substrate 2 during processes such as slicing, grinding, chamfering, and polishing.

The texturing can be performed on one surface of the silicon substrate 2 or on both surfaces of the silicon substrate 2. The specific texturing process conditions can be adjusted according to actual needs. For example, a mixed solution of sodium hydroxide and isopropyl alcohol can be used to etch a single crystal silicon wafer to obtain a velvet structure 1. For example, the shape of the velvet structure 1 includes one or more of a columnar, conical, terraced, arc-shaped groove or arc-shaped protrusion, and these velvet structures 1 are naturally formed during the texturing process. Velvet structures 1 of different sizes can be obtained by adjusting the concentration of sodium hydroxide and isopropyl alcohol, the etching temperature, and the etching time. The size of the velvet structure 1 is not limited in this embodiment.

Step S200, as shown in FIG2, the surface of the velvet structure 1 is doped to form a low-concentration doping layer 12 covering the velvet structure 1 and a high-concentration doping layer 11 covering the low-concentration doping layer 12, that is, the doping concentration of the surface layer close to the velvet structure 1 is larger, and the doping concentration of the surface layer away from the velvet structure 1 is smaller, as shown in FIG6; wherein, the thickness of the high-concentration doping layer 11 located at the top position of the velvet structure 1 is greater than the thickness of the high-concentration doping layer 11 located at the rest of the velvet structure 1. Since the top of the velvet structure 1 is smaller than the bottom cross-section, when the high-concentration doping layer 11 is formed, the doping atoms doped into the top position of the velvet structure 1 are more concentrated, and more doping atoms will reach the top position, making the doping concentration of this position higher than that of other positions under the same doping conditions. Based on Fick's first law, the doping speed at the top position is higher, so the doping depth is deeper, so that the thickness of the high-concentration doping layer 11 located at the top position of the velvet structure 1 is greater than the thickness of the high-concentration doping layer 11 located at the rest of the velvet structure 1.

In step S300, as shown in FIGS. 3-5 , the entire surface of the high-concentration doped layer 11 is etched, and the etching thickness of the etching is greater than or equal to the thickness of the high-concentration doped layer 11 located at the rest of the velvet structure 1, so as to remove the high-concentration doped layer 11 located at the rest of the velvet structure 1 and retain the remaining high-concentration doped layer 11 located at the top of the velvet structure 1.

Since the etching thickness H of each area of the entire high-concentration doped layer 11 is basically the same, as shown in Figure 4, but the thickness of the high-concentration doped layer 11 at the top position of the velvet structure 1 is thicker, and the etching thickness H is greater than or equal to the thickness of the high-concentration doped layer 11 located at the rest of the velvet structure 1, so after etching away the high-concentration doped layer 11 of the same thickness, the high-concentration doped layer 11 at the rest of the velvet structure 1 is removed to expose the low-concentration doped layer 12 underneath, and after etching away part of the high-concentration doped layer 11 at the top position of the velvet structure 1, the remaining thickness of the high-concentration doped layer 11 is still retained, and finally, all the velvet structures 1 of the entire silicon substrate 2 are formed with a selective emitter having only the high-concentration doped layer 11 at the top position and the low-concentration doped layer 12 at the rest of the position.

In the case of adopting the above technical solution, the surface of the velvet structure 1 is firstly doped as a whole to obtain a low-concentration doping layer 12 covering the entire velvet structure 1 and a high-concentration doping layer 11 covering the entire low-concentration doping layer 12. After that, the entire high-concentration doping layer 11 is etched. After etching away the high-concentration doping layer 11 of the same thickness, only the remaining high-concentration doping layer 11 at the top position of the velvet structure 1 is retained. Finally, all the velvet structures 1 of the entire silicon substrate 2 are formed with a selective emitter having only the high-concentration doping layer 11 at the top position and the low-concentration doping layer 12 at the remaining position. Compared with the existing preparation of high-concentration doping areas and low-concentration doping areas, the present application only uses the doping process and etching process used in the existing solution to obtain a selective emitter. The process of forming the high-concentration doping layer 11 and the low-concentration doping layer 12 does not require the mask process in the prior art. Therefore, the process is simplified and the manufacturing cost can be reduced. Moreover, the high-concentration doped layer 11 in the present application is formed along with the position of the velvet structure 1 on the silicon substrate 2, and there is no need to overlap and match the pattern of the high-concentration doped layer 11 with the pattern of the metal electrode. Therefore, high processing accuracy is not required, which reduces the manufacturing difficulty and improves the product yield.

In addition, when the selective emitter obtained by the preparation method of the present application is in conductive contact with the metal electrode, no matter what the pattern of the metal electrode is, as long as the metal electrode can be conductively contacted with the high-concentration doping layer 11 at the top position of the velvet structure 1 in the area below it, the conditions for forming an ohmic contact can be met. Although the high-concentration doping layer 11 in the present application is discretely distributed on one surface of the entire silicon substrate 2, it only exists at the top position of each velvet structure. The sum of the projected areas of all the high-concentration doping layers 11 on the silicon substrate 2 is equivalent to the proportion of the top positions of all the velvet structures 1 on the entire silicon substrate 2, which can reach 2% to 4%. Compared with the prior art, in order to ensure that the metal electrode printing falls within the high-concentration doping area, the area of the high-concentration doping area accounts for 6%-10%. The proportion of the high-concentration doping layer 11 in the present application is relatively small. Since the overall doping concentration of the silicon substrate 2 is relatively small, Auger recombination is reduced, thereby improving the photoelectric conversion efficiency of the solar cell.

In some embodiments, the maximum temperature of the doping treatment in step S200 is a value within the range of 760°C to 800°C. For example, the maximum temperature of the doping treatment may be 760°C, 765°C, 772°C, 778°C, 785°C, 790°C, 800°C, etc. When the doping treatment is performed at the maximum temperature, a doping structure having a high-concentration doping layer 11 near the surface and a low-concentration doping layer 12 far from the surface can be formed on the textured structure 1 of the silicon substrate 2. As shown in FIG6 , the thicknesses of the high-concentration doping layer 11 and the low-concentration doping layer 12 meet the requirements of subsequent etching treatment. If the temperature is lower than this temperature range, the doped structure with a high-concentration doped layer 11 on the surface may not be formed or the thickness of the formed high-concentration doped layer 11 may be thin, and the subsequent etching process is not easy to control, resulting in the high-concentration doped layer 11 being completely etched away. If the temperature is higher than this temperature range, the thickness of the high-concentration doped layer 11 in the doped structure may be too deep, which is not conducive to subsequent etching and removal. The etching removal is difficult and the etching time is long. The concentration of the required etching solution is relatively large, which may cause the velvet structure 1 to be destroyed and the reflectivity to increase, which is not conducive to the light trapping effect.

In some embodiments, in step S200, after doping treatment, the thickness of the high-concentration doping layer 11 formed at the remaining positions (non-top positions) of the velvet structure 1 is in the range of 5nm to 10nm. Specifically, the thickness of the high-concentration doping layer 11 at this position can be 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, etc.; the thickness of the low-concentration doping layer 12 formed on the velvet structure 1 is in the range of 120nm to 150nm. For example, the thickness of the low-concentration doping layer 12 is 120nm, 125nm, 130nm, 135nm, 140nm, 145nm, 150nm, etc. It should be noted that, as shown in Figures 2 and 4, the thickness of the high-concentration doping layer 11 formed by doping at the top position of the velvet structure 1 is greater than the thickness of the high-concentration doping layer 11 formed at the remaining positions. Specifically, when the thickness of the high-concentration doping layer 11 at the remaining positions is 5nm, the maximum thickness of the high-concentration doping layer 11 at the top position is 15nm; when the thickness of the high-concentration doping layer 11 at the remaining positions is 7nm, the maximum thickness of the high-concentration doping layer 11 at the top position is 17nm; when the thickness of the high-concentration doping layer 11 at the remaining positions is 10nm, the maximum thickness of the high-concentration doping layer 11 at the top position is 20nm, and so on.

Since the maximum temperature of the doping treatment is a value within the range of 760°C to 800°C, a high-concentration doping layer 11 with a thickness of 5nm to 10nm can be formed. The high-concentration doping layer 11 with this thickness can ensure that after the subsequent etching treatment, the high-concentration doping layer 11 retained at the top position can meet the conditions for forming ohmic contact with the metal electrode, and the overall thickness of the high-concentration doping layer 11 will not be too thick, which will increase the difficulty and efficiency of the etching treatment, thereby avoiding incomplete removal and increasing Auger recombination.

In this embodiment, as shown in Figure 4, the etching thickness H of the entire surface of the high-concentration doped layer 11 in step S300 is in the range of 5nm to 10nm, that is, the etching thickness H can completely remove the high-concentration doped layer 11 located at the remaining positions (non-top positions) of the velvet structure 1 to expose the low-concentration doped layer 12, and after the high-concentration doped layer 11 at the top position of the velvet structure 1 is etched away by the etching thickness H, the high-concentration doped layer 11 with a maximum thickness of 10nm to 25nm is still retained.

For example, as shown in Figure 4, when the thickness of the high-concentration doping layer 11 at the remaining positions is 5nm, the maximum thickness of the high-concentration doping layer 11 at the top position is 15nm, the etching thickness H is 5nm, and after etching, the maximum thickness of the high-concentration doping layer 11 retained at the top position is 10nm; when the thickness of the high-concentration doping layer 11 at the remaining positions is 7nm, the maximum thickness of the high-concentration doping layer 11 at the top position is 17nm, the etching thickness H is 7nm, and after etching, the maximum thickness of the high-concentration doping layer 11 retained at the top position is 10nm; when the thickness of the high-concentration doping layer 11 at the remaining positions is 10nm, the maximum thickness of the high-concentration doping layer 11 at the top position is 20nm, the etching thickness H is 10nm, and after etching, the maximum thickness of the high-concentration doping layer 11 retained at the top position is 10nm, and so on.

In some embodiments, the doping treatment is a thermal diffusion doping process, an ion implantation doping process, or a doping source coating and advancing process. Regardless of the doping method used, as long as the highest diffusion doping temperature of the thermal diffusion doping process is within the range of 760°C to 800°C, the annealing temperature of the ion implantation doping process is within the range of 760°C to 800°C, and the advancing temperature of the doping source coating and advancing process is within the range of 760°C to 800°C, a doping structure in which the surface layer of a suitable thickness is a high-concentration doping layer 11 and the layer far from the surface is a low-concentration doping layer 12 can be formed on the silicon substrate 2.

For example, when the doping treatment is a thermal diffusion doping process, the surface of the velvet structure 1 is doped by: introducing a doping source gas into a diffusion doping device, and performing thermal diffusion doping on the surface of the velvet structure 1 at a maximum temperature in the range of 760°C to 800°C. The doping source gas includes nitrogen, oxygen and a dopant, and the dopant is selected according to the doping type of the silicon substrate 2. For example, when the silicon substrate 2 is a boron-doped single crystal silicon wafer, the dopant is a phosphorus-containing dopant, and when the silicon substrate 2 is a phosphorus-doped single crystal silicon wafer, the dopant is a boron-containing dopant. The diffusion doping device can be a diffusion furnace, and the doping source gas is introduced into a closed quartz tube in the diffusion furnace for thermal diffusion treatment. For example, the flow rate of the doping source gas is in the range of 100sccm to 3000sccm, and the introduction time of the doping source gas is in the range of 100s to 2000s.

In the case of adopting the above technical solution, nitrogen carrying oxygen and dopants is introduced into the diffusion doping equipment, and the velvet structure 1 is thermally diffused and doped within the range of the highest diffusion temperature of 760°C to 800°C. The dopants are doped into the surface of the silicon substrate 2 at this temperature to form a high-concentration doped layer 11 as the surface layer and a low-concentration doped layer 12 away from the surface layer. The thickness of the obtained high-concentration doped layer 11 can meet the needs of subsequent etching processing, and the high-concentration doped layer 11 at the top position of the velvet structure 1 is retained.

In this embodiment, after etching, the sum of the projected areas of the high-concentration doped layer 11 retained at the top position of the velvet structure 1 on the silicon substrate 2 accounts for 2% to 4% of the area of one side of the silicon substrate 2. Although the high-concentration doped layer 11 in the present application is discretely distributed on the entire silicon substrate 2, it only exists at the top position of the velvet structure 1, and the sum of the projected areas of all the high-concentration doped layers 11 on the silicon substrate 2 accounts for the same proportion as the top position of the velvet structure 1 on the entire silicon substrate 2, which can reach 2% to 4%. Compared with the prior art, due to the error in the printing of the metal electrode, in order to ensure that the metal electrode printing falls within the high-concentration doped area, the current industry standard for the width of the high-concentration doped area is 90μm to 120μm, and the spacing is 0.9μm to 1.4μm, so that the area of the high-concentration doped area accounts for 6% to 10%, while the proportion of the high-concentration doped layer 11 in the present application is greatly reduced, which reduces Auger recombination, thereby improving the photoelectric conversion efficiency of the solar cell.

In some embodiments, etching the entire surface of the high-concentration doped layer 11 in step S300 includes: etching the entire surface of the high-concentration doped layer 11 using a potassium hydroxide solution with a concentration of 1.5% to 4%. For example, the concentration of the potassium hydroxide solution can be 1.5%, 2%, 2.6%, 3.2%, 4%, etc. Under the potassium hydroxide solution in this concentration range, it can be ensured that the high-concentration doped layer 11 is removed, and only the high-concentration doped layer 11 at the top of the velvet structure 1 is retained. If the concentration of potassium hydroxide is small, during the etching process, the high-concentration doped layer 11 may remain at the remaining positions, and the high-concentration doped layer 11 is not completely removed, which is not conducive to reducing Auger recombination; if the concentration of potassium hydroxide is too high, the high-concentration doped layer 11 at the top of the velvet structure 1 may also be removed, which is not conducive to the formation of ohmic contact between the metal electrode and the silicon substrate 2, and there may be excessive etching and polishing, resulting in an unclear velvet structure, weakened light trapping, and increased reflectivity.

As shown in FIG. 1 to FIG. 5, in this embodiment, the velvet structure 1 is a pyramid structure. It should be noted that the pyramid structure obtained by velveting is not a pyramid structure in the strict sense, but is similar to a pyramid structure. The pyramid structure is an approximate quadrangular pyramid structure, and the length of the bottom side of the pyramid structure is 50nm to 400nm. After etching, only the remaining high-concentration doped layer 11 in the top area of the pyramid structure is retained. For example, the length of the bottom side of the pyramid structure can be 50nm, 70nm, 100nm, 120nm, 150nm, 200nm, 240nm, 300nm, 330nm, 380nm, 400nm, etc.

Since the pyramid structure has a spire region, that is, the top position of the velvet structure 1, because the doping atoms entering the silicon body from multiple faces of the spire region will reach the spire region, the spire region has a higher doping concentration than the rest of the region under the same diffusion conditions. Based on Fick's first law, the spire region has a higher diffusion rate, and it is easier to form a high-concentration doping layer 11 with a higher concentration and a deeper depth in the spire region, which is conducive to the subsequent etching of the high-concentration doping layer 11 of the same thickness, and retaining the high-concentration doping layer 11 in the spire region. For a pyramid structure of this size, the spacing of the high-concentration doping layer 11 obtained after etching can achieve a tunneling spacing of 0.1μm to 0.6μm, and the total area of the high-concentration doping layer 11 accounts for about 2% to 4%, which can maintain the resistance between the metal electrode and silicon at an extremely low level, the series resistance rises less, and the open circuit voltage is greatly improved. Compared with the whole surface diffusion high-concentration doping layer, the photoelectric conversion efficiency of the present application can be increased by about 0.25% to 0.3%. If the length of the bottom side of the pyramid structure is less than 50nm, the size of the pyramid structure is too small and it is easy to be completely etched away and difficult to control. If the length of the bottom side of the pyramid structure is greater than 400nm, the spacing between the high-concentration doped layers 11 is too large, the metal electrode ohmic contact tunneling spacing is greater than 0.6μm, and the contact resistance between the metal electrode and silicon is too high, resulting in a decrease in photoelectric conversion efficiency.

Of course, suede structures 1 of other shapes, such as one or more of columnar, conical, terraced, arc-shaped grooves or arc-shaped protrusions, can also be applied.

The specific implementation process of the solar cell preparation method is introduced below:

In the first step, a boron-doped single crystal silicon wafer is provided, and at least one side of the boron-doped single crystal silicon wafer is corroded using a mixed solution of sodium hydroxide and isopropyl alcohol to obtain a velvet surface with continuously arranged pyramid structures, wherein the bottom side length of the pyramid structure is 200 nm.

In the second step, the boron-doped single crystal silicon wafer after texturing is placed in a tubular diffusion furnace, and phosphorus is diffused at a maximum diffusion doping temperature of 780°C to form a low-concentration doping layer 12 covering the entire velvet surface and a high-concentration doping layer 11 covering the entire low-concentration doping layer 12 on the velvet surface with a pyramid structure to prepare a PN junction. At the same time, a layer of phosphosilicate glass, i.e., a phosphorus-containing silicon dioxide layer, is prepared on the surface of the PN junction, wherein the average thickness of the high-concentration doping layer 11 located on the non-top area of the pyramid structure is 10nm, the maximum thickness of the high-concentration doping layer 11 located on the top area of the pyramid structure is 20nm, and the average thickness of the low-concentration doping layer 12 is 130nm.

In the third step, the high-concentration doped layer 11 is irradiated with a laser according to a preset pattern, and the laser pushes the phosphorus in the silicon dioxide layer into the high-concentration doped layer 11 to form a heavily doped pattern, and the doping thickness and concentration of the high-concentration doped layer 11 in the top area of the pyramid structure in the heavily doped pattern are further increased. Of course, when laser deep doping is not required, the third step can also be omitted, and phosphorus silicon glass can also not be formed on the surface of the high-concentration doped layer 11 in the second step.

In the fourth step, in a chain wet etcher, a potassium hydroxide solution with a concentration of 2% is used to corrode and clean the surface on one side after laser deep doping to remove the phosphorus-containing silicon dioxide layer on the surface. At the same time, the potassium hydroxide solution will also etch and remove the high-concentration doping layer 11 with an etching thickness of 10nm, leaving only the high-concentration doping layer 11 with a maximum thickness of 10nm located on the top area of the pyramid structure. The potassium hydroxide alkaline solution can also be used to chemically polish the other side surface that has not been laser deep doped. A selective emitter as shown in Figure 3 is obtained.

When the metal electrode is subsequently made, a paste containing spherical metal particles can be used to print on the heavily doped pattern, and the silver paste covers the pyramid structure in the heavily doped pattern. The paste contains glass material, and the spherical metal particles can be one or more combinations of silver particles or nickel particles, tin particles, etc. Among them, the D90 of the spherical metal particles is 200nm, which means that spherical metal particles with a particle size of less than 200nm account for 90% of all spherical metal particles. In the ideal case where the size distribution of the pyramid structure is extremely concentrated, four adjacent pyramid structures correspond to at most one spherical metal particle, so that the top of each pyramid structure forms a good ohmic contact with the spherical metal particles. When the size of a large number of spherical metal particles exceeds twice the length of the base of the pyramid structure, there will be squeezing between adjacent spherical metal particles, resulting in the apex of some pyramid structures may not be able to contact the spherical metal particles, thereby deteriorating the ohmic contact between the spherical metal particles and the surface of the pyramid structure, and increasing the contact resistance. After that, the silver paste is sintered, and the spherical silver particles in the silver paste melt and combine with the high-concentration doping layer in the spire area, and the metal electrode is obtained after annealing.

As shown in FIG3, FIG5 and FIG6, an embodiment of the present invention further provides a selective emitter, comprising a silicon substrate 2, at least one side of the silicon substrate 2 is a velvet structure 1, the top position of the velvet structure 1 is covered with a high-concentration doping layer 11, the rest of the velvet structure 1 is covered with a low-concentration doping layer 12, the top position of the velvet structure 1 is also covered with a low-concentration doping layer 12, the high-concentration doping layer 11 is covered on the low-concentration doping layer 12, and the doping concentration of the high-concentration doping layer 11 is greater than the doping concentration of the low-concentration doping layer 12. Wherein, the silicon substrate 2 can be a P-type single crystal silicon wafer or an N-type single crystal silicon wafer. For example, if the silicon substrate 2 is a boron-doped single crystal silicon wafer, the doping element is phosphorus, and the high-concentration doping layer 11 and the low-concentration doping layer 12 formed are phosphorus-doped layers; if the silicon substrate 2 is a phosphorus-doped single crystal silicon wafer, the doping element is boron, and the high-concentration doping layer 11 and the low-concentration doping layer 12 formed are boron-doped layers. The selective emitter can be obtained based on the method for preparing the selective emitter described in any of the above embodiments, or can be obtained by other methods.

When the above technical solution is adopted, the high-concentration doped layer 11 in the present application is formed along with the position of the velvet structure on the silicon substrate 2, and there is no need to overlap and match the pattern of the high-concentration doped area with the pattern of the metal electrode, so high processing accuracy is not required, which reduces the manufacturing difficulty and improves the yield of the product. In addition, when the selective emitter in the present application is in conductive contact with the metal electrode, no matter what the pattern of the metal electrode is, as long as the metal electrode can be conductively contacted with the high-concentration doped layer 11 at the top position of the velvet structure 1 below it, the conditions for forming an ohmic contact can be met.

In this embodiment, the sum of the projected areas of the high-concentration doping layer 11 on the silicon substrate 2 accounts for 2% to 4% of the area of one side of the silicon substrate 2. Although the high-concentration doping layer 11 in this application is discretely distributed on the entire silicon substrate 2, it only exists at the top position of the velvet structure 1. The sum of the projected areas of all the high-concentration doping layers 11 on the silicon substrate 2 accounts for an area equivalent to the top position of the velvet structure 1 on the entire silicon substrate 2, which can reach 2% to 4%. Compared with the prior art, in order to ensure that the metal electrode printing falls within the high-concentration doping area, the area of the high-concentration doping area accounts for 6%-10%. The high-concentration doping layer 11 of this application accounts for a smaller proportion, which reduces Auger recombination, thereby improving the photoelectric conversion efficiency of the solar cell.

Further, in the present embodiment, the maximum thickness of the high-concentration doping layer 11 located at the top position of the velvet structure 1 is 10nm to 25nm. For example, the maximum thickness of the high-concentration doping layer 11 can be 10nm, 12nm, 15nm, 19nm, 20nm, 21nm, 23nm, 25nm, etc. The thickness of the low-concentration doping layer 12 on the velvet structure 1 is 120nm to 150nm. For example, the thickness of the low-concentration doping layer 12 can be 120nm, 125nm, 130nm, 135nm, 140nm, 145nm, 150nm, etc. The high-concentration doping layer 11 located at the top position can meet the conditions for forming an ohmic contact with the metal electrode within the thickness range, and the high-concentration doping layer 11 of this thickness accounts for a small area at the top position, reaching 2% to 4%, which reduces Auger recombination and improves the photoelectric conversion efficiency.

In some embodiments, the velvet structure 1 is a pyramid structure, the length of the bottom side of the pyramid structure is 50nm to 400nm, and only the top area of the pyramid structure is covered with a high-concentration doping layer. For example, the length of the bottom side of the pyramid structure can be 50nm, 70nm, 100nm, 120nm, 150nm, 200nm, 240nm, 300nm, 330nm, 380nm, 400nm, etc. For a pyramid structure of this size, the spacing of the high-concentration doping layer 11 on the top area can achieve a tunneling spacing of 0.1μm to 0.6μm, and the total area of the high-concentration doping layer 11 accounts for about 2% to 4%, which can maintain the resistance between the metal electrode and silicon at an extremely low level, the series resistance increases less, and the open circuit voltage is greatly improved. Compared with the entire surface diffused high-concentration doping layer, the conversion efficiency can be improved by about 0.25% to 0.3%. If the bottom side length of the pyramid structure is less than 50nm, the pyramid structure is too small and can be easily completely etched away, making it difficult to control. If the bottom side length of the pyramid structure is greater than 400nm, the spacing between the high-concentration doped layers 11 is too large, the metal electrode ohmic contact tunneling spacing is too large, and the contact resistance is too high.

Based on the selective emitter described in any of the above embodiments, an embodiment of the present invention further provides a solar cell, comprising a selective emitter and a metal electrode, wherein the selective emitter is the selective emitter described in any of the above items, and the metal electrode is in conductive contact with the high-concentration doped layer 11 on a part of the velvet structure of the selective emitter. That is, the metal electrode is in conductive contact with the high-concentration doped layer 11 at the top position of the velvet structure located below it.

Since the solar cell adopts the selective emitter in the second aspect of the present application, the solar cell has the same technical effect as the selective emitter in the second aspect, which will not be described in detail here.

An embodiment of the present invention further provides a solar cell assembly, comprising a solar cell, a connection structure and a packaging structure, wherein the connection structure is used to enable the solar cell to form a direct current output, and the packaging structure is used to package the solar cell; the solar cell is the solar cell described in the third aspect.

Since the solar cell module adopts the solar cell in the present application, it has the same technical effect as the solar cell, which will not be described in detail here.

In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (14)

1. A method of preparing a selective emitter, comprising the steps of:

texturing at least one surface of the silicon substrate to obtain a textured structure;

Doping the surface of the suede structure to form a low-concentration doped layer covering the suede structure and a high-concentration doped layer covering the low-concentration doped layer; wherein the thickness of the high-concentration doped layer located at the top position of the suede structure is greater than the thickness of the high-concentration doped layer located at the rest position of the suede structure;

And carrying out etching treatment on the whole surface of the high-concentration doped layer, wherein the etching thickness of the etching treatment is larger than or equal to the thickness of the high-concentration doped layer positioned at the rest position of the suede structure so as to remove the high-concentration doped layer positioned at the rest position of the suede structure, and reserving the rest high-concentration doped layer positioned at the top position of the suede structure.

2. The method of manufacturing a selective emitter according to claim 1, characterized in that the maximum temperature of the doping treatment is a value in the range of 760 ℃ to 800 ℃.

3. The method of manufacturing a selective emitter according to claim 1 or 2, characterized in that the doping treatment is a thermal diffusion doping process, an ion implantation doping process or a doping source coating advancing process.

4. A method of fabricating a selective emitter according to claim 3, wherein when said doping process is a thermal diffusion doping process, said doping the surface of said textured structure comprises:

introducing doping source gas into diffusion doping equipment, and carrying out thermal diffusion doping on the surface of the suede structure within the range of 760-800 ℃ at the highest temperature; wherein the dopant source gas comprises nitrogen, oxygen, and a dopant.

5. The method of manufacturing a selective emitter according to claim 1, wherein a thickness of said high-concentration doped layer formed on said remaining portion of said textured structure after the doping treatment is in a range of 5nm to 10nm, and a thickness of said low-concentration doped layer formed on said textured structure is in a range of 120nm to 150 nm.

6. The method of manufacturing a selective emitter according to claim 1, wherein an etching thickness of etching the entire surface of the high concentration doped layer is in a range of 5nm to 10 nm.

7. The method of claim 1, wherein the sum of projected areas of the remaining heavily doped layer remaining on the top portion of the textured structure on the silicon substrate after the etching process is 2% -4% of a surface area of the silicon substrate.

8. The method of manufacturing a selective emitter according to claim 1, wherein the etching the entire surface of the high-concentration doped layer comprises:

And etching the whole surface of the high-concentration doped layer by using a potassium hydroxide solution with the concentration of 1.5% -4%.

9. The method for producing a selective emitter according to claim 1, wherein the textured structure has a shape selected from one or more of a columnar shape, a tapered shape, a mesa shape, an arc-shaped groove, and an arc-shaped protrusion.

10. The method for manufacturing a selective emitter according to claim 9, wherein the textured structure is a pyramid structure, the bottom side of the pyramid structure is 50 nm-400 nm long, and only a part of the thickness of the high-concentration doped layer in the cone tip region of the pyramid structure is reserved after etching treatment.

11. The selective emitter is characterized by comprising a silicon substrate, wherein at least one surface of the silicon substrate is of a textured structure, a high-concentration doped layer is covered on the top of the textured structure, a low-concentration doped layer is covered on the rest of the textured structure, the doping concentration of the high-concentration doped layer is larger than that of the low-concentration doped layer, the sum of projection areas of the high-concentration doped layer on the silicon substrate accounts for 2% -4% of one surface area of the silicon substrate, the maximum thickness of the high-concentration doped layer is 10-25 nm, and the thickness of the low-concentration doped layer is 120-150 nm.

12. The selective emitter according to claim 11, wherein said textured structure is a pyramid structure having a bottom side length of 50nm to 400nm, only a cone tip region of said pyramid structure being covered with said high concentration doped layer.

13. A solar cell comprising a selective emitter according to any one of claims 11-12 and a metal electrode in conductive contact with a highly doped layer on a portion of the textured structure of the selective emitter.

14. A solar module comprising a solar cell, a coupling structure for causing the solar cell to form a direct current output, and an encapsulation structure for encapsulating the solar cell; it is characterized in that the method comprises the steps of, the solar cell according to claim 13.