CN115910143B - Driving circuit, storage device and driving circuit control method - Google Patents

Abstract

The present application provides a driving circuit, a storage device and a driving circuit control method, wherein the driving circuit comprises: a first driving circuit, comprising a first transistor and a second transistor, wherein the control end of the first transistor is connected to the control end of the second transistor, and the second end of the first transistor is connected to the first end of the second transistor and serves as the output end of the driving circuit; a second driving circuit, having a power supply end and an output end, wherein the output end is connected to the control end of the first transistor; a power switching circuit, wherein the first end of the power switching circuit is connected to the power supply end of the signal generating circuit, the second end of the power switching circuit is connected to the first power supply, and the third end of the power switching circuit is connected to the second power supply, and is used to connect the power supply end of the second driving circuit to one of the first power supply and the second power supply under the control of a control signal; wherein the first power supply is greater than the second power supply. The scheme of the present application is used to improve the GIDL effect.

Description

Driving circuit, storage device and driving circuit control method

Technical Field

The present application relates to semiconductor technology, and in particular to a driving circuit, a storage device, and a driving circuit control method.

Background technique

As device sizes continue to shrink (for example, the gate oxide layer of MOS devices becomes thinner and thinner) and the demand for faster switching speeds and lower energy consumption is pursued, how to control the gate-induced drain leakage (GIDL) effect becomes particularly important.

Therefore, how to effectively reduce the GIDL effect has become an urgent problem to be solved.

Summary of the invention

Embodiments of the present application provide a driving circuit, a storage device, and a driving circuit control method to improve the GIDL effect.

According to some embodiments, the first aspect of the present application provides a driving circuit, comprising: a first driving circuit, comprising a first transistor and a second transistor, the control end of the first transistor and the control end of the second transistor being connected, the second end of the first transistor being connected to the first end of the second transistor and serving as the output end of the driving circuit; a second driving circuit, having a power supply end and an output end, the output end being connected to the control end of the first transistor; a power switching circuit, a first end of which is connected to the power supply end of the signal generating circuit, a second end of which is connected to the first power supply, and a third end of which is connected to the second power supply, for connecting the power supply end of the second driving circuit to one of the first power supply and the second power supply under the control of a control signal; wherein the first power supply is greater than the second power supply.

In some embodiments, the power switching circuit includes: a first controllable circuit and a second controllable circuit; the control signal is connected to the control ends of the first controllable circuit and the second controllable circuit, the first controllable circuit is connected between the first power supply and the power supply end, and the second controllable circuit is connected between the second power supply and the power supply end.

In some embodiments, the first controllable circuit includes a first switching element; the second controllable circuit includes an inverter and a second switching element; wherein the first switching element and the second switching element are of the same type; the control end of the first switching element is connected to the control signal, and the first switching element is connected between the first power supply and the power supply end; the input end of the inverter is connected to the control signal, and the output end of the inverter is connected to the control end of the second switching element; the second switching element is connected between the second power supply and the power supply end.

In some embodiments, the first switch element and the second switch element are PMOS transistors.

In some embodiments, the first controllable circuit includes a first switching element; the second controllable circuit includes a second switching element; wherein the first switching element and the second switching element are of different types; the control end of the first switching element is connected to the control signal, and the first switching element is connected between the first power supply and the power supply end; the control end of the second switching element is connected to the control signal, and the second switching element is connected between the second power supply and the power supply end.

In some embodiments, the first switch element is a PMOS transistor, and the second switch element is an NMOS transistor; or, the first switch element is an NMOS transistor, and the second switch element is a PMOS transistor.

In some embodiments, the first transistor is a PMOS transistor.

In some embodiments, the second driving circuit includes: a third transistor and a fourth transistor; the control end of the third transistor is connected to the control end of the fourth transistor and serves as the input end of the second driving circuit; the first end of the third transistor serves as the power supply end of the second driving circuit; the second end of the third transistor is connected to the first end of the fourth transistor and serves as the output end of the second driving circuit; the second end of the fourth transistor is connected to the first low level.

In some embodiments, the driving circuit further includes: a power supply circuit; an output end of the power supply circuit is connected to the first end of the first transistor.

In some embodiments, the power supply circuit includes: a fifth transistor and a sixth transistor; the control end of the fifth transistor is connected to the control end of the sixth transistor; the second end of the fifth transistor is connected to the first end of the sixth transistor and serves as the output end of the power supply circuit.

In some embodiments, the driving circuit is in a preparation mode or an operation mode in response to a control signal.

In some embodiments, the driving circuit further includes: a pull-down transistor; the first end of the pull-down transistor is connected to the output end of the driving circuit, the second end of the pull-down transistor is connected to the second end of the second transistor and a second low level, and the second low level is less than the first low level.

According to some embodiments, the second aspect of the present application provides a storage device, comprising: a word line driving circuit and a storage unit, the word line driving circuit comprising the driving circuit as described in the embodiment of the first aspect; wherein the output end of the word line driving circuit is connected to the storage unit; the word line driving circuit comprises a sub-word line driving circuit and a main word line driving circuit, wherein the sub-word line driving circuit comprises the first driving circuit, and the main word line driving circuit comprises the second driving circuit.

In some embodiments, the word line driving circuit is in a preparation mode or an operation mode in response to a control signal.

According to some embodiments, the third aspect of the present application provides a drive circuit control method, which is applied to the drive circuit as described in the embodiments of the first aspect or the second aspect, and the method includes: sending a control signal to a power switching circuit so that the power switching circuit responds to the control signal and connects the power supply end of the second drive circuit to one of the first power supply and the second power supply; wherein the first power supply is greater than the second power supply.

In some embodiments, sending a control signal to the power switching circuit includes: sending a first control signal to the power switching circuit so that the power switching circuit responds to the first control signal, connects the second power supply to the power supply end of the second drive circuit, and disconnects the connection between the first power supply and the power supply end of the second drive circuit.

In some embodiments, sending a control signal to the power switching circuit includes: sending a second control signal to the power switching circuit so that the power switching circuit responds to the second control signal, connects the first power supply to the power supply end of the second drive circuit, and disconnects the connection between the second power supply and the power supply end of the second drive circuit.

In the drive circuit, storage device and drive circuit control method provided by the embodiments of the present application, the output end of the second drive circuit is connected to the control end of the first transistor in the first drive circuit, and the power supply end of the second drive circuit is connected to the power switching circuit, which selects to connect the first power supply or the second power supply to the power supply end of the second drive circuit in response to the control signal, and the first power supply is greater than the second power supply. Based on the above power switching circuit, the voltage at the power supply end of the second drive circuit can be reduced when necessary, so as to reduce the control end voltage of the first transistor by reducing the signal voltage output by the second drive circuit, thereby reducing the voltage drop between the gate and the source/drain of the transistor and improving the GIDL effect.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the description, are used to explain the principles of the embodiments of the present application.

FIG. 1a is a schematic diagram of the structure of an exemplary storage device 10;

FIG1 b is a timing diagram of various signals in the storage device 10;

FIG2 is a schematic diagram of the structure of a driving circuit provided in Embodiment 1 of the present application;

FIG3 is a schematic diagram of the structure of a driving circuit provided in Embodiment 2 of the present application;

4a and 4b are schematic diagrams of a driving circuit provided in Embodiment 2 of the present application;

5a and 5b are schematic diagrams of a driving circuit provided in Embodiment 3 of the present application;

6a and 6b are schematic diagrams of a driving circuit provided in Embodiment 4 of the present application;

FIG7 is a schematic diagram of the structure of a driving circuit provided in Embodiment 5 of the present application;

FIG8 is a timing diagram of a driving circuit in Embodiment 5;

FIG9 is a schematic diagram of the structure of a storage device provided in Embodiment 6 of the present application;

FIG10 is a flow chart of a driving circuit control method provided in Embodiment 7 of the present application.

The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments.

Detailed ways

Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

The terms "including" and "having" in this application are used to express an open-ended inclusive meaning, and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first" and "second" etc. are used only as labels and are not intended to limit the number of their objects. In addition, the different elements and regions in the drawings are only schematically shown, so this application is not limited to the sizes or distances shown in the drawings.

A type of leakage current that causes static power consumption in transistor devices is gate-induced drain leakage current, also known as gate-induced drain leakage current, which occurs in the gate-drain overlap region. In some cases, when the device is in the off state or in the waiting state in the circuit, GIDL current dominates the leakage current. In particular, as the gate oxide layer of MOS devices becomes thinner and thinner, GIDL current increases sharply.

The following uses the word line driving scenario as an example to illustrate the impact of the GIDL current:

1a is a schematic diagram of the structure of an exemplary storage device 10, which includes: a main word line driving circuit 11, a sub-word line driving circuit 12 and a storage unit 13. The main word line driving circuit 11 receives a main word line MWL signal, outputs a MWLB signal as an input signal of the sub-word line driving circuit, and the sub-word line driving circuit outputs a word line driving signal, which is transmitted to the word line of the storage unit to drive the storage unit to be in a working mode or a standby mode.

FIG1b is a timing diagram of each signal in the storage device 10. In conjunction with FIG1b, if the storage cell is selected, the main word line MWL signal generation circuit (not shown in the figure) generates a high-level main word line MWL signal, and the main word line driving circuit outputs a low-level MWLB signal accordingly. Correspondingly, the sub-word line driving circuit outputs a high-level word line driving signal, which is transmitted to the storage cell through the word line of the storage cell, and drives the storage cell to enter the working mode. In addition, in conjunction with the preparation stage in FIG1b, if the storage cell is not selected, the main word line MWL signal generation circuit (not shown in the figure) generates a low-level main word line MWL signal, and the main word line driving circuit outputs a high-level MWLB signal accordingly. Correspondingly, the sub-word line driving circuit outputs a low-level word line driving signal, which is transmitted to the storage cell through the word line of the storage cell, and drives the storage cell to enter the preparation mode (or standby mode).

It is found that in the above process, in the preparation mode, the input end of the sub-word line driving circuit receives the high-level MWLB signal output by the main word line driving circuit, and the high-level MWLB signal is usually the common power supply VPP, such as 2.5 V. At this time, taking the pull-up transistor PMOS in the sub-word line driving circuit as an example, the gate voltage of the transistor is about 2.5 V, and the gate voltage is relatively large, which may cause a large GIDL current.

Some embodiments of the present application improve the GIDL current by reducing the voltage of the transistor gate.

The technical solution of the present application is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

Embodiment 1

FIG2 is a schematic diagram of the structure of a driving circuit provided in Embodiment 1 of the present application. The driving circuit provided in this embodiment is used to improve the GIDL current. As shown in FIG2 , the driving circuit 200 includes:

The first driving circuit 21 includes a first transistor 211 and a second transistor 212, wherein a control end of the first transistor 211 is connected to a control end of the second transistor 212, and a second end of the first transistor 211 is connected to a first end of the second transistor 212 and serves as an output end of the driving circuit 200;

The second driving circuit 22 has a power supply end and an output end, and the output end is connected to the control end of the first transistor 211;

The power switching circuit 23 has a first end connected to the power supply end of the second drive circuit 22, a second end connected to the first power supply 24, and a third end connected to the second power supply 25, and is used to connect the power supply end of the second drive circuit 22 to one of the first power supply 24 and the second power supply 25 under the control of a control signal; wherein the first power supply 24 is larger than the second power supply 25.

In practical applications, the driving circuit provided in this embodiment can be applied to various driving scenarios. As an example, the driving circuit can be applied to scenarios including but not limited to word line driving of storage devices.

In one example, the control terminals of the first transistor and the second transistor are connected as the input terminal of the first drive circuit, the second terminal of the first transistor is connected to the first terminal of the second transistor as the output terminal of the first drive circuit, and the first terminal of the first transistor serves as the power supply terminal of the first drive circuit. In one example, the second terminal of the second transistor is grounded. Wherein, grounding includes but is not limited to being connected to a common reference power supply VSS. Optionally, VSS can be 0 volts (V).

In one example, the first transistor is a PMOS transistor. Accordingly, the first end of the first transistor is the source of the PMOS transistor, and the second end of the first transistor is the drain of the PMOS transistor. Optionally, the second transistor is an NMOS transistor. Accordingly, the first end of the second transistor is the drain of the NMOS transistor, and the second end of the second transistor is the source of the NMOS transistor. In one example, the first transistor and the second transistor constitute an inverting circuit.

In this embodiment, the drive circuit includes a first drive circuit and a second drive circuit. In one example, the drive circuit is in a preparation mode or a working mode in response to a control signal. An example of the working process of the drive circuit is as follows: the input end of the second drive circuit receives an initial signal, which indicates that it is currently in a working mode or a preparation mode; under the power supply of the power switching circuit, the second drive circuit outputs a process signal, which is used as an input signal of the first drive circuit, and the first drive circuit outputs a corresponding signal as a drive signal output by the drive circuit, and different modes (working mode/preparation mode) correspond to different drive signals. During the working process of the drive circuit, the power switching circuit, under the control of the control signal, selects to provide the first power supply or the second power supply to the second drive circuit as its power supply voltage. It can be understood that the difference in power supply voltage will affect the different voltage values of the process signal output by the second drive circuit. In one example, the first power supply includes a common power supply VPP, and the second power supply is less than the common power supply VPP.

Taking the first transistor in the first driving circuit as an example, when the first transistor is switched to the off state, a GIDL current may be generated. Based on the driving circuit including the power switching circuit in this embodiment, a control signal is sent to the power switching circuit to selectively connect the power supply end of the second driving circuit to the second power supply. Since the second power supply is smaller than the first power supply, the process signal output by the second driving circuit under the power supply of the second power supply is reduced compared to the process signal output by the second driving circuit under the power supply of the first power supply, so as to achieve the goal of reducing the voltage at the control end of the first transistor while turning off the first transistor, thereby improving the GIDL current of the first transistor.

As an example, when the first transistor is switched to the on state, based on the driving circuit including the power switching circuit in this embodiment, a control signal is sent to the power switching circuit to selectively connect the power supply end of the second driving circuit to the first power supply. At this time, the first transistor needs to be turned on, and the GIDL current in this state can be ignored. In order to effectively and quickly turn on the transistor, the power supply end of the second driving circuit can be connected to the first power supply with a larger voltage based on the power switching circuit of this embodiment, so as to effectively and quickly turn on the first transistor.

In the driving circuit of this embodiment, the power switching circuit selects to connect the first power supply or the second power supply to the power supply terminal of the second driving circuit in response to the control signal, and the first power supply is greater than the second power supply. When necessary, the voltage at the power supply terminal of the second driving circuit can be reduced to reduce the signal voltage output by the second driving circuit, thereby reducing the control terminal voltage of the first transistor, thereby reducing the voltage drop between the gate and the source/drain of the transistor, and improving the GIDL effect.

Embodiment 2

FIG3 is a schematic diagram of a driving circuit provided in Embodiment 2 of the present application. This embodiment provides an example of a power switching circuit. The driving circuit provided in this embodiment is used to improve the GIDL current. As shown in FIG3 , the driving circuit 300 includes: a first driving circuit 31 , a second driving circuit 32 and a power switching circuit 33 .

Specifically, the first drive circuit 31 is similar to the first drive circuit in other embodiments, and the second drive circuit 32 is similar to the second drive circuit in other embodiments. In one example, the power switching circuit 33 includes: a first controllable circuit 331 and a second controllable circuit 332; a control signal is connected to the control end of the first controllable circuit 331 and the second controllable circuit 332, the first controllable circuit 331 is connected between the power supply end of the first power supply 24 and the second drive circuit 32, and the second controllable circuit 332 is connected between the second power supply and the power supply end of the second drive circuit 32, wherein the first power supply 24 is greater than the second power supply 25. The power switching circuit 33 is used to connect the power supply end of the second drive circuit 32 to one of the first power supply 24 and the second power supply 25 under the control of the control signal.

In this embodiment, the drive circuit includes a first drive circuit and a second drive circuit. In one example, the drive circuit is in a preparation mode or a working mode in response to a control signal. An example of the working process of the drive circuit is as follows: the input end of the second drive circuit receives an initial signal, which indicates that it is currently in a working mode or a preparation mode; under the power supply of the power switching circuit, the second drive circuit outputs a process signal, which is used as an input signal of the first drive circuit, and the first drive circuit outputs a corresponding signal as a drive signal output by the drive circuit. The power switching circuit includes a first controllable circuit corresponding to the first power supply and a second controllable circuit corresponding to the second power supply. During the working process of the drive circuit, the power switching circuit, under the control of the control signal, selects to turn on the first controllable circuit or the second controllable circuit to provide the first power supply or the second power supply to the second drive circuit as its power supply voltage. It can be understood that the difference in power supply voltage will affect the different voltage values of the process signal output by the second drive circuit.

In practical applications, the driving circuit provided in this embodiment can be applied to various driving scenarios. For example, the driving circuit can be applied to scenarios including but not limited to word line driving of storage devices. In one example, the control end of the first transistor and the second transistor are connected, serving as the input end of the first driving circuit, the second end of the first transistor is connected to the first end of the second transistor, serving as the output end of the first driving circuit, and the first end of the first transistor serves as the power supply end of the first driving circuit. In one example, the second end of the second transistor is grounded. Wherein, grounding includes but is not limited to connecting to a common reference power supply VSS. Optionally, VSS can be 0 volts (V).

Optionally, the first transistor is a PMOS transistor. Accordingly, the first end of the first transistor is the source of the PMOS transistor, and the second end of the first transistor is the drain of the PMOS transistor. Optionally, the second transistor is an NMOS transistor. Accordingly, the first end of the second transistor is the drain of the NMOS transistor, and the second end of the second transistor is the source of the NMOS transistor. In one example, the first transistor and the second transistor constitute an inverting circuit.

Taking the first transistor in the first driving circuit as an example, when the first transistor is switched to the off state, a GIDL current may be generated. Based on the driving circuit including the power switching circuit in this embodiment, a control signal is sent to the power switching circuit, and the power supply end of the second driving circuit is selectively connected to the second power supply by turning on the second controllable circuit and disconnecting the first controllable circuit. Since the second power supply is smaller than the first power supply, the process signal output by the second driving circuit under the power supply of the second power supply is reduced compared to the process signal output by the second driving circuit under the power supply of the first power supply, so as to achieve the voltage at the control end of the first transistor while turning off the first transistor, thereby improving the GIDL current of the first transistor. Taking the PMOS transistor as an example, the GIDL current can be improved by reducing the gate voltage.

As an example, when the first transistor is switched to the on state (conducting), based on the driving circuit including the power switching circuit in this embodiment, a control signal is sent to the power switching circuit, and the power supply end of the second driving circuit is selectively connected to the first power supply by turning on the first controllable circuit and disconnecting the second controllable circuit. At this time, the first transistor needs to be turned on, and the GIDL current in this state can be ignored. In order to effectively and quickly turn on the transistor, the power supply end of the second driving circuit can be connected to the first power supply with a larger voltage based on the power switching circuit of this embodiment, so as to effectively and quickly turn on the first transistor.

In one example, the circuit structure of the power switching circuit can refer to the relevant structure in Figure 4a. Figure 4a is a structural schematic diagram of a driving circuit provided in Example 2 of the present application. Based on other examples, this implementation mode comprises a first controllable circuit including a first switching element 41; the second controllable circuit includes an inverter 42 and a second switching element 43; the control end of the first switching element 41 is connected to the control signal, and the first switching element 41 is connected between the first power supply 24 and the power supply end of the second driving circuit 32; the input end of the inverter 42 is connected to the control signal, and the output end of the inverter 42 is connected to the control end of the second switching element 43; the second switching element 43 is connected between the second power supply 25 and the power supply end of the second driving circuit 32.

The first switch element 41 and the second switch element 43 are of the same type. The same type of switch elements mentioned here means that the switch elements are of the same type if the on/off states of the switch elements are consistent under the control of the same signal. In one example, the first switch element and the second switch element are both PMOS transistors to improve the response speed of the power switching circuit.

The working principle of the power switching circuit is exemplified in combination with the above scenario: during the operation of the driving circuit, the power switching circuit receives a control signal, and accordingly, the control signal is transmitted to the control end of the first switching element, and the first switching element is turned on/off; and, the control signal is transmitted to the inverter, and the inverse signal of the control signal is output via the inverter, and the inverse signal is transmitted to the control end of the second switching element, and the second switching element is turned off/on.

The power switching circuit of this embodiment realizes selectively turning on the first switch element or the second switch element by outputting an inverse signal of the control signal through the inverter, thereby realizing selectively connecting the first power supply or the second power supply.

In another example, the circuit structure of the power switching circuit can refer to the relevant structure in FIG. 4 b , which is a schematic diagram of the structure of a driving circuit provided in Embodiment 2 of the present application. In this implementation, based on other examples, the first controllable circuit includes a first switch element 44; the second controllable circuit includes a second switch element 45;

The control end of the first switch element 44 is connected to the control signal, and the first switch element 44 is connected between the first power supply 24 and the power supply end of the second drive circuit 32; the control end of the second switch element 45 is connected to the control signal, and the second switch element 45 is connected between the second power supply 25 and the power supply end of the second drive circuit 32.

Wherein, the types of the first switch element and the second switch element are different. The different types of switch elements mentioned here refer to that the on/off states of the switch elements are different under the control of the same signal, and the types of the switch elements are considered to be the same. In one example, the first switch element is a PMOS transistor and the second switch element is an NMOS tube. In another example, the first switch element is an NMOS transistor and the second switch element is a PMOS tube. The figure shows only an example structure.

The working principle of the power switching circuit is exemplified in combination with the above scenario: during the operation of the driving circuit, the power switching circuit receives a control signal, and accordingly, the control signal is transmitted to the control ends of the first switching element and the second switching element, and the first switching element is turned on/off, and the second switching element is turned off/on.

The power switching circuit of this embodiment realizes selectively turning on the first switch element or the second switch element through a simplified circuit structure, thereby realizing selectively connecting the first power source or the second power source.

In the driving circuit of this embodiment, the power switching circuit responds to the control signal, and selects to connect the first power supply or the second power supply to the power supply terminal of the second driving circuit by selectively turning on the first controllable circuit or the second controllable circuit, and the first power supply is greater than the second power supply. When necessary, the voltage at the power supply terminal of the second driving circuit can be reduced to reduce the signal voltage output by the second driving circuit, so as to reduce the control terminal voltage of the first transistor, thereby reducing the voltage drop between the gate and the source/drain of the transistor and improving the GIDL effect.

Embodiment 3

FIG5a is a schematic diagram of a driving circuit provided in Embodiment 3 of the present application. This embodiment provides an example of a second driving circuit, and the driving circuit provided in this embodiment is used to improve the GIDL current. As shown in FIG5a , the driving circuit 500 includes: a first driving circuit 51 , a second driving circuit 52 and a power switching circuit 53 .

Specifically, the first driving circuit 51 is similar to the first driving circuit in other embodiments, and the power switching circuit 53 is similar to the power switching circuit in other embodiments. In one example, the second driving circuit 52 includes: a third transistor 521 and a fourth transistor 522;

The control end of the third transistor 521 is connected to the control end of the fourth transistor 522 and serves as the input end of the second drive circuit 52; the first end of the third transistor 521 serves as the power supply end of the second drive circuit 52; the second end of the third transistor 521 is connected to the first end of the fourth transistor 522 and serves as the output end of the second drive circuit 52; the second end of the fourth transistor 522 is connected to the first low level.

In one example, the second driving circuit includes an inverter circuit composed of a third transistor and a fourth transistor.

In one example, the drive circuit is in a preparation mode or a working mode in response to a control signal. An example of the working process of the drive circuit is as follows: the input end of the second drive circuit receives an initial signal, which indicates that it is currently in a working mode or a preparation mode; under the power supply of the power switching circuit, the second drive circuit outputs a process signal, which is used as an input signal of the first drive circuit, and the first drive circuit outputs a corresponding signal as a drive signal output by the drive circuit. The power switching circuit includes a first controllable circuit corresponding to the first power supply and a second controllable circuit corresponding to the second power supply. During the working process of the drive circuit, the power switching circuit, under the control of the control signal, selects to turn on the first controllable circuit or the second controllable circuit to provide the first power supply or the second power supply to the second drive circuit as its power supply voltage. It can be understood that the difference in power supply voltage will affect the different voltage values of the process signal output by the second drive circuit.

In practical applications, the driving circuit provided in this embodiment can be applied to various driving scenarios. For example, the driving circuit can be applied to scenarios including but not limited to word line driving of storage devices. Optionally, the input end of the second driving circuit receives a main word line signal, and in response to the main word line signal, the second driving circuit outputs an opposite signal of the main word line signal, and the first driving circuit outputs a word line driving signal based on the opposite signal of the main word line signal.

In one example, the control terminals of the first transistor and the second transistor are connected as the input terminal of the first drive circuit, the second terminal of the first transistor is connected to the first terminal of the second transistor as the output terminal of the first drive circuit, and the first terminal of the first transistor serves as the power supply terminal of the first drive circuit. In one example, the second terminal of the second transistor is grounded. Wherein, grounding includes but is not limited to being connected to a common reference power supply VSS. Optionally, VSS can be 0 volts (V).

Optionally, the first transistor is a PMOS transistor. Accordingly, the first end of the first transistor is the source of the PMOS transistor, and the second end of the first transistor is the drain of the PMOS transistor. Optionally, the second transistor is an NMOS transistor. Accordingly, the first end of the second transistor is the drain of the NMOS transistor, and the second end of the second transistor is the source of the NMOS transistor. In one example, the first transistor and the second transistor constitute an inverting circuit.

Taking the first transistor in the first drive circuit as an example, when the first transistor is switched to the off state, a control signal is sent to the power switching circuit to selectively connect the power supply end of the second drive circuit to the second power supply. Since the second power supply is smaller than the first power supply, the process signal output by the second drive circuit under the power supply of the first power supply is reduced compared to the process signal output by the second drive circuit under the power supply of the first power supply, so as to achieve the goal of reducing the voltage at the control end of the first transistor while turning off the first transistor, thereby improving the GIDL current of the first transistor. When the first transistor is switched to the on state, a control signal is sent to the power switching circuit to selectively connect the power supply end of the second drive circuit to the first power supply, so as to effectively and quickly turn on the first transistor.

As shown in FIG5b, in one example, the driving circuit further includes: a pull-down transistor 54; a first end of the pull-down transistor 54 is connected to the output end of the driving circuit, and a second end of the pull-down transistor 54 is connected to the second end of the second transistor 212 and a second low level, and the second low level is less than the first low level. Optionally, the second low level VKK can be less than VSS, for example, VSS is 0V, and VKK is -0.2V.

Taking the word line driving scenario as an example, the driving signal output by the driving circuit is used to drive the transistor in the memory cell. When the transistor in the memory cell is in the standby mode, in order to reduce the channel leakage current of the transistor in the memory cell, the gate voltage of the transistor in the memory cell can be adjusted to be further less than the turn-off voltage, thereby effectively turning off the transistor in the memory cell and reducing the leakage current of the transistor in the memory cell.

In the driving circuit of this embodiment, the power switching circuit selects to connect the first power supply or the second power supply to the power supply terminal of the second driving circuit in response to the control signal, and the first power supply is greater than the second power supply. When necessary, through the above power switching, the voltage at the power supply terminal of the second driving circuit is reduced to reduce the signal voltage output by the second driving circuit, thereby reducing the control terminal voltage of the first transistor, thereby reducing the voltage drop between the gate and the source/drain of the transistor, and improving the GIDL effect.

Embodiment 4

FIG6a is a schematic diagram of the structure of a driving circuit provided in Embodiment 4 of the present application. The driving circuit of this embodiment further includes a power supply circuit, which is used to supply power to the first driving circuit. The following is an example of the power supply circuit. As shown in FIG6a , the driving circuit 600 includes:

A first driving circuit 61, a second driving circuit 62, a power switching circuit 63 and a power supply circuit 64;

Among them, the first drive circuit 61 is similar to the first drive circuit in other embodiments, the second drive circuit 62 is similar to the second drive circuit in other embodiments, and the power switching circuit 63 is similar to the power switching circuit in other embodiments. In one example, the output end of the power supply circuit 64 is connected to the first end of the first transistor of the first drive circuit 61. In this embodiment, the power supply circuit outputs a power supply signal to the first transistor to supply power to the first drive circuit. Optionally, the power supply signal includes but is not limited to a common power supply VPP.

In practical applications, the power supply circuit responds to the power supply control signal to start or stop outputting the power supply signal. Here, stopping outputting the power supply signal includes but is not limited to outputting a low-level signal, for example, a common reference power supply VSS.

In one example, the drive circuit is in a preparation mode or a working mode in response to a control signal. An example of the working process of the drive circuit is as follows: the input end of the second drive circuit receives an initial signal, which indicates that it is currently in a working mode or a preparation mode; under the power supply of the power switching circuit, the second drive circuit outputs a process signal, and the first drive circuit outputs a drive signal based on the process signal. In different modes, the power switching circuit, under the control of the control signal, selects to provide the first power supply or the second power supply to the second drive circuit as its power supply voltage. In one example, the first power supply includes a common power supply VPP, and the second power supply is less than the common power supply VPP. In the working mode, the power supply circuit responds to the power supply control signal to start outputting the power supply signal. In the preparation mode, the power supply circuit responds to the power supply control signal and stops outputting the power supply signal to reduce standby power consumption.

In one example, as shown in FIG6b, the power supply circuit includes: a fifth transistor 641 and a sixth transistor 642; the control end of the fifth transistor 641 is connected to the control end of the sixth transistor 642; the second end of the fifth transistor 641 is connected to the first end of the sixth transistor 642 and serves as the output end of the power supply circuit. The power supply circuit, based on the inverting circuit formed by the fifth transistor and the sixth transistor, realizes starting/stopping the output of the power supply signal in different working modes, thereby reducing the standby power consumption of the driving circuit.

Taking the first transistor in the first driving circuit as a PMOS transistor as an example, in the preparation mode, the first transistor is switched to the off state, the power supply circuit stops outputting the power supply signal, the source voltage of the first transistor is 0V, and the gate voltage is the process signal output by the second driving circuit. In a driving circuit without a power switching circuit, the gate voltage is usually VPP. In this embodiment, a control signal is sent to the power switching circuit to selectively connect the power supply end of the second driving circuit to the second power supply. Since the second power supply is smaller than the first power supply, the process signal output by the second driving circuit under the power supply of the second power supply is reduced compared to the process signal output by the second driving circuit under the power supply of the first power supply, so as to achieve the purpose of reducing the voltage at the control end of the first transistor while turning off the first transistor, thereby improving the GIDL current of the first transistor. When the first transistor is switched to the on state, the control power supply circuit starts to output the power supply signal, and the control power switching circuit selectively connects the power supply end of the second driving circuit to the first power supply to effectively and quickly turn on the first transistor.

In practical applications, the driving circuit provided in this embodiment can be applied to various driving scenarios. For example, the driving circuit can be applied to scenarios including but not limited to word line driving of storage devices. Optionally, the first transistor is a PMOS transistor. Accordingly, the first end of the first transistor is the source of the PMOS transistor, and the second end of the first transistor is the drain of the PMOS transistor. Optionally, the second transistor is an NMOS transistor. Accordingly, the first end of the second transistor is the drain of the NMOS transistor, and the second end of the second transistor is the source of the NMOS transistor. In one example, the first transistor and the second transistor constitute an inverting circuit.

In the driving circuit of this embodiment, the power switching circuit selects to connect the first power supply or the second power supply to the power supply terminal of the second driving circuit in response to the control signal, and the first power supply is greater than the second power supply. When necessary, through the above power switching, the voltage at the power supply terminal of the second driving circuit is reduced to reduce the signal voltage output by the second driving circuit, thereby reducing the control terminal voltage of the first transistor, thereby reducing the voltage drop between the gate and the source/drain of the transistor, and improving the GIDL effect.

Embodiment 5

It should be noted that the implementation methods in the above embodiments can be implemented separately or in combination, and the combination implementation method is not limited here. As an example, FIG. 7 is a schematic diagram of the structure of a driving circuit provided in Embodiment 5 of the present application. As shown in FIG. 7 , the driving circuit 700 includes:

The first driving circuit 71 includes a first transistor P1 and a second transistor N1, wherein the control end of the first transistor P1 is connected to the control end of the second transistor N1, and the second end of the first transistor P1 is connected to the first end of the second transistor N1 and serves as the output end of the driving circuit 700;

The second driving circuit 72 includes: a third transistor P2 and a fourth transistor N2; the control end of the third transistor P2 is connected to the control end of the fourth transistor N2 and serves as an input end of the second driving circuit 72; the first end of the third transistor P2 serves as a power supply end of the second driving circuit 72; the second end of the third transistor P2 is connected to the first end of the fourth transistor N2 and is connected to the control end of the first transistor P1 as an output end of the second driving circuit 72; the second end of the fourth transistor N2 is connected to the first low level VSS;

The power switching circuit 73 includes a first switch element P3, an inverter 731, and a second switch element P4; the control end of the first switch element P3 is connected to the control signal, and the first switch element P3 is connected between the first power source VPP1 and the power supply end of the second drive circuit 72; the input end of the inverter 731 is connected to the control signal, and the output end of the inverter 731 is connected to the control end of the second switch element P4; the second switch element P4 is connected between the second power source VPP2 and the power supply end of the second drive circuit 72;

The power supply circuit 74 includes: a fifth transistor N3 and a sixth transistor P5; the control end of the fifth transistor N3 is connected to the control end of the sixth transistor P5; the second end of the fifth transistor N3 is connected to the first end of the sixth transistor P5, and is connected to the first end of the first transistor P1 as the output end of the power supply circuit 74;

The pull-down transistor N4 has a first terminal connected to the output terminal of the driving circuit 700 , and a second terminal connected to the second terminal of the second transistor N1 and a second low level VKK, where VKK is less than VSS.

The working process of the driving circuit shown in Figure 7 is illustrated in conjunction with the timing diagram shown in Figure 8. Figure 8 is an example timing diagram of the driving circuit in Example 5: the input end of the second driving circuit 72 receives the initial signal MWL, which indicates that it is currently in working mode or preparation mode.

In the working mode, the initial signal MWL is high; the power supply control signal is low, the fifth transistor N3 is turned on, the sixth transistor P4 is turned off, and the FXT signal at the power supply end of the first drive circuit 71 is high; the FXB signal sent to the gate of the pull-down transistor N4 is low, and the pull-down transistor N4 is turned off; the control signal is low, the first switch element P3 is turned on, the second switch element P4 is turned off, and the power supply end of the second drive circuit, that is, the voltage at the node A in the figure is the larger first power supply VPP1, and the voltage of VPP1 can be VPP; the second drive circuit, under the power supply of VPP1, outputs a low-level MWLB signal based on the high-level initial signal MWL, and accordingly, the first transistor P1 is turned on, the second transistor N1 is turned off, and the first drive circuit 71 outputs a high-level drive signal, and the level of the drive signal can reach the level value of FXT.

In the preparation mode, the initial signal MWL is at a low level; the power supply control signal is at a high level, the fifth transistor N3 is disconnected, the sixth transistor P4 is turned on, and the FXT signal at the power supply end of the first drive circuit 71 is VSS; the FXB signal sent to the gate of the pull-down transistor N4 is at a high level, the pull-down transistor N4 is turned on, and the output end of the drive circuit is short-circuited to VKK; the control signal is at a high level, the first switch element P3 is disconnected, the second switch element P4 is turned on, and the power supply end of the second drive circuit, that is, the voltage at the node A in the figure is a smaller second power supply VPP2, and VPP2 is less than VPP; the second drive circuit outputs a high-level MWLB signal based on the low-level initial signal MWL under the power supply of VPP2. The dotted line in the figure shows the timing of the A node and the MWLB signal in the preparation mode in the scheme without the power switching circuit. It can be seen that in the embodiment based on the power switching circuit, in the preparation mode, the gate voltage of the first transistor, that is, the voltage of the MWLB signal decreases, and the voltage of the MWLB signal reaches the value of VPP2, thereby improving the GIDL effect. Correspondingly, the first transistor P1 is turned off, the second transistor N1 is turned on, and the first driving circuit 71 outputs a low-level driving signal. It should be noted that in this embodiment, because the voltage value of FXT is VSS, the voltage value of the driving signal is VKK, and VKK is less than VSS, for example, VKK can be -0.2V, and VSS is 0V, so that a GIDL current is formed between the drain of the first transistor P1 and the substrate of the first transistor P1.

In the above process, the signal for controlling the first transistor to be disconnected is generated by the second driving circuit under the power supply of the smaller second power supply. Therefore, compared with the signal generated by using a single power supply, this embodiment is based on the power switching circuit, which can reduce the potential difference between the gate and the drain of the transistor and improve the GIDL effect. In the above timing diagram, the signal state before entering the working mode is only an example of an initial state.

Embodiment 6

FIG9 is a schematic diagram of the structure of a storage device provided in Embodiment 6 of the present application. As shown in FIG9 , the storage device includes: a word line driving circuit 81 and a storage unit 82, wherein the word line driving circuit 81 includes a driving circuit as described in any one of Embodiments 1 to 5;

The output end of the word line driving circuit 81 is connected to the storage unit 82; the word line driving circuit 81 includes a sub-word line driving circuit 811 and a main word line driving circuit 812, wherein the sub-word line driving circuit 811 includes the first driving circuit in the aforementioned embodiment, and the main word line driving circuit 812 includes the second driving circuit in the aforementioned embodiment. It should be noted that the figure is only an example, and the structure and working principle of each circuit in this embodiment can refer to the relevant content in the aforementioned embodiment.

In one example, the word line driving circuit is in a preparation mode or a working mode in response to a control signal. The working process of the word line driving circuit is as follows: the main word line driving circuit receives an initial signal, which indicates that it is currently in a working mode or a preparation mode; under the power supply of the power switching circuit, the main word line driving circuit outputs a process signal, which is used as an input signal of the sub-word line driving circuit, and the sub-word line driving circuit outputs a word line driving signal, and different modes (working mode/preparation mode) correspond to different driving signals. In the working process of the word line driving circuit, the power switching circuit, under the control of the control signal, selects to provide the first power supply or the second power supply to the main word line driving circuit as its power supply voltage.

In this embodiment, the power switching circuit can adjust the power supply voltage of the main word line driving circuit. Compared with using a single power supply to power the main word line driving circuit in different modes, this embodiment uses power supplies of different sizes to power the main word line driving circuit in different modes, which can ensure the response speed in different modes and improve the GIDL current of the transistor.

Embodiment 7

FIG10 is a flow chart of a driving circuit control method provided in Embodiment 7 of the present application. The driving circuit control method is applied to the circuit described in any one of Embodiments 1 to 6. The method includes:

Sending a control signal to a power switching circuit, so that the power switching circuit connects the power supply end of the second driving circuit to one of the first power supply and the second power supply in response to the control signal; wherein the first power supply is greater than the second power supply;

In one example, the circuit is in a standby mode or an operating mode in response to a control signal.

Optionally, in the working mode, sending a control signal to the power switching circuit specifically includes:

S901: Send a second control signal to the power switching circuit, so that the power switching circuit responds to the second control signal, connects the first power supply to the power supply end of the second drive circuit, and disconnects the second power supply from the power supply end of the second drive circuit.

Optionally, in the preparation mode, sending a control signal to the power switching circuit specifically includes:

S902: Send a first control signal to the power switching circuit, so that the power switching circuit responds to the first control signal, connects the second power supply to the power supply end of the second drive circuit, and disconnects the first power supply from the power supply end of the second drive circuit.

The working process example is as follows: the input end of the second drive circuit receives an initial signal, which indicates that it is currently in a working mode or a standby mode; under the power supply of the power switching circuit, the second drive circuit outputs a process signal, and the first drive circuit outputs a drive signal based on the process signal. In different modes, the power switching circuit, under the control of the control signal, selects to provide the first power supply or the second power supply to the second drive circuit as its power supply voltage.

In this embodiment, the power switching circuit can adjust the power supply voltage of the main word line driving circuit. Compared with using a single power supply to power the main word line driving circuit in different modes, this embodiment uses power supplies of different sizes to power the main word line driving circuit in different modes, which can ensure the response speed in different modes and improve the GIDL current of the transistor.

Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims (14)

1. A driving circuit, characterized in that the driving circuit has a working mode and a standby mode, comprising: A first driving circuit comprises a first transistor and a second transistor, wherein a control end of the first transistor is connected to a control end of the second transistor, and a second end of the first transistor is connected to a first end of the second transistor and serves as an output end of the driving circuit; The second driving circuit has a power supply terminal and an output terminal, the output terminal is connected to the control terminal of the first transistor, the second driving circuit includes a third transistor and a fourth transistor, the control terminal of the third transistor is connected to the control terminal of the fourth transistor and serves as the input terminal of the second driving circuit; the first terminal of the third transistor serves as the power supply terminal of the second driving circuit; the second terminal of the third transistor is connected to the first terminal of the fourth transistor and serves as the output terminal of the second driving circuit; the second terminal of the fourth transistor is connected to the first low level; A power switching circuit, a first end of which is connected to the power supply end of the second drive circuit, a second end of which is connected to the first power supply, and a third end of which is connected to the second power supply, and is used to connect the power supply end of the second drive circuit to one of the first power supply and the second power supply under the control of a control signal representing the working mode or the preparation mode, the first power supply is used to turn off the first transistor in the working mode, and the second power supply is used to turn off the first transistor in the preparation mode; wherein the first power supply is greater than the second power supply. 2. The driving circuit according to claim 1, characterized in that the power switching circuit comprises: a first controllable circuit and a second controllable circuit; The control signal is used to turn on or off the first controllable circuit and the second controllable circuit, the first controllable circuit is connected between the first power supply and the power supply end, and the second controllable circuit is connected between the second power supply and the power supply end. 3. The driving circuit according to claim 2, characterized in that the first controllable circuit comprises a first switch element; the second controllable circuit comprises an inverter and a second switch element; wherein the first switch element and the second switch element are of the same type; The control end of the first switching element is connected to the control signal, and the first switching element is connected between the first power supply and the power supply end; the input end of the inverter is connected to the control signal, and the output end of the inverter is connected to the control end of the second switching element; the second switching element is connected between the second power supply and the power supply end. 4 . The driving circuit according to claim 3 , wherein the first switch element and the second switch element are PMOS transistors. 5. The driving circuit according to claim 2, characterized in that the first controllable circuit comprises a first switch element; the second controllable circuit comprises a second switch element; wherein the first switch element and the second switch element are of different types; The control end of the first switch element is connected to the control signal, and the first switch element is connected between the first power supply and the power supply end; the control end of the second switch element is connected to the control signal, and the second switch element is connected between the second power supply and the power supply end. 6 . The driving circuit according to claim 5 , wherein the first switch element is a PMOS transistor, and the second switch element is an NMOS transistor; or, the first switch element is an NMOS transistor, and the second switch element is a PMOS transistor. 7 . The driving circuit according to claim 1 , wherein the first transistor is a PMOS transistor. 8. The driving circuit according to claim 1, characterized in that the driving circuit further comprises: a power supply circuit; The output end of the power supply circuit is connected to the first end of the first transistor. 9. The driving circuit according to claim 8, characterized in that the power supply circuit comprises: a fifth transistor and a sixth transistor; The control end of the fifth transistor is connected to the control end of the sixth transistor; the second end of the fifth transistor is connected to the first end of the sixth transistor and serves as the output end of the power supply circuit. 10. The driving circuit according to claim 1, characterized in that the driving circuit further comprises: a pull-down transistor; The first end of the pull-down transistor is connected to the output end of the driving circuit, and the second end of the pull-down transistor is connected to the second end of the second transistor and a second low level, which is less than the first low level. 11. A storage device, comprising: a word line driving circuit and a storage unit, wherein the word line driving circuit comprises the driving circuit according to any one of claims 1 to 9; The output end of the word line driving circuit is connected to the storage unit; the word line driving circuit includes a sub-word line driving circuit and a main word line driving circuit, wherein the sub-word line driving circuit includes the first driving circuit and the main word line driving circuit includes the second driving circuit. 12. A driving circuit control method, characterized in that it is applied to the driving circuit according to any one of claims 1 to 10, the driving circuit having a working mode and a standby mode, and the method comprises: A control signal representing the working mode or the preparation mode is sent to the power switching circuit, so that the power switching circuit connects the power supply end of the second drive circuit to one of the first power supply and the second power supply in response to the control signal, the first power supply is used to turn off the first transistor in the working mode, and the second power supply is used to turn off the first transistor in the preparation mode; wherein the first power supply is greater than the second power supply. 13. The method according to claim 12, wherein sending a control signal to the power switching circuit comprises: A first control signal is sent to the power switching circuit so that the power switching circuit connects the second power supply to the power supply end of the second drive circuit in response to the first control signal, and disconnects the first power supply from the power supply end of the second drive circuit. 14. The method according to claim 12, wherein sending a control signal to the power switching circuit comprises: A second control signal is sent to the power switching circuit so that the power switching circuit connects the first power supply to the power supply end of the second drive circuit and disconnects the second power supply from the power supply end of the second drive circuit in response to the second control signal.