CN115902424A

CN115902424A - Parasitic inductance measuring method and device

Info

Publication number: CN115902424A
Application number: CN202211724121.1A
Authority: CN
Inventors: 房亮
Original assignee: Jingwei Hengrun Tianjin Research And Development Co ltd
Current assignee: Jingwei Hengrun Tianjin Research And Development Co ltd
Priority date: 2022-12-30
Filing date: 2022-12-30
Publication date: 2023-04-04

Abstract

The application discloses a parasitic inductance measuring method and device, and relates to the technical field of power electronics. The parasitic inductance measurement method comprises the following steps: measuring to obtain a first current waveform of a switching transient process of the second power switch device under the first bus voltage by sending a double-pulse driving signal to the second power switch device; adjusting a grid driving parameter of a second power switch device, wherein the switching-on speed of the second power switch device after adjustment is higher than the switching-on speed of the second power switch device before adjustment; measuring to obtain a second current waveform in the switching-on transient process of the second power switch device under the first bus voltage by sending a double-pulse driving signal to the second power switch device; and under the condition that the first current waveform and the second current waveform are matched, measuring the loop parasitic inductance in the parasitic inductance test circuit. According to the embodiment of the application, the accurate measurement of the parasitic inductance in the loop can be effectively realized.

Description

Parasitic inductance measuring method and device

Technical Field

The application belongs to the technical field of power electronics, and particularly relates to a parasitic inductance measuring method and device.

Background

In various power electronic systems, such as inverters, dc buck-boost systems, etc., power Semiconductor devices, such as Metal-Oxide-Semiconductor Field-Effect transistors (MOSFETs), insulated Gate Bipolar Transistors (IGBTs), etc., are widely used as switching elements to form topologies, such as half-bridge, full-bridge, and three-phase bridge, and the corresponding functions are realized by switching the power Semiconductor devices. In the switching process of the device switch, the current path in the system is obviously changed, the current on part of the path is increased, the current on part of the path is reduced, and the commutation process is completed. In the process, the current change rate on the path is fast and can reach more than 2000A/us.

In an actual power electronic system, current paths of each part, such as a copper bar, device pins, copper-clad Printed Circuit Board (PCB), and inner lead of a package, cannot be regarded as ideal wires, and have corresponding parasitic inductance and resistance, and capacitors and resistors used in the system cannot be regarded as ideal elements, and equivalent parasitic inductance exists. These parasitic inductances can cause problems of voltage overshoot, voltage current oscillation, increased switching losses, etc. during system commutation. The accurate evaluation and measurement of the parasitic inductance have important significance for the design and optimization of the power electronic system.

However, the solutions for measuring and evaluating the parasitic inductance in the prior art generally have the problems of difficulty in accurate measurement, difficulty in solving, low precision, and the like, and therefore, a new solution is still urgently needed in the industry to achieve accurate measurement of the parasitic inductance.

Disclosure of Invention

The embodiment of the application provides a parasitic inductance measuring method and device, which can effectively realize accurate measurement of parasitic inductance in a loop.

In a first aspect, an embodiment of the present application provides a parasitic inductance measurement method, where the parasitic inductance measurement method is applied to a parasitic inductance test circuit, and the parasitic inductance test circuit includes:

the direct-current bus comprises a bus capacitor, a first power switch device, a second power switch device and a load inductor, wherein the bus capacitor, the first power switch device and the second power switch device are sequentially connected in series through a direct-current bus; the bus capacitor is connected with a direct-current voltage source in parallel, and the direct-current voltage source outputs a first bus voltage;

the parasitic inductance measuring method comprises the following steps:

measuring and obtaining a first current waveform of an on-transient process of a second power switch device under the voltage of a first bus by sending a double-pulse driving signal to the second power switch device, wherein the working process of the second power switch device comprises the on-transient process under the action of the double-pulse driving signal;

adjusting a grid driving parameter of a second power switch device, wherein the switching-on speed of the second power switch device after adjustment is higher than the switching-on speed of the second power switch device before adjustment;

measuring a second current waveform in the switching-on transient process of the second power switch device under the first bus voltage by sending a double-pulse driving signal to the second power switch device;

under the condition that the first current waveform is matched with the second current waveform, measuring loop parasitic inductance in the parasitic inductance test circuit;

wherein, the first current waveform and the second current waveform match the characterization: the time of the current linear rising process in the first current waveform and the second current waveform is larger than a preset threshold value.

In some possible embodiments, measuring loop parasitic inductance in a parasitic inductance test circuit includes:

determining a rate of change of current of the second power switch device based on at least one of the first current waveform and the second current waveform;

determining loop parasitic inductance in the parasitic inductance test circuit through a first calculation formula;

the first calculation formula is:

wherein,

is the rate of change of current, L, of the second power switch device _loop Is a loop parasitic inductance, U _DC Is a first bus voltage, V _S1 Is the conduction voltage drop, V, of the anti-parallel diode in the first power switch device _S2 Is the forward conduction voltage drop of the second power switch device.

In some possible embodiments, measuring loop parasitic inductance in a parasitic inductance test circuit with the first current waveform and the second current waveform matched comprises:

matching a first current linear transformation segment in the first current waveform with a second current linear transformation segment in the second current waveform;

and under the condition that the first current linear transformation section is matched with the second current linear transformation section, measuring the loop parasitic inductance in the parasitic inductance test circuit.

In some possible embodiments, after measuring a second current waveform during a turn-on transient of the second power switch device at the first bus voltage, the parasitic inductance measurement method further comprises:

under the condition that the first current waveform and the second current waveform are not matched, adjusting target parameters, wherein the target parameters are as follows: the bus voltage output by the direct current voltage source; or, a gate drive parameter of the second power switch device;

measuring a third current waveform of the switching-on transient process of the second power switch device after the target parameter is adjusted by sending a double-pulse driving signal to the second power switch device;

and determining whether to measure the loop parasitic inductance in the parasitic inductance test circuit according to the third current waveform.

In some possible embodiments, in the case that the target parameter is a bus voltage output by a dc voltage source, in the case that the first current waveform and the second current waveform do not match, adjusting the target parameter includes:

under the condition that the first current waveform and the second current waveform are not matched, the first bus voltage output by the direct current voltage source is adjusted to be the second bus voltage;

determining whether to measure loop parasitic inductance in a parasitic inductance test circuit based on the third current waveform, comprising:

measuring a fourth current waveform of the switching transient process of the second power switch device under the second bus voltage by sending a double-pulse driving signal to the second power switch device;

and under the condition that the third current waveform and the fourth current waveform are matched, measuring the loop parasitic inductance in the parasitic inductance test circuit.

In some possible embodiments, in the case that the first current waveform and the second current waveform do not match, adjusting the first bus voltage output by the dc voltage source to the second bus voltage includes:

and under the condition that the first current waveform and the second current waveform are not matched and the difference value between the switching speed of the second power switch device and the upper limit value of the switching speed of the second power switch device is smaller than a first threshold value, adjusting the first bus voltage output by the direct-current voltage source into a second bus voltage.

In some possible embodiments, in the case where the first current waveform and the second current waveform match, the parasitic inductance measurement method further includes:

measuring a first voltage waveform at two ends of a branch to be tested in a parasitic inductance test circuit in a target time period, wherein the target time period is a time period corresponding to the turn-on transient process of a second power switch device under the voltage of a first bus; the branch to be tested does not comprise a bus capacitor;

determining a first voltage value of a first voltage segment in a first voltage waveform; the difference value between the voltage value corresponding to each moment in the first voltage section and the first voltage value is smaller than a second threshold value; the time period corresponding to the first voltage segment is matched with the time period corresponding to the current rising segment in the target current waveform; the target current waveform is determined based on the first current waveform and/or the second current waveform;

determining the parasitic inductance of the branch to be tested through a second calculation formula;

the second calculation formula is:

wherein L is _DUT Parasitic electricity for branch under testThe feeling of the human body is that,

is the rate of change of current, U, of the second power switch device _DUT Is the first voltage value.

In some possible embodiments, in the case that the first current waveform and the second current waveform match, the parasitic inductance measurement method further includes:

measuring a second voltage waveform of a bus capacitor in the parasitic inductance test circuit in the target time period;

determining a second voltage value of a second voltage segment in the second voltage waveform; the time period corresponding to the second voltage segment is matched with the time period corresponding to the current rising segment in the target current waveform; the difference value between the voltage value corresponding to each moment in the second voltage section and the second voltage value is smaller than a third threshold value;

determining the parasitic inductance of the bus capacitor through a third calculation formula;

the third calculation formula is:

wherein L is ₁ Is the parasitic inductance of the bus capacitance,

is the rate of change of current, U, of the second power switch device _C Is a second voltage value, U _DC Is the first bus voltage.

In some possible embodiments, the bus voltage output by the dc voltage source ranges between 10V and 50V.

In a second aspect, an embodiment of the present application provides a parasitic inductance measurement apparatus, which is applied to a parasitic inductance test circuit, where the parasitic inductance test circuit includes:

the parasitic inductance measuring device includes:

the first measurement module is used for measuring and obtaining a first current waveform of an on-transient process of the second power switch device under the voltage of the first bus by sending a double-pulse driving signal to the second power switch device, wherein under the action of the double-pulse driving signal, the working process of the second power switch device comprises the on-transient process;

the first adjusting module is used for adjusting the grid driving parameters of the second power switch device, wherein the switching-on speed of the second power switch device after adjustment is higher than the switching-on speed of the second power switch device before adjustment;

the second measurement module is used for measuring a second current waveform in the switching-on transient process of the second power switch device under the first bus voltage by sending a double-pulse driving signal to the second power switch device;

the third measuring module is used for measuring the loop parasitic inductance in the parasitic inductance testing circuit under the condition that the first current waveform is matched with the second current waveform;

the first current waveform and the second current waveform are matched and characterized: the time of the current linear rising process in the first current waveform and the second current waveform is larger than a preset threshold value.

In a third aspect, an embodiment of the present application provides a parasitic inductance measurement apparatus, including:

a processor and a memory storing computer program instructions;

the processor, when executing the computer program instructions, implements a parasitic inductance measurement method as provided in any of the embodiments of the present application described above.

In a fourth aspect, embodiments of the present application provide a computer storage medium having computer program instructions stored thereon, which when executed by a processor, implement a parasitic inductance measurement method as provided in any one of the embodiments of the present application.

In a fifth aspect, the present application provides a computer program product, and instructions in the computer program product, when executed by a processor of an electronic device, cause the electronic device to perform the parasitic inductance measurement method as provided in any one of the embodiments of the present application.

According to the parasitic inductance measuring method and device, the double-pulse driving signal is sent to the second power switch device, the first current waveform of the second power switch device in the transient switching-on process under the first bus voltage is measured, the grid driving parameter of the second power switch device is adjusted, and the adjusted second current waveform is measured. In this way, the loop parasitic inductance in the parasitic inductance test circuit is measured through the matching condition of the first current waveform and the second current waveform. According to the parasitic inductance measuring method and device provided by the embodiment of the application, whether the characteristics of the grid driving parameters of the first bus voltage and the second power switch device are matched or not can be verified based on the matching condition of the first current waveform and the second current waveform, and the loop parasitic inductance is measured under the condition that the characteristics of the grid driving parameters of the first bus voltage and the second power switch device are matched and the time of the linear rising process of the current in the first current waveform and the time of the linear rising process of the current in the second current waveform are both larger than the preset threshold value, so that the accurate measurement of the parasitic inductance in the loop is effectively guaranteed.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic flowchart of a parasitic inductance measurement method according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a parasitic inductance measurement circuit according to an embodiment of the present application;

FIG. 3 is a waveform diagram of the parasitic inductance measurement circuit shown in FIG. 2 according to an embodiment of the present application;

FIG. 4 is a voltage-current waveform schematic diagram of the parasitic inductance measurement circuit shown in FIG. 2 according to an embodiment of the present application;

fig. 5 is a schematic diagram of another structure of a parasitic inductance measurement circuit according to an embodiment of the present application;

fig. 6 is a schematic diagram of another structure of a parasitic inductance measurement circuit according to an embodiment of the present application;

fig. 7 is a schematic diagram of another structure of a parasitic inductance measurement circuit according to an embodiment of the present application;

FIG. 8 is a voltage-current waveform schematic diagram of the parasitic inductance measurement circuit shown in FIG. 7 according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a parasitic inductance measurement apparatus according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a parasitic inductance measurement apparatus according to an embodiment of the present application.

Detailed Description

Features of various aspects and exemplary embodiments of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of, and not restrictive on, the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising 8230; \8230;" comprises 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

The inventor finds that, because commutation in a power electronic system often occurs in a certain half-bridge loop, evaluation and measurement of parasitic inductance are often performed on a system of bus capacitance, a bus bar and a power half-bridge. The evaluation of the parasitic inductance specifically includes two methods, i.e., simulation calculation and experimental measurement. The simulation calculation method is based on a current path space geometric model, and the parasitic inductance value of the current path is calculated by adopting methods such as theoretical formula approximation, finite element and the like. However, the method has the problems that the calculation accuracy is influenced by the modeling accuracy, the method cannot completely correspond to an actual system, parasitic inductance of passive devices such as capacitance and resistance is difficult to consider, and the like, and generally requires comparison and verification of experimental measurement results.

Therefore, the current method for estimating the parasitic inductance through experimental measurement comprises solving according to the peak value of the turn-off voltage and the change rate of the turn-off current, solving the resonance frequency obtained by oscillating the system through artificial excitation, and solving according to the change rate of the current and the voltage platform in the turn-on process of the device under inductive load. The former two have the problems of relying on transient signal test, being influenced by junction capacitance change and the like, and the accuracy is poor. Based on this, solving from the rate of change of current and the voltage plateau during the turn-on process is a commonly used type of method. However, through further research by the inventor, it is found that since the current change rate is controlled by the gate charging process and the device output characteristics together, it is difficult to stabilize for a long time, and thus there is also a problem that accurate measurement and solution are difficult. Meanwhile, the method is limited by the problem of voltage measurement points, and it is generally difficult to measure the parasitic inductance inside the package.

In view of the above, to solve the problems in the prior art, embodiments of the present application provide a parasitic inductance measurement method, apparatus, device, storage medium, and computer program product. It should be noted that the examples provided herein are not intended to limit the scope of the present disclosure.

First, a method for measuring parasitic inductance provided in the embodiments of the present application will be described below.

Fig. 1 shows a schematic flow chart of a parasitic inductance measurement method according to an embodiment of the present application. The parasitic inductance measuring method is applied to a parasitic inductance testing circuit, and the parasitic inductance testing circuit comprises the following steps:

the parasitic inductance measurement method may include:

s110, a first current waveform of a switching-on transient process of the second power switch device under the first bus voltage is measured and obtained by sending a double-pulse driving signal to the second power switch device, wherein under the action of the double-pulse driving signal, the working process of the second power switch device can comprise the switching-on transient process;

s120, adjusting grid driving parameters of a second power switch device, wherein the switching-on speed of the second power switch device after adjustment is higher than the switching-on speed of the second power switch device before adjustment;

s130, a second current waveform in the switching-on transient process of the second power switch device under the first bus voltage is measured by sending a double-pulse driving signal to the second power switch device;

s140, measuring loop parasitic inductance in the parasitic inductance test circuit under the condition that the first current waveform is matched with the second current waveform; wherein, the first current waveform and the second current waveform match the characterization: the time of the current linear rising process in the first current waveform and the second current waveform is larger than a preset threshold value.

According to the parasitic inductance measuring method, the double-pulse driving signal is sent to the second power switch device firstly, the first current waveform of the second power switch device in the transient switching-on process under the voltage of the first bus is obtained through measurement, then the grid driving parameter of the second power switch device is adjusted, and the adjusted second current waveform is measured. In this way, the loop parasitic inductance in the parasitic inductance test circuit is measured through the matching condition of the first current waveform and the second current waveform.

According to the parasitic inductance measuring method provided by the embodiment of the application, whether the characteristics of the grid driving parameters of the first bus voltage and the second power switch device are matched or not can be verified based on the matching condition of the first current waveform and the second current waveform. When the characteristics of the grid driving parameters of the first bus voltage and the second power switch device are matched, and the time of the linear rising process of the current in the first current waveform and the second current waveform is greater than a preset threshold value (the first current waveform and the second current waveform comprise a long-time stable current rising section), the loop parasitic inductance is measured, and therefore the accurate measurement of the parasitic inductance in the loop is effectively guaranteed.

The following describes a specific implementation of the above steps 110 to 140 in detail.

To facilitate better understanding of the following embodiments of the present application, please refer to fig. 2 and fig. 3, first, fig. 2 is a schematic structural diagram of a parasitic inductance measurement circuit according to an embodiment of the present application; fig. 3 is a waveform diagram of the parasitic inductance measurement circuit shown in fig. 2 according to an embodiment of the present application.

In fig. 2, S1 is a first power switch device, S2 is a second power switch device, the first/second power switch device may be specifically MOSFET, IGBT, etc., C is a bus capacitor, I _DS A current sensor (such as Rogowski coil, shunt resistor, hall sensor, etc.) for measuring current passing through the S2 element, L is a load inductor for double-pulse test, the inductance value is in uH level, L1 is a parasitic inductor of bus capacitor, L2-L5 are parasitic inductors corresponding to partial current paths, the inductance values of L1-L5 are generally in tens nH level, the grid electrode of the second power switch device S2 is connected with a double-pulse signal transmitting platform for conducting or closing according to a double-pulse signal received by the grid electrodeAnd (7) breaking.

In general, evaluating the characteristics of a power electronic system generally requires measuring the total parasitic inductance of a loop, the loop parasitic inductance L in the parasitic inductance measurement circuit shown in fig. 2 _loop The expression is shown as formula 1.

L _loop ＝L ₁ +L ₂ +L ₃ +L ₄ +L ₅ Formula 1

The operation of the parasitic inductance measurement circuit of fig. 2 will be described with reference to fig. 3.

In FIG. 3, V _GS(S2) Is the gate-source voltage, I, of the element S2 _L Is the current of the load inductor L, I _DS(S2) For a drain-source current through the element S2, V _DS(S2) Is the drain-source voltage of source S2.

With reference to fig. 3, during a specific test procedure, the first power switch S1 is always turned off.

At t ₀ At the moment, the second power switch device S2 is switched on, so that the load inductor generates continuously rising current under the action of the bus voltage output by the direct-current voltage operator, and the current I passes through the second power switch device S2 _DS(S2) And then rises, keeping the same with the inductor current.

In the time period from t0 to t1, the voltage V at the two ends of the S2 device _DS(S2) Reducing to a conduction drop (typically smaller, much less than the bus voltage). The current path in this circuit is shown as a solid line in fig. 2 during this process. By controlling t ₀ ～t ₁ Time of, can control t ₁ Device current before time, i.e. test current I _norm . Test current I _norm Determined by equation 2:

wherein L is the inductance of the load inductor, U _dc Is the bus voltage.

At t ₁ At this moment, the second power switch device S2 is turned off to form an open circuit, and the load inductor passes through the first switch power device because the load inductor current cannot suddenly changeThe anti-parallel diode in S1 freewheels, after which the current path in this current is shown as a dashed line in fig. 2.

In the period from t1 to t2, the freewheeling diode and the loop parasitic resistance in the first power switch device consume the inductive energy to reduce the current by a small amount, but the reduction speed and the reduction amplitude are much smaller than the current rise rate when S2 is turned on, so that the inductive currents at the time points t1 and t2 are considered to be the same. And, at this stage, since the second power switch S2 is turned off, the current I through the second power switch S2 _DS(S2) Zero, the voltage V across the second power switch S2 _DS(S2) Equal to the bus voltage.

At time t2, the second power switch S2 is turned on again and the current path changes back to the solid path in fig. 2. At time t3, the second power switch S2 is closed again, and the current path changes to the dashed path in fig. 2, and continues until the inductor energy is depleted.

Referring to fig. 4, for the turn-on process of the second power switch at the time t2, fig. 4 is a schematic voltage-current waveform diagram of the parasitic inductance measurement circuit shown in fig. 2 according to an embodiment of the present disclosure.

Fig. 4 shows I corresponding to the turn-on transient process of the second power switching device S2 measured at the time t2 under the corresponding bus voltage _DS(S2) Current waveform, V _GS(S2) Voltage waveform and V _DS(S2) A voltage waveform. Please see, I shown in fig. 4 _DS(S2) And the current waveform can generate a current linear change section of one ns level at the moment when the second power switch device is switched on at the moment of t 2.

Returning to the parasitic inductance measurement method provided by the present application, in S110, in a specific implementation, a double-pulse driving signal is sent to the second power switching device, and a first current waveform of an on-transient process of the second power switching device at the first bus voltage at time t2 is measured, where an operating process of the second power switching device includes the on-transient process under the action of the double-pulse driving signal.

When the waveform is specifically measured, the current sensor, for example, the rogowski coil, the shunt resistor, the hall sensor, and the like, may be disposed in the parasitic inductance measurement circuit, and then the oscilloscope and the like are combined to obtain the first current waveform of the switching transient process of the second power switch device under the first bus voltage.

In S120, in a specific implementation, after the first current waveform is obtained through measurement, a gate driving parameter of the second power switch device is adjusted to increase an on speed of the second power switch device. The adjusted turn-on speed of the second power switch device is higher than the turn-on speed of the second power switch device before adjustment, that is, when the adjusted gate driving parameter is used for driving the second power switch device to be turned on, the turn-on speed of the second power switch device is higher than the turn-on speed of the second power switch device when the adjusted gate driving parameter is used for driving the second power switch device to be turned on.

The adjusting of the gate driving parameter of the second power switch device may specifically be reducing a gate resistance, increasing a positive gate voltage value during turn-on, or reducing a gate capacitance value when an external gate capacitance exists, and the like, which is not specifically limited by the present application.

In S130, in a concrete implementation, after the gate driving parameter of the second power switching device is adjusted to increase the turn-on speed of the second power switching device at the time t2, the second current waveform in the turn-on transient process of the second power switching device under the first bus voltage is measured by sending the double-pulse driving signal to the second power switching device again.

The second current waveform is measured in a manner consistent with the manner of measuring the first current waveform, except that: the turn-on speed of the second power switch device corresponding to the second current waveform has been increased by adjusting the gate drive parameter.

In S140, in a specific implementation, the first current waveform and the second current waveform obtained by measurement are matched, and specifically, for example, whether current variation trends and the like corresponding to a certain time period in the first current waveform and the second current waveform are consistent or not may be checked. In this way, the loop parasitic inductance in the parasitic inductance test circuit is measured again in the case where it is determined that the first current waveform and the second current waveform match.

Because the first current waveform and the second current waveform are matched and characterized: the characteristics of the grid driving parameters of the first bus voltage and the second power switch device are matched, and the time of the current linear rising process in the first current waveform and the second current waveform is larger than a preset threshold value (the first current waveform and the second current waveform comprise a stable current rising section with a longer time). At the moment, the parasitic inductance of the loop is measured specifically, so that the accurate measurement of the parasitic inductance in the loop can be effectively guaranteed.

In some possible embodiments, measuring the loop parasitic inductance in the parasitic inductance test circuit may include:

the first calculation formula is as follows:

wherein,

In specific implementation, for example, a current linear transformation section in which a current appears a stable linear rise may be selected from a first current waveform, a second current waveform, or a current waveform obtained by fusing the first current waveform and the second current waveform by using a related image processing means, so as to determine a current change rate of the second power switch device according to the current linear transformation section, and then a first calculation formula is combined to specifically calculate a loop parasitic inductance in the parasitic inductance test circuit.

In this embodiment, considering that the conduction voltage drop of the anti-parallel diode after being completely turned on is relatively small along with the change of the current, the diode conduction voltage drop V can be directly used _F Approximate substitution, i.e.

V _S1 ＝V _F

Wherein, V _F The value can be obtained by the device datasheet.

V _S2 The forward conduction voltage drop of the second power switch device S2, which can be approximated by the following equation when the second power switch device S2 is a MOSFET

V _S2 ＝I _norm ·R _DS(on)

Wherein, I _norm Is the test current in the aforementioned formula 2, R _DS(on) Is the on-resistance of the second power switch S2.

When the second power switch device S2 is an IGBT, the forward saturation voltage drop of the second power switch device S2 can be approximately substituted, where V _CEsat The value can be obtained by the device datasheet.

V _S2 ＝V _CEsat

By adopting the parasitic inductance measurement method provided by the application to measure the loop parasitic inductance, because the first current waveform is matched with the second current waveform, the characteristics of the bus voltage of the direct-current voltage source and the grid drive parameter of the second power switch device are matched, the linearity of the current rise process is good, the duration of the rise stage is long, and the stable current change rate is easy to extract

And higher measurement accuracy is obtained.

In addition, the parasitic inductance measuring method provided by the application only needs one current measuring probe during actual measurement, a voltage probe is not needed, and the measuring requirement and complexity are effectively reduced. Meanwhile, by adopting the measuring method provided by the invention, the measurement of the parasitic inductance of the whole system including the parasitic inductance inside the module can be completed without arranging a measuring point in the power module, so that the integrity of the measuring result is improved.

In some possible embodiments, considering the actual need of measuring the parasitic inductance, the step S140 of measuring the loop parasitic inductance in the parasitic inductance test circuit in the case that the first current waveform and the second current waveform match may include:

The first current linear transformation end in the first current waveform and the second current linear transformation section in the second current waveform may specifically refer to the current linear transformation section indicated in fig. 4.

Specifically, when the first current linear transformation segment and the second current linear transformation segment are matched, the current transformation rates (transformation segment slopes) of the first current linear transformation segment and the second current linear transformation segment may be compared, and if the current transformation rates of the first current linear transformation segment and the second current linear transformation segment are consistent or almost consistent, the first current linear transformation segment and the second current linear transformation segment may be considered to be matched, that is, the first current waveform and the second current waveform are matched. At the moment, the loop parasitic inductance in the parasitic inductance measuring circuit is measured and calculated, so that the accuracy of the measured loop parasitic inductance can be fully guaranteed.

In some possible embodiments, for the case that the first current waveform and the second current waveform do not match, that is, the bus voltage does not match the characteristics of the gate driving parameters of the second power switching device, it is necessary to perform adjustment based on the parasitic capacitance measurement loop, so that the final bus voltage matches the characteristics of the gate driving parameters of the second power switching device, and thus a stable current linear rising section of a long time in the current waveform of the second power switching device in the on transient process is obtained. Therefore, after measuring the second current waveform during the turn-on transient of the second power switch device at the first bus voltage, the parasitic inductance measurement method may further include:

measuring to obtain a third current waveform of the second power switch device in the switching-on transient process after the target parameter is adjusted by sending a double-pulse driving signal to the second power switch device;

In the specific implementation, the gate driving parameter of the dc bus source or the second power switching device may be adjusted, a current waveform corresponding to the adjusted turn-on transient process of the second power switching device is measured, and whether the loop parasitic inductance in the parasitic inductance test circuit may be measured is determined according to the current waveform.

In some possible embodiments, in order to achieve rationality of adjusting the target parameter so as to further ensure accurate measurement of the loop parasitic inductance, in the case that the target parameter is a gate driving parameter of the second power switch device, determining whether to measure the loop parasitic inductance in the parasitic inductance test circuit according to the third current waveform may include:

and under the condition that the third current waveform is matched with the second current waveform, measuring the loop parasitic inductance in the parasitic inductance test circuit.

In some possible embodiments, in order to achieve rationality of adjustment of the target parameter, so as to further ensure accurate measurement of the loop parasitic inductance, in a case where the target parameter is a bus voltage output by a dc voltage source, and in a case where the first current waveform and the second current waveform do not match, the adjusting of the target parameter may specifically include:

under the condition that the first current waveform and the second current waveform are not matched, the first bus voltage output by the direct-current voltage source is adjusted to be the second bus voltage;

determining whether to measure loop parasitic inductance in the parasitic inductance test circuit based on the third current waveform may include:

In concrete implementation, under the condition that the first current waveform and the second current waveform are not matched, the first bus voltage output by the direct-current voltage source is adjusted to be the second bus voltage, and the third current waveform of the second power switch device in the switching transient process under the second bus voltage is measured. At this time, the gate driving parameter of the second power switch device is adjusted to increase the turn-on speed of the second power switch device. After the grid driving parameter of the second power switch device is adjusted, a double-pulse driving signal is sent to the second power switch device, and a fourth current waveform of the adjusted switching transient process of the second power switch device under the second bus voltage is measured and obtained.

In this way, the loop parasitic inductance in the parasitic inductance test circuit is measured by judging whether the third current waveform and the fourth current waveform match or not and under the condition that the third current waveform and the fourth current waveform are determined to match.

In some possible embodiments, although the target parameter may be a bus voltage of a dc voltage source or a gate driving parameter of a second power switch device, the inventors of the present application have found, in combination with an actual parasitic capacitance measurement experimental scenario, that direct adjustment of the bus voltage is avoided as much as possible in order to reduce an experimental measurement error. That is, when the first current waveform and the second current waveform are not matched, the gate driving parameter of the second power switch device is preferentially adjusted to increase the turn-on speed of the second power switch device.

However, the on speed of the power switch device has an upper limit, and if the on speed is too high, the device may be damaged or burned out. Based on this, in order to achieve more reasonable adjustment of the target parameter, the adjusting the first bus voltage output by the dc voltage source to the second bus voltage when the first current waveform and the second current waveform are not matched may include:

and under the condition that the first current waveform and the second current waveform are not matched and the difference value between the switching-on speed of the second power switch device and the upper limit value of the switching-on speed of the second power switch device is smaller than a first threshold value, adjusting the first bus voltage output by the direct-current voltage source into a second bus voltage.

It should be noted that the upper limit value of the on speed of the second power switch device may be determined by looking up the device datasheet.

In the parasitic inductance measurement method of the present application, when the foregoing description is given by taking fig. 2 as an example, S2 is used as a second power switch device to perform a double pulse test, so as to implement measurement of parasitic inductance. However, in some other embodiments, see fig. 5, fig. 5 is still another schematic structural diagram of the parasitic inductance measurement circuit provided in an embodiment of the present application, and a double pulse test may also be performed by using S1 as the second power switch device of the present solution, so as to implement measurement of parasitic inductance.

In addition to the above-mentioned measurement method for measuring the loop parasitic inductance, the parasitic inductance measurement method provided by the present application can also be used for measuring the parasitic inductance of a specific part of the current path. In some possible embodiments, in particular, in case the first current waveform and the second current waveform match, the parasitic inductance measurement method may further include:

measuring first voltage waveforms at two ends of a branch to be tested in the parasitic inductance test circuit in a target time period, wherein the target time period is a time period corresponding to the switching-on transient process of a second power switch device under the voltage of a first bus; the branch to be tested cannot comprise a bus capacitor;

the second calculation formula may be:

wherein L is _DUT Is the parasitic inductance of the branch to be tested,

is the rate of change of current, U, of the second power switch device _DUT Is a first voltage value.

Referring to fig. 6, fig. 6 is a schematic diagram of another structure of a parasitic inductance measurement circuit according to an embodiment of the present application. As shown in fig. 6, the voltage probe may be connected to two sides of the current path to be measured (branch to be measured), and the first voltage waveform U at two ends of the current path to be measured during the transient state of turning on of the second power switch device S2 is recorded at the time t2 _DUT (t)。

At the second switching power device current I _ds During the rise, the first voltage waveform U _DUT (t) a voltage plateau (first voltage segment) appears, and the plateau voltage value U is recorded _DUT (first voltage value), the parasitic inductance of the portion of the current path can be calculated using a second calculation formula.

In some possible embodiments, similarly, the parasitic inductance measurement method provided by the application can also be used for measuring the parasitic inductance of the bus capacitance. Specifically, in the case where the first current waveform and the second current waveform match, the parasitic inductance measurement method may further include:

the third calculation formula may be:

wherein L is ₁ Is the parasitic inductance of the bus capacitance,

is the rate of change of current, U, of the second power switch device _C Is a second voltage value, U _DC Is a first bus voltage.

Referring to fig. 7, fig. 7 is a schematic diagram of another structure of a parasitic inductance measurement circuit according to an embodiment of the present disclosure. As shown in fig. 7, the voltage probe is used to record the voltage waveform U at both ends of the current path to be measured during the transient state of turning on of the second power switch device S2 at the time t2 _C (t), referring to fig. 8 in particular, fig. 8 is a schematic voltage-current waveform diagram of the parasitic inductance measurement circuit shown in fig. 7 according to an embodiment of the present application. Referring to fig. 8, the current I is flowing in the second switching power device S2 _DS During the rise, the second voltage waveform U _C (t) a voltage plateau (second voltage segment) appears, and the plateau voltage value U is recorded _C (second voltage value), the parasitic inductance of the bus capacitance can be calculated by using a third calculation formula.

In some possible embodiments, in order to further improve the accuracy of the parasitic inductance measurement, the bus voltage output by the dc voltage source ranges between 10V and 50V. In the foregoing embodiment, the first bus voltage or the second bus voltage output by the dc voltage source may be both in the range of 10V to 50V.

The inventor of the present application has recognized that, in the parasitic inductance measurement scheme applied to the parasitic inductance measurement circuit, if the bus voltage output by the dc voltage source is too low, the ratio of the conduction voltage of the second power switch device occupied in the actual loop parasitic inductance calculation step is too large, and the parasitic inductance measurement accuracy may be affected. If the bus voltage output by the direct-current voltage source is too high, the long-time current stable linear rising section of the second power switch device in the switching-on transient process is not easy to measure, and the actual calculation of the subsequent parasitic capacitance is not facilitated.

Therefore, in combination with the above considerations, the inventor of the present application has studied to limit the range of the bus voltage output by the dc voltage source in the present application to 10V to 50V, so as to further achieve accurate measurement of the parasitic inductance.

It should be added that the parasitic inductance measurement method provided by the present application can be applied to, but is not limited to, a power electronic system with low on-resistance and large rated current, and preferably, for the rated current not less than 80A, the rated on-voltage drop is not higher than 2.5V.

Under the precondition, the longer rise time of the current during the switching-on can be obtained under the same test condition only by providing a larger test current, so that the measurement process is more accurate. In addition, if the rated current of the second power switch device is small and cannot bear a large current test, a relatively low bus voltage can be selected as much as possible to reduce the current change rate in the switching-on process and improve the current rise time of the second power switch device during switching-on.

Based on the parasitic inductance measurement method provided in the foregoing embodiment, the present application further provides a parasitic inductance measurement apparatus corresponding to the parasitic inductance measurement method, and the parasitic inductance measurement apparatus is described in detail with reference to fig. 9.

Fig. 9 shows a schematic structural diagram of a parasitic inductance measurement apparatus according to an embodiment of the present application.

The parasitic inductance measuring apparatus 900 shown in fig. 9 includes:

this parasitic inductance measuring device is applied to parasitic inductance test circuit, and this parasitic inductance test circuit includes:

the parasitic inductance measuring apparatus may include:

a first measurement module 910, configured to measure a first current waveform of a turn-on transient process of a second power switching device at a first bus voltage by sending a double-pulse driving signal to the second power switching device, where a working process of the second power switching device includes the turn-on transient process under an action of the double-pulse driving signal;

a first adjusting module 920, configured to adjust a gate driving parameter of a second power switching device, where an adjusted turn-on speed of the second power switching device is higher than a turn-on speed of the second power switching device before adjustment;

a second measurement module 930, configured to measure a second current waveform in a turn-on transient process of the second power switch device under the first bus voltage by sending a double-pulse driving signal to the second power switch device;

a third measuring module 940, configured to measure the loop parasitic inductance in the parasitic inductance test circuit when the first current waveform and the second current waveform match;

In some possible embodiments, the third measurement module 940 may include:

a first determination submodule operable to determine a rate of change of current of the second power switching device based on at least one of the first current waveform and the second current waveform;

the second determining submodule can be used for determining the loop parasitic inductance in the parasitic inductance testing circuit through the first calculation formula;

the first calculation formula is:

wherein,

is the rate of change of current, L, of the second power switch device _loop Is a loop parasitic inductance, U _DC Is a first bus voltage, V _S1 Is the voltage drop, V, of the conduction of the anti-parallel diode in the first power switch _S2 Is the forward conduction voltage drop of the second power switch device.

In some possible embodiments, the third measurement module 940 may include:

the matching submodule can be used for matching a first current linear transformation section in the first current waveform with a second current linear transformation section in the second current waveform;

and the first measurement submodule can be used for measuring the loop parasitic inductance in the parasitic inductance test circuit under the condition that the first current linear transformation section is matched with the second current linear transformation section.

In some possible embodiments, after measuring the second current waveform during the turn-on transient of the second power switch device at the first bus voltage, the parasitic inductance measurement device may further include:

the second adjusting module may be configured to adjust a target parameter when the first current waveform and the second current waveform are not matched, where the target parameter is: the bus voltage output by the direct current voltage source; or, a gate drive parameter of the second power switch device;

the fourth measurement module may be configured to measure a third current waveform of the second power switching device during the transient switching-on process after the target parameter is adjusted by sending a double-pulse driving signal to the second power switching device;

and the first determining module can be used for determining whether to measure the loop parasitic inductance in the parasitic inductance test circuit according to the third current waveform.

In some possible embodiments, in the case that the target parameter is a bus voltage output by a dc voltage source, the second adjusting module may specifically include:

the first adjusting submodule can be used for adjusting the first bus voltage output by the direct-current voltage source into a second bus voltage under the condition that the first current waveform and the second current waveform are not matched;

the first determining module may include:

the second adjusting submodule can be used for adjusting the grid driving parameter of the second power switching device, wherein the switching-on speed of the second power switching device after adjustment is higher than the switching-on speed of the second power switching device before adjustment;

the second measurement submodule can be used for measuring a fourth current waveform of the second power switching device in the switching-on transient process under the second bus voltage by sending a double-pulse driving signal to the second power switching device;

and the third measurement submodule can be used for measuring the loop parasitic inductance in the parasitic inductance test circuit under the condition that the third current waveform and the fourth current waveform are matched.

In some possible embodiments, the first adjusting submodule may include:

In some possible embodiments, in the case that the first current waveform and the second current waveform match, the parasitic inductance measurement device may further include:

the fifth measurement module can be used for measuring the first voltage waveforms at two ends of a branch to be tested in the parasitic inductance test circuit in a target time period, wherein the target time period is a time period corresponding to the turn-on transient process of the second power switch device under the voltage of the first bus; the branch to be tested cannot comprise a bus capacitor;

a second determination module operable to determine a first voltage value of a first voltage segment in the first voltage waveform; the difference value between the voltage value corresponding to each moment in the first voltage section and the first voltage value is smaller than a second threshold value; the time period corresponding to the first voltage segment is matched with the time period corresponding to the current rising segment in the target current waveform; the target current waveform is determined based on the first current waveform and/or the second current waveform;

the third determining module can be used for determining the parasitic inductance of the branch to be tested through a second calculation formula;

the second calculation formula may be:

wherein L is _DUT Is the parasitic inductance of the branch to be tested,

the sixth measurement module can be used for measuring a second voltage waveform of the bus capacitor in the parasitic inductance test circuit in the target time period;

a fourth determining module operable to determine a second voltage value of a second voltage segment in the second voltage waveform; the time period corresponding to the second voltage segment is matched with the time period corresponding to the current rising segment in the target current waveform; the difference value between the voltage value corresponding to each moment in the second voltage section and the second voltage value is smaller than a third threshold value;

the fifth determining module can be used for determining the parasitic inductance of the bus capacitor through a third calculation formula;

the third calculation formula is:

wherein L is ₁ Is the parasitic inductance of the bus capacitance,

In some possible embodiments, the bus voltage output by the dc voltage source may range between 10V and 50V.

The parasitic inductance measurement device may include a processor 1001 and a memory 1002 having computer program instructions stored therein.

Specifically, the processor 1001 may include a Central Processing Unit (CPU), or an Application Specific Integrated Circuit (ASIC), or may be configured to implement one or more Integrated circuits of the embodiments of the present Application.

Memory 1002 may include mass storage for data or instructions. By way of example, and not limitation, memory 1002 may include a Hard Disk Drive (HDD), a floppy Disk Drive, flash memory, an optical Disk, a magneto-optical Disk, magnetic tape, or a Universal Serial Bus (USB) Drive or a combination of two or more of these. Memory 1002 may include removable or non-removable (or fixed) media, where appropriate. The memory 1002 may be internal or external to the integrated gateway disaster recovery device, where appropriate. In a particular embodiment, the memory 1002 is non-volatile solid-state memory.

The memory may include Read Only Memory (ROM), random Access Memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical, or other physical/tangible memory storage devices. Thus, in general, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software comprising computer-executable instructions and when the software is executed (e.g., by one or more processors), it is operable to perform operations described with reference to the methods according to an aspect of the present disclosure.

The processor 1001 reads and executes the computer program instructions stored in the memory 1002 to implement any one of the parasitic inductance measurement methods in the above embodiments.

In one example, the data parasitic inductance measurement device may also include a communication interface 1003 and a bus 1010. As shown in fig. 10, the processor 1001, the memory 1002, and the communication interface 1003 are connected to each other via a bus 1010 to complete communication therebetween.

The communication interface 1003 is mainly used to implement communication between each module, apparatus, unit and/or device in this embodiment.

Bus 1010 includes hardware, software, or both to couple the components of the parasitic inductance measurement device to each other. By way of example, and not limitation, a bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hypertransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an infiniband interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a video electronics standards association local (VLB) bus, or other suitable bus or a combination of two or more of these. Bus 1010 may include one or more buses, where appropriate. Although specific buses are described and shown in the embodiments of the application, any suitable buses or interconnects are contemplated by the application.

The parasitic inductance measuring apparatus performs the parasitic inductance measuring method in the embodiment of the present application, thereby implementing the parasitic inductance measuring method described in fig. 1.

In addition, in combination with the parasitic inductance measurement method in the foregoing embodiments, the embodiments of the present application may provide a computer storage medium to implement. The computer storage medium having computer program instructions stored thereon; the computer program instructions, when executed by a processor, implement any of the parasitic inductance measurement methods of the above embodiments.

Based on the parasitic inductance measurement method in the foregoing embodiments, an embodiment of the present application provides a computer program product, and when executed by a processor of an electronic device, instructions in the computer program product cause the electronic device to perform the parasitic inductance measurement method provided in any one of the foregoing embodiments of the present application.

It is to be understood that the present application is not limited to the particular arrangements and instrumentality described above and shown in the attached drawings. A detailed description of known methods is omitted herein for the sake of brevity. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and illustrated, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps, after comprehending the spirit of the present application.

The functional blocks shown in the above-described structural block diagrams may be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, plug-in, function card, or the like. When implemented in software, the elements of the present application are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine-readable medium or transmitted by a data signal carried in a carrier wave over a transmission medium or a communication link. A "machine-readable medium" may include any medium that can store or transfer information. Examples of a machine-readable medium include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio Frequency (RF) links, and so forth. The code segments may be downloaded via computer networks such as the internet, intranets, etc.

It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, may be performed in an order different from the order in the embodiments, or may be performed simultaneously.

Aspects of the present disclosure are described above with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, implement the functions/acts specified in the flowchart and/or block diagram block or blocks. Such a processor may be, but is not limited to, a general purpose processor, a special purpose processor, an application specific processor, or a field programmable logic circuit. It will also be understood that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware for performing the specified functions or acts, or combinations of special purpose hardware and computer instructions.

As described above, only the specific embodiments of the present application are provided, and it can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system, the module and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present application, and these modifications or substitutions should be covered within the scope of the present application.

Claims

1. A parasitic inductance measuring method is applied to a parasitic inductance test circuit, and the parasitic inductance test circuit comprises the following steps:

the direct-current bus comprises a bus capacitor, a first power switch device, a second power switch device and a load inductor, wherein the bus capacitor, the first power switch device and the second power switch device are sequentially connected in series through a direct-current bus; the bus capacitor is connected with a direct current voltage source in parallel, and the direct current voltage source outputs a first bus voltage;

the parasitic inductance measurement method comprises the following steps:

measuring a first current waveform of a switching-on transient process of the second power switch device under the first bus voltage by sending a double-pulse driving signal to the second power switch device, wherein under the action of the double-pulse driving signal, a working process of the second power switch device comprises the switching-on transient process;

adjusting a grid driving parameter of the second power switch device, wherein the switching-on speed of the second power switch device after adjustment is higher than the switching-on speed of the second power switch device before adjustment;

measuring a loop parasitic inductance in the parasitic inductance test circuit if the first current waveform and the second current waveform match;

wherein the first current waveform and the second current waveform match a characterization of: the time of the current linear rising process in the first current waveform and the second current waveform is larger than a preset threshold value.

2. The method of claim 1, wherein the measuring the loop parasitic inductance in the parasitic inductance test circuit comprises:

the first calculation formula is:

wherein,

is the rate of change of current, L, of the second power switch device _loop Is the parasitic inductance of the loop, U _DC Is the first bus voltage, V _S1 Is the conduction voltage drop, V, of the anti-parallel diode in the first power switch device _S2 Is the forward conduction voltage drop of the second power switch device.

3. The parasitic inductance measurement method according to claim 1, wherein said measuring a loop parasitic inductance in said parasitic inductance test circuit in a case where said first current waveform and said second current waveform match comprises:

measuring a loop parasitic inductance in the parasitic inductance test circuit if the first current linear transformation segment matches the second current linear transformation segment.

4. The method of claim 1, wherein after said measuring a second current waveform during a turn-on transient of said second power switch at said first bus voltage, said method further comprises:

when the first current waveform and the second current waveform are not matched, adjusting a target parameter, wherein the target parameter is as follows: the bus voltage output by the direct current voltage source; or, a gate drive parameter of the second power switch device;

measuring a third current waveform of the second power switch device in the switching-on transient process after the target parameter is adjusted by sending a double-pulse driving signal to the second power switch device;

5. The method of claim 4, wherein in the case that the target parameter is a bus voltage outputted by the DC voltage source, and in the case that the first current waveform and the second current waveform do not match, adjusting the target parameter comprises:

under the condition that the first current waveform and the second current waveform are not matched, the first bus voltage output by the direct-current voltage source is adjusted to be a second bus voltage;

the determining whether to measure the loop parasitic inductance in the parasitic inductance test circuit according to the third current waveform comprises:

adjusting a gate drive parameter of the second power switch device, wherein the adjusted turn-on speed of the second power switch device is higher than the turn-on speed of the second power switch device before adjustment;

measuring a fourth current waveform of the second power switch device in the switching transient process under the second bus voltage by sending a double-pulse driving signal to the second power switch device;

6. The parasitic inductance measuring method according to claim 5, wherein the adjusting the first bus voltage output by the dc voltage source to a second bus voltage when the first current waveform and the second current waveform do not match comprises:

and under the condition that the first current waveform and the second current waveform are not matched and the difference value between the switching-on speed of the second power switch device and the upper limit value of the switching-on speed of the second power switch device is smaller than a first threshold value, adjusting the first bus voltage output by the direct-current voltage source to be the second bus voltage.

7. The parasitic inductance measurement method according to claim 1, wherein in a case where the first current waveform and the second current waveform match, the method further comprises:

measuring a first voltage waveform at two ends of a branch to be tested in the parasitic inductance test circuit in a target time period, wherein the target time period is a time period corresponding to the turn-on transient process of the second power switch device under the first bus voltage; the branch to be tested does not comprise the bus capacitor;

determining a first voltage value of a first voltage segment in the first voltage waveform; the difference value between the voltage value corresponding to each moment in the first voltage segment and the first voltage value is smaller than a second threshold value; the time period corresponding to the first voltage segment is matched with the time period corresponding to the current rising segment in the target current waveform; the target current waveform is determined based on the first current waveform and/or the second current waveform;

the second calculation formula is:

wherein L is _DUT Is the parasitic inductance of the branch to be tested,

is the rate of change of current, U, of the second power switch device _DUT Is the first voltage value. />

8. The parasitic inductance measurement method according to claim 7, wherein in a case where the first current waveform and the second current waveform match, the method further comprises:

measuring a second voltage waveform of the bus capacitance in the parasitic inductance test circuit for the target time period;

the third calculation formula is:

wherein L is ₁ Is the parasitic inductance of the bus capacitance,

is the rate of change of current, U, of the second power switch device _C Is the second voltage value, U _DC Is the first bus voltage.

9. The method of any one of claims 1-8, wherein the dc voltage source outputs a bus voltage in a range between 10V and 50V.

10. A parasitic inductance measuring apparatus is applied to a parasitic inductance test circuit, and the parasitic inductance test circuit includes:

the parasitic inductance measuring apparatus includes:

the first measurement module is used for measuring a first current waveform of an on-transient process of the second power switch device under the first bus voltage by sending a double-pulse driving signal to the second power switch device, wherein under the action of the double-pulse driving signal, the working process of the second power switch device comprises the on-transient process;

the first adjusting module is used for adjusting the grid driving parameter of the second power switch device, wherein the adjusted switching-on speed of the second power switch device is higher than the switching-on speed of the second power switch device before adjustment;

the second measurement module is used for measuring a second current waveform in the on-transient state process of the second power switch device under the first bus voltage by sending a double-pulse driving signal to the second power switch device;

wherein the first current waveform and the second current waveform match characterizations: the time of the current linear rising process in the first current waveform and the second current waveform is larger than a preset threshold value.