CN115881690A - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises a semiconductor-on-insulator structure, a dielectric layer and a contact structure. The semiconductor-on-insulator structure comprises a bottom substrate, a buried insulating layer and a semiconductor layer. The buried insulating layer is disposed on the bottom substrate, and the semiconductor layer is disposed on the buried insulating layer. A dielectric layer is disposed on the semiconductor-on-insulator structure. The contact structure includes a first portion and a second portion. The first portion penetrates through the semiconductor layer and the embedded insulating layer in a vertical direction, and the second portion is disposed on and connected to the first portion. The second portion extends through the dielectric layer in a vertical direction, and a material composition of the first portion is different from a material composition of the second portion.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

The present invention relates to a semiconductor structure and a method for fabricating the same, and more particularly, to a semiconductor structure including a Semiconductor On Insulator (SOI) structure and a method for fabricating the same.

Background

The technology of semiconductor integrated circuits has grown over time, with products from each new generation having smaller and more complex circuit designs than the previous generation. The number and density of functional devices on each chip area must be continuously increased due to the demands of product innovation, which of course leads to smaller and smaller device geometries. For example, in integrated circuits, contact structures extending vertically through dielectric material layers may be used to electrically connect devices at different levels, and as the dimensions of the contact structures are required to be reduced or/and the contact structures must be designed to extend through more material layers, the aspect ratio (aspect ratio) of the openings corresponding to the contact structures may increase, thereby increasing the associated manufacturing process difficulties and affecting the manufacturing process yield.

Disclosure of Invention

The invention provides a semiconductor structure and a manufacturing method thereof, which form a contact structure by a two-stage mode and can integrate the manufacturing process of the contact structure with the manufacturing process of other parts in the semiconductor structure, thereby achieving the effects of improving the related manufacturing yield or/and simplifying the manufacturing process.

An embodiment of the present invention provides a semiconductor structure, which includes a Semiconductor On Insulator (SOI) structure, a dielectric layer, and a contact structure. The semiconductor-on-insulator structure comprises a bottom substrate, a buried insulating layer and a semiconductor layer. The buried insulating layer is disposed on the bottom substrate, and the semiconductor layer is disposed on the buried insulating layer. A dielectric layer is disposed on the semiconductor-on-insulator structure. The contact structure includes a first portion and a second portion. The first portion penetrates through the semiconductor layer and the embedded insulating layer in a vertical direction. The second portion is disposed on and connected to the first portion. The second portion penetrates the dielectric layer in a vertical direction, and a material composition of the first portion is different from a material composition of the second portion.

An embodiment of the present invention provides a method for fabricating a semiconductor structure, which includes the following steps. A Semiconductor On Insulator (SOI) structure is provided. The semiconductor-on-insulator structure includes a bottom substrate, a buried insulating layer and a semiconductor layer. The embedded insulating layer is disposed on the bottom substrate, and the semiconductor layer is disposed on the embedded insulating layer. A first portion of a contact structure is formed, and the first portion penetrates through the semiconductor layer and the embedded insulation layer in a vertical direction. A dielectric layer is formed on the semiconductor-on-insulator structure. A second portion of the contact structure is formed. The second portion is disposed on and connected to the first portion, penetrates the dielectric layer in a vertical direction, and has a material composition different from that of the second portion.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure according to a first embodiment of the present invention;

fig. 2 to 5 are schematic views illustrating a method for fabricating a semiconductor structure according to an embodiment of the invention, wherein

FIG. 3 is a view of the situation following FIG. 2;

FIG. 4 is a schematic view of the situation following FIG. 3;

FIG. 5 is a view of the situation following FIG. 4;

FIG. 6 is a schematic view of a semiconductor structure according to a second embodiment of the present invention;

fig. 7 is a schematic diagram of a semiconductor structure according to a third embodiment of the invention.

Description of the main elements

10. Semiconductor-on-insulator structure

12. Bottom substrate

14. High trapping layer

16. Embedded insulating layer

18. Semiconductor layer

18A body region

19. Masking layer

20. Masking layer

22. Conductive material

24. Isolation structure

24A first layer

24B second layer

26. Silicide layer

28. Silicide layer

30. Dielectric layer

42. Barrier layer

44. Conductive material

50. Interlayer dielectric layer

90. Planarization manufacturing process

101. Semiconductor structure

102. Semiconductor structure

103. Semiconductor structure

BC contact structure

CS1 connection structure

CS2 connection structure

First conductive structure of CT1

Second conductive structure of CT2

GS grid structure

LDD lightly doped region

OP1 opening

OP2 opening

OP3 opening

OP4 opening

P1 first part

P2 second part

S1 upper surface

S2 bottom surface

SD source/drain structure

SP spacer

TR transistor structure

TS1 Upper surface

TS2 Upper surface

In the Z vertical direction

Detailed Description

The following detailed description of the invention has disclosed sufficient detail to enable those skilled in the art to practice the invention. The embodiments set forth below should be considered as illustrative and not restrictive. It will be apparent to persons skilled in the relevant art that various changes and modifications in form and detail can be made therein without departing from the spirit and scope of the invention.

Before further description of the various embodiments, specific terminology used throughout the following description is set forth.

The meaning of the terms "on …", "above …" and "above …" should be read in the broadest manner such that "on …" means not only "directly on" something but also on something with other intervening features or layers in between, and "above …" or "above …" means not only "above" or "on" something, but may also include its meaning "above" or "on" something with no other intervening features or layers in between (i.e., directly on something).

Ordinal numbers such as "first," "second," and the like, used in the specification and the claims to modify a claim element are not by itself intended to imply any previous ordinal number with respect to the claim element, nor the order in which a claim element is ordered to another claim element or a method of manufacture, and are used solely to distinguish one claim element having a certain name from another claim element having a same name, unless otherwise specifically stated.

The term "etching" is used herein generally to describe a fabrication process used to pattern a material such that at least a portion of the material is left behind after the etching is completed. When a material is "etched," at least a portion of the material may be retained after the etching is complete. In contrast, when material is "removed," substantially all of the material may be removed in the process. However, in some embodiments, "removing" may be considered a broad term to include etching.

The term "forming" or "disposing" is used hereinafter to describe the act of applying a layer of material to a substrate. These terms are intended to describe any viable layer formation technique including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like.

Please refer to fig. 1. Fig. 1 is a schematic diagram of a semiconductor structure 101 according to a first embodiment of the invention. As shown in fig. 1, the semiconductor structure 101 includes a Semiconductor On Insulator (SOI) structure 10, a dielectric layer 30, and a contact structure BC. The semiconductor-on-insulator structure 10 includes a base substrate 12, a buried insulator layer 16, and a semiconductor layer 18. The buried insulating layer 16 is disposed on the bottom substrate 12, the semiconductor layer 18 is disposed on the buried insulating layer 16, and the buried insulating layer 16 is located between the semiconductor layer 18 and the bottom substrate 12 in a vertical direction Z. A dielectric layer 30 is disposed on the semiconductor-on-insulator structure 10. The contact structure BC includes a first portion P1 and a second portion P2. The first portion P1 penetrates the semiconductor layer 18 and the buried insulating layer 16 in the vertical direction Z, and the second portion P2 is disposed on the first portion P1 and connected to the first portion P1. The second portion P2 penetrates the dielectric layer 30 in the vertical direction Z, and the material composition of the first portion P1 is different from that of the second portion P2. The two-stage method is used to form the contact structure BC to avoid the influence of the excessive aspect ratio (aspect ratio) of the corresponding opening on the related manufacturing process conditions, so as to improve the yield of the related manufacturing process. In addition, the first portion P1 and the second portion P2 of the contact structure BC can be integrated with the manufacturing process of other components in the semiconductor structure 101, thereby achieving the effect of simplifying the manufacturing process.

In some embodiments, the vertical direction Z may be considered as a thickness direction of the semiconductor-on-insulator structure 10 or/and the base substrate 12, the base substrate 12 may have an upper surface S1 and a bottom surface S2 opposite to each other in the vertical direction Z, and the buried insulating layer 16, the semiconductor layer 18 and the contact structure BC may be disposed on one side of the upper surface S1. The horizontal direction substantially orthogonal to the vertical direction Z may be substantially parallel to the upper surface S1 or/and the bottom surface S2 of the bottom substrate 12, but is not limited thereto. Further, the position relatively higher in the vertical direction Z or/and the distance between the component and the bottom surface S2 of the bottom base 12 in the vertical direction Z described herein may be greater than the position relatively lower in the vertical direction Z or/and the distance between the component and the bottom surface S2 of the bottom base 12 in the vertical direction Z, the lower portion or the bottom portion of each component may be closer to the bottom surface S2 of the bottom base 12 in the vertical direction Z than the upper portion or the top portion of this component, another component above a certain component may be regarded as being relatively farther from the bottom surface S2 of the bottom base 12 in the vertical direction Z, and another component below a certain component may be regarded as being relatively closer to the bottom surface S2 of the bottom base 12 in the vertical direction Z, but not limited thereto.

In some embodiments, the first portion P1 of the contact structure BC may include a non-metal conductive material (e.g., doped polysilicon) or other suitable conductive material, and the second portion P2 of the contact structure BC may include a metal conductive material, such as a barrier layer 42 and a conductive material 44 disposed on the barrier layer 42, but not limited thereto. Barrier layer 42 may comprise titanium, titanium nitride, tantalum nitride, or other suitable barrier materials, and conductive material 44 may comprise a relatively low resistivity conductive material such as, but not limited to, copper, aluminum, tungsten, etc. In some embodiments, the base substrate 12 may comprise a silicon substrate or other suitable substrate, the buried insulator layer 16 may comprise an oxide insulator layer such as a Buried Oxide (BOX) or other suitable insulator material, and the semiconductor layer 18 may comprise a silicon-containing semiconductor layer (e.g., a single crystal silicon semiconductor layer) or other types of semiconductor materials.

In some embodiments, the semiconductor structure 101 may further include an isolation structure 24, a gate structure GS, a plurality of source/drain structures SD, and a plurality of lightly doped regions LDD. The isolation structure 24 may be disposed in the semiconductor layer 18 to define a bulk region 18A of the transistor structure TR in the semiconductor layer 18, and the isolation structure 24 may include a single layer or multiple layers of insulating materials, such as an oxide insulating material, a nitride insulating material, or an oxynitride insulating material, but is not limited thereto. For example, the isolation structure 24 may include a first layer 24A and a second layer 24B disposed on the first layer 24A, and a material composition (e.g., an oxide insulating material) of the first layer 24A may be different from a material composition (e.g., a nitride insulating material or an oxynitride insulating material) of the second layer 24B, but is not limited thereto. In some embodiments, the first portion P1 of the contact structure BC may penetrate the isolation structure 24 in the vertical direction Z, and at least a portion of the isolation structure 24 may be located between the first portion P1 of the contact structure BC and the semiconductor layer 18, thereby physically and electrically isolating the first portion P1 of the contact structure BC from the semiconductor layer 18. Furthermore, in some embodiments, the upper surface TS2 of the first portion P1 of the contact structure BC and the upper surface TS1 of the isolation structure 24 may be substantially coplanar, but not limited thereto.

In some embodiments, a portion of semiconductor layer 18 may be a body region 18A of transistor structure TR, gate structure GS may be disposed on semiconductor layer 18 (e.g., body region 18A), and source/drain structure SD and lightly doped region LDD may be disposed in semiconductor layer 18. The gate structure GS, the lightly doped region LDD, the source/drain structure SD, and the body region 18A may form a transistor structure TR, and the dielectric layer 30 may be disposed on the semiconductor-on-insulator structure 10 and cover the transistor structure TR (e.g., cover the gate structure GS and the source/drain structure SD). In some embodiments, the source/drain structure SD and the lightly doped region LDD may be doped regions doped with N-type dopants or P-type dopants, respectively, the gate structure GS may include a gate dielectric layer (not shown) and a gate electrode (not shown) disposed on the gate dielectric layer, the gate dielectric layer may include an oxide layer such as a silicon oxide layer or other suitable dielectric material, and the gate electrode may include a non-metal gate such as a polysilicon gate or other suitable conductive material. In addition, the dielectric layer 30 may include multiple layers of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) materials, or other suitable dielectric materials.

In some embodiments, the semiconductor structure 101 may further include a spacer SP, a first conductive structure CT1, a second conductive structure CT2, a silicide layer 26, and a silicide layer 28. Spacers SP may be disposed on sidewalls of the gate structure GS to assist in forming the lightly doped regions LDD or/and the source/drain structure SD during the manufacturing process, and the spacers SP may comprise a single layer or multiple layers of insulating materials such as silicon oxide, silicon nitride or other suitable insulating materials. The silicide layer 26 and the silicide layer 28 may be disposed on the source/drain structure SD and the gate structure GS, respectively, the first conductive structure CT1 may penetrate the dielectric layer 30 on the gate structure GS and be electrically connected to the gate structure GS through the silicide layer 28, and the second conductive structure CT2 may penetrate the dielectric layer 30 on the source/drain structure SD and be electrically connected to the source/drain structure SD through the silicide layer 26. Silicide layers 26 and 28 may each comprise cobalt-metal silicide (cobalt-silicide), nickel-metal silicide (nickel-silicide), or other suitable metal silicide. In some embodiments, the first conductive structure CT1, the second conductive structure CT2 and the second portion P2 of the contact structure BC may be formed by the same manufacturing process and/or material and have the same material composition, but not limited thereto.

Please refer to fig. 1 to 5. Fig. 2 to 5 are schematic diagrams illustrating a method for manufacturing a semiconductor structure according to an embodiment of the invention, wherein fig. 3 is a schematic diagram illustrating a situation after fig. 2, fig. 4 is a schematic diagram illustrating a situation after fig. 3, fig. 5 is a schematic diagram illustrating a situation after fig. 4, and fig. 1 can be regarded as a schematic diagram illustrating a situation after fig. 5, but is not limited thereto. As shown in fig. 1, the method of fabricating a semiconductor structure may include the following steps. First, a semiconductor-on-insulator structure 10 is provided, and the semiconductor-on-insulator structure 10 includes a bottom substrate 12, a buried insulating layer, and a semiconductor layer 18. A buried insulating layer 16 is disposed on the base substrate 12, and a semiconductor layer 18 is disposed on the buried insulating layer 16. Then, a first portion P1 of the contact structure BC is formed, and the first portion P1 penetrates the semiconductor layer 18 and the buried insulating layer 16 in the vertical direction Z. A dielectric layer 30 is formed on the semiconductor-on-insulator structure 10 and a second portion P2 of the contact structure BC is formed. The second portion P2 is disposed on the first portion P1 and connected to the first portion P1, the second portion P2 penetrates the dielectric layer 30 in the vertical direction Z, and the material composition of the first portion P1 is different from that of the second portion P2.

In further illustration, the method of fabricating the semiconductor structure may include, but is not limited to, the following steps. As shown in fig. 2, in some embodiments, a mask layer (e.g., the mask layer 19 and the mask layer 20 shown in fig. 2) may be formed on the soi structure 10 and the semiconductor layer 18 may be etched using the mask layer as an etching mask to form a trench corresponding to the isolation structure 24, and then the trench may be filled with an insulating material and a planarization process may be performed to form the isolation structure 24 in the semiconductor layer 18. The mask layer may include a single layer or multiple layers of mask materials, for example, the mask layer 19 may be an oxide insulating layer and the mask layer 20 may be a nitride insulating layer, but not limited thereto. After the isolation structure 24 is formed, an opening OP1 is formed to penetrate through the isolation structure 24 and the embedded insulation layer 16 in the vertical direction Z, and the opening OP1 may correspond to the first portion of the contact structure. As shown in fig. 2 and 3, after the opening OP1 is formed, a conductive material 22 may be formed, a portion of the conductive material 22 may be formed on the semiconductor layer 18, the mask layer 19, the mask layer 20 and the isolation structure 24, and another portion of the conductive material 22 may fill the opening OP 1. Then, as shown in fig. 3 and 4, a planarization process 90 may be performed to remove the conductive material 22 outside the opening OP1 to form a first portion P1 of the contact structure BC. The planarization process 90 may include a Chemical Mechanical Polishing (CMP) process or other suitable planarization method, and the conductive material 22 may include doped polysilicon or other suitable conductive material. In other words, the first portion P1 of the contact structure BC may be at least a portion of the conductive material 22 formed in the opening OP1, the first portion P1 of the contact structure BC may be formed after the isolation structure 24, and the first portion P1 of the contact structure BC may penetrate through the isolation structure 24 in the vertical direction Z.

As shown in fig. 4 and 5, in some embodiments, after the formation of the first portion P1 of the contact structure BC and before the formation of the transistor structure TR, another planarization process may be performed to remove at least part of the mask layer 20 and the mask layer 19, thereby exposing the semiconductor layer 18, and the upper surface TS2 of the first portion P1 of the contact structure BC may thus be substantially coplanar with the upper surface TS1 of the isolation structure 24, but not limited thereto. In some embodiments, since the first portion P1 of the contact structure BC is exposed to the planarization process, the material of the first portion P1 of the contact structure BC is preferably removed by the planarization process in a manner similar to the removal of the mask layer 20 and the mask layer 19 by the planarization process, thereby avoiding significant unevenness. Therefore, the first portion P1 of the contact structure BC may preferably comprise a non-metallic conductive material (e.g. doped polysilicon) or other conductive material having similar planarization characteristics as the mask layer 20 and the mask layer 19.

As shown in fig. 5 and fig. 1, after the first portion P1 of the contact structure BC is formed, the gate structure GS, the spacer SP, the lightly doped region LDD, the source/drain structure SD, the silicide layer 26, the silicide layer 28, the dielectric layer 30, the first conductive structure CT1, the second conductive structure CT2 and the second portion P2 of the contact structure BC may be formed. The gate structure GS may be formed on the semiconductor layer 18, the spacers SP may be formed on sidewalls of the gate structure GS, the lightly doped regions LDD and the source/drain structures SD may be at least partially formed in the semiconductor layer 18, the silicide layers 26 and 28 may be formed on the source/drain structures SD and the gate structure GS, respectively, and the dielectric layer 30 may cover the transistor structure TR, for example, the gate structure GS and the source/drain structures SD. The first conductive structure CT1 may penetrate the dielectric layer 30 on the gate structure GS to be electrically connected to the gate structure GS, and the second conductive structure CT2 may penetrate the dielectric layer 30 on the source/drain structure SD to be electrically connected to the source/drain structure SD.

In some embodiments, the second portion P2 of the contact structure BC may be formed together with the first conductive structure CT1 or/and the second conductive structure CT2 by the same manufacturing process and have the same material composition, so as to achieve the effect of simplifying the manufacturing process, but not limited thereto. For example, the second portion P2 of the contact structure BC, the first conductive structure CT1 and the second conductive structure CT2 may be formed by forming the opening OP2, the opening OP3 and the opening OP4 in the dielectric layer 30, and then forming the conductive materials, such as the barrier layer 42 and the conductive material 44, in the opening OP2, the opening OP3 and the opening OP4, so as to form the second portion P2 of the contact structure BC, the first conductive structure CT1 and the second conductive structure CT2. In some embodiments, the dielectric layer 30 may be formed after forming the first portion P1 of the contact structure BC, and the second portion P2 of the contact structure BC may be formed after forming the dielectric layer 30, so that the first portion P1 and the second portion P2 of the contact structure BC may be formed by different manufacturing processes. Therefore, the manufacturing method of the present invention can form the contact structure BC in a two-stage manner, thereby avoiding forming a contact structure with an excessive aspect ratio (aspect ratio), and relatively reducing the Critical Dimension (CD) of the contact structure BC. Furthermore, the manufacturing process of the contact structure BC may be integrated with the manufacturing process of other components in the semiconductor structure (e.g. the transistor structure TR or/and the conductive structure corresponding to the transistor structure TR), thereby improving the manufacturing yield and/or simplifying the manufacturing process. For example, the related process problems caused by the high aspect ratio of the opening corresponding to the single contact structure, such as the difficulty in controlling the etching stop, the difficulty in removing the etching residue due to the complicated etching material layer and/or the relatively long etching time, and the undesirable gap-filling effect due to the high aspect ratio, can be avoided or/and improved.

The following description mainly details the differences between the embodiments, and the descriptions of the same parts are not repeated herein for the sake of simplicity. In addition, the same elements in the embodiments of the present invention are denoted by the same reference numerals to facilitate the comparison between the embodiments.

Please refer to fig. 6. FIG. 6 is a schematic diagram of a semiconductor structure 102 according to a second embodiment of the invention. As shown in fig. 6, the semiconductor structure 102 may further include a connection structure CS1, a connection structure CS2 and an interlayer dielectric layer 50. The connection structure CS1 may be disposed on the dielectric layer 30 and electrically connected to the second portion P2 of the contact structure BC, the first conductive structure CT1 or/and the second conductive structure CT2, and the interlayer dielectric layer 50 may be disposed on the dielectric layer 30 and cover the connection structure CS1. The connection structure CS2 may be disposed under the first portion P1 of the contact structure BC in the vertical direction Z and penetrate the base substrate 12, and the connection structure CS2 and the first portion P1 of the contact structure BC may be connected to each other to form an electrical connection. In some embodiments, the connection structure CS2 and the contact structure BC may be considered as a backside connection structure, and other external elements may be electrically connected to the transistor structure TR through the connection structure CS2, the contact structure BC, the connection structure CS1, the first conductive structure CT1 or/and the second conductive structure CT2, but not limited thereto. In some embodiments, the interlayer dielectric layer 50 may include a single layer or multiple layers of dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, low-k material or other suitable dielectric materials, and the connection structures CS1 and CS2 may respectively include a metal conductive material such as a barrier layer (not shown) and a conductive material (not shown) disposed on the barrier layer, but not limited thereto. In addition, in some embodiments, the connection structure CS2 may be formed after the connection structure CS1 and the interlayer dielectric layer 50, and the bottom substrate 10 may be thinned from the bottom surface S2 of the bottom substrate 10 before the connection structure CS2 is formed, so as to reduce the thickness of the bottom substrate 10, but not limited thereto.

Please refer to fig. 7. Fig. 7 is a schematic diagram of a semiconductor structure 103 according to a third embodiment of the invention. As shown in fig. 7, in some embodiments, the semiconductor-on-insulator structure 10 may further include a high trapping (trap rich) layer 14 disposed between the buried insulating layer 16 and the bottom substrate 12, and the first portion P1 of the contact structure BC may directly contact the high trapping layer 14, but is not limited thereto. In some embodiments, the semiconductor-on-insulator structure 10 with the high trapping layer 14 may be used to form a Radio Frequency (RF) device (for example, the transistor structure TR may be a radio frequency switching device, but not limited thereto), and the high trapping layer 14 may be used to trap electrons scattered in the device under high frequency use, thereby improving the performance of the radio frequency device. Therefore, the material composition of the high-trapping layer 14 is different from the material composition of the bottom substrate 12 and the material composition of the buried insulating layer 16 in the semiconductor-on-insulator structure 10, and the trapping capability of the high-trapping layer 14 for electrons is higher than that of the bottom substrate 12 and the buried insulating layer 16. In some embodiments, the high-trapping layer 14 may comprise polysilicon, such as undoped polysilicon or other materials having a relatively high ability to trap electrons. In addition, the high trapping layer 14 of the present embodiment can also be applied to other embodiments of the present invention as design needs dictate.

In summary, in the semiconductor structure and the method for fabricating the same of the present invention, the contact structure can be formed in a two-stage manner, thereby avoiding the formation of the contact structure with an excessively high aspect ratio, and the fabrication process of the contact structure can be integrated with the fabrication process of other components in the semiconductor structure, so as to achieve the effects of increasing the related fabrication yield or/and simplifying the fabrication process.

The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in the claims of the present invention should be covered by the present invention.

Claims (20)

1. A semiconductor structure, comprising:

a Semiconductor On Insulator (SOI) structure comprising:

a bottom substrate;

a buried insulating layer disposed on the bottom substrate; and

a semiconductor layer disposed on the buried insulating layer;

a dielectric layer disposed on the semiconductor-on-insulator structure; and

a contact structure, comprising:

a first portion penetrating the semiconductor layer and the buried insulating layer in a vertical direction; and

and a second portion disposed on and connected to the first portion, wherein the second portion penetrates the dielectric layer in the vertical direction, and a material composition of the first portion is different from a material composition of the second portion.

2. The semiconductor structure of claim 1, further comprising:

an isolation structure disposed in the semiconductor layer, wherein the first portion of the contact structure penetrates the isolation structure in the vertical direction.

3. The semiconductor structure of claim 2, wherein an upper surface of said first portion of said contact structure is coplanar with an upper surface of said isolation structure.

4. The semiconductor structure of claim 1, wherein said first portion of said contact structure comprises a non-metallic conductive material.

5. The semiconductor structure of claim 1, wherein said first portion of said contact structure comprises doped polysilicon.

6. The semiconductor structure of claim 1, further comprising:

a gate structure disposed on the semiconductor layer, wherein the dielectric layer covers the gate structure; and

a first conductive structure extending through the dielectric layer on the gate structure and electrically connected to the gate structure, wherein a material composition of the first conductive structure is the same as the material composition of the second portion of the contact structure.

7. The semiconductor structure of claim 1, further comprising:

a source/drain structure at least partially disposed in the semiconductor layer, wherein the dielectric layer covers the source/drain structure; and

a second conductive structure extending through the dielectric layer over the source/drain structure and electrically connected to the source/drain structure, wherein a material composition of the second conductive structure is the same as the material composition of the second portion of the contact structure.

8. The semiconductor structure of claim 1, wherein said semiconductor-on-insulator structure further comprises a high trapping (trap rich) layer disposed between said buried insulating layer and said bottom substrate.

9. The semiconductor structure of claim 8, wherein said first portion of said contact structure contacts said high-trapping layer.

10. The semiconductor structure of claim 1, further comprising:

a connection structure disposed below the first portion of the contact structure in the vertical direction and penetrating the bottom substrate, wherein the connection structure is electrically connected with the first portion of the contact structure.

11. A method for fabricating a semiconductor structure, comprising:

providing a semiconductor-on-insulator (SOI) structure, the SOI structure comprising:

a bottom substrate;

a buried insulating layer disposed on the bottom substrate; and

a semiconductor layer disposed on the buried insulating layer;

forming a first portion of a contact structure, wherein the first portion penetrates through the semiconductor layer and the buried insulating layer in a vertical direction;

forming a dielectric layer on the semiconductor-on-insulator structure; and

forming a second portion of the contact structure, wherein the second portion is disposed on and connected to the first portion, the second portion penetrates the dielectric layer in the vertical direction, and a material composition of the first portion is different from a material composition of the second portion.

12. The method of claim 11, wherein the first portion and the second portion of the contact structure are formed by different processes.

13. The method of claim 11, wherein the dielectric layer is formed after the first portion of the contact structure is formed, and the second portion of the contact structure is formed after the dielectric layer is formed.

14. The method of fabricating a semiconductor structure according to claim 11, further comprising:

an isolation structure is formed in the semiconductor layer, wherein the first portion of the contact structure is formed after the isolation structure and the first portion of the contact structure penetrates the isolation structure in the vertical direction.

15. The method of claim 14, wherein forming the first portion of the contact structure comprises:

forming an opening penetrating the isolation structure and the embedded insulation layer in the vertical direction;

forming a conductive material, wherein a portion of the conductive material is formed on the semiconductor layer and another portion of the conductive material fills the opening; and

a planarization process is performed to remove the conductive material outside the opening to form the first portion of the contact structure.

16. The method of claim 15, wherein an upper surface of the first portion of the contact structure is coplanar with an upper surface of the isolation structure.

17. The method of claim 15, wherein said conductive material comprises doped polysilicon.

18. The method of fabricating a semiconductor structure according to claim 11, further comprising:

forming a gate structure on the semiconductor layer, wherein the dielectric layer covers the gate structure; and

forming a first conductive structure through the dielectric layer on the gate structure to electrically connect with the gate structure, wherein the first conductive structure and the second portion of the contact structure are formed together by the same process.

19. The method of fabricating a semiconductor structure according to claim 11, further comprising:

forming a source/drain structure at least partially formed in the semiconductor layer, wherein the dielectric layer covers the source/drain structure; and

forming a second conductive structure through the dielectric layer on the source/drain structure to electrically connect to the source/drain structure, wherein the second conductive structure and the second portion of the contact structure are formed together by the same process.

20. The method of claim 11, wherein the semiconductor-on-insulator structure further comprises a high-trapping (trap rich) layer disposed between the buried insulating layer and the bottom substrate, and the first portion of the contact structure contacts the high-trapping layer.

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