CN115881523A - Groove type grid and manufacturing method thereof - Google Patents
Groove type grid and manufacturing method thereof Download PDFInfo
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- CN115881523A CN115881523A CN202310076932.3A CN202310076932A CN115881523A CN 115881523 A CN115881523 A CN 115881523A CN 202310076932 A CN202310076932 A CN 202310076932A CN 115881523 A CN115881523 A CN 115881523A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 83
- 238000000034 method Methods 0.000 claims abstract description 48
- 239000000463 material Substances 0.000 claims description 57
- 238000005530 etching Methods 0.000 claims description 10
- 238000005468 ion implantation Methods 0.000 claims description 8
- 238000004140 cleaning Methods 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000009279 wet oxidation reaction Methods 0.000 claims description 3
- 239000007772 electrode material Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention provides a trench type grid and a manufacturing method thereof, wherein the method comprises the following steps: providing a substrate, and forming a grid electrode on the substrate; forming a first gate oxide layer on the top and the side wall of the gate; and forming an epitaxial layer which is positioned on the substrate at two sides of the grid electrode. According to the invention, the grid electrode is formed firstly, and then the epitaxial layer is formed, so that the side wall and the bottom of the grid electrode are surrounded by the epitaxial layer and the substrate, and the groove type grid electrode is formed.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a trench type grid and a manufacturing method thereof.
Background
Power devices typically include planar gate devices and trench gate devices. The groove type grid of the groove grid device is formed by etching a substrate or an epitaxial layer to form a groove, and polycrystalline silicon is filled in the groove to form a grid, so that the grid is positioned in the substrate. The trench gate device has a low switching loss and a high switching speed due to its high concentration, low on-resistance, low gate-drain charge density and large current capacity, and is widely used in the field of low-voltage power.
However, as the integration density of integrated circuits increases, the Aspect ratio (Aspect ratio) of the trench increases, and voids are easily formed in the trench when the trench is filled with polysilicon, thereby affecting the performance of the device.
Fig. 1 is a schematic structural diagram of a trench gate in the prior art, and as shown in fig. 1, a trench 11 is formed in a substrate 10, a gate oxide layer 12 is formed on the sidewall and the bottom of the trench 11, and a polysilicon gate 13 is filled in the trench 11. However, due to the increase of the aspect ratio of the trench 11, voids are easily generated when filling the polysilicon, so that the voids 14 are formed in the gate 13, thereby affecting the performance of the device.
Disclosure of Invention
The invention aims to provide a trench type grid and a manufacturing method thereof, which do not need to form a trench, thereby avoiding filling polycrystalline silicon in the trench, avoiding the generation of pores in the trench type grid and improving the performance of a device.
In order to solve the above technical problem, the present invention provides a method for manufacturing a trench gate, including the following steps: providing a substrate, and forming a grid electrode on the substrate;
forming a first gate oxide layer on the top and the side wall of the gate; and the number of the first and second groups,
and forming an epitaxial layer which is positioned on the substrate at two sides of the grid electrode.
Optionally, the manufacturing method further includes: and forming a second gate oxide layer on the substrate, wherein the second gate oxide layer is positioned between the gate and the substrate.
Optionally, the step of forming the second gate oxide layer and the gate electrode includes:
sequentially forming a gate oxide material layer and a gate material layer on the substrate;
forming a patterned mask layer on the grid material layer;
etching the grid electrode material layer and the grid oxide material layer in sequence by taking the patterned mask layer as a mask until the substrate is exposed to form the grid electrode and the second grid oxide layer; and the number of the first and second groups,
and removing the patterned mask layer.
Optionally, the method for forming the first gate oxide layer includes: wet oxidation, dry oxidation or chemical vapor deposition.
Optionally, after forming the first gate oxide layer and before forming the epitaxial layer, the manufacturing method further includes: and (3) pretreating and passivating the surface of the substrate by using an RCA standard cleaning method.
Optionally, the method for forming an epitaxial layer on the substrate on both sides of the gate includes:
forming an epitaxial material layer covering the substrate and the grid; and the number of the first and second groups,
and removing part of the epitaxial material layer until the first gate oxide layer is exposed, and taking the residual epitaxial material layer as an epitaxial layer to surround the side wall of the gate.
Optionally, forming the epitaxial material layer by an epitaxial growth method; and removing part of the epitaxial material layer through a planarization process or an etching process.
Optionally, before forming the gate, the manufacturing method further includes: and carrying out ion implantation on the substrate, and forming a drain region on one surface of the substrate, which is far away from the grid electrode.
Optionally, after the epitaxial layer is formed, the manufacturing method further includes: and carrying out ion implantation on the epitaxial layer to form a source region.
Correspondingly, the invention also provides a trench type grid which is manufactured by adopting the manufacturing method of the trench type grid.
The invention provides a groove type grid and a manufacturing method thereof, wherein a grid is formed on a substrate at first, then a first grid oxide layer is formed on the top and the side wall of the grid, and then an epitaxial layer is formed on the substrate at the two sides of the grid, so that the side wall and the bottom of the grid are surrounded by the epitaxial layer and the substrate, thereby forming the groove type grid.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention.
Fig. 1 is a schematic diagram of a trench gate in the prior art.
Fig. 2 is a flowchart of a method for manufacturing a trench gate according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram after forming a gate according to an embodiment of the invention.
Fig. 4 is a schematic structural diagram after a first gate oxide layer is formed according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram after an epitaxial material layer is formed according to an embodiment of the invention.
Fig. 6 is a schematic structural diagram after an epitaxial layer is formed according to an embodiment of the invention.
Reference numerals:
in fig. 1: 10-a substrate; 11-a trench; 12-a gate oxide layer; 13-a gate; 14-pores.
In fig. 3-6, 100 — substrate; 110-a second gate oxide layer; 120-gate; 130-a first gate oxide layer; 140-a layer of epitaxial material; 150-epitaxial layer.
Detailed Description
To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in simplified form and are not to scale, but are provided for the purpose of facilitating and clearly illustrating embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
As used in this application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a" and "an" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, features defined as "first," "second," and "third" may explicitly or implicitly include one or at least two of the features unless the content clearly dictates otherwise.
Fig. 2 is a flowchart of a method for manufacturing a trench gate according to an embodiment of the invention.
As shown in fig. 2, the method for manufacturing the trench gate includes the following steps:
s1: providing a substrate, and forming a grid electrode on the substrate;
s2: forming a first gate oxide layer on the top and the side wall of the gate;
s3: and forming an epitaxial layer which is positioned on the substrate at two sides of the grid electrode.
According to the manufacturing method of the groove type grid electrode, the grid electrode is formed on the substrate firstly, then the first grid oxide layer is formed on the top and the side wall of the grid electrode, then the epitaxial layer is formed on the substrate on the two sides of the grid electrode, the side wall and the bottom of the grid electrode are surrounded by the epitaxial layer and the substrate, and therefore the groove type grid electrode is formed.
Fig. 3 is a schematic structural diagram after a gate is formed according to an embodiment of the present invention, fig. 4 is a schematic structural diagram after a first gate oxide layer is formed according to an embodiment of the present invention, fig. 5 is a schematic structural diagram after an epitaxial material layer is formed according to an embodiment of the present invention, and fig. 6 is a schematic structural diagram after an epitaxial layer is formed according to an embodiment of the present invention. Next, a method for manufacturing a trench gate according to an embodiment of the present invention will be described in detail with reference to fig. 2 and fig. 3 to 6.
In step S1, referring to fig. 2, a substrate 100 is provided, and a gate 120 is formed on the substrate 100.
The substrate 100 may be made of silicon, germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or the like, or may be made of silicon on insulator or germanium on insulator; or may be other materials such as group III-V compounds such as gallium arsenide. In the present embodiment, the material of the substrate 100 is silicon, and is preferably monocrystalline silicon.
A second gate oxide layer 110 is also formed on the substrate 100, the second gate oxide layer 110 is located between the substrate 100 and the gate 120, and the size of the second gate oxide layer 110 is consistent with that of the gate 120. The material of the second gate oxide layer 110 includes silicon oxide, and the material of the gate electrode 120 includes polysilicon, but is not limited thereto.
Specifically, first, a gate oxide layer (not shown) and a gate material layer (not shown) are sequentially formed on the substrate 100; then, forming a mask layer (not shown) on the gate material layer, where the mask layer may be made of silicon nitride, for example, forming a photoresist layer on the mask layer, exposing and developing the photoresist layer to form a patterned photoresist layer, and etching the mask layer with the patterned photoresist layer as a mask to form a patterned mask layer; sequentially etching the gate material layer and the gate oxide material layer by taking the patterned mask layer as a mask until the substrate 100 is exposed to form a second gate oxide layer 110 and a gate 120; and finally, removing the patterned photoresist layer and the patterned mask layer, wherein the patterned photoresist layer can be directly removed after the patterned mask layer is formed.
In this embodiment, the gate oxide layer and the gate material layer are sequentially formed and then etched to form the gate electrode 120 and the second gate oxide layer 110. In other embodiments, the gate oxide material layer may be formed and then directly etched to form the second gate oxide layer 110, and then a gate material layer is formed, where the gate material layer covers the second gate oxide layer 110 and the substrate 100, and then the gate material layer is etched to form the gate 120 on the second gate oxide layer 110, which is not limited in this disclosure.
In this embodiment, the gate oxide material layer may be formed by a thermal oxidation method, the gate material layer may be formed by a chemical vapor deposition method, and of course, the gate oxide material layer and the gate material layer may also be formed by other methods known to those skilled in the art. The gate material layer and the gate oxide material layer may be etched by an isotropic method, for example, plasma chemical etching, or may be etched by an anisotropic method, for example, plasma physical etching, which is not limited in the present invention.
In this embodiment, a plurality of gate electrodes 120 may be formed as required, and fig. 3 illustrates two gate electrodes 120 as an example, and a second gate oxide layer 110 is formed between each gate electrode 120 and the substrate 100.
In step S2, referring to fig. 4, a first gate oxide layer 130 is formed on the top and sidewalls of the gate 120.
Specifically, first, the first gate oxide layer 130 may be formed by a wet oxidation method, a dry oxidation method or a chemical vapor deposition method, where the first gate oxide layer 130 covers the substrate 100 and the top and the sidewall of the gate 120, and then, the first gate oxide layer 130 on the substrate 100 is removed, and the first gate oxide layer 130 on the top and the sidewall of the gate 120 is remained, so as to form the structure shown in fig. 4.
The material of the first gate oxide layer 130 is preferably silicon oxide. The first gate oxide layer 130 is used for protecting the gate electrode 120, and is used as an isolation window between the substrate 100 and the gate electrode 120 when the epitaxial material layer 140 is subsequently epitaxially grown, and simultaneously, the first gate oxide layer 130 and the second gate oxide layer 110 are used as gate oxide layers of subsequent trench type gate electrodes.
In step S3, please refer to fig. 6, an epitaxial layer 150 is formed, wherein the epitaxial layer 150 is located on the substrate 100 at two sides of the gate 120.
First, the surface of the substrate 100 is pretreated and passivated by RCA standard cleaning. RCA is a commonly used wet chemical cleaning method, which was proposed in 1965 by Kern and Puotinen et al, princeton RCA laboratories, N.J.. The RCA standard cleaning method generally removes organic contaminants on the surface of the substrate 100 first, then dissolves an oxide film, and finally removes contaminants of particles, metals, etc., while passivating the surface of the substrate 100.
Then, referring to fig. 5, an epitaxial material layer 140 is formed, wherein the epitaxial material layer 140 covers the substrate 100 and the gate 120. Illustratively, the Epitaxial material layer 140 may be formed by an Epitaxial Growth method (Epitaxial Growth), the Epitaxial material layer 140 on the substrate 100 is monocrystalline silicon, and the Epitaxial material layer 140 on the top of the gate 120 formed due to the different crystal orientations is polycrystalline silicon. Then, part of the epitaxial material layer 140 is removed until the first gate oxide layer 130 is exposed, and the remaining epitaxial material layer 140 serves as an epitaxial layer 150, so as to form the structure shown in fig. 6. The epitaxial material layer 140 on the top of the gate 120 is removed, the epitaxial layer 150 is formed on the substrate 100 by an epitaxial growth method, the epitaxial layer 150 and the substrate 100 are made of the same material, and are preferably made of monocrystalline silicon, and the sidewall and the bottom of the gate 120 are surrounded by the epitaxial layer 150 and the substrate 100, thereby forming a trench gate.
A planarization process may be used to remove a portion of the epitaxial material layer 140, for example, by performing a chemical mechanical polishing on the epitaxial material layer 140 until the first gate oxide layer 130 is exposed. Alternatively, an etching process may be used to remove a portion of the epitaxial material layer 140 until the first gate oxide layer 130 is exposed, which is not limited in the present invention.
In the method for manufacturing the trench gate provided by the invention, the gate 120 is formed on the substrate 100 at first, then the first gate oxide layer 130 is formed on the top and the side wall of the gate 120, and then the epitaxial layer 150 is formed on the substrate 100 at two sides of the gate 120, so that the side wall and the bottom of the gate 120 are surrounded by the epitaxial layer 150 and the substrate 100, thereby forming the trench gate.
In this embodiment, before forming the gate 120 on the substrate 100, the manufacturing method further includes: the substrate 100 is ion implanted to form a drain region (not shown) on a side of the substrate 100 away from the gate electrode 120. Taking the surface of the substrate 100 on which the gate electrode 120 is formed as a front surface and the opposite surface as a back surface, first performing ion implantation on the back surface of the substrate 100 to form a drain region, and then forming the second gate oxide layer 110 and the gate electrode 120 on the front surface of the substrate 100, of course, after forming the drain region, before forming the second gate oxide layer 110, or before forming the drain region, ion implantation may also be performed on the front surface or the back surface of the substrate 100, so that the substrate 100 is an N-type substrate, for example, an N + substrate. After the epitaxial layer 150 is formed, ion implantation may be performed on the epitaxial layer 150 to form source regions on both sides of the gate 120.
Different reaction gases may be introduced during the process of forming the epitaxial material layer 140 so that the epitaxial material layer 140 itself has specific P or N type conductor characteristics. Or after the epitaxial layer 150 is finally formed, ion implantation is performed on the epitaxial layer 150, so that the epitaxial layer 150 is a P-type epitaxial layer or an N-type epitaxial layer. For example, in this embodiment, the bottom of the epitaxial layer 150 (i.e., the region surrounding the bottom and the bottom of the sidewall of the gate 120) is an N-type epitaxial layer, a P-well region is formed in the middle of the epitaxial layer 150 (i.e., the region surrounding the middle of the sidewall of the gate 120), and then a source region (i.e., the region surrounding the top of the sidewall of the gate 120) is formed on the P-well region.
Correspondingly, the invention also provides a trench type grid which is manufactured by adopting the manufacturing method of the trench type grid. Referring to fig. 6, the trench gate includes:
a substrate 100;
an epitaxial layer 150 on the substrate 100;
a trench in the epitaxial layer 150, the trench exposing the substrate 100;
a second gate oxide layer 110 located at the bottom of the trench;
a first gate oxide layer 130 on the sidewall and the top of the trench;
and the gate 120 is positioned in the groove and is surrounded by the first gate oxide layer 130 and the second gate oxide layer 110.
As can be seen from fig. 6, a trench is formed in the epitaxial layer 150, and the gate 120 is located in the trench to form a trench gate, that is, the structure of the trench gate manufactured by the method for manufacturing a trench gate according to the present invention is the same as the structure of the trench gate manufactured by the method for forming a trench by etching an epitaxial layer first and then forming a gate in the trench in the prior art. However, in the method for manufacturing the trench gate according to the present invention, the gate 120 is formed first, and then the epitaxial layer 150 surrounding the sidewall of the gate 120 is formed, and the trench is not required to be formed and then filled.
In summary, in the trench gate and the method for manufacturing the same provided by the present invention, the gate is formed on the substrate, the first gate oxide layer is formed on the top and the side wall of the gate, and then the epitaxial layer is formed on the substrate on both sides of the gate, so that the side wall and the bottom of the gate are surrounded by the epitaxial layer and the substrate, thereby forming the trench gate.
The above description is only for the purpose of describing the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are intended to fall within the scope of the appended claims.
Claims (10)
1. A method for manufacturing a trench gate is characterized by comprising the following steps:
providing a substrate, and forming a grid electrode on the substrate;
forming a first gate oxide layer on the top and the side wall of the gate; and the number of the first and second groups,
and forming an epitaxial layer which is positioned on the substrate at two sides of the grid electrode.
2. The method of claim 1, further comprising: and forming a second gate oxide layer on the substrate, wherein the second gate oxide layer is positioned between the gate and the substrate.
3. The method of claim 2 wherein the step of forming the second gate oxide layer and the gate comprises:
sequentially forming a gate oxide material layer and a gate material layer on the substrate;
forming a patterned mask layer on the gate material layer;
etching the grid electrode material layer and the grid oxide material layer in sequence by taking the patterned mask layer as a mask until the substrate is exposed to form the grid electrode and the second grid oxide layer; and the number of the first and second groups,
and removing the patterned mask layer.
4. The method of claim 1 wherein forming the first gate oxide layer comprises: wet oxidation, dry oxidation or chemical vapor deposition.
5. The method of forming a trench gate of claim 1 wherein after forming said first gate oxide layer and before forming said epitaxial layer, said method further comprises: and (3) pretreating and passivating the surface of the substrate by using an RCA standard cleaning method.
6. The method of claim 1, wherein forming an epitaxial layer on the substrate on both sides of the gate comprises:
forming an epitaxial material layer, wherein the epitaxial material layer covers the substrate and the grid; and (c) a second step of,
and removing part of the epitaxial material layer until the first gate oxide layer is exposed, and taking the residual epitaxial material layer as an epitaxial layer to surround the side wall of the gate.
7. The method of claim 6, wherein the epitaxial material layer is formed by epitaxial growth; and removing part of the epitaxial material layer through a planarization process or an etching process.
8. The method of claim 1, wherein prior to forming the gate, the method further comprises: and carrying out ion implantation on the substrate, and forming a drain region on one surface of the substrate, which is far away from the grid electrode.
9. The method of claim 1, wherein after forming the epitaxial layer, the method further comprises: and carrying out ion implantation on the epitaxial layer to form a source region.
10. A trench gate formed by the method of claim 1~9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310076932.3A CN115881523A (en) | 2023-02-08 | 2023-02-08 | Groove type grid and manufacturing method thereof |
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| CN202310076932.3A CN115881523A (en) | 2023-02-08 | 2023-02-08 | Groove type grid and manufacturing method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103035500A (en) * | 2012-06-04 | 2013-04-10 | 上海华虹Nec电子有限公司 | Formation method of trench gate |
| US20140335663A1 (en) * | 2013-02-11 | 2014-11-13 | Commissariat A L'energie Atomique Et Aux Ene Alt | Method of making a transitor |
| CN104253151A (en) * | 2013-06-27 | 2014-12-31 | 无锡华润上华半导体有限公司 | Field stop type reverse conducting insulated gate bipolar transistor and manufacturing method thereof |
| CN112951715A (en) * | 2019-12-10 | 2021-06-11 | 芯恩（青岛）集成电路有限公司 | Groove gate structure and preparation method of groove type field effect transistor structure |
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- 2023-02-08 CN CN202310076932.3A patent/CN115881523A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103035500A (en) * | 2012-06-04 | 2013-04-10 | 上海华虹Nec电子有限公司 | Formation method of trench gate |
| US20140335663A1 (en) * | 2013-02-11 | 2014-11-13 | Commissariat A L'energie Atomique Et Aux Ene Alt | Method of making a transitor |
| CN104253151A (en) * | 2013-06-27 | 2014-12-31 | 无锡华润上华半导体有限公司 | Field stop type reverse conducting insulated gate bipolar transistor and manufacturing method thereof |
| CN112951715A (en) * | 2019-12-10 | 2021-06-11 | 芯恩（青岛）集成电路有限公司 | Groove gate structure and preparation method of groove type field effect transistor structure |
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Application publication date: 20230331 |