CN115881018A - Decoding circuit, source driving circuit and equipment - Google Patents

Abstract

The decoding circuit comprises a pre-decoder and a decoding array, wherein the pre-decoder is used for pre-decoding a first data signal, determining a gamma voltage to be output, and outputting a second data signal and a third data signal corresponding to the gamma voltage to be output, at least a first switch in the decoding array can be conducted under the control of the second data signal, and a second switch is conducted under the control of the third data signal, so that the gamma voltage to be output is output. Therefore, the decoding circuit can output one gamma voltage only by two switches at most, and a plurality of gamma voltages can also share one second switch, so that the number of switches in the decoding circuit is small, and the size and the power consumption of the decoding circuit are small.

Description

Decoding circuit, source driving circuit and equipment

technical field

The present disclosure relates to the field of display technology, in particular to a decoder, a source driving circuit and equipment.

Background technique

The source driving circuit can generate and output a corresponding driving voltage to drive the display panel to display according to the image data to be displayed. As the display resolution increases, the source drive circuit needs to analyze the more digits of the digital signal, and the decoding circuit used in the source drive circuit to decode the digital signal output by the logic circuit (TCON) into the corresponding gamma voltage The number of transistors in the circuit will also increase, especially for a full-type decoding circuit, the number of transistors that needs to be increased is very large for each additional bit of data signal.

Contents of the invention

The disclosure proposes a decoding circuit, a source driving circuit and equipment. The specific plan is as follows:

An embodiment of the present disclosure proposes a decoding circuit, including: sequentially connected pre-decoders and decoding arrays;

Wherein, the pre-decoder is configured to pre-decode the n-bit first data signal to be decoded to determine the gamma voltage to be output, and output the n-bit second data signal corresponding to the gamma voltage and n A third data signal, n is an integer greater than 1;

The decoding array includes a plurality of first switch groups and a plurality of second switches respectively connected to a plurality of gamma voltages, each of the first switch groups includes a plurality of first switches, and each of the first One end of the switch is connected to a gamma voltage, the other ends of the plurality of first switches in each of the first switch groups are respectively connected to one end of a second switch, and the other ends of the plurality of second switches are connected to each other The decoding array is used to decode the second data signal and the third data signal respectively, so as to control at least one first switch and one second switch to be turned on, and output the gamma voltage to be output.

Another embodiment of the present disclosure proposes a source driving circuit, including a sequentially connected gamma voltage generating circuit, a decoding circuit and an amplifier as described above;

Wherein, the gamma voltage generating circuit is used to generate the gamma voltage, and the amplifier is used to amplify the gamma voltage output by the decoding circuit.

Another embodiment of the present disclosure provides a display driver integrated circuit DDIC, including the source driver circuit as described in the above aspect.

Another embodiment of the present disclosure provides a device, including the above-mentioned source driving circuit and a display panel.

In the decoding circuit, source driving circuit and equipment of the embodiments of the present disclosure, the decoding circuit includes a pre-decoder and a decoding array. First, the pre-decoder is used to pre-decode the first data signal, determine the gamma voltage to be output, and output The second data signal and the third data signal corresponding to the gamma voltage to be output, and then at least the first switch in the decoding array can be turned on under the control of the second data signal, and a second switch can be turned on under the control of the third data signal is turned on under the control of to output the gamma voltage to be output. Therefore, the decoding circuit only needs two switches at most to output a gamma voltage, and multiple gamma voltages can also share a second switch, the number of switches in the decoding circuit is small, and the size and power consumption of the decoding circuit Small.

Additional aspects and advantages of the disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the disclosure.

Description of drawings

The above and/or additional aspects and advantages of the present disclosure will become apparent and understandable from the following description of the embodiments in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic structural diagram of a decoding circuit provided by an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of another decoding circuit provided by an embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of a predecoder provided by an embodiment of the present disclosure;

FIG. 4 is a schematic structural diagram of another decoding circuit provided by an embodiment of the present disclosure;

FIG. 5 is a schematic structural diagram of another decoding circuit provided by an embodiment of the present disclosure;

FIG. 6 is a schematic structural diagram of a source driving circuit provided by an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of a device provided by an embodiment of the present disclosure.

Detailed ways

Embodiments of the present disclosure are described in detail below, examples of which are illustrated in the drawings, in which the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary and are intended to explain the present disclosure and should not be construed as limiting the present disclosure.

In this disclosure, as the number of bits of the data signal to be analyzed gradually increases, the number of transistors in the decoding circuit will also increase sharply, which not only leads to an excessive size of the driving circuit, but also increases the complexity and difficulty of decoding circuit control problem, a decoding circuit is proposed. By using the pre-decoder to pre-decode the first data signal to be decoded to determine the gamma voltage to be output, and then output the second signal for controlling the conduction of the switch branch connected to the gamma voltage, thereby That is, a switch branch in the decoding array is controlled to be turned on to output a corresponding gamma voltage. Thus, the number of transistors (switches) used in the decoding circuit is reduced.

FIG. 1 is a schematic structural diagram of a decoding circuit provided by an embodiment of the present disclosure. As shown in FIG. 1 , the decoding circuit provided by the present disclosure includes: a pre-decoder 11 and a decoding array 12 connected in sequence.

Wherein, the pre-decoder 11 is configured to pre-decode the n-bit first data signal to be decoded, so as to determine the gamma voltage to be output, and output the n-th second data signal corresponding to the gamma voltage and n-bit third data signal;

The decoding array 12 includes a plurality of first switch groups 121 and a plurality of second switches 122, each of the first switch groups 121 includes a plurality of first switches (1211), each of the first switches One end is connected to a gamma voltage, and the other ends of the plurality of first switches in each of the first switch groups 121 are respectively connected to one end of a second switch 122, and the other ends of the plurality of second switches 122 are connected to each other. connected, the decoding array is used to decode the second data signal and the third data signal respectively, so as to control the conduction of at least one first switch 1211 and one second switch 122, and perform decoding to output the The gamma voltage to output.

Wherein, the first switch 1211 and the second switch 122 may be any type of switching device, for example, both the first switch 1211 and the second switch 122 are transistors. Optionally, the turn-on logic of the first switch 1211 and the second switch 122 can be the same or different, for example, the first switch 1211 is a P-type transistor, and the second switch 122 is an N-type transistor; or, the first switch 1211 and the The second switches 122 are all P-type transistors, or all are N-type transistors, which is not limited in the present disclosure.

In the decoding circuit in the present disclosure, first, the pre-decoder is used to pre-decode the first data signal, determine the gamma voltage to be output, and output the second data signal and the third data signal corresponding to the gamma voltage to be output , and then at least the first switch in the decoding array can be turned on under the control of the second data signal, and one second switch can be turned on under the control of the third data signal, thereby outputting the gamma voltage to be output.

It can be seen from Figure 1 that all the decoding arrays in the decoding circuit adopt a non-full-type decoding method, and the output of each gamma voltage only needs two switching devices, and multiple gamma voltages can also share the same first The two switches greatly reduce the number of switching devices used in the decoding circuit, which not only reduces the size of the decoding circuit, but also reduces the power consumption of the circuit.

个，第二开关的数量也为/>

个，且每个第一开关组中包括/>

个第一开关。In some possible implementation forms, if the number of bits n of the first data signal is an even number, for example, n is 4, 6, 8, 10 or 12, etc., the number of gamma voltages that the decoding array needs to output at this time is 2 ⁿ is a perfect square number, then the number of the first switch group in the decoding array can be

, the number of the second switch is also />

, and each first switch group includes />

first switch.

个第一开关组121及32个第二开关122、且每个第一开关组121中包括32个第一开关1211。For example, if n=4, the decoding circuit decoding array 12 includes 4 first switch groups 121 and 4 second switches 122 , and each first switch group 121 includes 4 first switches 1211 . Or, if n=10, the decoding array 12 of the decoding circuit includes

There are a first switch group 121 and 32 second switches 122, and each first switch group 121 includes 32 first switches 1211.

Taking n=4, the first switch and the second switch are transistors of the same type as an example, for example, both are P-type transistors, to further describe the structure of the decoding circuit provided by the present disclosure. FIG. 2 is a schematic structural diagram of another decoding circuit provided by an embodiment of the present disclosure.

As shown in Figure 2, the decoding array 12 includes 4 first switch tube groups 121 and 4 second switches 122. One end of the 16 first switches 1211 in the 4 first switch groups 121 are respectively connected with the 16 Ga The horse voltage (V0-V15) is connected, the other end of the four first switches 1211 in each first switch group 121 is connected to one end of a second switch 122, and the other ends of the four second switches 122 are connected to each other as a decoding The output terminal (out) of the array.

Since the second data signal (such as B1-B4 in FIG. 2) and the third data signal (such as A1-A4 in FIG. 2) contain only n bits respectively, in order to select one of the 2 ⁿ gamma voltages at a time For gamma voltage output, each first switch 1211 in each first switch group 121 can be controlled by a second data signal, and each second switch 122 can be controlled by a third data signal.

Further, the pre-decoder 11 may be composed of gate circuits. For example, the pre-decoder 11 may include a NOT gate and a NAND gate to logically process the n-bit first data signal to obtain an n-bit second data signal and an n-bit second data signal. bit third data signal.

As shown in FIG. 2 , the pre-decoder 11 includes a first gate circuit 111 , a second gate circuit 112 and a third gate circuit 113 .

Wherein, the first gate circuit 111 is configured to invert the first data signal (D0-D3) to obtain a fourth data signal (DB0-DB1);

The second gate circuit 112 is used to output the n-bit first signal according to the n/2 high-order signals (D2-D3) in the first data signal and the n/2 high-order signals (DB2-DB3) in the fourth data signal. Two data signals (B1~B4);

The third gate circuit 113 is used to output the n-bit third Data signal (A1~A4).

Wherein, the first gate circuit 111 may be composed of a plurality of NOT gates. The second gate circuit 112 and the third gate circuit 113 may be composed of a plurality of NAND gates.

Fig. 3 is a schematic structural diagram of a 4-bit pre-decoder provided by an embodiment of the present disclosure.

As shown in FIG. 3 , the pre-decoder includes 4 NOT gates and 8 NAND gates.

Wherein, the 4 NOT gates are respectively used to invert the input 4-bit first data signals (D0-D3) to obtain 4-bit fourth data signals (DB0-DB3).

Each of the 4 NAND gates is used to process two signals in D2, D3, DB2 and DB3 respectively to obtain a second signal. According to the circuit diagram shown in Figure 3, it can be known that

Each of the other 4 NAND gates is used to process two signals in D1, D0, DB1 and DB0 respectively to obtain a third signal. According to the circuit diagram shown in Figure 3, it can be known that

或者，也可以如下所示：

等等，本公开对此不做限定。另外，第三数据信号与第一数据信号中各位的对应关系也可以根据需要进行调整，此处不再赘述。由图2和图3可知，第一开关组121中的各个第一开关1211的控制端分别与第二门电路112的不同输出端连接，其中，第二门电路112的每个输出端输出一个所述第二数据信号中的一个位；It should be noted that, the corresponding relationship between each bit of the second signal and the third signal and the first signal shown in FIG. 3 is only a schematic illustration. In actual use, it can be adjusted according to the connection relationship between the first switch and the gamma voltage. For example, the corresponding relationship between each bit in the second data signal and each bit in the first data signal may be as follows:

Alternatively, it could also look like this:

Etc., the present disclosure does not limit this. In addition, the corresponding relationship between the third data signal and each bit in the first data signal can also be adjusted as required, which will not be repeated here. It can be seen from FIG. 2 and FIG. 3 that the control terminals of each first switch 1211 in the first switch group 121 are respectively connected to different output terminals of the second gate circuit 112, wherein each output terminal of the second gate circuit 112 outputs a a bit in the second data signal;

A control terminal of each second switch 122 is connected to a different output terminal of the third gate circuit 113, wherein each output terminal of the third gate circuit 113 outputs a bit in a third data signal.

For example, when the first data signal is 0000, the decoding circuit shown in Fig. 2 and Fig. 3 is adopted, B4=0 in the second data signal, and the second data signals of the remaining bits: B1, B2 and B3 are all 1. A4=0 in the third data signal, and the third data signals A1, A2 and A3 of the remaining bits are all 1. At this time, since the first switch tube and the second switch tube are both P-type transistors, the first switch tube connected to the gamma voltage V0 is turned on, and a second switch tube connected to it is turned on, so that the decoding circuit outputs Gamma voltage V0.

When the first data signal is 0001, adopt the decoding circuit shown in Fig. 2 and Fig. 3, B4=0 in the second data signal, the second data signal of the remaining bits: B1, B2 and B3 are all 1, the third A3=0 in the data signal, and the third data signals A1 , A2 and A4 of the remaining bits are all 1. At this time, the first switch connected to the gamma voltage V1 is turned on, and a second switch connected to it is turned on, so that the decoding circuit outputs the gamma voltage V1.

When the first data signal is 0010, adopt the decoding circuit shown in Fig. 2 and Fig. 3, B4=0 in the second data signal, the second data signal of the remaining bits: B1, B2 and B3 are all 1, the third A2 in the data signal=0, and the third data signals A1 , A3 and A4 of the remaining bits are all 1. At this time, the first switch connected to the gamma voltage V1 is turned on, and a second switch connected to it is turned on, so that the decoding circuit outputs the gamma voltage V2.

By analogy, the decoding circuit can sequentially decode and output a gamma voltage corresponding to the input first data signal. It can be seen from the above figure that the number of logic gates included in the first gate circuit 111 , the second gate circuit 112 and the third gate circuit 113 in the pre-decoder 11 is related to the number of bits of the first data signal. If n=6, the first gate circuit includes 6 NAND gates, the second gate circuit includes 2 ³ =8 NAND gates, and the third gate circuit also includes 8 NAND gates. The first switch group includes 8 first switch groups and 8 second switches, and each first switch group includes 8 first switches. That is to say, the second data signal output by the second gate circuit includes 8 bits (B1-B8) in total, and the third data signal output by the third gate circuit includes 8 bits (A1-A8) in total. Therefore, the second data signal can respectively drive one of the first switches in the eight first switch groups to be turned on at each moment, and the third data signal can drive one of the second switches to be turned on at each moment, that is, only with the conduction The gamma voltage corresponding to the first switch connected to the second switch that is turned on will be output, so that one gamma voltage is selected and output from 2 ⁶ =64 gamma voltages at a time.

个，第二开关的数量也为/>

个，且每个第一开关组中包括/>

个第一开关。In some possible implementation forms, if the number of bits n of the first data signal is an odd number, for example, n is 5, 7, 9, 11, etc., at this time, the number of gamma voltages that the decoding array needs to output is 2 ⁿ incomplete square number, and 2 ^n-1 is a complete square number, then the number of the first switch group that needs to be included in the decoding array is

, the number of the second switch is also />

, and each first switch group includes />

first switch.

At this time, the structure of the decoding circuit is shown in FIG. 4 . FIG. 4 is a schematic structural diagram of another decoding circuit provided by an embodiment of the present disclosure. As shown in FIG. 4 , the decoding array 12 of the decoding circuit further includes two third switches 123 .

个第二开关122的另一端连接，两个第三开关123的另一端互相连接，用于在所述第一数据信号的最高位的控制下，输出待输出的伽马电压。Wherein, the n-1 lower bits of the first data signal are connected to the input end of the predecoder 11, and one end of each third switch 123 is respectively connected to

The other ends of the two second switches 122 are connected, and the other ends of the two third switches 123 are connected to each other, for outputting the gamma voltage to be output under the control of the highest bit of the first data signal.

个第一开关组121及/>

个第二开关122，其中，每个第一开关组121中包括/>

个第一开关1211。且第一开关组121可以分成两部分121a和121b，其中，每个部分都包含/>

个第一开关组，也就是与每个部分中的第一开关组121连接的多个第二开关122的另一端互相连接，并与一个第三开关123的一端连接。As can be seen from FIG. 4, at this time, the decoding array 12 includes

a first switch group 121 and />

a second switch 122, wherein each first switch group 121 includes />

a first switch 1211. And the first switch group 121 can be divided into two parts 121a and 121b, wherein each part contains

A first switch group, that is, the other ends of the plurality of second switches 122 connected to the first switch group 121 in each part are connected to each other, and are connected to one end of a third switch 123.

Taking n=5 and the first switch and the second switch being transistors of the same type as an example, the structure of the decoding circuit provided by the present disclosure will be further described below. FIG. 5 is a schematic structural diagram of another decoding circuit provided by an embodiment of the present disclosure.

As shown in FIG. 5 , the structure of the pre-decoder 11 in the decoding circuit when n=5 is the same as the structure of the pre-decoder 11 in the decoding circuit when n=4.

Since n=5, the decoding circuit needs to select a gamma voltage to output from 2 ⁵ =32 gamma voltages, and at this time, the decoding array 12 needs to include 32 first switch tubes 1211 . The 32 first switch tubes 1211 can be divided into 8 first switch groups 121 , and each switch group 121 includes 4 first switch tubes 1211 . In addition, the decoding array 12 further includes eight second switches 122 , one end of each second switch is connected to the other end of four first switches in one first switch group 121 .

In addition, as shown in Figure 5, the other ends of every four second switches 122 are connected to one end of a third switch 123, and the other ends of the two third switches 123 are connected to each other as the output ends of the decoding array for outputting Gamma voltage.

In FIG. 5 , the two third switches 123 are of the same type, so they can be controlled respectively based on the highest bit D4 in the first data signal and the inverse phase DB4 corresponding to the highest bit. If the types of the two third switches 123 are different, then the two third switches 123 may also be controlled by DB4, which is not limited in the present disclosure.

According to Fig. 5 and Fig. 3, when the decoding circuit provided by the present disclosure is adopted, when the number of bits of the first data signal increases, there is no need to change the pre-decoder and the control logic of the decoding switch array, only according to the new first For the number of bits of data, appropriately increasing the number of the first switch group and the second switch in the decoding array, and using the highest bit data signal to control the conduction state of the third switch can realize accurate decoding of higher bit data signals.

Through the above analysis, it can be seen that if the number of bits of the first data signal is an even number, then the decoding circuit can adopt the form shown in Figure 2; if the number of bits of the first data signal is an odd number, then the decoding circuit can adopt the form shown in Figure 4 or 5 the form shown.

The decoding circuit provided by the present disclosure first performs pre-decoding processing on the first data signal by using a pre-decoder to obtain the second data signal and the third data signal with the same number of bits of the pre-decoded data signal, and then based on the decoding array By decoding the second data signal and the third data signal, an accurate gamma voltage can be output. For each gamma voltage, at most three switching tubes are required, and multiple gamma voltages also share a second switching tube and a third switching tube, thereby greatly reducing the number of switching tubes used in the decoding circuit, The size of the decoding circuit is reduced.

Based on the decoding circuit provided by the above embodiments, the embodiments of the present disclosure may further provide a source driving circuit. FIG. 6 is a schematic structural diagram of a source driving circuit provided by an embodiment of the present disclosure. As shown in FIG. 6 , the source driving circuit includes a gamma voltage generating circuit 61 , a decoding circuit 62 and an amplifier 63 connected in sequence.

Wherein, the gamma voltage generating circuit 61 is used to generate the gamma voltage, and the amplifier 63 is used to amplify the gamma voltage output by the decoding circuit 62 .

In addition, for the structure and implementation principle of the decoding circuit 62 , reference may be made to the detailed description of any embodiment of the present disclosure, which will not be repeated here.

Based on the source drive circuit provided in the above embodiments, the embodiments of the present disclosure may also provide a display driver integrated circuit (DDIC), and the above explanations on the source drive circuit are also applicable to this embodiment. DDIC, so I won’t go into details here.

Based on the source driving circuit provided by the above embodiments, embodiments of the present disclosure may further provide a device. FIG. 7 is a schematic structural diagram of a device provided by an embodiment of the present disclosure. As shown in FIG. 7 , the device includes a source driving circuit 71 and a display panel 72 .

The above explanations on the source driving circuit are also applicable to the device of this embodiment, so details will not be repeated here.

The source driver circuit, DDIC and decoding circuit in the device provided by the present disclosure include a pre-decoder and a decoding array. The first data signal is pre-decoded by using the pre-decoder, and then the gamma voltage corresponding to the input first data signal can be output by using a very small number of switches. Therefore, the number of switches used in the source driving circuit is greatly reduced, and the volume and loss of the source driving circuit are reduced.

In the description of this specification, the terms "first" and "second" are used for description purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In the description of the present disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limitations on the present disclosure, and those skilled in the art can understand the above-mentioned embodiments within the scope of the present disclosure. The embodiments are subject to changes, modifications, substitutions and variations.

Claims (11)

1. A decoding circuit, comprising: a pre-decoder and a decoding array which are connected in sequence;

the pre-decoder is used for pre-decoding n bits of first data signals to be decoded to determine gamma voltages to be output, and outputting n bits of second data signals and n bits of third data signals corresponding to the gamma voltages, wherein n is an integer greater than 1;

the decoding array comprises a plurality of first switch groups and a plurality of second switches which are respectively connected with a plurality of gamma voltages, each first switch group comprises a plurality of first switches, one end of each first switch is connected with one gamma voltage, the other ends of the first switches in each first switch group are respectively connected with one end of one second switch, the other ends of the second switches are mutually connected, and the decoding array is used for respectively decoding the second data signals and the third data signals so as to control at least one first switch and one second switch to be conducted and output the gamma voltages to be output.

2. The circuit of claim 1,

n is an even number, and the decoding array comprises 2 ⁿ A first switch group and 2 ⁿ A second switch, wherein each first switch group comprises 2 ⁿ A first switch.

3. The circuit of claim 2, wherein the predecoder includes a first gate circuit, a second gate circuit, and a third gate circuit;

the first gate circuit is used for carrying out inversion processing on the first data signal so as to obtain a fourth data signal;

the second gate circuit is used for outputting n bits of the second data signal according to n/2 high-order signals in the first data signal and n/2 high-order signals in the fourth data signal;

and the third gate circuit is used for outputting n bits of the third data signal according to n/2 low-order signals in the first data signal and n/2 low-order signals in the fourth data signal.

4. The circuit of claim 3,

the control end of each first switch in each first switch group is respectively connected with different output ends of the second gate circuit, wherein each output end of the second gate circuit outputs one bit of the second data signal;

and the control end of each second switch is connected with different output ends of the third gate circuit, wherein each output end of the third gate circuit outputs one bit in one third data signal.

5. The circuit of claim 1,

n is an odd number, and the decoding array comprises 2 x 2 ^n-1 A first switch group and 2 × 2 ^n-1 A second switch, wherein each first switch group comprises 2 ^n-1 A first switch;

the decoding array further comprises: two third switches;

the n-1 lower bits of the first data signal are connected with the input end of the pre-decoder, and one end of each third switch is respectively connected with 2 ^n-1 The other ends of the second switches are connected, and the other ends of the two third switches are connected with each other and used for outputting the gamma voltage to be output under the control of the highest bit of the first data signal.

6. The circuit of claim 5,

a first set of the first switch groups for receiving the second data signal in the first range from 2 ⁿ Selecting one gamma voltage from the gamma voltages to output;

a second one of the first switch groups for inputting the second data signal in the second range ⁿ The gamma voltages select a gamma voltage output, wherein each first switch set includes 2 ^n-1 A first switch group.

7. The circuit of claim 6, wherein the predecoder includes a first gate circuit, a second gate circuit, and a third gate circuit;

the first gate circuit is used for carrying out reverse phase processing on n-1 low-order signals in the first data signal so as to obtain a fourth data signal;

the second gate circuit is configured to output n bits of the second data signal according to (n-1)/2 high-order signals in the first data signal and (n-1)/2 high-order signals in the fourth data signal;

and the third gate circuit is used for outputting n bits of the third data signal according to (n-1)/2 low-order signals in the first data signal and (n-1)/2 low-order signals in the fourth data signal.

8. The circuit of claim 7,

the control end of each first switch in each first switch group is respectively connected with different output ends of the second gate circuit, wherein each output end of the second gate circuit outputs one bit of the second data signal;

the control ends of every two second switches are connected with one output end of the third gate circuit, wherein each output end of the third gate circuit outputs one bit in the third data signal.

9. A source driver circuit, comprising: a gamma voltage generating circuit, a decoding circuit according to any one of claims 1 to 8 and an amplifier connected in sequence;

the gamma voltage generating circuit is used for generating gamma voltages, and the amplifier is used for amplifying the gamma voltages output by the decoding circuit.

10. A display driving integrated circuit DDIC comprising the source driving circuit of claim 9.

11. A device comprising the source driver circuit according to claim 9 and a display panel.

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