CN115877617B - Array substrate, liquid crystal display panel, driving method and liquid crystal display device - Google Patents
Array substrate, liquid crystal display panel, driving method and liquid crystal display device Download PDFInfo
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Abstract
The application provides an array substrate, a liquid crystal display panel, a driving method and a liquid crystal display device, and relates to the technical field of liquid crystal display, wherein the array substrate comprises common electrodes and pixel electrodes, each row of pixel electrodes and the corresponding row of common electrodes are arranged in a staggered manner in the row direction, a projection area of each pixel electrode on the substrate of the array substrate is partially overlapped with a projection area of two corresponding adjacent common electrodes on the substrate in the row direction, pixel units of the array substrate corresponding to each overlapped area are different, each row of common electrodes and the corresponding row of pixel electrodes share a data line, each pixel electrode and a corresponding common electrode share a combined switch, and the combined switch comprises a thin film transistor and a signal selection unit, and the signal selection unit is used for controlling the data line to transmit signals to the common electrodes or the pixel electrodes. The technical scheme provided by the application can improve the resolution and reduce the influence on the aperture opening ratio.
Description
Technical Field
The present application relates to the field of liquid crystal display technologies, and in particular, to an array substrate, a liquid crystal display panel, a driving method thereof, and a liquid crystal display device.
Background
With the continued maturity of liquid crystal display technology, liquid crystal display devices such as thin film transistor liquid crystal displays (Thin Film Transistor Liquid CRYSTAL DISPLAY, TFT-LCDs) are increasingly being used in various fields.
For TFT-LCD, resolution improvement can significantly improve the definition of the display screen, and it is common to increase the number of pixel units in the display by reducing the area of the pixel units in the display, so as to improve the resolution.
However, to ensure the charging rate, devices and wires in the pixel unit occupy a certain area, which makes the area reduction of the pixel unit limited, and the resolution reaches the bottleneck, so how to improve the resolution of the liquid crystal display device is a technical problem that needs to be solved by the person skilled in the art.
Disclosure of Invention
In view of the above, the present application provides an array substrate, a liquid crystal display panel, a driving method thereof, and a liquid crystal display device for improving resolution of the liquid crystal display device.
In order to achieve the above object, in a first aspect, an embodiment of the present application provides an array substrate, including: the pixel electrode layer comprises a plurality of pixel electrodes which are arranged in an array, each column of the common electrodes corresponds to each column of the pixel electrodes one by one, and each column of the pixel electrodes and the common electrode of the corresponding column are arranged in a staggered manner in the column direction;
The projection area of each pixel electrode on the substrate of the array substrate is partially overlapped with the projection areas of the corresponding two adjacent common electrodes on the substrate in the column direction, and the pixel units of the array substrate corresponding to each overlapped area are different;
Each column of common electrodes and each corresponding column of pixel electrodes share a data line, each pixel electrode and a corresponding common electrode share a combination switch, and the combination switch comprises a thin film transistor and a signal selection unit, wherein the signal selection unit is used for controlling the data line to transmit data signals to the common electrode or the pixel electrode when the thin film transistor is conducted.
As an optional implementation manner of the embodiment of the present application, the signal selection unit includes a first unidirectional conduction element, a second unidirectional conduction element, a third unidirectional conduction element, and a fourth unidirectional conduction element;
The control end of the thin film transistor is electrically connected with the grid line, the input end of the thin film transistor is electrically connected with the data line, and the output end of the thin film transistor is respectively electrically connected with the positive electrode of the first unidirectional conducting element and the negative electrode of the third unidirectional conducting element;
the negative electrode of the first unidirectional conducting element is electrically connected with the public electrode and the positive electrode of the second unidirectional conducting element respectively, and the negative electrode of the second unidirectional conducting element is electrically connected with a first reset signal line;
The positive electrode of the third unidirectional conducting element is electrically connected with the pixel electrode and the negative electrode of the fourth unidirectional conducting element respectively, and the positive electrode of the fourth unidirectional conducting element is electrically connected with the second reset signal line.
As an alternative implementation of the embodiment of the present application, a light shielding unit is disposed between adjacent common electrodes in the column direction.
As an alternative implementation manner of the embodiment of the present application, in the column direction, a projection of a center line between boundaries of adjacent common electrodes on a substrate of the array substrate overlaps with a projection of a center line of a corresponding pixel electrode in the row direction on the substrate.
As an optional implementation manner of the embodiment of the present application, the array substrate includes: the pixel electrode comprises a substrate base plate, a first metal layer, the public electrode layer, a first PN junction layer, an insulating layer, a semiconductor layer, a second metal layer, a first passivation layer, a third metal layer, a second passivation layer, the pixel electrode layer, a second PN junction layer, a third passivation layer and a first oxide conductive layer;
the first metal layer and the common electrode layer are positioned above the substrate, the first metal layer comprises a plurality of gate lines and metal spacing units, the metal spacing units are positioned above the substrate and the common electrode layer, and the first PN junction layer is positioned above the common electrode layer;
the insulating layer is positioned above the substrate base plate, the first metal layer, the public electrode layer and the first PN junction layer, the semiconductor layer is positioned above the insulating layer, and the second metal layer is positioned above the semiconductor layer and the insulating layer;
The first passivation layer is located above the insulating layer, the semiconductor layer and the second metal layer, the third metal layer is located above the first passivation layer, the third metal layer comprises a plurality of reset signal lines, and the second passivation layer is located above the first passivation layer and the third metal layer;
the pixel electrode layer is positioned above the second passivation layer, and each pixel electrode in the pixel electrode layer is contacted with the second metal layer and the metal interval unit through a via hole;
The second PN junction layer is located above the pixel electrode layer, the third passivation layer is located above the second passivation layer, the pixel electrode layer and the second PN junction layer, and the first oxide conductive layer is located above the third passivation layer.
In a second aspect, an embodiment of the present application provides a liquid crystal display panel, including a color film substrate, an array substrate as set forth in the first aspect or any one of the first aspects, and a liquid crystal layer disposed between the array substrate and the color film substrate, where the color film substrate and the array substrate are disposed opposite to each other.
As an optional implementation manner of the embodiment of the present application, a second oxide conductive layer is disposed below the color film substrate, the second oxide conductive layer is disposed in a partitioned manner, and patterns of the first oxide conductive layer and the second oxide conductive layer of the array substrate are consistent.
In a third aspect, an embodiment of the present application provides a method for driving a liquid crystal display panel, which is applied to the liquid crystal display panel according to the second aspect or any one of the second aspects, and the method includes:
For each pixel unit in the liquid crystal display panel, determining a second voltage of a second electrode corresponding to the pixel unit according to the pre-display gray scale of the pixel unit and the first voltage of the first electrode corresponding to the pixel unit; the first electrode is a common electrode, the second electrode is a pixel electrode, or the first electrode is a pixel electrode, and the second electrode is a common electrode;
Outputting the second voltage to the second electrode.
As an optional implementation manner of the embodiment of the present application, the determining, according to the pre-display gray level of the pixel unit and the first voltage of the first electrode corresponding to the pixel unit, the second voltage of the second electrode corresponding to the pixel unit includes:
Determining an absolute value of a voltage difference between the first electrode and the second electrode according to the pre-display gray scale of the pixel unit;
when the first electrode is a common electrode, determining the sum of the first voltage and the absolute value of the voltage difference as the second voltage;
When the first electrode is a pixel electrode, a difference between the first voltage and the absolute value of the voltage difference is determined as the second voltage.
In a fourth aspect, an embodiment of the present application provides a liquid crystal display device, including a backlight source and a liquid crystal display panel according to the second aspect or any one of the second aspects, where the backlight source is located at a side of the array substrate facing away from the color film substrate.
The technical scheme provided by the embodiment of the application comprises a public electrode layer and a pixel electrode layer, wherein the public electrode layer comprises a plurality of public electrodes which are arranged in an array, the pixel electrode layer comprises a plurality of pixel electrodes which are arranged in an array, each row of public electrodes corresponds to each row of pixel electrodes one by one, and each row of pixel electrodes and the public electrodes of the corresponding row are arranged in a staggered manner in the row direction; the projection area of each pixel electrode on the substrate of the array substrate is partially overlapped with the projection areas of the corresponding two adjacent common electrodes on the substrate in the column direction, and the pixel units of the array substrate corresponding to each overlapped area are different; each column of common electrodes and each corresponding column of pixel electrodes share a data line, each pixel electrode and a corresponding common electrode share a combined switch, and the combined switch comprises a thin film transistor and a signal selection unit, wherein the signal selection unit is used for controlling the data line to transmit data signals to the common electrode or the pixel electrode when the thin film transistor is conducted. In the above technical solution, since each column of pixel electrodes and the common electrode of the corresponding column are arranged in a staggered manner in the column direction, so that one pixel electrode can respectively form a horizontal electric field with the corresponding two adjacent common electrodes in the column direction, if different voltages are output to the two adjacent common electrodes, the display areas corresponding to the two horizontal electric fields can display different gray scales, that is, the display area corresponding to one pixel electrode can display two different gray scales in the column direction, compared with the display area corresponding to one pixel electrode at present, only one gray scale can be displayed in the column direction, and the solution can improve the resolution by one time in the column direction of the liquid crystal display device; in addition, each column of common electrode and each corresponding column of pixel electrode share one data line, and each pixel electrode and each corresponding common electrode share one combined switch, so that new data lines and thin film transistors are not needed to be added, and the influence on the aperture ratio of the liquid crystal display device can be reduced.
Drawings
Fig. 1 is a schematic structural diagram of a liquid crystal display device according to an embodiment of the present application;
fig. 2 is a schematic arrangement diagram of a common electrode and a pixel electrode in a column direction according to an embodiment of the present application;
FIG. 3 is a schematic circuit diagram of a combination switch according to an embodiment of the present application;
fig. 4 is a top view of an array substrate in a column direction according to an embodiment of the present application;
FIG. 5 is a cross-sectional view of an array substrate along A-A' according to an embodiment of the present application;
FIG. 6 is a cross-sectional view of an array substrate along B-B' according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a first oxide conductive layer according to an embodiment of the present application;
FIG. 8 is a schematic diagram of a relationship between a common electrode and a pixel electrode in any column in an array substrate according to an embodiment of the present application;
Fig. 9 is a timing chart of a reset signal and a gate driving signal according to an embodiment of the present application.
Reference numerals illustrate:
1-a backlight; 2-a color film substrate;
3-an array substrate; a 4-liquid crystal layer;
311-substrate base plate; 312-a first metal layer;
313-a common electrode layer; 314-a first PN junction layer;
315 an insulating layer; 316-a semiconductor layer;
317-a second metal layer; 318-a first passivation layer;
319-a third metal layer; 320-a second passivation layer;
321-a pixel electrode layer; 322-a second PN junction layer;
323-a third passivation layer; 324-a first oxide conductive layer;
325-via;
3121-gate lines; 3122-metal spacer units.
Detailed Description
Embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. The terminology used in the description of the embodiments of the application is for the purpose of describing particular embodiments of the application only and is not intended to be limiting of the application. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.
Fig. 1 is a schematic structural diagram of a liquid crystal display device according to an embodiment of the present application, and as shown in fig. 1, the liquid crystal display device according to an embodiment of the present application may include a liquid crystal display panel and a backlight 1.
The liquid crystal display panel may be a transverse electric field effect (In-PLANE SWITCHING, IPS) display panel, or may be another type of display panel, and In this embodiment, the liquid crystal display panel is taken as an IPS display panel for example, and exemplary description is made.
The liquid crystal display panel may include: color film substrate 2, array substrate 3 and liquid crystal layer 4.
The array substrate 3 and the color film substrate 2 are arranged oppositely, and the liquid crystal layer 4 is positioned between the array substrate 3 and the color film substrate 2.
The backlight source 1 is located at one side of the array substrate 3 away from the color film substrate 2, and is used for providing a backlight source for the liquid crystal display panel.
The array substrate 3 may include a common electrode layer and a pixel electrode layer, the common electrode layer may include a plurality of common electrodes arranged in an array, the pixel electrode layer may include a plurality of pixel electrodes arranged in an array, the number of columns of the common electrodes and the pixel electrodes is the same, each column of the common electrodes corresponds to one column of the pixel electrodes, and each column of the common electrodes corresponds to a different column of the pixel electrodes.
Fig. 2 is a schematic arrangement diagram of common electrodes and pixel electrodes in a column direction, as shown in fig. 2, where each column of pixel electrodes and the corresponding column of common electrodes are arranged in a staggered manner, a projection area of each pixel electrode on a substrate of the array substrate 3 and a projection area of two corresponding adjacent common electrodes (a first common electrode and a second common electrode) on the substrate are partially overlapped in the column direction, each overlapped area corresponds to one pixel unit of the array substrate 3, and the pixel units corresponding to each overlapped area are different. In this way, one pixel electrode and two corresponding adjacent common electrodes can form horizontal electric fields respectively in the column direction, if different voltages are output to the two adjacent common electrodes, different gray scales can be displayed in display areas (namely, a first pixel unit and a second pixel unit) corresponding to the two horizontal electric fields respectively, so that two different gray scales can be displayed in the column direction in the display area corresponding to one pixel electrode.
The projection of the center line between the boundaries of the adjacent common electrodes onto the substrate of the array substrate 3 may overlap with the projection of the center line of the corresponding pixel electrode in the row direction onto the substrate. The lengths of the two horizontal electric fields corresponding to the pixel electrode in the column direction are equal, namely the areas of the pixel electrode corresponding to the first display area and the second display area are equal, so that the display effect of the liquid crystal display device is improved.
Each column of the common electrode and the pixel electrode of the corresponding column may share one data line, and each pixel electrode may share one combination switch with the corresponding one of the common electrodes. The combination switch may include a thin film transistor (a thin film transistor corresponding to the pixel electrode, not a newly added thin film transistor) and a signal selection unit for controlling the data line to transmit the data signal to the common electrode or the pixel electrode when the thin film transistor is turned on. Thus, the data lines and the thin film transistors of the pixel electrodes corresponding to the common electrodes can be multiplexed, and the influence on the aperture ratio of the liquid crystal display device can be reduced without adding the data lines and the thin film transistors to the common electrodes.
Each pixel electrode can share a combination switch with the corresponding first common electrode, can also share a combination switch with the corresponding second common electrode, the present embodiment will be described by taking, as an example, a case where each pixel electrode shares a combination switch with the corresponding first common electrode.
The signal selection unit may be a unidirectional conductive circuit element, such as a diode, a thyristor, or the like. The present embodiment will be described by taking the signal selecting unit as an example of a diode.
Fig. 3 is a schematic circuit diagram of a combination switch according to an embodiment of the present application, as shown in fig. 3, the signal selecting unit may include a first diode P1, a second diode P2, a third diode P3, and a fourth diode P4.
The control terminal of the thin film transistor T1 is electrically connected to the gate line Scan, the input terminal of the thin film transistor T1 is electrically connected to the Data line Data, and the output terminal of the thin film transistor T1 is electrically connected to the input terminal of the first diode P1 and the output terminal of the third diode P3, respectively.
The output end of the first diode P1 is respectively and electrically connected with the common electrode of the liquid crystal capacitor Cst and the input end of the second diode P2, and the output end of the second diode P2 is electrically connected with a first reset signal line; the input end of the third diode P3 is electrically connected to the pixel electrode of the liquid crystal capacitor Cst and the output end of the fourth diode P4, respectively, and the input end of the fourth diode P4 is electrically connected to the second reset signal line.
When the scanning line transmits the scanning signal, the thin film transistor T1 is turned on, at this time, if the potential of the Data signal transmitted by the Data line Data is higher than the potential at the pixel electrode, the first diode P1 is turned on, the Data signal transmitted by the Data line Data charges the pixel electrode, and due to the existence of the second diode P2, most of the current flows to the pixel electrode during charging, at this time, the potential of the first reset signal line is high, and the second diode P2 is turned off, so as to reduce the influence of the first reset signal line on the potential at the pixel electrode. It will be appreciated that the third diode P3 is turned off when the potential of the data signal is higher than the potential at the common electrode, and the data signal does not charge the common electrode.
If the potential of the Data signal transmitted by the Data line Data is lower than the potential at the common electrode, the third diode P3 is turned on, the Data signal charges to the common electrode, and most of the current flows to the common electrode during charging due to the fourth diode P4, at this time, the potential of the second reset signal line is low, and the fourth diode P4 is turned off, so as to reduce the influence of the second reset signal line on the potential at the common electrode. It will be appreciated that the first diode P1 is turned off when the potential of the data signal is lower than the potential at the pixel electrode, and the data signal does not charge the pixel electrode.
The first reset signal line is used for resetting the potential of the pixel electrode, the second reset signal line is used for resetting the potential of the common electrode, and the first reset signal line can be electrically connected with the first peripheral reset signal line through a first switching tube T2; the first reset signal line may be electrically connected to the second peripheral reset signal line through the second switching transistor T3.
The first switching tube T2 and the second switching tube T3 may be disposed in a non-display area of the array substrate 3 to save an in-plane space.
The diodes can also reduce off-state leakage current of the thin film transistor T1, the first switching tube T2 and the second switching tube T3, and further block the leakage current so as to reduce the influence of the leakage current on the common electrode and the pixel electrode.
Fig. 4 is a top view of an array substrate in a column direction according to an embodiment of the present application, as shown in fig. 4,
The array substrate 3 may include a plurality of gate lines extending in a row direction and a plurality of data lines extending in a column direction.
In the column direction, a shading unit can be arranged between the adjacent public electrodes so as to reduce the influence of liquid crystal disorder between horizontal electric fields corresponding to the adjacent public electrodes on the display effect; a light shielding unit may be disposed between adjacent pixel electrodes to reduce the influence of liquid crystal disturbance between horizontal electric fields corresponding to the adjacent pixel electrodes on the display effect.
In the column direction, the projection of the center line between the boundaries of the adjacent common electrodes on the substrate of the array substrate 3 may be located in the projection area of the corresponding gate lines and reset signal lines of the array substrate 3 on the substrate, that is, the gate lines and the reset signal lines are located in the interval area of the adjacent common electrodes in the column direction, and since the interval area of the adjacent common electrodes does not emit light (is blocked by the corresponding light shielding unit), the gate lines and the reset signal lines will not block light, and the loss of the aperture ratio of the liquid crystal display device caused by the gate lines and the reset signal lines is reduced.
Fig. 5 is a cross-sectional view of an array substrate 3 along A-A 'provided by an embodiment of the present application, and fig. 6 is a cross-sectional view of an array substrate 3 along B-B' provided by an embodiment of the present application, where, as shown in fig. 5 and 6, the array substrate 3 may include: the substrate 311, the first metal layer 312, the common electrode layer 313, the first PN junction layer 314, the insulating layer 315, the semiconductor layer 316, the second metal layer 317, the first passivation layer 318, the third metal layer 319, the second passivation layer 320, the pixel electrode layer 321, the second PN junction layer 322, the third passivation layer 323, and the first oxide conductive layer 324.
The substrate 311 may be made of quartz, glass, organic polymer, silicon, metal, or other semiconductor materials.
The first metal layer 312 and the common electrode layer 313 are located above the substrate 311, the first metal layer 312 may include a plurality of gate lines 3121 and metal spacer units 3122, the metal spacer units 3122 are located above the substrate 311 and the common electrode layer 313, the first metal layer 312 may be formed using a sputtering process, and the first metal layer 312 may be one or more of aluminum, molybdenum, copper, and silver, and the first metal layer 312 formed of the above materials may achieve low resistance and high adhesion effects.
The common electrode layer 313 may be formed by forming a metal film over the substrate 311 using a sputtering process, and then performing exposure development on the metal film.
The first PN junction layer 314 is located above the common electrode layer 313, and the first PN junction layer 314 may include a plurality of PN junctions disposed at intervals.
An insulating layer 315 is disposed over the substrate base 311, the first metal layer 312, the common electrode layer 313, and the first PN junction layer 314, and the insulating layer 315 may be formed using a plasma enhanced chemical vapor deposition process.
The semiconductor layer 316 is located above the insulating layer 315, and the material of the semiconductor layer 316 may be hydrogenated amorphous silicon doped with phosphorus tri-hydride or other semiconductor materials, and the semiconductor layer 316 is formed by using the above materials, so that good contact between the semiconductor layer 316 and the metal electrode of the second metal layer 317 can be formed, the contact resistance between the semiconductor layer 316 and the second metal layer 317 is reduced, and the electron transmission rate is improved.
A second metal layer 317 is over the semiconductor layer 316 and the insulating layer 315, and the first metal layer 312 may include a drain electrode and a source electrode. The second metal layer 317 may be formed by a sputtering process, and the material of the second metal layer 317 may include one or more of aluminum, molybdenum, copper, and silver, and the second metal layer 317 formed by the above materials can achieve the effects of low resistance and high adhesion.
The first passivation layer 318 is disposed over the insulating layer 315, the semiconductor layer 316, and the second metal layer 317, and the first passivation layer 318 may be formed using a plasma enhanced chemical vapor deposition process, and the first passivation layer 318 serves to protect the insulating layer 315, the semiconductor layer 316, and the second metal layer 317.
The third metal layer 319 is over the first passivation layer 318, and the third metal layer 319 may include a plurality of reset signal lines, each of which is bridged with a corresponding pixel electrode or common electrode through a via 325. The third metal layer 319 may be made of one or more of aluminum, molybdenum, copper, and silver.
The second passivation layer 320 is over the first passivation layer 318 and the third metal layer 319, and the second passivation layer 320 may be formed using a plasma enhanced chemical vapor deposition process.
The pixel electrode layer 321 is located over the second passivation layer 320, and each pixel electrode in the pixel electrode layer 321 is in contact with the second metal layer 317 and the metal spacer unit 3122 through the via hole 325. The common electrode and the corresponding pixel electrode are bridged by the via hole 325, and the high-low potential data signal outputted from the data line is transmitted to the common electrode and the high-potential data signal outputted from the data line is transmitted to the pixel electrode by the selective PN junction, thereby forming a voltage difference between the common electrode and the corresponding pixel electrode.
The second PN junction layer 322 is located above the pixel electrode layer 321, and the first PN junction layer 314 may include a plurality of PN junctions disposed at intervals.
The third passivation layer 323 is positioned over the second passivation layer 320, the pixel electrode layer 321, and the second PN junction layer 322, and the third passivation layer 323 may be formed using a plasma enhanced chemical vapor deposition process. The third passivation layer 323 may be provided as a thin layer to reduce an influence on the inversion of the liquid crystal in the normal opening area.
The first oxide conductive layer 324 is over the third passivation layer 323, and a material of the first oxide conductive layer 324 may be indium tin oxide or the like. The first oxide conductive layer 324 is for holding the potential of the corresponding reset signal line.
Specifically, a direct current signal may be supplied to the first oxide conductive layer 324, so that a holding capacitance is formed between the first oxide conductive layer 324 and the reset signal line, and the potential of the reset signal line signal is held.
Fig. 7 is a schematic diagram of a first oxide conductive layer according to an embodiment of the present application, as shown in fig. 7, the first oxide conductive layer may be configured as a plurality of partitions, each partition may be in a grid shape, and each partition may be connected to a pin through a wire, so as to be connected to a printed circuit board (Printed Circuit Board, PCB).
The wiring connected to the lead can be covered on the data line, so that the electrode formed by the first oxide conductive layer can not form a chaotic electric field with the opening area to influence the inversion of the liquid crystal.
The second oxide conductive layer can be arranged below the color film substrate, the second oxide conductive layer can be consistent with the pattern of the first oxide conductive layer to form a plurality of grid-shaped subareas, and the same signals as the subareas of the corresponding first oxide conductive layer can be introduced into each subarea. Therefore, after the finger of the user touches the display panel, a capacitor is formed between the finger and the second oxide conductive layer, so that the electric signal of the corresponding partition of the second oxide conductive layer changes, and due to the capacitive coupling effect between the first oxide conductive layer and the second oxide conductive layer, the electric signal of the corresponding partition of the second oxide conductive layer also changes, and therefore, the change of the electric signal of the corresponding partition of the second oxide conductive layer can be identified through the IC of the PCB connected with the corresponding partition of the second oxide conductive layer through the pins, so that tracking of touch signals is realized, and a touch function is formed on the display panel.
The following describes a driving method of a liquid crystal display panel provided in an embodiment of the present application.
In driving the liquid crystal display panel for display, a progressive scanning method may be employed. When scanning to the nth row and the mth column of the liquid crystal display panel, determining a second voltage of a second electrode corresponding to the pixel unit according to the pre-display gray scale of the nth row and the mth column pixel unit in the liquid crystal display panel and the first voltage of the first electrode corresponding to the pixel unit, wherein M, N is a positive integer; the first electrode is a common electrode, the second electrode is a pixel electrode, or the first electrode is a pixel electrode, and the second electrode is a common electrode.
After determining the second voltage of the second electrode, the second voltage may be output to the second electrode.
Fig. 8 is a schematic diagram of a relationship between a common electrode and a pixel electrode in any column in the array substrate provided by the embodiment of the application, as shown in fig. 8, the pixel cell P 2n-3 corresponds to the pixel electrode PXL n-1 and the common electrode COM n-2, the pixel cell P 2n-2 corresponds to the pixel electrode PXL n-1 and the common electrode COM n-1, the pixel cell P 2n-1 corresponds to the pixel electrode PXL n and the common electrode COM n-1, the pixel cell P 2n corresponds to the pixel electrode PXL n and the common electrode COM n, the pixel cell P 2n+1 corresponds to the pixel electrode PXL n+1 and the common electrode COM n, and the pixel cell P 2n+2 corresponds to the pixel electrode PXL n+1 and the common electrode COM n+1.
When scanning to the n-1 th row, the gate line G n-1 may be a high level signal, the corresponding TFTs of the pixel electrode PXL n-1 and the common electrode COM n-1 are turned on, at this time, a corresponding voltage difference may be determined according to the pre-display gray level of the pixel cell P 2n-3, then the voltage of the pixel electrode PXL n-1 is determined according to the voltage difference and the voltage of the common electrode COM n-1 (the data line has already output the data signal to the common electrode COM n-1 in the previous row of scanning), then the corresponding data signal is output to the pixel electrode PXL n-1 through the data line, at this time, the liquid crystal between the overlapping areas of the common electrode COM n-2 and the pixel electrode PXL n-1 is turned over, and the pixel cell P 2n-3 displays the corresponding gray level.
Then, a corresponding voltage difference can be determined according to the pre-display gray level of the pixel unit P 2n-2, then, a voltage of the common electrode COM n-1 is determined according to the voltage difference and the voltage of the pixel electrode PXL n-1, and then, a corresponding data signal is output to the common electrode COM n-1 through the data line, at this time, the liquid crystal between the overlapping areas of the pixel electrode PXL n-1 and the common electrode COM n-1 is turned over, and the pixel unit P 2n-2 displays the corresponding gray level.
When scanning to the nth row, the gate line G n may be a high-level signal, the corresponding TFTs of the pixel electrode PXL n and the common electrode COM n are turned on, at this time, a corresponding voltage difference may be determined according to the pre-display gray level of the pixel unit P 2n-1, then the voltage of the pixel electrode PXL n is determined according to the voltage difference and the voltage of the common electrode COM n, and then a corresponding data signal is output to the pixel electrode PXL n through the data line, at this time, the liquid crystal between the overlapping areas of the common electrode COM n-1 and the pixel electrode PXL n is turned over, and the pixel unit P 2n-1 displays the corresponding gray level.
Then, a corresponding voltage difference can be determined according to the pre-display gray level of the pixel unit P 2n, then, a voltage of the common electrode COM n is determined according to the voltage difference and the voltage of the pixel electrode PXL n, and then, a corresponding data signal is output to the common electrode COM n through the data line, at this time, the liquid crystal between the overlapping areas of the pixel electrode PXL n and the common electrode COM n is turned over, and the pixel unit P 2n displays the corresponding gray level.
And so on, the liquid crystal display panel is lighted row by row.
In addition, since the degree of inversion of the liquid crystal is related to the absolute value of the voltage difference and is independent of the direction, when the voltage of the corresponding pixel electrode is determined from the voltage of the common electrode and the voltage difference, the sum of the voltage difference and the voltage of the common electrode can be determined as the voltage of the pixel electrode; when the voltage of the corresponding common electrode is determined according to the voltage of the pixel electrode and the voltage difference, the difference between the voltage of the pixel electrode and the voltage difference may be determined as the voltage of the common electrode. This maintains the voltages of the pixel electrodes and the common electrode of each row of the display device not too high.
When scanned in the above manner, the potential of each row of common electrodes is always smaller than the potential of the pixel electrode. Fig. 9 is a timing chart of the reset signal and the gate driving signal when scanning in the above manner, and as shown in fig. 9, the signal of the reset signal 1 outputted from the first reset signal line when it is in the trough is the lowest potential signal of the common electrode of the previous line when it is combined with the signal of the common electrode of the previous line, and the duration of the combined signal may be 1/2H (the specific time of H may be adjusted according to the refresh rate and resolution of the display device). The reset signal 1 is the highest potential signal input to the pixel electrode corresponding to the current row at other time.
The signal of the reset signal 2 outputted by the second reset signal line at the peak is the highest potential signal of the pixel electrode of the current row, and the duration of the composite signal can be 1/2H. The signal of the reset signal 2 at other time is the lowest potential signal of the pixel electrode corresponding to the present row.
The first reset signal line and the second reset signal line may input signals when the current-row gate driving signal is turned on, and may hold signals when the current-row gate driving signal is not turned on.
The data line signal may charge a high potential signal to the pixel electrode at the first 1/2H of each H and a low potential signal to the common electrode at the second half frame of the second 1/2H.
The technical scheme provided by the embodiment of the application comprises a public electrode layer and a pixel electrode layer, wherein the public electrode layer comprises a plurality of public electrodes which are arranged in an array, the pixel electrode layer comprises a plurality of pixel electrodes which are arranged in an array, each row of public electrodes corresponds to each row of pixel electrodes one by one, and each row of pixel electrodes and the public electrodes of the corresponding row are arranged in a staggered manner in the row direction; the projection area of each pixel electrode on the substrate of the array substrate is partially overlapped with the projection areas of the corresponding two adjacent common electrodes on the substrate in the column direction, and the pixel units of the array substrate corresponding to each overlapped area are different; each column of common electrodes and each corresponding column of pixel electrodes share a data line, each pixel electrode and a corresponding common electrode share a combined switch, and the combined switch comprises a thin film transistor and a signal selection unit, wherein the signal selection unit is used for controlling the data line to transmit data signals to the common electrode or the pixel electrode when the thin film transistor is conducted. In the above technical solution, since each column of pixel electrodes and the common electrode of the corresponding column are arranged in a staggered manner in the column direction, so that one pixel electrode can respectively form a horizontal electric field with the corresponding two adjacent common electrodes in the column direction, if different voltages are output to the two adjacent common electrodes, the display areas corresponding to the two horizontal electric fields can display different gray scales, that is, the display area corresponding to one pixel electrode can display two different gray scales in the column direction, compared with the display area corresponding to one pixel electrode at present, only one gray scale can be displayed in the column direction, and the solution can improve the resolution by one time in the column direction of the liquid crystal display device; in addition, each column of common electrode and each corresponding column of pixel electrode share one data line, and each pixel electrode and each corresponding common electrode share one combined switch, so that new data lines and thin film transistors are not needed to be added, and the influence on the aperture ratio of the liquid crystal display device can be reduced.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/device and method may be implemented in other manners. For example, the apparatus/device embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
In the description of the present application, unless otherwise indicated, "/" means that the objects associated in tandem are in a "or" relationship, e.g., A/B may represent A or B; the "and/or" in the present application is merely an association relationship describing the association object, and indicates that three relationships may exist, for example, a and/or B may indicate: there are three cases, a alone, a and B together, and B alone, wherein a, B may be singular or plural.
Also, in the description of the present application, unless otherwise indicated, "a plurality" means two or more than two. "at least one of the following" or similar expressions thereof, means any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.
As used in the present description and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
Furthermore, in the description of the present specification and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.
Claims (9)
1. An array substrate, characterized by comprising: the pixel electrode layer comprises a plurality of pixel electrodes which are arranged in an array, each column of the common electrodes corresponds to each column of the pixel electrodes one by one, and each column of the pixel electrodes and the common electrode of the corresponding column are arranged in a staggered manner in the column direction;
The projection area of each pixel electrode on the substrate of the array substrate is partially overlapped with the projection areas of the corresponding two adjacent common electrodes on the substrate in the column direction, and the pixel units of the array substrate corresponding to each overlapped area are different;
Each column of common electrodes and each corresponding column of pixel electrodes share a data line, each pixel electrode and a corresponding common electrode share a combination switch, the combination switch comprises a thin film transistor and a signal selection unit, and the signal selection unit is used for controlling the data line to transmit data signals to the common electrode or the pixel electrode when the thin film transistor is conducted;
the signal selection unit comprises a first unidirectional conduction element, a second unidirectional conduction element, a third unidirectional conduction element and a fourth unidirectional conduction element;
The control end of the thin film transistor is electrically connected with the grid line, the input end of the thin film transistor is electrically connected with the data line, and the output end of the thin film transistor is respectively electrically connected with the positive electrode of the first unidirectional conducting element and the negative electrode of the third unidirectional conducting element;
The negative electrode of the first unidirectional conducting element is electrically connected with the pixel electrode and the positive electrode of the second unidirectional conducting element respectively, and the negative electrode of the second unidirectional conducting element is electrically connected with a first reset signal line;
the positive electrode of the third unidirectional conducting element is electrically connected with the public electrode and the negative electrode of the fourth unidirectional conducting element respectively, and the positive electrode of the fourth unidirectional conducting element is electrically connected with the second reset signal line.
2. The array substrate according to claim 1, wherein a light shielding unit is provided between adjacent common electrodes in a column direction.
3. The array substrate according to claim 1, wherein a projection of a center line between boundaries of adjacent common electrodes on a substrate of the array substrate in a column direction overlaps with a projection of a center line of corresponding pixel electrodes on the substrate in a row direction.
4. The array substrate of any one of claims 1-3, wherein the array substrate comprises: the pixel electrode comprises a substrate base plate, a first metal layer, the public electrode layer, a first PN junction layer, an insulating layer, a semiconductor layer, a second metal layer, a first passivation layer, a third metal layer, a second passivation layer, the pixel electrode layer, a second PN junction layer, a third passivation layer and a first oxide conductive layer;
the first metal layer and the common electrode layer are positioned above the substrate, the first metal layer comprises a plurality of gate lines and metal spacing units, the metal spacing units are positioned above the substrate and the common electrode layer, and the first PN junction layer is positioned above the common electrode layer;
the insulating layer is positioned above the substrate base plate, the first metal layer, the public electrode layer and the first PN junction layer, the semiconductor layer is positioned above the insulating layer, and the second metal layer is positioned above the semiconductor layer and the insulating layer;
The first passivation layer is located above the insulating layer, the semiconductor layer and the second metal layer, the third metal layer is located above the first passivation layer, the third metal layer comprises a plurality of reset signal lines, and the second passivation layer is located above the first passivation layer and the third metal layer;
the pixel electrode layer is positioned above the second passivation layer, and each pixel electrode in the pixel electrode layer is contacted with the second metal layer and the metal interval unit through a via hole;
The second PN junction layer is located above the pixel electrode layer, the third passivation layer is located above the second passivation layer, the pixel electrode layer and the second PN junction layer, and the first oxide conductive layer is located above the third passivation layer.
5. A liquid crystal display panel, comprising a color film substrate, an array substrate according to any one of claims 1 to 4, and a liquid crystal layer between the array substrate and the color film substrate, wherein the color film substrate and the array substrate are disposed opposite to each other.
6. The liquid crystal display panel according to claim 5, wherein a second oxide conductive layer is disposed under the color film substrate, the second oxide conductive layer is disposed in a partitioned manner, and the first oxide conductive layer and the second oxide conductive layer of the array substrate have a uniform pattern.
7. A liquid crystal display panel driving method, characterized by being applied to the liquid crystal display panel according to claim 5 or 6, comprising:
For each pixel unit in the liquid crystal display panel, determining a second voltage of a second electrode corresponding to the pixel unit according to the pre-display gray scale of the pixel unit and the first voltage of the first electrode corresponding to the pixel unit; the first electrode is a common electrode, the second electrode is a pixel electrode, or the first electrode is a pixel electrode, and the second electrode is a common electrode;
Outputting the second voltage to the second electrode.
8. The method of claim 7, wherein determining the second voltage of the second electrode corresponding to the pixel cell according to the pre-display gray level of the pixel cell and the first voltage of the first electrode corresponding to the pixel cell comprises:
Determining an absolute value of a voltage difference between the first electrode and the second electrode according to the pre-display gray scale of the pixel unit;
when the first electrode is a common electrode, determining the sum of the first voltage and the absolute value of the voltage difference as the second voltage;
When the first electrode is a pixel electrode, a difference between the first voltage and the absolute value of the voltage difference is determined as the second voltage.
9. A liquid crystal display device comprising a backlight and the liquid crystal display panel of claim 5 or 6, wherein the backlight is located at a side of the array substrate facing away from the color film substrate.
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| KR20080061720A (en) * | 2006-12-28 | 2008-07-03 | 엘지디스플레이 주식회사 | Array Board for Liquid Crystal Display |
| CN106338864B (en) * | 2016-08-25 | 2023-10-03 | 合肥京东方光电科技有限公司 | Array substrate, driving method, liquid crystal display panel and display device |
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| CN108873513B (en) * | 2018-06-07 | 2021-12-14 | 昆山龙腾光电股份有限公司 | Array substrate, liquid crystal display panel and driving method thereof |
| CN109164655B (en) * | 2018-09-28 | 2021-03-23 | 合肥鑫晟光电科技有限公司 | Array substrate, display device, manufacturing and driving methods of array substrate and display device, and substrate manufacturing method |
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