CN115867124B

CN115867124B - Phase-change memory unit, phase-change memory, preparation method of phase-change memory and electronic equipment

Info

Publication number: CN115867124B
Application number: CN202310116278.4A
Authority: CN
Inventors: 廖昱程; 刘文杰; 文浚硕
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-02-15
Filing date: 2023-02-15
Publication date: 2023-04-28
Anticipated expiration: 2043-02-15
Also published as: CN115867124A

Abstract

The disclosure relates to a phase-change memory cell, a phase-change memory, a preparation method of the phase-change memory cell and electronic equipment. The phase change memory cell includes: the device comprises a first electrode, a heater, an insulating layer, a heat insulating layer, a phase change layer and a second electrode; wherein, the heater includes: at least two heating structures arranged on the first electrode at intervals; the insulating layer is arranged on the outer side wall of the heater; the heat insulation layer is arranged at the bottom of the interval between the adjacent heating structures and at the tops of the heating structures and the insulating layer; the phase change layer fills at least the space between adjacent heating structures; the second electrode covers the phase change layer. The method and the device can improve heating uniformity and heating efficiency, reduce the risk of thermal crosstalk between adjacent phase change memory cells, reduce RC delay and optimize the memory performance of the phase change memory.

Description

Phase-change memory unit, phase-change memory, preparation method of phase-change memory and electronic equipment

Technical Field

The disclosure relates to the technical field of memories, in particular to a phase-change memory cell, a phase-change memory, a preparation method of the phase-change memory and electronic equipment.

Background

With the wide application of various technologies such as mobile internet, cloud computing, big data, deep learning, and internet of things, the demand of the data storage field for ultra-high storage density and ultra-large storage capacity is rapidly increasing. The phase change memory (Phase Change Memory, PCM for short) has the advantages of low power consumption, high density, small size and the like, and can be used as one of nonvolatile memory technologies with good application prospect.

Currently, phase change memories store data mainly by the difference in conductivity exhibited by phase change materials when they are transformed between crystalline and amorphous states by means of heat generated by electrical pulses. In addition, adjacent phase change memory cells in the phase change memory are mainly isolated by an insulating medium. During each read and write operation of the phase change memory cell, the phase change memory cell may experience a temperature increase. However, if the insulating medium has poor heat insulating ability, heat is easily diffused to adjacent phase change memory cells, resulting in a phenomenon in which thermal crosstalk occurs, thereby affecting the memory performance of the phase change memory.

Disclosure of Invention

The embodiment of the disclosure provides a phase-change memory unit, a phase-change memory, a preparation method thereof and electronic equipment, which are beneficial to improving heating uniformity and heating efficiency, reducing the risk of thermal crosstalk between adjacent phase-change memory units, reducing RC delay, and optimizing the memory performance of the phase-change memory.

In one aspect, some embodiments of the present disclosure provide a phase change memory cell, comprising: the device comprises a first electrode, a heater, an insulating layer, a heat insulating layer, a phase change layer and a second electrode; wherein, the heater includes: at least two heating structures arranged on the first electrode at intervals; the insulating layer is arranged on the outer side wall of the heater; the heat insulation layer is arranged at the bottom of the interval between the adjacent heating structures and at the tops of the heating structures and the insulating layer; the phase change layer fills at least the space between adjacent heating structures; the second electrode covers the phase change layer.

According to some embodiments of the present disclosure, the number of first electrodes and heaters is two; wherein, the insulating layer between the two heaters is connected into an integrated structure; the phase change layers corresponding to the two heaters are connected into an integrated structure.

According to some embodiments of the present disclosure, two heaters and each heating structure in the same heater are arranged at intervals in a first direction; wherein, the heat insulation layers which are positioned at the tops of the two heaters and are adjacent to each other in the first direction are connected; the phase change layer also covers the insulating layer and extends in the first direction.

According to some embodiments of the present disclosure, two heaters are arranged at intervals in a first direction, and each heating structure in the same heater is arranged at intervals in a second direction; wherein the first direction and the second direction intersect; the phase change layer is located in the space between adjacent heating structures and extends in a first direction.

According to some embodiments of the present disclosure, a heating structure includes: a nitride laminated structure in which titanium nitride layers and tantalum nitride layers are alternately laminated.

According to some embodiments of the present disclosure, the insulating layer comprises a zirconium dioxide layer.

According to some embodiments of the present disclosure, the thickness of the insulating layer is less than or equal to one half the height of the heating structure.

In another aspect, some embodiments of the present disclosure provide a phase change memory, comprising: a substrate, and a phase change memory cell disposed on the substrate and as described in some embodiments above.

According to some embodiments of the present disclosure, the phase change memory further includes: the transistor is gated. The gate transistor is located between the substrate and the first electrode and is connected to the first electrode.

According to some embodiments of the present disclosure, the phase change memory further includes: an interlayer dielectric layer. The interlayer dielectric layer covers the substrate and the gating transistor and is provided with a containing groove; the phase change memory unit is arranged in the accommodating groove.

According to some embodiments of the present disclosure, the phase change memory further includes: and a read signal line. The read signal line is positioned on the interlayer dielectric layer and connected with the second electrode.

According to some embodiments of the present disclosure, the phase change memory further includes: a low-K dielectric layer. The low-K dielectric layer is located between the interlayer dielectric layer and the read signal line.

According to some embodiments of the present disclosure, the low-K dielectric layer includes a silicon carbonitride layer, a silicon oxynitride layer, or a silicon oxycarbide layer.

In yet another aspect, some embodiments of the present disclosure provide a method for manufacturing a phase change memory, where the method is used to manufacture the phase change memory in some embodiments. The preparation method of the phase change memory comprises the following steps.

A substrate is provided.

An interlayer dielectric layer is formed on the substrate, and the interlayer dielectric layer is provided with a containing groove.

And forming a first electrode material layer and a heating material layer in the accommodating groove in an inner layer.

Patterning the heating material layer and the first electrode material layer to form a heater and a first electrode. The heater includes at least two heating structures disposed on the first electrode at intervals.

An insulating layer is formed to cover the outer sidewall of the heater.

And forming a heat insulation layer at the bottom of the interval between the adjacent heating structures and at the tops of the heating structures and the insulating layer.

At least the phase change layer is formed in the interval between adjacent heating structures.

A second electrode is formed overlying the phase change layer.

According to some embodiments of the present disclosure, patterning the heating material layer and the first electrode material layer to form a heater and a first electrode further includes: two first electrodes arranged at intervals in a first direction are formed, and heaters are respectively positioned on the two first electrodes. Wherein, each heating structure in the same heater is arranged at intervals in the first direction; alternatively, the heating structures in the same heater are arranged at intervals in the second direction; the second direction intersects the first direction.

According to some embodiments of the present disclosure, the heating material layer includes a nitride stack of alternating layers of titanium nitride material and tantalum nitride material.

According to some embodiments of the present disclosure, the forming of the insulating layer at the bottom of the space between adjacent heating structures, and at the top of the heating structures and insulating layer, includes: forming a heat insulating material layer filling the space between adjacent heating structures and covering the heating structures and the insulating layer; the insulating material layer is patterned to form an insulating layer and expose a portion of the inner sidewall of the heating structure.

According to some embodiments of the present disclosure, the forming the second electrode covering the phase change layer further includes the following steps.

And forming a low-K dielectric material layer for covering the inter-layer dielectric layer and the phase-change layer.

And patterning the low-K dielectric material layer to form the low-K dielectric layer. The low-K dielectric layer has an opening exposing the phase change layer.

And forming a second electrode in the opening.

According to some embodiments of the disclosure, the method further comprises: a read signal line is formed on the low-K dielectric layer and the second electrode.

In yet another aspect, some embodiments of the present disclosure provide an electronic device, comprising: the phase change memory as described in some embodiments above.

In the embodiment of the disclosure, at least two heating structures are arranged on the first electrode at intervals, so that the heating structures on the same first electrode form a heater together, thereby improving the heating efficiency of the heater and effectively improving the heating uniformity of the heater through the interval distribution of the heating structures in the heater. And, this disclosed embodiment sets up the insulating layer on the lateral wall of heater to set up the insulating layer in the bottom of interval between adjacent heating structure and the top of heating structure and insulating layer, not only can ensure to have great area of contact between insulating layer and the heating structure, can also effectively separate the heating structure and carry out the heat conduction to its top surface direction and adjacent heating structure. Thereby facilitating concentration of heat from the heater within the space between adjacent heating structures and effectively providing for a phase change layer filling at least the space between adjacent heating structures to optimize the memory performance of the phase change memory cell. Thereby optimizing the storage performance of the phase change memory.

In addition, in some embodiments of the present disclosure, the phase change memory unit is disposed in the accommodating groove of the interlayer dielectric layer, and the insulating layer and the interlayer dielectric layer on the outer sidewall of the heater can be utilized to perform good heat preservation and insulation on the heater, and effectively block the heater from conducting heat in the direction of the outer sidewall, so that the risk of thermal crosstalk between adjacent phase change memory units is effectively reduced, and the memory performance of the phase change memory unit and the phase change memory is further improved.

In some embodiments of the present disclosure, the second electrode is disposed in the opening of the low-K dielectric layer and is connected to the read signal line on the surface of the low-K dielectric layer. The low-K dielectric layer is, for example, a silicon carbonitride layer, and is also beneficial to reducing RC delay through the material characteristics of the low-K dielectric layer with lower dielectric constant so as to further improve the storage performance of the phase-change memory cell and the phase-change memory.

Drawings

In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1a is a schematic top view of a phase change memory according to some embodiments;

FIG. 1b is a schematic cross-sectional view of the phase change memory of FIG. 1a along the direction A-A';

FIG. 2 is a schematic circuit diagram of a phase change memory cell provided in some embodiments;

FIG. 3 is a schematic diagram of a phase change memory cell according to some embodiments;

FIG. 4 is a schematic diagram of another phase change memory cell provided in some embodiments;

FIG. 5a is a schematic diagram of another phase change memory provided in some embodiments;

FIG. 5b is a schematic cross-sectional view of the phase change memory of FIG. 5a along the direction A-A';

FIG. 6 is a flow chart of a method of fabricating a phase change memory according to some embodiments;

FIG. 7 is a schematic flow chart of a method for preparing a thermal insulation layer according to some embodiments;

FIG. 8 is a flow chart of a method for fabricating a second electrode and a read signal line according to some embodiments;

FIG. 9 is a schematic diagram of a structure resulting from the formation of a gate transistor, as provided in some embodiments;

FIG. 10 is a schematic diagram of a structure after forming an interlayer dielectric layer according to some embodiments;

FIG. 11 is a schematic diagram of the structure resulting after formation of a nitride material stack, as provided in some embodiments;

FIG. 12 is a schematic illustration of the resulting structure after formation of a heating structure, as provided in some embodiments;

FIG. 13 is a schematic illustration of the resulting structure after formation of a layer of insulating material, as provided in some embodiments;

FIG. 14 is a schematic diagram of the structure after formation of an insulating layer, as provided in some embodiments;

FIG. 15 is a schematic structural view of a resulting structure after formation of a layer of insulating material, as provided in some embodiments;

FIG. 16 is a schematic illustration of the structure after formation of an insulating layer, as provided in some embodiments;

FIG. 17 is a schematic diagram of the resulting structure after formation of a low-K dielectric material layer, as provided in some embodiments;

FIG. 18 is a schematic diagram of a structure after forming read signal lines according to some embodiments.

Reference numerals illustrate:

1-substrate, STI-shallow trench isolation structure; u-phase change memory cell, M-gating transistor, SL-gating signal line;

21-a first electrode, 22-a heater, 22-a heating structure, 23-an insulating layer, 24-a heat insulating layer, 25-a phase change layer, 26-a second electrode;

221-titanium nitride layer, 222-tantalum nitride layer; 210-a first electrode material layer, 230-an insulating material layer, 240-a heat insulating material layer;

an L1-titanium nitride material layer, an L2-tantalum nitride material layer; 31-drain region, 32-source region, 33-gate structure, 34-contact structure;

331-gate dielectric layer, 332-gate, 333-isolation layer; 4-an interlayer dielectric layer, 41-a first sub-layer, 42-a second sub-layer and a G-containing groove;

a 5-read signal line, a 6-low K dielectric layer; a layer of 60-low K dielectric material; k-opening.

Detailed Description

In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present.

It will be understood that, although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, in this specification, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.

The phase change memory (Phase Change Memory, PCM) can be used for data storage in electronic devices such as mobile phones, tablet computers, notebook computers, wearable devices, vehicle-mounted devices and the like. The phase change memory is used as a nonvolatile memory and can be prepared based on a chalcogenide phase change material. The memory cells in the phase change memory can realize the conversion of different resistance states under the action of heat. Therefore, the read-write operation and storage of data can be realized by utilizing the resistance difference of the memory cell in different resistance states.

Referring to fig. 1a and 1b, some embodiments of the present disclosure provide a phase change memory cell and a phase change memory, which can improve heating uniformity and heating efficiency, reduce risk of thermal crosstalk between adjacent phase change memory cells, and reduce RC delay, thereby optimizing memory performance of the phase change memory.

In some embodiments of the present disclosure, as shown in fig. 1a and 1b, a phase change memory includes 1: substrate 1 and phase change memory cell U disposed on substrate 1.

Illustratively, the substrate 1 may be constructed of a semiconductor material, an insulating material, a conductor material, or any combination thereof. For example, the substrate 1 may be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Alternatively, the substrate 1 may be a layered substrate comprising, for example, si/SiGe, si/SiC, silicon-on-insulator (SOI) or silicon-germanium-on-insulator.

For example, the number of phase change memory cells U may be one or more. In some examples, the plurality of phase change memory cells U may be arranged in one layer or stacked in multiple layers in a direction (e.g., Z direction) perpendicular to the substrate 1.

For example, in embodiments having multiple layers of phase change memory cells U, the relative positions between the phase change memory cells U in each layer may be in an array or honeycomb distribution, or other shaped distribution. Here, a honeycomb-shaped distribution is understood to mean a distribution of a plurality of rows of the phase-change memory cells U and a dislocation distribution between adjacent rows of the phase-change memory cells U such that the geometric center of each phase-change memory cell U of a column of the phase-change memory cells U is not on a straight line, i.e., does not constitute an array distribution. The honeycomb-shaped distribution is only for illustrating the relative positions of the geometric centers of the phase change memory cells U, and does not limit the outer contour shape of the phase change memory cells U themselves.

In some embodiments of the present disclosure, referring to fig. 1b, a phase change memory cell U includes: a first electrode 21, a heater 22, an insulating layer 23, a heat insulating layer 24, a phase change layer 25, and a second electrode 26. The heater 22 includes: at least two heating structures 22A disposed on the first electrode 21 at intervals. An insulating layer 23 is provided on the outer side wall of the heater 22. The insulating layer 24 is disposed at the bottom of the space between adjacent heating structures 22A, and at the top of the heating structures 22A and insulating layer 23. The phase change layer 25 fills at least the space between adjacent heating structures 22A. The second electrode 26 covers the phase change layer 25.

Illustratively, the first electrode 21 and the second electrode 26 are disposed opposite to each other in a direction (e.g., Z direction) perpendicular to the substrate 1. The heater 22, the insulating layer 24 and the phase change layer 25 are all located between the first electrode 21 and the second electrode 26.

Illustratively, the materials of the first electrode 21 and the second electrode 26 include, but are not limited to, metals or metal compounds having excellent electrical conductivity. The first electrode 21 and the second electrode 26 may have a single-layer structure or a stacked-layer structure.

In some examples, the first electrode 21 is a single-layer structure, and the first electrode 21 is, for example, a titanium (Ti) layer or a titanium nitride (TiN) layer, or a mixed layer of a titanium (Ti) layer and a titanium nitride (TiN) layer.

In some examples, the second electrode 26 is a stacked structure, and the second electrode 26 includes, for example, a stack of a titanium (Ti) layer and a tungsten (W) metal layer, or a stack of a titanium nitride (TiN) layer and a tungsten (W) metal layer, which are stacked.

For example, the number of the first electrodes 21 in the phase change memory cell U may be one or more. The heaters 22 are in one-to-one correspondence with the first electrodes 21, and the heaters 22 may be disposed on a surface of the first electrodes 21 facing away from the substrate 1. The heater 22 includes, for example, 2 or more heating structures 22A arranged at intervals.

In some examples, each heating structure 22A in the heater 22 is spaced apart, which may be represented as: the heating structures 22A are uniformly distributed on the edge of the heater 22, so that the central area of the heater 22 is empty and can be used for accommodating the heat insulating layer 24 and the phase change layer 25. Thus, the insulating layer 23 is provided on the outer side wall of the heater 22, and can be expressed as: an insulating layer 23 is provided on the side wall of each heating structure 22A facing away from the central region of the heater 22.

In some examples, insulating layer 23 includes a low temperature silicon nitride layer and a high temperature silicon nitride layer in a stacked arrangement. The deposition temperature of the low-temperature silicon nitride layer is 550 ℃ or lower, and may be 350 ℃, 400 ℃, 500 ℃, 550 ℃ or the like. The deposition temperature of the high temperature silicon nitride layer is 600 ℃ or higher, and may be 600 ℃, 800 ℃, 900 ℃, 1200 ℃ or the like, for example.

In some examples, heating structure 22A includes: a nitride stack structure in which titanium nitride (TiN) layers 221 and tantalum nitride (TaN) layers 222 are alternately stacked. Among them, the number of layers of the titanium nitride (TiN) layer 221 and the tantalum nitride (TaN) layer 222 may be set according to the need. The number of layers of titanium nitride (TiN) layer 221 and tantalum nitride (TaN) layer 222 in heating structure 22A is illustrated in fig. 1b as only two, but it is understood that there may be more layers of titanium nitride (TiN) layer 221 and tantalum nitride (TaN) layer 222.

Here, the Conductivity (connectivity) of the titanium nitride (TiN) layer 221 is greater than the Conductivity of the tantalum nitride (TaN) layer 222, and the Resistivity (Resistivity) of the titanium nitride (TiN) layer 221 is less than the Resistivity of the tantalum nitride (TaN) layer 222.

Illustratively, the thermal insulation layer 24 is disposed at the bottom of the space between adjacent heating structures 22A, and the tops of the heating structures 22A and the insulating layer 23, so that a large contact area between the thermal insulation layer 24 and the heating structures 22A can be ensured. For example, the portion of the insulating layer 24 at the bottom of the space between the adjacent heating structures 22A can reduce the contact area between the phase change layer 25 and the heating structures 22A, effectively block heat conduction between the adjacent heating structures 22A, and increase joule heat, and the portion of the insulating layer 24 at the top surfaces of the heating structures 22A and the insulating layer 23 can effectively block heat conduction from the heating structures 22A to the top surfaces thereof.

In some examples, the insulating layer 24 includes a layer of zirconium dioxide (ZrO 2), which may have a low thermal conductivity, to facilitate the thermal isolation effect of the insulating heat 24.

In some examples, the thickness of the insulating layer 24 is less than or equal to one-half the height of the heating structure 22A, which may ensure that the contact area of the insulating layer 24 with the heating structure 22A can meet the insulation requirements.

Illustratively, the phase change layer 25 fills at least the space between adjacent heating structures 22A, and may be represented as: the phase change layer 25 fills only the spaces between adjacent heating structures 22A (i.e., contacts the sidewalls of the heating structures 22A not covered by the insulating layer 24); alternatively, the phase change layer 25 extends to cover the sidewalls and top surface of the insulating layer 24 on the top surface of the heating structures 22A in addition to filling the spaces between adjacent heating structures 22A.

It is understood that the phase change layer 25 may have two or more resistance states, and that the resistance values of the phase change layer 25 in different resistance states are different. Some embodiments of the present disclosure are illustrated with the phase change layer 25 having a first resistance state and a second resistance state, and the resistance value of the phase change layer 25 in the first resistance state is different from the resistance value of the phase change layer 25 in the second resistance state. In addition, as can be understood from fig. 2, the phase-change memory unit U may be equivalently an adjustable resistor, so by controlling the heater 22 in the phase-change memory unit U, the phase-change layer 25 can be in different resistance states along with the change of heat, so that the read-write operation of data is realized based on the change of the resistance value of the phase-change layer 25.

In some examples, the material of the phase change layer 25 may be a compound including at least one element of germanium (Ge), antimony (Sb), tellurium (Te), gallium (Ga), or bismuth (Bi); alternatively, the material of the phase-change layer 25 may be a material doped with at least one element of carbon (C), nitrogen (N), oxygen (O), silicon (Si), sulfur (S), indium (In), aluminum (Al), tin (Sn), selenium (Se), gold (Au), hafnium (Hf), lead (Pd), copper (Cu), cobalt (Co), silver (Ag), platinum (Pt), scandium (Sc), titanium (Ti), or tantalum (Ta).

From the above, in the embodiment of the present disclosure, at least two heating structures 22A are disposed at intervals on the first electrode 21, so that each heating structure 22A located on the same first electrode 21 forms the heater 22 together, so as to facilitate improving the heating efficiency of the heater 22, and facilitate effectively improving the heating uniformity of the heater 22 through the interval distribution of each heating structure 22A in the heater 22.

In addition, the insulating layer 23 is disposed on the outer sidewall of the heater 22, and the insulating layer 24 is disposed at the bottom of the interval between the adjacent heating structures 22A and at the top of the heating structures 22A and the insulating layer 23, so that a larger contact area between the insulating layer 24 and the heating structures 22A can be ensured, and the heating structures 22A can be effectively prevented from conducting heat to the top surface direction and the adjacent heating structures 22A. Thereby facilitating concentration of heat from the heater 22 within the spaces between adjacent heating structures 22A and effectively providing for at least the phase change layer 25 filling the spaces between adjacent heating structures 22A to optimize the memory performance of the phase change memory cell U. Thereby optimizing the storage performance of the phase change memory.

It should be noted that, in some embodiments of the present disclosure, please continue to refer to fig. 1a and 1b, the number of the first electrodes 21 and the heaters 22 in the phase change memory unit U is two; wherein the insulating layer 23 between the two heaters 22 is connected as an integral structure; the phase change layers 25 corresponding to the two heaters 22 are connected as an integral structure. That is, two heaters 22 may be insulated by the same insulating layer 23, and two heaters 22 may be used to control the same phase change layer 25.

Here, it is understood that the phase change layer 25 serves as a data storage portion of the phase change memory cell U, and one phase change memory cell U may have one phase change layer 25. And the number of the first electrode 21 and the heater 22 may be two or more. In an example in which the number of the first electrodes 21 and the heaters 22 is greater in the phase change memory cell U, the insulating layers 23 between any adjacent heaters 22 may be integrally connected, and the phase change layers 25 between any adjacent heaters 22 may be integrally connected.

On the basis of the foregoing examples, the following embodiments of the present disclosure are illustrated with two numbers of the first electrodes 21 and the heaters 22 in the phase change memory cells U, but it is understood that the technical solutions in the following embodiments can be extended to the examples with more numbers of the first electrodes 21 and the heaters 22 in the phase change memory cells U, which are not limited to this embodiment.

In some embodiments of the present disclosure, referring to fig. 3, two heaters 22 and each heating structure 22A in the same heater 22 are arranged at intervals in a first direction (for example, X direction); wherein the heat insulating layers 23 located on top of the two heaters 22 and adjacent in a first direction (for example, X direction) are connected; the phase change layer 25 also covers the insulating layer 23 and extends in a first direction (e.g., X-direction). In this manner, it is convenient to achieve a sequential arrangement of the heaters 22 in a first direction (e.g., the X-direction) to occupy a smaller area in a second direction (e.g., the Y-direction). In addition, each heater 22 in the same phase change memory cell U can be driven and controlled by the electric signal provided by the corresponding first electrode 21, and each heater 22 can share the same second electrode 26.

In other embodiments of the present disclosure, referring to fig. 4, two heaters 22 are arranged at intervals in a first direction (e.g., X-direction), and each heating structure 22A in the same heater 22 is arranged at intervals in a second direction (e.g., Y-direction). Wherein the first direction and the second direction intersect, e.g. perpendicular. The phase change layer 25 is located in the space between adjacent heating structures 22A and extends in a first direction (e.g., X-direction). In this manner, it is convenient to achieve a side-by-side arrangement of the heaters 22 in a first direction (e.g., the X-direction) to occupy a smaller area in the first direction (e.g., the X-direction). In addition, each heater 22 in the same phase change memory cell U can be driven and controlled by the electric signal provided by the corresponding first electrode 21, and each heater 22 can share the same phase change layer 25 and the same second electrode 26. In addition, the phase change layer 25 and the second electrode 26 in the same phase change memory cell U may be disposed in the space between the adjacent heating structures 22A in each heater 22.

Referring to fig. 5a and 5b, in another phase change memory provided in the embodiments of the present disclosure, the first electrode 21 and the heater 22 in the phase change memory unit U are configured as shown in fig. 4, and the structure of the phase change memory can be understood in conjunction with the description of the foregoing embodiments, which is not described in detail herein.

It should be noted that, in the phase change memory provided in some embodiments of the present disclosure, please continue to refer to fig. 1a, fig. 1b, fig. 2, fig. 5a and fig. 5b, the phase change memory further includes: the transistor M is gated. The gate transistor M is located between the substrate 1 and the first electrode 21, and is connected to the first electrode 21.

Here, the gate transistors M may be disposed in one-to-one correspondence with the first electrodes 21 to independently control the corresponding heaters 22 through the first electrodes 21.

Illustratively, the gating transistor M includes: a drain 31, a source 32, and a gate structure 33 between the drain 31 and the source 32. Wherein the drain electrode 31 and the source electrode 32 may be obtained by doping regions of corresponding regions of the substrate 1, and a portion of the substrate 1 between the drain electrode 31 and the source electrode 32 may constitute a channel region. The gate structure 33 includes: a gate dielectric layer 331 covering at least the channel region, a gate 332 on the top surface of the gate dielectric layer 331, and an isolation layer 333 surrounding the sidewalls and top surface of the gate 332.

As can be appreciated in connection with the schematic circuit diagram shown in fig. 2, the gate 332 of the gating transistor M may be connected to the control word line WL, the source 32 may be connected to the gating signal line SL, and the drain 31 may be connected to the first electrode 21 of the phase change memory cell U. The control word line WL may control the on and off of the gate transistor M to correspond to control the heating state of the heater 22.

In some embodiments of the present disclosure, as shown in fig. 1b and 5b, the phase change memory further includes: an interlayer dielectric layer 4. The interlayer dielectric layer 4 covers the substrate 1 and the gate transistor M and has a receiving groove (not shown in fig. 1 b); the phase change memory unit U is arranged in the accommodating groove.

Illustratively, the interlayer dielectric layer 4 is formed using an insulating material. The interlayer dielectric layer 4 can be one layer or multiple layers according to the preparation process of the gating transistor M.

Illustratively, the surface of the phase change layer 25 facing away from the substrate 1 is flush with the surface of the interlayer dielectric layer 4 facing away from the substrate 1.

In the embodiment of the disclosure, the phase change memory unit U may be disposed in the interlayer dielectric layer 4 based on a receiving slot in the interlayer dielectric layer 4 for receiving the phase change memory unit U. Therefore, the insulating layer 23 and the interlayer dielectric layer 4 on the outer side wall of the heater 22 can be utilized to perform good heat preservation and insulation on the heater 22, and the heater 22 is effectively prevented from conducting heat in the direction of the outer side wall, so that the risk of thermal crosstalk between adjacent phase-change memory units U is effectively reduced, and the memory performance of the phase-change memory units U is further improved.

In some embodiments of the present disclosure, referring to fig. 1a, 1b, 2, 5a and 5b, the phase change memory further includes: the signal line 5 is read. The read signal line 5 is located on the interlayer dielectric layer 4 and connected to the second electrode 26. The read signal line 5 is, for example, a read bit line BL.

In some embodiments of the present disclosure, please continue with fig. 1a, 1b, 5a and 5b, the phase change memory further includes: a low K dielectric layer 6. A low K dielectric layer 6 is located between the interlayer dielectric layer 4 and the read signal line 5.

Here, K is the dielectric constant, which is a measure of the ability of a material to store a charge. The low-K dielectric layer 6 is formed of a low-K dielectric material, and the K value is typically less than 3.0.

Illustratively, the low-K dielectric layer 6 includes a silicon carbonitride (SiCN) layer, a silicon oxynitride (SiON) layer, or a silicon oxycarbide (SiOC) layer.

In some embodiments, as shown in fig. 1b, the low-K dielectric layer 6 has an opening K, and the second electrode 26 is disposed in the opening K of the low-K dielectric layer 6, and a surface of the second electrode 26 facing away from the substrate 1 is flush with a surface of the low-K dielectric layer 6 facing away from the substrate 1. In the embodiment of the disclosure, the second electrode 26 is disposed in the opening of the low-K dielectric layer 6 and is connected to the read signal line 5 on the surface of the low-K dielectric layer 6, which is further beneficial to reducing RC delay through the material characteristic of the low-K dielectric layer 6 with a lower dielectric constant, so as to further improve the storage performance of the phase-change memory cell U.

In other embodiments, as shown in fig. 5b, the low-K dielectric layer 6 has an opening, and the second electrode 26 is disposed in the opening of the low-K dielectric layer 6. And, the read signal line 5 may be disposed in the corresponding trench of the low-K dielectric layer 6 and contact-connected with the second electrode 26 disposed in the opening of the low-K dielectric layer 6. Thus, the material characteristics of the low-K dielectric layer 6 with a lower dielectric constant are also facilitated, and the RC delay is reduced, so as to further improve the storage performance of the phase-change memory cell U.

Referring to fig. 6, some embodiments of the present disclosure provide a method for manufacturing a phase change memory, which is used to manufacture the phase change memory in some embodiments. The preparation method of the phase change memory comprises the following steps.

S100, providing a substrate.

S200, forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer is provided with a containing groove.

S300, a first electrode material layer and a heating material layer are formed in the accommodating groove in an inner layer mode.

And S400, patterning the heating material layer and the first electrode material layer to form a heater and a first electrode. The heater includes at least two heating structures disposed on the first electrode at intervals.

S500, forming an insulating layer covering the outer side wall of the heater.

And S600, forming a heat insulation layer at the bottom of the interval between the adjacent heating structures and at the tops of the heating structures and the insulating layer.

And S700, forming a phase change layer at least in the interval of the adjacent heating structures.

S800, forming a second electrode covering the phase change layer.

Thus, the first electrode, the heater, the insulating layer, the heat insulating layer, the phase change layer and the second electrode jointly form the phase change memory cell.

In the embodiment of the disclosure, each heating structure of the heater in the phase change memory unit can be obtained by forming the heating material layer in the accommodating groove and then patterning after forming the accommodating groove in the interlayer dielectric layer, so that the preparation process of the heater is simplified. And the first electrode and the corresponding heating structure in the phase-change memory unit can be formed in a patterning way by adopting the same etching process, so that the preparation process of the phase-change memory unit is further simplified. Thereby being beneficial to improving the production efficiency.

Further, it is understood that the number of phase change memory cells in a phase change memory may be one or more. The method for manufacturing the phase change memory according to the embodiments of the present disclosure does not limit the number of phase change memory cells; that is, one or more phase change memory cells may be prepared according to the aforementioned preparation method.

In some embodiments of the present disclosure, the heating material layer comprises a nitride stack of alternating layers of titanium nitride material and tantalum nitride material.

In some embodiments of the present disclosure, taking a phase change memory cell as an example, the patterning of the heating material layer and the first electrode material layer in step S400 to form the heater and the first electrode further includes: two first electrodes arranged at intervals in a first direction are formed, and heaters are respectively positioned on the two first electrodes. Wherein the heating structures in the same heater are all arranged at intervals in a first direction, such as shown in fig. 3; alternatively, the heating structures in the same heater are arranged at intervals in the second direction, such as shown in fig. 4; the second direction intersects the first direction.

Here, it is understood that the first electrodes are in one-to-one correspondence with the heaters, and the number of the first electrodes in the phase change memory cell is not limited to two. In the embodiment of the present disclosure, two are illustrated, but the arrangement of the two first electrodes and the corresponding heaters may be referred to and extended to more.

In some embodiments of the present disclosure, referring to fig. 7, step S600 forms a thermal insulating layer at the bottom of the space between adjacent heating structures, and at the top of the heating structures and the insulating layer, which may include S610 and S620.

And S610, forming a heat insulation material layer which fills the interval between the adjacent heating structures and covers the heating structures and the insulation layer.

Illustratively, the insulating material layer is a zirconium dioxide (ZrO 2) layer.

And S620, patterning the heat insulation material layer to form a heat insulation layer, and exposing part of the inner side wall of the heating structure.

In the embodiment of the disclosure, after each heating structure is formed, the heat insulation layer respectively located at the bottom of the interval between adjacent heating structures and the heat insulation layer located at the top surfaces of the heating structures and the heat insulation layer can be obtained by filling the heat insulation material layer and etching back based on the step difference between the heating structures and the first electrode, so that the preparation process of the heat insulation layer is simplified.

As shown in fig. 8, in some embodiments of the present disclosure, step S800 forms a second electrode covering the phase change layer, which may include S810 to S830.

And S810, forming a low-K dielectric material layer for covering the inter-layer dielectric layer and the phase change layer.

S820, patterning the low-K dielectric material layer to form the low-K dielectric layer. The low-K dielectric layer has an opening exposing the phase change layer.

And S830, forming a second electrode in the opening.

Illustratively, the low-K dielectric material layer is a silicon carbonitride (SiCN), silicon oxynitride (SiON) or silicon oxycarbide (SiOC) layer.

In some embodiments of the present disclosure, referring to fig. 8, the preparation method further includes S900.

S900, forming a reading signal line on the low-K dielectric layer and the second electrode.

In order to more clearly illustrate the method for fabricating the phase change memory in some of the above embodiments, the following embodiments describe a method for fabricating the phase change memory in the embodiments of the disclosure in detail with reference to fig. 9 to 18, and the structure of the phase change memory is shown in fig. 1b, for example. In addition, the preparation method of the phase change memory shown in fig. 5b can be adaptively performed with reference to the preparation method of the phase change memory shown in fig. 1 b.

In step S100, referring to fig. 9, a substrate 1 is provided.

Illustratively, an array of gating transistors M is prepared on one side of the substrate 1.

Illustratively, the gating transistor M includes: a drain 31, a source 32, and a gate structure 33 between the drain 31 and the source 32. Wherein the drain electrode 31 and the source electrode 32 may be obtained by doping regions (e.g., a drain region D and a source region S) of corresponding regions of the substrate 1, and a portion of the substrate 1 between the drain electrode 31 and the source electrode 32 may constitute a channel region. The gate structure 33 includes: a gate dielectric layer 331 covering at least the channel region, a gate 332 on the top surface of the gate dielectric layer 331, and an isolation layer 333 surrounding the sidewalls and top surface of the gate 332.

In some examples, substrate 1 is a P-type substrate, drain region D and source region S are N-type doped regions, respectively, and may correspond to drain 31 and source 32 as gate transistor M.

In some examples, gate dielectric layer 331 includes, but is not limited to, an oxide layer, which may be, for example, a silicon oxide layer.

In some examples, isolation layer 333 includes, but is not limited to, a silicon nitride layer.

As can be appreciated in connection with the schematic circuit diagram shown in fig. 2, the gate 332 of the gating transistor M may be connected to the control word line WL, the source 32 may be connected to the gating signal line SL, and the drain 31 may be connected to the first electrode 21 of the phase change memory cell U.

In some examples, the gate 332 of the gating transistor M may be integral with the control word line WL, i.e.: the gate 332 of the gate transistor M may be formed as a portion of the same conductive line located in a different region from the control word line WL.

In some examples, both the control word line WL and the gate signal line SL may extend in a first direction (e.g., X direction).

In step S200, as will be understood with reference to fig. 9 and 10, an interlayer dielectric layer 4 is formed on the substrate 1, and the interlayer dielectric layer 4 has a receiving groove G.

In some examples, the interlayer dielectric layer 4 may have a single-layer structure.

In other examples, the interlayer dielectric layer 4 may have a stacked structure, for example, the interlayer dielectric layer 4 includes a first sub-layer 41 and a second sub-layer 42 stacked.

As illustrated in fig. 9, a first sub-layer 41 is formed on the substrate 1 to cover the gate transistor M, the first sub-layer 41 having connection vias that can be connected to the drain electrode 31 and the source electrode 32 of the gate transistor M, respectively, for accommodating the contact structure 34.

Illustratively, as shown in fig. 9, a plurality of gate signal lines SL disposed at parallel intervals are formed on the top surface of the first sub-layer 41 before the second sub-layer 42 is formed; the gate signal line SL may extend in a second direction (e.g., Y direction) and correspondingly cover the plurality of contact structures 34 arranged in the second direction to be connected to the source electrode 32 of the corresponding gate transistor M through each contact structure 34, respectively.

In some examples, the contact structure 34 is formed using a conductive material, such as metallic tungsten (W).

Illustratively, as shown in fig. 10, a second sub-layer 42 is formed covering the first sub-layer 41 and the gate signal line SL. The first sub-layer 41 and the second sub-layer 42 together constitute the interlayer dielectric layer 4. The accommodating groove G penetrates the second sub-layer 42, and may expose a portion of the top surface of the first sub-layer 41 and the contact structure 34 connecting the drain electrode 31 of the gate transistor M.

In step S300, referring to fig. 11, a first electrode material layer 210 and a heating material layer are stacked in the accommodating groove G.

Illustratively, the heating material layer includes a nitride stack of alternating layers of titanium nitride material layers L1 and tantalum nitride material layers L2.

In step S400, referring to fig. 12, the heating material layer and the first electrode material layer 210 are patterned to form the heater 22 and the first electrode 21. The heater 22 includes at least two heating structures 22A disposed on the first electrode 21 at intervals.

Here, the heating material layer may be patterned to obtain each heating structure 22A satisfying the requirement, matching the number and distribution positions of the heating structures 22A in the heater 22. In addition, in the example that the materials of the first electrode material layer 210 and the titanium nitride material layer L1 are the same or similar, the first electrode material layer 210 and the heating material layer may also be formed by patterning by using the same etching process, so as to further simplify the preparation process of the phase change memory cell, thereby improving the production efficiency.

In step S500, referring to fig. 13 and 14, an insulating layer 23 is formed to cover the outer sidewall of the heater 22.

Illustratively, as shown in fig. 13, an insulating material layer 230 is formed that covers the first electrode 21 and the heating structure 22A and fills the accommodating groove G. As shown in fig. 14, the insulating material layer 230 is patterned to leave the portion of the insulating material layer 230 located on the outer sidewall of the heater 22 as the insulating layer 23, and to ensure that the inner sidewall and the top surface of each heating structure 22A are exposed, and the first electrode 21 is exposed in the space between the adjacent heating structures 22A.

In some examples, insulating material layer 230 is formed from a low temperature silicon nitride layer and a high temperature silicon nitride layer stacked together, i.e., the low temperature silicon nitride layer may be prepared prior to the low temperature environment and then the high temperature silicon nitride layer may be prepared in the high temperature environment. Wherein the temperature of the low temperature environment is, for example, 550 ℃ or less, and the temperature of the high temperature environment is, for example, 600 ℃ or more.

In step S600, referring to fig. 15 and 16, a thermal insulation layer 24 is formed at the bottom of the space between the adjacent heating structures 22A, and at the top of the heating structures 22A and the insulating layer 23. Step S600 may include S610 and S620.

In step S610, as shown in fig. 15, the heat insulating material layer 240 filling the space between the adjacent heating structures 22A and covering the heating structures 22A and the insulating layer 23 is formed.

Illustratively, the insulating material layer 240 is a zirconium dioxide (ZrO 2) layer.

In step S620, as shown in fig. 16, the insulating material layer 240 is patterned to form the insulating layer 24 and expose a portion of the inner sidewall of the heating structure 22A.

In step S700, as shown in fig. 17, the phase change layer 25 is formed at least in the interval of the adjacent heating structures 22A.

Illustratively, the phase change layer 25 may also cover the inner sidewall and top surface of the insulating layer 24 on the top surface of the heating structure 22A.

Illustratively, the material of the phase change layer 25 may be a compound including at least one element of germanium (Ge), antimony (Sb), tellurium (Te), gallium (Ga), or bismuth (Bi); alternatively, the material of the phase-change layer 25 may be a material doped with at least one element of carbon (C), nitrogen (N), oxygen (O), silicon (Si), sulfur (S), indium (In), aluminum (Al), tin (Sn), selenium (Se), gold (Au), hafnium (Hf), lead (Pd), copper (Cu), cobalt (Co), silver (Ag), platinum (Pt), scandium (Sc), titanium (Ti), or tantalum (Ta).

In step S800, as will be understood in conjunction with fig. 17 and 18, a second electrode 26 is formed to cover the phase change layer 25. Step S800 may include S810-S830.

In step S810, as shown in fig. 17, the low-K dielectric material layer 60 covering the inter-layer dielectric layer 4 and the phase change layer 25 is formed.

Illustratively, the low-K dielectric material layer 60 is a silicon carbonitride (SiCN) layer.

In step S820, referring to fig. 18, the low-K dielectric material layer 60 is patterned to form a low-K dielectric layer 6. The low-K dielectric layer 6 has an opening K exposing the phase-change layer 25.

Illustratively, the front projection of the opening K onto the substrate 1 overlaps or substantially overlaps with the front projection of the receiving groove G in the interlayer dielectric layer 4 onto the substrate 1.

In step S830, as shown in fig. 18, the second electrode 26 is formed in the opening K.

The second electrode 26 includes, for example, a titanium nitride (TiN) layer and a tungsten (W) metal layer stacked in a direction away from the phase change layer 25.

The surface of the second electrode 26 facing away from the substrate 1 is illustratively flush with the surface of the low-K dielectric layer 6 facing away from the substrate 1.

In step S900, as shown in fig. 18, the read signal line 5 is formed on the low K dielectric layer 6 and the second electrode 26.

The read signal line 5 is, for example, a read bit line BL.

It should be noted that fig. 1a and fig. 5a also respectively show a distribution schematic diagram of a strobe signal line SL, a control word line WL, and a read bit line BL (i.e., a read signal line 5) in the phase change memory; wherein the gate signal lines SL and the control word lines WL extend in the same direction, for example, both extend in a second direction (e.g., Y direction); the read bit lines BL extend in a direction orthogonal to the extending directions of the gate signal lines SL and the control word lines WL, for example, each extending in a first direction (for example, X direction).

Based on this, it can be appreciated that in some examples, the corresponding gating transistors M of the plurality of phase change memory cells U may be distributed in an array in the phase change memory, e.g., arranged in rows along a first direction (e.g., X-direction) and columns along a second direction (e.g., Y-direction). One gate signal line SL and one control word line WL may be correspondingly connected to one column of gate transistors M. And, one read bit line BL may be correspondingly connected to the second electrode 26 of the phase change memory cell U corresponding to one row of the gate transistors M.

It will be appreciated that in the above embodiments of the disclosure, the steps of the method are not strictly limited to the order of execution unless explicitly recited herein, and the steps may not necessarily be executed in the order described, but may be executed in other ways. Moreover, at least a portion of the steps of any one of the steps may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the sub-steps or stages are performed necessarily occur sequentially, but may be performed alternately or alternately with at least a portion of the sub-steps or stages of other steps or other steps.

Some embodiments of the present disclosure also provide an electronic device including a phase change memory as described in some embodiments above. The phase change memory has the technical advantages that the electronic equipment is also provided.

The electronic device includes a circuit board and a phase change memory disposed on the circuit board.

By way of example, electronic devices include computing devices (e.g., servers), network devices (e.g., switches), storage devices (e.g., storage arrays), vehicle devices (e.g., vehicle speakers, vehicle navigators, etc.), and terminal devices (e.g., wearable devices, computers, cell phones, tablet computers, etc.), among others.

The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims

1. A phase change memory cell, comprising:

a first electrode;

a heater, comprising: at least two heating structures arranged on the first electrode at intervals;

an insulating layer disposed on an outer sidewall of the heater;

the heat insulation layer is arranged at the bottom of the interval between the adjacent heating structures and the tops of the heating structures and the insulating layer;

A phase change layer filling at least the space between adjacent heating structures;

and a second electrode covering the phase change layer.

2. The phase change memory cell according to claim 1, wherein the number of the first electrode and the heater is two; wherein,,

the insulating layers between the two heaters are connected into an integrated structure;

the phase change layers corresponding to the two heaters are connected into an integrated structure.

3. The phase change memory cell according to claim 2, wherein two of the heaters and each of the heating structures in the same heater are arranged at intervals in a first direction; wherein,,

the heat insulation layers are positioned at the tops of the two heaters and adjacent to each other in the first direction;

the phase change layer also covers the insulating layer and extends in the first direction.

4. The phase-change memory cell of claim 2, wherein,

the two heaters are arranged at intervals in the first direction, and the heating structures in the same heater are arranged at intervals in the second direction; wherein,,

the first direction and the second direction intersect; the phase change layer is located in a space between adjacent heating structures and extends in the first direction.

5. The phase change memory cell according to any one of claims 1 to 4, wherein the heating structure comprises: a nitride laminated structure in which titanium nitride layers and tantalum nitride layers are alternately laminated.

6. The phase change memory cell according to any one of claims 1-4, wherein the thermal barrier layer comprises a zirconium dioxide layer.

7. The phase-change memory cell of any one of claims 1-4, wherein a thickness of the insulating layer is less than or equal to one half a height of the heating structure.

8. A phase change memory, comprising: a substrate and a phase change memory cell as claimed in any one of claims 1 to 7 disposed on the substrate.

9. The phase change memory of claim 8, further comprising:

and a gate transistor between the substrate and the first electrode and connected to the first electrode.

10. The phase change memory of claim 9, further comprising:

an interlayer dielectric layer which covers the substrate and the gating transistor and is provided with a containing groove;

the phase change memory unit is arranged in the accommodating groove.

11. The phase change memory of claim 10, further comprising:

and the reading signal line is positioned on the interlayer dielectric layer and connected with the second electrode.

12. The phase change memory of claim 11, further comprising:

and the low-K dielectric layer is positioned between the interlayer dielectric layer and the reading signal line.

13. The phase change memory according to claim 12, wherein the low-K dielectric layer comprises a silicon carbonitride layer, a silicon oxynitride layer or a silicon oxycarbide layer.

14. A method of fabricating a phase change memory, comprising:

providing a substrate;

forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer is provided with a containing groove;

forming a first electrode material layer and a heating material layer in the accommodating groove in an inner layer manner;

patterning the heating material layer and the first electrode material layer to form a heater and a first electrode; the heater comprises at least two heating structures which are arranged on the first electrode at intervals;

forming an insulating layer covering the outer side wall of the heater;

forming a heat insulating layer at the bottom of the interval between the adjacent heating structures and at the tops of the heating structures and the insulating layer;

Forming a phase change layer at least in the interval between adjacent heating structures;

and forming a second electrode covering the phase change layer.

15. The method of claim 14, wherein patterning the heating material layer and the first electrode material layer to form a heater and a first electrode, further comprises:

two first electrodes formed to be spaced apart in a first direction, and the heaters respectively located on the two first electrodes; wherein,,

each heating structure in the same heater is arranged at intervals in the first direction;

alternatively, each of the heating structures in the same heater is arranged at intervals in the second direction; the second direction intersects the first direction.

16. The method of claim 14, wherein the heating material layer comprises a nitride stack of alternating layers of titanium nitride material and tantalum nitride material.

17. The method of fabricating a phase change memory according to claim 14, wherein the forming a thermal insulating layer between the bottom of the space between adjacent heating structures and the top of the heating structures and the insulating layer comprises:

Forming a heat insulating material layer filling a space between adjacent heating structures and covering the heating structures and the insulating layer;

patterning the insulating material layer to form the insulating layer and exposing a part of the inner side wall of the heating structure.

18. The method of fabricating a phase change memory according to claim 14, wherein forming a second electrode overlying the phase change layer further comprises:

forming a low-K dielectric material layer covering the interlayer dielectric layer and the phase change layer;

patterning the low-K dielectric material layer to form a low-K dielectric layer; the low-K dielectric layer has an opening exposing the phase change layer;

and forming the second electrode in the opening.

19. The method of manufacturing a phase change memory according to claim 18, further comprising:

and forming a read signal line on the low-K dielectric layer and the second electrode.

20. An electronic device, comprising: the phase change memory according to any one of claims 8 to 13.