CN115865092A - Analog-digital conversion controller, control method and system - Google Patents
Analog-digital conversion controller, control method and system Download PDFInfo
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Abstract
The application relates to an analog-digital conversion controller, a control method and a control system. The configuration register in the controller obtains an enabling signal, a data processing control signal and a trigger signal according to the obtained sampling request transmitted by the external host, and transmits the trigger signal to the control state machine, and the control state machine transmits the generated sampling control signal to the analog-to-digital conversion module; enabling the analog-to-digital conversion module to convert the received analog signals into digital signals; the configuration register transmits the data processing control signal to the data processing module, the data processing module performs data processing on the digital signal to obtain a processed digital signal, and the buffer receives and caches the processed digital signal; the configuration register transmits the enabling signal to the buffer, and the buffer transmits the processed digital signal to the external host through the configuration register, so that the efficiency of reading ADC sampling data is improved, delay is reduced, and the flexibility and the working speed of the ADC are improved.
Description
Technical Field
The present application relates to the field of data processing technologies, and in particular, to an analog-to-digital conversion controller, and a control method and system thereof.
Background
With the development of Digital signal processing technology, the improvement of the operating speed of Digital circuits, and the increasing demand for system sensitivity, etc., higher demands are being made on the indexes of high-speed and high-precision ADCs (Analog to Digital converters).
The ADC is an important external device of the MCU (Microcontroller Unit), and is mainly used for data acquisition of the sensor. The analog part of the ADC in the MCU mostly adopts a serial mode to collect data, a specific sampling channel is selected by the controller to sample, and the data converted by the sampling channel is received for other parts to use. The design of the controller affects the flexibility and speed of the ADC.
In the implementation process, the inventor finds that at least the following problems exist in the traditional technology: the controller of the ADC in the existing MCU has low efficiency of reading sampling data, large delay and low flexibility and working speed of the ADC.
Disclosure of Invention
Therefore, it is necessary to provide an analog-to-digital conversion controller, a control method and a system that can improve the efficiency of reading the ADC sampling data, reduce the delay, and improve the flexibility and the operating speed of the ADC, in order to solve the above problems in the conventional controller of the ADC in the MCU.
In a first aspect, the present application provides an analog-to-digital conversion controller, comprising:
the control state machine is connected with the analog-to-digital conversion module and is configured to generate a sampling control signal according to the received trigger signal and transmit the sampling control signal to the analog-to-digital conversion module; the sampling control signal is used for indicating the analog-to-digital conversion module to convert the received analog signal into a digital signal;
the data processing module is connected with the analog-to-digital conversion module and is configured to perform data processing on the digital signal according to the acquired data processing control signal to obtain a processed digital signal;
the buffer is connected with the data processing module and is configured to receive and buffer the processed digital signals;
the configuration register is respectively connected with the external host, the buffer, the control state machine and the data processing module, and is configured to acquire a sampling request transmitted by the external host, acquire an enable signal, a data processing control signal and a trigger signal according to the sampling request, transmit the enable signal to the buffer, transmit the data processing control signal to the data processing module and transmit the trigger signal to the control state machine; the enable signal is used for instructing the buffer to transmit the corresponding processed digital signal to an external host through the configuration register.
Optionally, the configuration register includes a plurality of sequence units; the sequence unit comprises a plurality of sampling channels;
the configuration register is used for configuring the priority of each sequence unit and the priority of each sampling channel based on a preset priority condition according to the sampling request to obtain a configured sequence unit and a configured sampling channel, and transmitting the processed digital signal to an external host based on the configured sequence unit and the configured sampling channel.
Optionally, the preset priority condition is: the priority of the small sequence number in each sequence unit of the same configuration register is high, and the priority of the small channel number in each sampling channel of the same sequence unit is high.
Optionally, the trigger type of the trigger signal is internal trigger or external trigger;
the configuration register is also used for configuring the trigger type of the control state machine according to the sampling request and transmitting a trigger signal to the control state machine according to the configuration result.
Optionally, the buffer includes a plurality of buffer units; each buffer unit corresponds to each sequence unit one by one.
Optionally, the data processing module is further configured to screen the digital signal based on a preset resolution screening condition according to the data processing control signal, so as to obtain a screened digital signal; the data processing module is also used for carrying out overflow judgment processing on the screened digital signals to obtain processed digital signals.
Optionally, the external host is connected to the configuration register through an AMBA _ APB bus.
Optionally, the external host is a central processing unit or a DMA module.
In a second aspect, the present application provides an analog-to-digital conversion control method, including the steps of:
acquiring a sampling request transmitted by an external host;
obtaining an enabling signal, a data processing control signal and a triggering signal according to the sampling request;
transmitting the trigger signal to a control state machine so that the control state machine generates a sampling control signal according to the received trigger signal and transmits the sampling control signal to an analog-to-digital conversion module; the sampling control signal is used for indicating the analog-to-digital conversion module to convert the received analog signal into a digital signal;
transmitting the data processing control signal to a data processing module so that the data processing module performs data processing on the digital signal according to the acquired data processing control signal to obtain a processed digital signal; transmitting the processed digital signal to a buffer so that the buffer receives and buffers the processed digital signal;
and transmitting the enabling signal to the buffer, wherein the enabling signal is used for indicating the buffer to transmit the corresponding processed digital signal to an external host.
In a third aspect, the present application provides an analog-to-digital conversion control system, including an external host, an analog-to-digital conversion module, and any one of the above analog-to-digital conversion controllers; the analog-to-digital conversion controller is respectively connected with an external host and the analog-to-digital conversion module;
the analog-to-digital conversion controller is used for executing the steps of the analog-to-digital conversion control method.
One of the above technical solutions has the following advantages and beneficial effects:
the analog-to-digital conversion controller comprises a control state machine, a data processing module, a buffer and a configuration register, wherein the control state machine is connected with the analog-to-digital conversion module, the data processing module is connected with the analog-to-digital conversion module, the buffer is connected with the data processing module, the configuration register is respectively connected with an external host, the buffer, the control state machine and the data processing module, the configuration register acquires a sampling request transmitted by the external host, obtains an enabling signal, a data processing control signal and a trigger signal according to the sampling request, transmits the trigger signal to the control state machine, generates a sampling control signal according to the received trigger signal and transmits the sampling control signal to the analog-to-digital conversion module; the analog-to-digital conversion module converts the received analog signal into a digital signal according to the sampling control signal; the configuration register also transmits the data processing control signal to the data processing module, and then the data processing module performs data processing on the digital signal according to the acquired data processing control signal to obtain a processed digital signal, so that the buffer receives and caches the processed digital signal; the configuration register further transmits the enabling signal to the buffer, and then the buffer transmits the corresponding processed digital signal to an external host through the configuration register according to the enabling signal, so that high-efficiency and low-delay ADC sampling is achieved. According to the method and the device, the configuration register and the buffer which are configured in sequence are arranged in the controller, received conversion data are stored in the buffer, the speed of reading ADC sampling result data by an external host can be improved, delay overhead is reduced, meanwhile, a sampling channel can be flexibly configured, the requirements of low design speed and low efficiency of the controller of the ADC in the external host are improved, low cost and low power consumption are guaranteed, and the flexibility and the working speed of the ADC are improved.
Drawings
FIG. 1 is a diagram illustrating a first exemplary embodiment of an analog-to-digital converter controller;
FIG. 2 is a diagram illustrating a second structure of an analog-to-digital conversion controller according to an embodiment;
FIG. 3 is a diagram illustrating a third exemplary embodiment of an analog-to-digital converter controller;
FIG. 4 is a flow diagram illustrating an embodiment of an analog-to-digital conversion control method;
fig. 5 is a schematic structural diagram of an analog-to-digital conversion control system in one embodiment.
Reference numerals:
10. an analog-to-digital conversion controller; 110. a control state machine; 120. a data processing module; 130. a buffer; 132. a buffer unit; 140. a configuration register; 142. a sequence unit; 20. an external host; 30. and an analog-to-digital conversion module.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In addition, the term "plurality" shall mean two as well as more than two.
It should be noted that, in the present application, the embodiments and features of the embodiments may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to solve the problems in the controller of the ADC in the conventional MCU, in one embodiment, as shown in fig. 1, there is provided an analog-to-digital conversion controller 10 comprising a control state machine 110, a data processing module 120, a buffer 130 and a configuration register 140.
The control state machine 110 is connected to the analog-to-digital conversion module 30, and the control state machine 110 is configured to generate a sampling control signal according to the received trigger signal and transmit the sampling control signal to the analog-to-digital conversion module 30; the sampling control signal is used to instruct the analog-to-digital conversion module 30 to convert the received analog signal into a digital signal; the data processing module 120 is connected to the analog-to-digital conversion module 30, and the data processing module 120 is configured to perform data processing on the digital signal according to the acquired data processing control signal to obtain a processed digital signal; the buffer 130 is connected to the data processing module 120, and the buffer 130 is configured to receive and buffer the processed digital signal; the configuration register 140 is respectively connected to the external host 20, the buffer 130, the control state machine 110, and the data processing module 120, and the configuration register 140 is configured to obtain a sampling request transmitted by the external host 20, obtain an enable signal, a data processing control signal, and a trigger signal according to the sampling request, transmit the enable signal to the buffer 130, transmit the data processing control signal to the data processing module 120, and transmit the trigger signal to the control state machine 110; the enable signal is used to instruct the buffer 130 to transmit the corresponding processed digital signal to the external host 20 through the configuration register 140.
The control state machine 110 may be composed of a state register and a combinational logic circuit, among others. The analog-to-digital conversion module 30 is used to collect analog signals and convert analog signals of continuous variables into discrete digital signals. The external host 20 may be, but is not limited to, a Central Processing Unit (CPU) or a DMA module (direct memory access). Configuration registers 140 may be used to configure the series cell and sampling channel addresses, and configuration registers 140 may be used to configure either internal trigger sampling or external trigger sampling.
Based on the external host 20 connecting the configuration register 140, the control state machine 110 connecting the analog-to-digital conversion module 30, the control state machine 110 connecting the configuration register 140, the external host 20 may want the configuration register 140 to transmit the sampling request, and then the configuration register 140 generating the trigger signal according to the sampling request and transmitting the trigger signal to the control state machine 110. The control state machine 110 receives the trigger signal, generates a sampling control signal according to the received trigger signal, and transmits the sampling control signal to the analog-to-digital conversion module 30, so that the analog-to-digital conversion module 30 converts the received analog signal into a digital signal according to the sampling control signal. For example, when the control state machine 110 receives a trigger signal transmitted by the external host 20, the sampling control signal may be generated by jumping of the control state machine 110, and then the analog-to-digital conversion module 30 is controlled by the sampling control signal to start sampling the analog signal and converting the analog signal into a digital signal. After the conversion is completed, the analog-to-digital conversion module 30 generates a conversion completion signal and transmits the digital signal to the data processing module 120.
The data processing module 120 may be used to process the received digital signals. Based on that the data processing module 120 is connected to the analog-to-digital conversion module 30, the configuration register 140 is connected to the data processing module 120, and then the configuration register 140 can generate a data processing control signal according to the sampling request transmitted by the external host 20, and transmit the data processing control signal to the data processing module 120. The data processing module 120 performs data processing on the digital signal according to the acquired data processing control signal to obtain a processed digital signal.
The buffer 130 may be used to buffer the processed digital signal. Illustratively, the buffer 130 may include a plurality of buffer units 132. Based on the connection of the buffer 130 to the data processing module 120, the buffer 130 is connected to the configuration register 140, and the buffer 130 can buffer the received processed digital signal. The configuration register 140 may generate an enable signal according to a sampling request transmitted from the external host 20 and transmit the enable signal to the buffer 130. The buffer 130 transmits a corresponding processed digital signal to the external host 20 through the configuration register 140 according to the enable signal. Illustratively, the external host 20 may read the processed digital signal through the AMB _ APB bus.
In the above embodiment, the control-based state machine 110 is connected to the analog-to-digital conversion module 30, the data processing module 120 is connected to the analog-to-digital conversion module 30, the buffer 130 is connected to the data processing module 120, the configuration register 140 is respectively connected to the external host 20, the buffer 130, the control state machine 110, and the data processing module 120, the configuration register 140 obtains a sampling request transmitted by the external host 20, obtains an enable signal, a data processing control signal, and a trigger signal according to the sampling request, and transmits the trigger signal to the control state machine 110, so that the control state machine 110 generates a sampling control signal according to the received trigger signal, and transmits the sampling control signal to the analog-to-digital conversion module 30; so that the analog-to-digital conversion module 30 converts the received analog signal into a digital signal according to the sampling control signal; the configuration register 140 further transmits the data processing control signal to the data processing module 120, and the data processing module 120 performs data processing on the digital signal according to the acquired data processing control signal to obtain a processed digital signal, so that the buffer 130 receives and buffers the processed digital signal; the configuration register 140 further transmits the enable signal to the buffer 130, and the buffer 130 transmits the corresponding processed digital signal to the external host 20 through the configuration register 140 according to the enable signal, thereby implementing ADC sampling with high efficiency and low delay. According to the method, the configuration register 140 and the buffer 130 which are configured in sequence are arranged in the controller, received conversion data are stored in the buffer 130, the speed of reading ADC sampling result data by an external host can be improved, delay overhead is reduced, a sampling channel can be flexibly configured, the requirements of low design speed and low efficiency of the controller of the ADC in the external host are improved, low cost and low power consumption are ensured, and the flexibility and the working speed of the ADC are improved.
In one embodiment, as shown in FIG. 2, configuration register 140 includes a number of sequence units 142; sequence unit 142 includes several sampling channels. The configuration register 140 is configured to configure the priority of each sequence unit 142 and the priority of each sampling channel based on a preset priority condition according to the sampling request, to obtain a configured sequence unit 142 and a configured sampling channel, and to transmit the processed digital signal to the external host 20 based on the configured sequence unit 142 and the configured sampling channel.
For example, configuration register 140 may set 4 sequence units 142, and each sequence unit 142 may configure 8 sampling lanes. It should be noted that the number of sampling channels configured by the sequence unit 142 can be determined according to the number of analog sampling channels supported by the external analog circuit. The configuration register 140 is further configured to configure priorities of 4 sequence units 142 and priorities of 8 sampling channels based on a preset priority condition according to the sampling request, to obtain configured sequence units 142 and configured sampling channels, and to transmit the processed digital signals to the external host 20 based on the configured sequence units 142 and the configured sampling channels. By designing the configuration register 140 with multiple serial ADC sampling channels, the external host 20 can pre-configure the sampling requirements according to the application scenarios, and thus can improve the flexibility of using the ADC.
In one example, the preset priority condition is: the priority of the sequence number smaller in each sequence unit 142 of the same configuration register 140 is higher, and the priority of the channel number smaller in each sampling channel of the same sequence unit 142 is higher.
In one example, the trigger type of the trigger signal is an internal trigger or an external trigger; the configuration register 140 is also used to configure the trigger type of the control state machine 110 according to the sampling request, and transmit a trigger signal to the control state machine 110 according to the configured result. Further, each sequence unit 142 in the configuration register 140 may be configured with internal trigger sampling or external trigger sampling, and the sampling channels in the sequence unit 142 may be serially sampled in a sequential scanning manner.
In one example, as shown in fig. 3, the buffer 130 includes several buffer units 132; each buffer unit 132 corresponds to each sequence unit 142.
For example, the buffer 130 includes 4 buffer units 132, the configuration register 140 includes 4 sequence units 142, and the 4 buffer units 132 and the 4 sequence units 142 are disposed in a one-to-one correspondence. Each set of sequence units 142 corresponds to a first-in-first-out buffer unit 132, and the digital signals obtained by the enabled sampling channels in the sequence units 142 are buffered in the corresponding buffer 130 units. The 4 groups of sequence units 142 can flexibly configure sampling channels, and the 4 groups of buffer units 132 buffer the processed digital signals, so that the efficiency of reading ADC sampling data is improved, and delay is reduced.
In an example, the data processing module 120 is further configured to filter the digital signal according to the data processing control signal based on a preset resolution filtering condition to obtain a filtered digital signal; the data processing module 120 is further configured to perform overflow judgment processing on the screened digital signal to obtain a processed digital signal.
The data processing module 120 may select the digital signal according to the resolution based on a preset resolution screening condition, perform overflow judgment on the screened signal to obtain a processed digital signal, and transmit the processed digital signal to the corresponding buffer unit 132.
In one example, external host 20 is coupled to configuration registers 140 via an AMBA _ APB bus. A sampling request that external host 20 may issue to configuration register 140 via the AMB _ APB bus; the external host 20 may also read data out of the corresponding buffer unit 132 through the AMB _ APB bus.
In the above embodiment, the configuration register 140 and the buffer 130 configured in sequence are arranged in the controller, and the received conversion data is stored in the buffer 130, so that the rate of reading the ADC sampling result data by the external host 20 can be increased, the delay overhead can be reduced, and the sampling channel can be flexibly configured, so as to improve the requirements of low design speed and low efficiency of the controller with the ADC in the external host 20, ensure low cost and low power consumption, and increase the flexibility and the working speed of the ADC.
In one embodiment, as shown in fig. 4, an analog-to-digital conversion control method is provided, which is described by taking the method as an example applied to the configuration register in fig. 1, and includes the following steps:
step S410, a sampling request transmitted by an external host is obtained.
Step S420, obtaining an enable signal, a data processing control signal and a trigger signal according to the sampling request.
Step S430, transmitting the trigger signal to a control state machine so that the control state machine generates a sampling control signal according to the received trigger signal and transmits the sampling control signal to an analog-to-digital conversion module; the sampling control signal is used for instructing the analog-to-digital conversion module to convert the received analog signal into a digital signal.
Step S440, transmitting the data processing control signal to a data processing module, so that the data processing module performs data processing on the digital signal according to the acquired data processing control signal to obtain a processed digital signal; and transmitting the processed digital signal to a buffer so that the buffer receives and buffers the processed digital signal.
And step S450, transmitting an enable signal to the buffer, wherein the enable signal is used for indicating the buffer to transmit the corresponding processed digital signal to an external host.
Specifically, the configuration register acquires a sampling request transmitted by an external host, obtains an enable signal, a data processing control signal and a trigger signal according to the sampling request, transmits the trigger signal to the control state machine, and then the control state machine generates a sampling control signal according to the received trigger signal and transmits the sampling control signal to the analog-to-digital conversion module; the analog-to-digital conversion module converts the received analog signal into a digital signal according to the sampling control signal; the configuration register also transmits the data processing control signal to the data processing module, and the data processing module performs data processing on the digital signal according to the acquired data processing control signal to obtain a processed digital signal, so that the buffer receives and caches the processed digital signal; the configuration register further transmits the enabling signal to the buffer, and then the buffer transmits the corresponding processed digital signal to an external host through the configuration register according to the enabling signal, so that high-efficiency and low-delay ADC sampling is achieved. According to the method and the device, the configuration register and the buffer which are configured in sequence are arranged in the controller, received conversion data are stored in the buffer, the speed of reading ADC sampling result data by an external host can be improved, delay overhead is reduced, meanwhile, a sampling channel can be flexibly configured, the requirements of low design speed and low efficiency of the controller of the ADC in the external host are improved, low cost and low power consumption are guaranteed, and the flexibility and the working speed of the ADC are improved.
It should be understood that, although the steps in the flowchart of fig. 4 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 4 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
In one embodiment, there is also provided an analog-to-digital conversion control apparatus including:
and the request acquisition unit is used for acquiring the sampling request transmitted by the external host.
And the request processing unit is used for obtaining an enabling signal, a data processing control signal and a triggering signal according to the sampling request.
The trigger unit is used for transmitting the trigger signal to the control state machine so that the control state machine generates a sampling control signal according to the received trigger signal and transmits the sampling control signal to the analog-to-digital conversion module; the sampling control signal is used for instructing the analog-to-digital conversion module to convert the received analog signal into a digital signal.
The data processing unit is used for transmitting the data processing control signal to the data processing module so that the data processing module performs data processing on the digital signal according to the acquired data processing control signal to obtain a processed digital signal; and transmitting the processed digital signal to a buffer so that the buffer receives and buffers the processed digital signal.
And the enabling unit is used for transmitting the enabling signal to the buffer, and the enabling signal is used for indicating the buffer to transmit the corresponding processed digital signal to the external host.
For the specific definition of the analog-to-digital conversion control device, reference may be made to the above definition of the analog-to-digital conversion control method, which is not described herein again. All or part of the modules in the analog-to-digital conversion control device can be realized by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the analog-to-digital conversion control system, and can also be stored in a memory in the analog-to-digital conversion control system in a software form, so that the processor can call and execute the corresponding operations of the modules.
In one embodiment, as shown in fig. 5, there is further provided an analog-to-digital conversion control system, including an external host 20, an analog-to-digital conversion module 30, and the analog-to-digital conversion controller 10 of any one of the above embodiments; the analog-to-digital conversion controller 10 is respectively connected with an external host 20 and an analog-to-digital conversion module 30; the analog-to-digital conversion controller 10 is configured to execute the steps of the analog-to-digital conversion control method.
For specific descriptions of the external host 20, the analog-to-digital conversion module 30 and the analog-to-digital conversion controller 10, reference may be made to the above descriptions of the external host, the analog-to-digital conversion module 30 and the analog-to-digital conversion controller 10, and no further description is given here.
In the above embodiment, the control state machine is connected to the analog-to-digital conversion module, the data processing module is connected to the analog-to-digital conversion module, the buffer is connected to the data processing module, the configuration register is respectively connected to the external host, the buffer, the control state machine, and the data processing module, the configuration register obtains a sampling request transmitted by the external host, obtains an enable signal, a data processing control signal, and a trigger signal according to the sampling request, and transmits the trigger signal to the control state machine, and then the control state machine generates a sampling control signal according to the received trigger signal, and transmits the sampling control signal to the analog-to-digital conversion module; the analog-to-digital conversion module converts the received analog signal into a digital signal according to the sampling control signal; the configuration register also transmits the data processing control signal to the data processing module, and the data processing module performs data processing on the digital signal according to the acquired data processing control signal to obtain a processed digital signal, so that the buffer receives and caches the processed digital signal; the configuration register further transmits the enabling signal to the buffer, and then the buffer transmits the corresponding processed digital signal to an external host through the configuration register according to the enabling signal, so that high-efficiency and low-delay ADC sampling is achieved. The configuration register and the buffer configured in sequence are arranged in the controller, received conversion data are stored in the buffer, the speed of reading ADC sampling result data by an external host can be improved, delay overhead is reduced, a sampling channel can be flexibly configured, the requirements of low design speed and low efficiency of the controller with the ADC in the external host are improved, low cost and low power consumption are ensured, and the flexibility and the working speed of the ADC are improved.
It will be understood by those skilled in the art that the structure shown in fig. 5 is a block diagram of only a part of the structure related to the present application, and does not constitute a limitation to the analog-to-digital conversion control system to which the present application is applied, and a specific analog-to-digital conversion control system may include more or less components than those shown in the figure, or combine some components, or have a different arrangement of components.
In one example, the present application further provides a computer storage medium on which a computer program is stored, the computer program, when executed by a processor, implementing the steps of the analog-to-digital conversion control method of any one of the above.
In one example, the computer program when executed by the processor implements the steps of:
acquiring a sampling request transmitted by an external host; obtaining an enabling signal, a data processing control signal and a triggering signal according to the sampling request; transmitting the trigger signal to a control state machine so that the control state machine generates a sampling control signal according to the received trigger signal and transmits the sampling control signal to an analog-to-digital conversion module; the sampling control signal is used for indicating the analog-to-digital conversion module to convert the received analog signal into a digital signal; transmitting the data processing control signal to a data processing module so that the data processing module performs data processing on the digital signal according to the acquired data processing control signal to obtain a processed digital signal; transmitting the processed digital signal to a buffer so that the buffer receives and buffers the processed digital signal; and transmitting the enabling signal to the buffer, wherein the enabling signal is used for indicating the buffer to transmit the corresponding processed digital signal to an external host.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), rambus (Rambus) direct RAM (RDRAM), direct Rambus Dynamic RAM (DRDRAM), and Rambus Dynamic RAM (RDRAM), among others.
All possible combinations of the technical features of the above embodiments may not be described for the sake of brevity, but should be considered as within the scope of the present disclosure as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. An analog-to-digital conversion controller, comprising:
the control state machine is connected with the analog-to-digital conversion module and is configured to generate a sampling control signal according to a received trigger signal and transmit the sampling control signal to the analog-to-digital conversion module; the sampling control signal is used for instructing the analog-to-digital conversion module to convert the received analog signal into a digital signal;
the data processing module is connected with the analog-to-digital conversion module and is configured to perform data processing on the digital signal according to the acquired data processing control signal to obtain a processed digital signal;
a buffer connected to the data processing module, the buffer configured to receive and buffer the processed digital signal;
the configuration register is respectively connected with an external host, the buffer, the control state machine and the data processing module, and is configured to acquire a sampling request transmitted by the external host, obtain an enable signal, a data processing control signal and the trigger signal according to the sampling request, transmit the enable signal to the buffer, transmit the data processing control signal to the data processing module and transmit the trigger signal to the control state machine; the enable signal is used for instructing the buffer to transmit the corresponding processed digital signal to the external host through the configuration register.
2. The analog-to-digital conversion controller of claim 1, wherein said configuration register comprises a number of sequence units; the sequence unit comprises a plurality of sampling channels;
the configuration register is used for configuring the priority of each sequence unit and the priority of each sampling channel based on a preset priority condition according to the sampling request to obtain a configured sequence unit and a configured sampling channel, and transmitting the processed digital signal to the external host based on the configured sequence unit and the configured sampling channel.
3. The modulo conversion controller according to claim 2, wherein the predetermined priority condition is: the priority of the small sequence number in each sequence unit of the same configuration register is high, and the priority of the small channel number in each sampling channel of the same sequence unit is high.
4. The analog-to-digital conversion controller according to claim 2, wherein the trigger type of the trigger signal is an internal trigger or an external trigger;
the configuration register is further configured to configure a trigger type of the control state machine according to the sampling request, and transmit the trigger signal to the control state machine according to a configuration result.
5. The analog-to-digital conversion controller of claim 2, wherein said buffer comprises a plurality of buffer cells; and each buffer unit corresponds to each sequence unit one by one.
6. The analog-to-digital conversion controller according to claim 1, wherein the data processing module is further configured to filter the digital signal according to the data processing control signal based on a preset resolution filtering condition to obtain a filtered digital signal; the data processing module is further configured to perform overflow judgment processing on the screened digital signals to obtain the processed digital signals.
7. A modulus conversion controller according to any of claims 1 to 6, wherein said external host is coupled to said configuration register via an AMBA _ APB bus.
8. The analog-to-digital conversion controller of claim 7, wherein said external host is a central processing unit or a DMA module.
9. An analog-to-digital conversion control method is characterized by comprising the following steps:
acquiring a sampling request transmitted by an external host;
obtaining an enabling signal, a data processing control signal and a triggering signal according to the sampling request;
transmitting the trigger signal to a control state machine so that the control state machine generates a sampling control signal according to the received trigger signal and transmits the sampling control signal to an analog-to-digital conversion module; the sampling control signal is used for instructing the analog-to-digital conversion module to convert the received analog signal into a digital signal;
transmitting the data processing control signal to a data processing module so that the data processing module performs data processing on the digital signal according to the acquired data processing control signal to obtain a processed digital signal; transmitting the processed digital signal to a buffer so that the buffer receives and buffers the processed digital signal;
and transmitting the enabling signal to the buffer, wherein the enabling signal is used for indicating the buffer to transmit the corresponding processed digital signal to the external host.
10. An analog-to-digital conversion control system, comprising an external host, an analog-to-digital conversion module and the analog-to-digital conversion controller of any one of claims 1 to 8; the analog-to-digital conversion controller is respectively connected with the external host and the analog-to-digital conversion module;
the analog-to-digital conversion controller is configured to execute the steps of the analog-to-digital conversion control method of claim 9.
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