CN115858425B - Memory allocation method and system under MPU protection scene - Google Patents
Memory allocation method and system under MPU protection scene Download PDFInfo
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Abstract
The embodiment of the invention provides a memory allocation method and a memory allocation system under an application MPU protection scene, and belongs to the technical field of memory processing. The method comprises the following steps: s10) obtaining information to be stored and current storage state information, and determining a division scheme of a storage area based on the information to be stored and the current storage state information; s20) setting a corresponding MPU protection register based on the determined partitioning scheme; s30) determining the next division scheme based on the information of the corresponding MPU protection register; s40) repeating steps S20) to S30) until the division of the storage area is completed, wherein the division scheme of each division is determined based on the setting result of the MPU protection register by the last division. The scheme of the invention utilizes the cooperation of a plurality of MPU protection registers and the subdivision of the protection area, and can effectively reduce the waste of storage space caused by the alignment requirement of the cooperation of a single MPU protection register.
Description
Technical Field
The invention relates to the technical field of memory processing, in particular to a memory allocation method under an application MPU protection scene and a memory allocation system under the application MPU protection scene.
Background
A memory protection unit (memory protection unit), abbreviated as MPU. The method can set the memory access characteristics (such as supporting only privileged access or full access) and the memory attributes (such as cacheable, bufferable and shareable) of different memory areas, and protect the memory (mainly the memory and the peripheral), thereby improving the reliability of the system. The MPU can divide the memory map of the memmorymap into a plurality of areas with access rules, and can realize memory protection, peripheral protection and code access protection after rule setting. The embedded operating system employs multithreading to accomplish multitasking, such as ucos (multitasking real-time kernel operating system), freeRTOS (a real-time operating system kernel), RT-thread (an open source real-time operating system), and the like. For example, a bare metal program developed in Cortex-M or a program using an embedded operating system, which is shared for each task for resources on the MCU, may be considered a single-process multithreading model. When the operation system uses MPU protection to separate tasks, the protection address of the MPU needs to be allocated to each section (code section and data section) of each task, and the protection address of the MPU has alignment requirement, thus the waste of storage space is likely to be caused, and when serious, the allocation of task memory is likely to fail because the massive space cannot be aligned.
Memory space start address protected by MPU and protection size of 2 n Byte alignment causes a large amount of memory waste due to the alignment rule when memory allocation is performed. Aiming at the problem that a large amount of storage space is wasted due to the requirement on address alignment in the existing MPU protection mode, a new memory allocation method in an MPU protection scene needs to be created.
Disclosure of Invention
The invention aims to provide a memory allocation method and a memory allocation system under an MPU protection scene, which at least solve the problem that a large amount of memory space is wasted due to the address alignment requirement in the existing MPU protection mode.
In order to achieve the above object, a first aspect of the present invention provides a memory allocation method in a protection scenario using an MPU, the method comprising: s10) obtaining information to be stored and current storage state information, and determining a division scheme of a storage area based on the information to be stored and the current storage state information; s20) setting a corresponding MPU protection register based on the determined division scheme; s30) determining the next division scheme based on the information of the corresponding MPU protection register; s40) repeating steps S20) to S30) until the division of the storage area is completed, wherein the division scheme of each division is determined based on the setting result of the MPU protection register by the last division.
Optionally, the information to be stored is size information of the data to be stored; the current storage state information is size information of a storage space which is used currently.
Optionally, in step S10), the determining a partition scheme of the storage area based on the information to be stored and the current storage status information includes: based on the alignment rule of the MPU protection register, starting from the use end address of the currently used storage space, distributing a storage area with a corresponding size for the data to be stored according to the size information of the data to be stored by presetting a first dividing principle; based on a preset first division principle, determining an information setting rule of an MPU protection register under the first division in an allocated storage area, and taking the determined information setting rule as a division scheme of the storage area.
Optionally, the information setting rule of the MPU protection register under the first division includes: the number of MPU protection registers under the first division, the protection size of each MPU protection register under the first division, the starting address alignment size of each MPU protection register under the first division, and the starting address of each MPU protection register under the first division.
Optionally, the preset first dividing rule includes: the total protection size of MPU protection registers used for the first time is not smaller than the size of data to be stored; in MPU protection registers used for the first time, the protection size of any MPU protection register is not larger than the size of data to be stored; the starting address of the first MPU protection register in the first divided MPU protection registers coincides with the use ending address of the used storage space or is positioned before the use ending address of the used storage space; the starting address of the secondary MPU protection register in the first divided MPU protection registers is overlapped with the ending address of the adjacent previous MPU protection register in sequence.
Optionally, the determining the next partitioning scheme based on the information of the corresponding MPU protection register includes: on the basis of completing the first division of the storage area based on a preset first division principle, determining an information setting rule of an MPU protection register under the next division based on a preset subsequent division principle, and taking the determined information setting rule as the next division scheme of the storage area.
Optionally, the information setting rule of the MPU protection register under the subsequent round division includes, in addition to the first division: the protection size of each MPU protection register under the subsequent round division, the starting address alignment size of each MPU protection register under the subsequent round division, and the starting address of each MPU protection register under the subsequent round division.
Optionally, the preset subsequent dividing principle is a principle that all subsequent dividing schemes of the round division except the first division are adhered to together; the preset subsequent dividing principle comprises the following steps: the protection size and the initial address alignment size of the first MPU protection register in the divided MPU protection registers are the sub-area size of the forward MPU protection register under the last division scheme; the start address of the first MPU protection register in the divided MPU protection registers coincides with the use end address of the used storage space or is positioned before the use end address of the used storage space; the sum of the protection size and the initial address alignment size of the subsequent MPU protection registers in the divided MPU protection registers is equal to the size of the subarea of the backward MPU protection registers under the last division scheme; the start address of the subsequent MPU protection register in the divided MPU protection registers is determined based on the one-by-one alignment of the storage areas allocated with the size information of the data currently to be stored.
Optionally, the forward MPU protection register under the first partitioning scheme is the first MPU protection register under the first partitioning scheme; the backward MPU protection register under the first division scheme is the last MPU protection register under the first division scheme; the forward MPU protection register under the subsequent round division scheme is the first MPU protection register under the corresponding round division scheme; the backward MPU protection register under the subsequent round division scheme is the last MPU protection register under the corresponding round division scheme.
Optionally, the rule that the start address of the subsequent MPU protection register in the divided MPU protection registers is determined based on the one-by-one alignment of the storage areas allocated with the size information of the current data to be stored includes: determining the end address of the currently allocated storage area based on the end address of the currently used storage space and the storage area with the corresponding size of the data to be stored; the starting address of the first MPU protection register in the follow-up MPU protection registers coincides with the ending address of the current allocation storage area or is positioned before the ending address of the current allocation storage area; other MPU protection registers except the first MPU protection register in the subsequent MPU protection registers are aligned one by one based on the end address of the last MPU protection register.
Optionally, in step S40), the determination rule for completing the division of the storage area is: and obtaining a section of accessible storage space with the same size as the data to be stored from the using end address of the currently used storage space as a starting point, and determining the end address of the storage space of the current section.
The second aspect of the present invention provides a memory allocation system in a protected scenario using an MPU, the system comprising: the acquisition unit is used for acquiring information to be stored and current storage state information, and determining a division scheme of a storage area based on the information to be stored and the current storage state information; a processing unit for performing division of a plurality of storage areas, comprising the steps of: s1) setting a corresponding MPU protection register based on the determined division scheme; s2) determining the next dividing scheme based on the information of the corresponding MPU protection register; s3) repeatedly executing the steps S1) to S2) until the division of the storage area is completed, wherein the division scheme of each division is determined based on the setting result of the MPU protection register by the last division; and the output unit is used for outputting the storage area division result.
Optionally, the information to be stored is size information of the data to be stored; the current storage state information is the size information of the currently used storage space; the processing unit is further configured to: based on the alignment rule of the MPU protection register, starting from the use end address of the currently used storage space, distributing a storage area with a corresponding size for the data to be stored according to the size information of the data to be stored by presetting a first dividing principle; based on a preset first division principle, determining an information setting rule of an MPU protection register under the first division in an allocated storage area, and taking the determined information setting rule as a division scheme of the storage area.
Optionally, in step S3), the determination rule for completing the division of the storage area is: and obtaining a section of accessible storage space with the same size as the data to be stored from the using end address of the currently used storage space as a starting point, and determining the end address of the storage space of the current section.
In another aspect, the present invention provides a computer readable storage medium having instructions stored thereon, which when executed on a computer cause the computer to perform the above-described memory allocation method in an application MPU protection scenario.
Through the technical scheme, the protection areas of the MPU protection registers can be nested and overlapped, and the access authority can be independently set for each subarea, so that the memory space waste caused by the alignment requirement of matching with a single MPU protection register can be effectively reduced by matching the MPU protection registers and subdividing the protection areas.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain, without limitation, the embodiments of the invention. In the drawings:
FIG. 1 is a flowchart showing steps of a memory allocation method in a protected scenario using an MPU according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating an exemplary memory partition according to an embodiment of the present invention;
fig. 3 is a system configuration diagram of a memory allocation system in a protected scenario using an MPU according to an embodiment of the present invention.
Detailed Description
The following describes specific embodiments of the present invention in detail with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
A memory protection unit (memory protection unit), abbreviated as MPU. The method can set the memory access characteristics (such as supporting only privileged access or full access) and the memory attributes (such as cacheable, bufferable and shareable) of different memory areas, and protect the memory (mainly the memory and the peripheral), thereby improving the reliability of the system. The MPU can divide the memory map of the memmorymap into a plurality of areas with access rules, and can realize memory protection, peripheral protection and code access protection after rule setting. The MPU specifically acts as follows:
1) One task is prevented from accessing the data area of the other task, thereby isolating the tasks.
2) The user application is prevented from corrupting the data used by the operating system.
3) The key data area is set to be read-only, so that the possibility of being destroyed is fundamentally solved.
4) Unexpected memory accesses, such as stack overflows, array out-of-bounds, etc., are detected.
For systems without embedded OS, MPU may be programmed to a static configuration that can be used for the following functions:
1) The RAM and SRAM areas are set to be read-only, so that important data is prevented from being damaged accidentally.
2) A portion of the RAM, SRAM space at the bottom of the stack is made inaccessible to detect stack overflow.
3) And setting the RAM and SRAM areas to XN, and avoiding code injection attack.
For a system with an embedded OS, the MPU can be configured each time the context switches, and each application task has a different MPU configuration, the functions are as follows:
1) The memory access authority is defined, so that the application task can only access the stack space allocated to the application task, and other stacks can be prevented from being damaged due to stack leakage.
2) Memory access rights are defined such that application tasks can only access limited peripherals.
3) Memory access rights are defined such that application tasks can only access their own data or programs.
An embedded system running a real-time operating system defines storage space access rights and memory space configurations for each task to ensure that each task does not destroy other tasks or the address space of the operating system kernel.
The embedded operating system employs multithreading to accomplish multitasking, such as ucos, freeRTOS, RT-thread, and the like. For example, a bare metal program developed in Cortex-M or a program using an embedded operating system, which is shared for each task for resources on the MCU, may be considered a single-process multithreading model. When the operation system uses MPU protection to separate tasks, the protection address of the MPU needs to be allocated to each section (code section and data section) of each task, and the protection address of the MPU has alignment requirement, thus the waste of storage space is likely to be caused, and when serious, the allocation of task memory is likely to fail because the massive space cannot be aligned.
Memory space start address protected by MPU and protection size of 2 n Byte alignment, n is equal to or greater than 5, and an MPU protection register will be 2 n Byte 8 is equally divided into 8 sub-areas, and the 8 sub-areas can independently set access rights. In the current MPU protection mode, an MPU protection register is generally utilized to protect a data segment. The disadvantage of this is that the running memory of the application or system is allocated in the same memory, e.g. RAM, which results in a waste of space due to the alignment mechanism of the MPU. For example, in one specific application scenario, the kernel uses 129KB of memory space. Protection using an MPU protection register is required since it is protected with 2 n Byte alignment, so up to 256KB is required. This results in 127KB of memory being wasted because the application program that uses 200KB of memory must start its allocation at the 256KB starting address when it allocates memory.
Aiming at the problem that a large amount of storage space is wasted due to the requirement on address alignment in the existing MPU protection mode, the scheme of the invention provides a novel memory allocation method under the MPU protection scene. The scheme of the invention fully utilizes the characteristics of the MPU protection registers, utilizes the cooperation of a plurality of MPU protection registers and the subdivision of the protection area, and can effectively reduce the waste of storage space caused by the alignment requirement of the cooperation of a single MPU protection register.
Fig. 1 is a flowchart of a method for memory allocation in a protected scenario using an MPU according to an embodiment of the present invention. As shown in fig. 1, an embodiment of the present invention provides a memory allocation method in a protection scenario using an MPU, where the method includes:
step S10: and acquiring information to be stored and current storage state information, and determining a division scheme of a storage area based on the information to be stored and the current storage state information.
Specifically, the MPU protection has a remarkable characteristic that protection areas of a plurality of MPU protection registers can be nested and overlapped, then sub-area division can be performed by combining the MPU protection registers, and each sub-area can be independently provided with access rights. The allocation scheme suitable for the size of the storage space to be allocated can be performed by a combination mode of a plurality of MPU protection registers and by the access authority setting characteristics of the independent sub-areas. In short, the conventional MPU protection registers and the protection data are one-to-one, and because the alignment mode of the MPU protection registers is fixed, when the corresponding data segment is protected, only the nearest alignment mode with the current data segment length of heavy rain can be selected for setting the MPU protection registers. However, this closest concept tends to result in a significant amount of wasted memory because it grows exponentially with the difference in alignment length of each subsequent stage becoming larger. The scheme of the application is based on a mode of combining a plurality of MPU protection registers and the characteristic of the self-region which can be subdivided, so that the length of the matching unit is thinned, and the specific size of the region which is matched with the size of the storage file in the corresponding file is finally solved, and even if the storage space is wasted, the size of the region is reduced by an order of magnitude compared with the prior art.
To achieve this, it is first necessary to collect information to be stored in order to allocate a storage area of a corresponding size and current storage state information in order to allocate an area that is an idle area. Preferably, the information to be stored is size information of data to be stored; the current storage state information is the size information of the storage space which is used currently.
Specifically, determining the first division scheme of the storage area based on the information to be stored and the current storage state information includes: based on an alignment rule of an MPU protection register, starting from a storage space use end address of currently used storage space size information, and based on a preset first division principle, matching the size information of data to be stored to allocate a storage area with a corresponding size; in the allocated storage area, a setting rule for dividing MPU protection register information for the first time is determined based on a preset first division principle, and the setting rule is used as a first division scheme of the storage area.
Wherein, the setting rule of the first MPU protection register information comprises: the number of MPU protection registers in the first division, the protection size of each MPU protection register, the initial address alignment size of each MPU protection register, and the initial address of each MPU protection register.
Specifically, the preset first division principle includes: the total protection size of MPU protection registers used for the first time is not smaller than the size information of data to be stored; in MPU protection registers used for the first time, any MPU protection register protects size information of which the size is not larger than that of data to be stored; the first MPU of the first partition protects the register for the first time that the start address coincides with the end of use address of the used memory space size information or is located before the end of use address of the used memory space size information.
For example, when the memory used is 129KB and the size of the data to be stored is 100KB, based on the first partitioning rule, the two alignment lengths closest to the size of the stored data are 64KB and 128KB, respectively, because any one of the MPU protection registers used for the first partitioning protects size information of the data to be stored. Two 64KB MPUs are required to protect the registers. Then the starting address of the first MPU protected register is the end address of the memory that has been used, i.e., 128KB (aligned with the last MPU protected register alignment node), and the starting address of the second MPU protected register is 192KB (128kb+64kb). The number of MPU protection registers of the first partitioning scheme under this example is 2; the protection size and the initial address alignment size of the first MPU protection register and the second MPU protection register are 64KB; the first MPU protection register has a start address of 128KB and the second MPU protection register has a start address of 192KB.
In another possible implementation, the memory already used is 129KB, and when the size of the data to be stored is 260KB, then 2 or 3 MPU protection registers are needed for the first partition. The former is divided into 256KB+8KB (the former needs to be aligned with the alignment point of the protection register of the previous MPU, so that an overlapping area exists, the protection size needs to be expanded, if the used memory coincides with the alignment node, the area allocated based on the alignment rule can be the same as the area to be allocated in size), and the latter is divided into 128KB+128KB+8KB. So in order to optimize the rules, when there are multiple subdivision possibilities, the least combination rule is preferably the final allocation rule.
Step S20: and setting a corresponding MPU protection register based on the determined partitioning scheme.
Specifically, based on the setting rule for determining the MPU protection register information, the first division is performed, that is, the corresponding MPU protection register setting is performed according to the rule. After the complete setting, because the size of the corresponding stored data is not completely matched at present, for example, the total protection size of the two MPU protection registers allocated for 100KB is 128KB according to the above-mentioned exemplary scheme, and if the current data protection is directly performed based on the allocation scheme, a 28KB waste area still exists. To further reduce the wasted size, a further sub-region division is required, for example, aligning each sub-region of 64KB in length to a size of 8KB, then the total guard size of the first MPU guard register plus the sub-region size of the second guard register is 108KB, at which point the wasted size is only 8KB. And so on, multiple divisions are performed, sub-regions of 8KB are combined by 1KB, the total guard size reaches 101KB, and the wasted region size at this time is only 1 KB.
Based on the above, the scheme of the invention needs to realize multiple divisions based on the characteristic that each subarea of the MPU protection register can be independently provided with the authority until the division obtains the accessible storage space equal to the size information of the data to be stored.
Specifically, determining the second partitioning scheme based on the first partitioning MPU protection register information includes: on the basis of completing the first divided storage area, determining a setting rule of protecting register information by the MPU for the second time based on a preset follow-up dividing principle, and taking the setting rule as a second dividing scheme of the storage area.
Further, in addition to the first division, the setting rules for dividing the MPU protection registers in the subsequent other times include: the protection size of each MPU protection register, the initial address alignment size of each MPU protection register and the initial address of each MPU protection register under the subsequent corresponding sub-division.
Further, for the subsequent partitioning scheme, because further partitioning is required based on the first partitioning result, the number and the size of the MPU protection registers of the subsequent partitioning scheme can be freely combined according to different alignment states of the first partitioning result, and only the protection size of the MPU protection registers of the subsequent rule needs to be ensured to meet the partitioning requirement. For convenience of explanation of the scheme, the following subsequent partitioning schemes are all explained by 2 MPU protection registers, but the number of MPU protection registers in the subsequent partitioning scheme of the present invention is not limited to 2, and may be freely combined under the condition of requiring protection size.
Further, the preset subsequent dividing principle is a principle that all the dividing schemes of the subsequent sub-divisions follow together except the first division; the preset subsequent dividing principle comprises the following steps: the protection size and the initial address alignment size of the first MPU protection register are the sub-area size of the forward MPU protection register under the last division scheme; the start address of the first MPU protection register coincides with the storage space use end address of the used storage space size information or is located before the storage space use end address of the used storage space size information; the protection size and the initial address alignment size of the second MPU protection register are the sub-area size of the backward MPU protection register under the previous dividing scheme; the start address of the second MPU-protected register is determined based on the storage area allocated by the size information of the data currently to be stored.
The forward MPU protection register under the first partitioning scheme is the first MPU protection register under the first partitioning scheme; the forward MPU protection register under the first division scheme is the last MPU protection register under the first division scheme; the forward MPU protection register under the subsequent division scheme is the first MPU protection register under the corresponding sub-division scheme; the backward MPU protection register under the subsequent division scheme is the second MPU protection register under the corresponding sub-division scheme.
Specifically, the start address determination rule of the second MPU protection register includes: based on the storage space use end address of the currently used storage space size information and the size information matched with the data to be stored, distributing a storage area with a corresponding size, and determining the end address of the currently distributed storage area; the start address of the second MPU protection register coincides with or is located before the end address of the current allocation storage area.
Step S30: based on the information of the corresponding MPU protection register, the next partitioning scheme is determined.
Specifically, in the same manner as the step of executing the first partitioning, after the second partitioning scheme is determined, setting the MPU protection registers directly based on the determined protection size of each MPU protection register, the starting address alignment size of each MPU protection register, and the starting address of each MPU protection register in the second partitioning, so as to complete the second partitioning.
Step S40: repeatedly executing step S20) to step S30) until the division of the storage area is completed, wherein the division scheme of each division is determined based on the setting result of the MPU protection register by the last division.
Specifically, the reason why the scheme of the present invention performs division multiple times has been described in step S30, so the first division, the second division, …, and the nth division are performed in order until the storage area division triggering rule is satisfied. The method comprises the steps of obtaining a section of accessible storage space which is equal to the size information of data to be stored, and determining the starting address and the ending address of the storage space of the current section.
For example, as in FIG. 2, the memory that has been used is 129KB, and 200KB of memory is allocated. According to the above method, the first division is performed using 2 MPU protection registers, the first MPU protection register (MPU protection register 1) having a start address alignment size and protection size of 128KB, the start address of 128K, and the second MPU protection register (MPU protection register 2) having a start address alignment size and protection size of 128KB, the start address of 256K. The second division, the first MPU protection register (MPU protection register 3) has a start address alignment size and a protection size of 16KB (128/8), a start address of 128K, and the second MPU protection register (MPU protection register 4) has a start address alignment size and a protection size of 16KB, and a start address of 320K. At this time, the MPU protection register 3 is in the 1 st subregion of the MPU protection register 1, the MPU protection register 4 is in the 5 th subregion of the MPU protection register 2, the subregion 1 (2 KB size) of the MPU protection register 3 is set inaccessible according to the characteristics of the MPU protection register, the rest subregions are accessible, all subregions of the MPU protection register 3 are set accessible, the subregions 1-5 of the MPU protection register 2 are set accessible, 6-8 are set inaccessible, the subregions 1-5 of the MPU protection register 4 are set accessible, and 6-8 are set inaccessible, so that a 200KB memory accessible space from the start address 130K (1286 k+2k) to the end 330K (255 k+16k 4+2k 5) can be obtained, and the wasted space is between 129K and 130K at this time, compared with the existing method, the space waste is greatly reduced, and the utilization rate of the memory space is improved.
In the embodiment of the invention, the scheme firstly uses 1 or more MPU protection registers to divide the whole storage area of the system for the first time according to the size of the storage space to be allocated and the size of the storage space already used, wherein the principle of the first time is that the divided area can cover the size of the storage space to be allocated, and the starting address of the MPU protection registers of the first time falls at the end of the storage space already used or just before the end of the storage space already used. Then, performing a second partition, wherein the second partition uses 2 MPU protection registers, the protection size of the first MPU protection register and the start address of protection are aligned to the sub-area size of the forward MPU protection register of the first partition (namely, 1/8 of the alignment size of the forward MPU protection register of the first partition), and the start address is determined according to the used memory; the starting address alignment size and the protection size of the second MPU protection register are the sub-area size of the first divided backward MPU protection register, the starting address and the sub-area are determined according to the current allocated storage space, the third division uses 2 MPU protection registers, the first MPU protection register has the protection size and the protection starting address aligned to the second divided forward MPU protection register, and the starting address is determined according to the used memory; the starting address alignment size and the protection size of the two MPU protection registers are the sub-area size of the backward MPU protection registers divided for the first time, and the starting address and the sub-area are determined according to the current allocated storage space. According to the MPU of the processor protecting register resources, the fourth to nth allocations thereafter are analogized according to the method of the third allocation above.
The scheme of the invention utilizes the MPU protection registers to protect the internal memory of the system and the equipment, and uses a mode that a plurality of MPU protection registers are matched and continuously subdivided to protect a storage space, thereby improving the utilization rate of the storage space. The protection areas of the MPU protection registers can be nested and overlapped, and each subarea can be independently provided with access rights.
Fig. 3 is a system configuration diagram of a memory allocation system in a protected scenario using an MPU according to an embodiment of the present invention. As shown in fig. 3, an embodiment of the present invention provides a memory allocation system in a protected scenario using an MPU, where the system includes: the acquisition unit is used for acquiring information to be stored and current storage state information, and determining a division scheme of a storage area based on the information to be stored and the current storage state information; a processing unit for performing division of a plurality of storage areas, comprising the steps of: s1) setting a corresponding MPU protection register based on the determined division scheme; s2) determining the next dividing scheme based on the information of the corresponding MPU protection register; s3) repeatedly executing the steps S1) to S2) until the division of the storage area is completed, wherein the division scheme of each division is determined based on the setting result of the MPU protection register by the last division; and the output unit is used for outputting the storage area division result.
Preferably, the information to be stored is size information of data to be stored; the current storage state information is the size information of the currently used storage space; the processing unit is further configured to: based on an alignment rule of an MPU protection register, starting from a storage space use end address of a currently used storage space, based on a preset first division principle, distributing a storage area with a corresponding size for data to be stored based on size information of the data to be stored; based on a preset first division principle, determining an information setting rule of an MPU protection register under the first division in an allocated storage area, and taking the determined information setting rule as a division scheme of the storage area.
Preferably, in step S3), the determination rule for completing the division of the storage area is: and obtaining a section of accessible storage space with the same size as the data to be stored from the using end address of the currently used storage space as a starting point, and determining the end address of the storage space of the current section.
The embodiment of the invention also provides a computer readable storage medium, wherein the computer readable storage medium stores instructions, and when the computer runs on the computer, the computer executes the memory allocation method under the application MPU protection scene.
Those skilled in the art will appreciate that all or part of the steps in a method for implementing the above embodiments may be implemented by a program stored in a storage medium, where the program includes several instructions for causing a single-chip microcomputer, chip or processor (processor) to perform all or part of the steps in a method according to the embodiments of the invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-only memory (ROM), a random access memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The alternative embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the embodiments of the present invention are not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solutions of the embodiments of the present invention within the scope of the technical concept of the embodiments of the present invention, and all the simple modifications belong to the protection scope of the embodiments of the present invention. In addition, the specific features described in the above embodiments may be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the various possible combinations of embodiments of the invention are not described in detail.
In addition, any combination of the various embodiments of the present invention may be made, so long as it does not deviate from the idea of the embodiments of the present invention, and it should also be regarded as what is disclosed in the embodiments of the present invention.
Claims (14)
1. The memory allocation method under the application MPU protection scene is characterized by comprising the following steps:
s10) obtaining information to be stored and current storage state information, and determining a division scheme of a storage area based on the information to be stored and the current storage state information;
s20) setting a corresponding MPU protection register based on the determined partitioning scheme;
s30) determining the next division scheme based on the information of the corresponding MPU protection register; comprising the following steps:
on the basis of completing the first division of the storage area based on a preset first division principle, determining an information setting rule of an MPU protection register under the next division based on a preset subsequent division principle, and taking the determined information setting rule as the next division scheme of the storage area;
the preset subsequent dividing principle comprises the following steps:
the protection size and the initial address alignment size of the first MPU protection register in the divided MPU protection registers are the sub-area size of the forward MPU protection register under the last division scheme;
the start address of the first MPU protection register in the divided MPU protection registers coincides with the use end address of the used storage space or is positioned before the use end address of the used storage space;
the sum of the protection size and the initial address alignment size of the subsequent MPU protection registers in the divided MPU protection registers is equal to the size of the subarea of the backward MPU protection registers under the last division scheme;
the starting address of a subsequent MPU protection register in the divided MPU protection registers is determined based on one-by-one alignment of storage areas distributed according to the size information of the current data to be stored;
s40) repeating steps S20) to S30) until the division of the storage area is completed, wherein the division scheme of each division is determined based on the setting result of the MPU protection register by the last division.
2. The method according to claim 1, wherein the information to be stored is size information of data to be stored;
the current storage state information is size information of a storage space which is used currently.
3. The method according to claim 2, wherein in step S10), the determining a partitioning scheme of a storage area based on the information to be stored and the current storage state information includes:
based on the alignment rule of the MPU protection register, starting from the use end address of the currently used storage space, distributing a storage area with a corresponding size for the data to be stored according to the size information of the data to be stored by presetting a first dividing principle;
based on a preset first division principle, determining an information setting rule of an MPU protection register under the first division in an allocated storage area, and taking the determined information setting rule as a division scheme of the storage area.
4. A method according to claim 3, wherein the preset first partitioning principle comprises:
the total protection size of MPU protection registers used for the first time is not smaller than the size of data to be stored;
in MPU protection registers used for the first time, the protection size of any MPU protection register is not larger than the size of data to be stored;
the start address of the first MPU protection register in the first divided MPU protection registers coincides with the use end address of the used storage space or is positioned before the use end address of the used storage space;
the start address of the secondary MPU protection register in the first divided MPU protection registers is overlapped with the end address of the adjacent previous MPU protection register in sequence.
5. The method according to claim 1, wherein in step S20), the determining the next partitioning scheme based on the information of the corresponding MPU protection register includes:
on the basis of completing the first division of the storage area based on a preset first division principle, determining an information setting rule of an MPU protection register under the next division based on a preset subsequent division principle, and taking the determined information setting rule as the next division scheme of the storage area.
6. The method according to claim 5, wherein the information setting rule of the MPU protection register under the subsequent round of division includes, in addition to the first division:
the protection size of each MPU protection register under the subsequent round division, the starting address alignment size of each MPU protection register under the subsequent round division, and the starting address of each MPU protection register under the subsequent round division.
7. The method of claim 6, wherein the predetermined subsequent division principle is a principle that a division scheme of all subsequent round divisions except the first division is commonly followed.
8. The method of claim 7, wherein the forward MPU protected register under the first split scheme is the first MPU protected register under the first split scheme;
the backward MPU protection register under the first division scheme is the last MPU protection register under the first division scheme;
the forward MPU protection register under the subsequent round division scheme is the first MPU protection register under the corresponding round division scheme;
the backward MPU protection register under the subsequent round division scheme is the last MPU protection register under the corresponding round division scheme.
9. The method according to claim 7, wherein the rule that the start address of the subsequent MPU protection register among the divided MPU protection registers is determined based on the one-by-one alignment of the storage areas allocated with the size information of the current data to be stored comprises:
determining the end address of the currently allocated storage area based on the end address of the currently used storage space and the storage area with the corresponding size of the data to be stored;
the starting address of the first MPU protection register in the follow-up MPU protection registers coincides with the ending address of the current allocation storage area or is positioned before the ending address of the current allocation storage area;
other MPU protection registers except the first MPU protection register in the subsequent MPU protection registers are aligned one by one based on the end address of the last MPU protection register.
10. The method according to claim 2, wherein in step S40), the determination rule for completing the division of the storage area is:
and obtaining a section of accessible storage space with the same size as the data to be stored from the using end address of the currently used storage space as a starting point, and determining the end address of the current section of storage space.
11. A memory allocation system in an application MPU protected scenario, the system comprising:
the acquisition unit is used for acquiring information to be stored and current storage state information, and determining a division scheme of a storage area based on the information to be stored and the current storage state information;
a processing unit for performing division of a plurality of storage areas, comprising the steps of:
s1) setting a corresponding MPU protection register based on the determined division scheme;
s2) determining the next dividing scheme based on the information of the corresponding MPU protection register; comprising the following steps:
on the basis of completing the first division of the storage area based on a preset first division principle, determining an information setting rule of an MPU protection register under the next division based on a preset subsequent division principle, and taking the determined information setting rule as the next division scheme of the storage area;
the preset subsequent dividing principle comprises the following steps:
the protection size and the initial address alignment size of the first MPU protection register in the divided MPU protection registers are the sub-area size of the forward MPU protection register under the last division scheme;
the start address of the first MPU protection register in the divided MPU protection registers coincides with the use end address of the used storage space or is positioned before the use end address of the used storage space;
the sum of the protection size and the initial address alignment size of the subsequent MPU protection registers in the divided MPU protection registers is equal to the size of the subarea of the backward MPU protection registers under the last division scheme;
the starting address of a subsequent MPU protection register in the divided MPU protection registers is determined based on one-by-one alignment of storage areas distributed according to the size information of the current data to be stored;
s3) repeatedly executing the steps S1) to S2) until the division of the storage area is completed, wherein the division scheme of each division is determined based on the setting result of the MPU protection register by the last division;
and the output unit is used for outputting the storage area division result.
12. The system of claim 11, wherein the information to be stored is size information of data to be stored;
the current storage state information is the size information of the currently used storage space;
the processing unit is further configured to:
based on the alignment rule of the MPU protection register, starting from the use end address of the currently used storage space, distributing a storage area with a corresponding size for the data to be stored according to the size information of the data to be stored by presetting a first dividing principle;
based on a preset first division principle, determining an information setting rule of an MPU protection register under the first division in an allocated storage area, and taking the determined information setting rule as a division scheme of the storage area.
13. The system according to claim 12, wherein in step S3), the determination rule for completing the division of the storage area is:
and obtaining a section of accessible storage space with the same size as the data to be stored from the using end address of the currently used storage space as a starting point, and determining the end address of the current section of storage space.
14. A computer readable storage medium having instructions stored thereon, which when run on a computer causes the computer to perform the memory allocation method in the application MPU protection scenario of any one of claims 1 to 10.
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