CN115841954A - Three-dimensional stacked integrated device and direct hybrid bonding process thereof - Google Patents

Abstract

The invention discloses a three-dimensional stacked integrated device and a direct hybrid bonding process thereof, belonging to the technical field of semiconductor packaging, and solves the problem in the prior art that a complete and mature process flow cannot be used to realize direct hybrid bonding from chips to wafers. The process is to apply a protective adhesive layer on the front side of the wafer to be diced, heat and cure; perform a scribing of the wafer to be diced; thin the back side of the diced wafer, and paste The carrier film is cleaned and removed to remove the protective adhesive layer; the chip to be activated and the target wafer are plasma activated; the chip to be activated and the carrier film are subtractively bonded, and the front side of the activated chip is flip-chip pre-bonded to the front side of the target wafer to be activated. Process the device; sequentially perform annealing and secondary scribing on the device to be processed to obtain a three-dimensional stacked integrated device. The three-dimensional stacked integrated device and its direct hybrid bonding process of the present invention can realize direct hybrid bonding from chips to wafers.

Description

A three-dimensional stacked integrated device and its direct hybrid bonding process

technical field

The invention belongs to the technical field of semiconductor packaging, and in particular relates to a three-dimensional stacked integrated device and a direct hybrid bonding process thereof.

Background technique

Die-to-wafer (D2W) hybrid bonding technology is the core technology to achieve high-performance 3D heterogeneous integration.

At present, there are two main processes to realize D2W hybrid bonding, one is to transfer the chip to the wafer carrier and then carry out wafer-to-wafer (W2W) hybrid bonding, which is called indirect D2W hybrid bonding process; One is to bond the chip directly to the wafer, called direct D2W hybrid bonding.

Among them, compared with the indirect D2W hybrid bonding process, the direct D2W hybrid bonding has higher bonding precision and the multi-layer bonding process is flexible, but it is more sensitive to the cleanliness of the chip surface, and the process is difficult to implement, so it cannot be adopted at present. The complete and mature process flow realizes direct hybrid bonding of chips to wafers.

Contents of the invention

In view of the above analysis, the present invention aims to provide a three-dimensional stacked integrated device and its direct hybrid bonding process, which solves the problem in the prior art that a complete and mature process flow cannot be used to realize direct hybrid bonding.

The purpose of the present invention is mainly achieved through the following technical solutions:

The present invention provides a direct hybrid bonding process for direct hybrid bonding from a chip to a wafer. The direct hybrid bonding process includes the following steps:

Step 1: Provide a wafer to be diced and a target wafer;

Step 2: Use a glue applicator to coat a protective glue layer on the front of the wafer to be diced, and heat and cure;

Step 3: Scribing the wafer to be diced obtained in step 2 to obtain a dicing wafer;

Step 4: Thinning the reverse side of the diced wafer, attaching a carrier film 5 and a support ring 6 (for example, a metal ring) to the reverse side of the thinned diced wafer to obtain a film-attached chip, cleaning to remove the protective adhesive layer, and obtaining Multiple chips to be activated;

Step 5: Perform plasma activation on the chip to be activated and the target wafer obtained in step 4 to obtain the activated chip and the target wafer for activation;

Step 6: Perform subtractive bonding on the active chip and the carrier film, perform flip-chip pre-bonding on the front of the active chip and the front of the target wafer to obtain the device to be processed;

Step 7: Perform annealing and secondary scribing in sequence on the device to be processed to obtain a three-dimensional stacked integrated device.

Further, the protective glue layer is a photoresist layer.

Further, the support ring is a metal ring.

Further, the following steps are also included between the above step 1 and step 2:

Pre-process the front side of the wafer to be diced and the front side of the target wafer.

Further, preprocessing includes the following steps:

Step a: performing mechanochemical polishing on the front side of the wafer to be diced and the front side of the target wafer;

Step b: Organic acid and deionized water alternately clean the front side of the wafer to be diced and the front side of the target wafer after mechanical polishing.

Further, the organic acid is citric acid.

Further, in the above step a, after the mechanochemical polishing, the metal layer is recessed relative to the dielectric layer, and the recess depth is <15nm.

Further, in the above step a, after mechanochemical polishing, the surface roughness Rq of the dielectric layer is less than 0.5 nm.

Further, the material of the dielectric layer is SiO ₂ , SiN, SICN or SiON.

Further, the metal layer is Cu, Au or Ag.

Further, mechanochemical polishing is used to polish the grinding media layer. The composition of the grinding liquid is calculated by volume ratio: grinding material 1, deionized water 0.5-1.5 and hydrogen peroxide 0.005-0.02, the average particle size of the grinding material is 60-200nm, and the grinding The liquid flow rate is 100-500ml/min, the grinding speed is 60-120/50-110RPM, and the grinding pressure from the edge to the center: 10-1psi.

Further, mechanical chemical polishing is used to grind the copper metal layer. The composition of the grinding liquid is calculated by volume ratio, including: grinding material 1, deionized water 5-20 and hydrogen peroxide 0.1-0.5, and the average particle size of the grinding material is 30-150nm. The flow rate of the grinding liquid is 100-500ml/min, the grinding speed is 60-120/50-110RPM, and the grinding pressure from the edge to the center: 10-1psi.

Further, in the above step 2, the thickness of the protective adhesive layer is 5-10 μm.

Further, in the above step 3, the wafer to be diced obtained in step 2 is diced once by using a blade dicing machine or a plasma dicing machine.

Further, in step 4, the following steps are also included between attaching the carrier film 5 and the support ring 6 and removing the protective adhesive layer:

Step 41: performing subtractive bonding on the film-attached chip and the carrier film;

Step 42: Provide a new carrier film, and transfer the film-mounted chips to the new carrier film by using a placement machine.

Further, after the film-attached chips are transferred to the new carrier film, the pitch of the film-attached chips is 100-200 μm.

Further, in the above step 4, the organic solvent and deionized water are used to wash in sequence.

Further, in step 4 above, the carrier film is a glass carrier.

Further, in the above step 5, the plasma activation power is 50-150W, and the atmosphere is N ₂ and/or O ₂ .

Further, between the above step 5 and step 6, the following steps are also included:

Clean the active chip front side and the active target wafer front side.

Further, in the above step 6, the flip-chip pre-bonding includes the following steps:

Step 61: Pick up the front of the activation chip by using the Bernoulli suction method, the four-side gripping method of the suction head, or the method of ultra-clean direct contact with the suction head, so that the activation chip is separated from the carrier film;

Step 62: Pick up the reverse side of the activation chip by using the Bernoulli suction method, the four-side gripping method of the suction head, or the ultra-clean direct contact suction method, and place the activation chip on the activation target wafer;

Step 63: The activation chip is moved towards the direction of the activation target wafer, and the front side of the activation chip is flip-chip pre-bonded with the front side of the activation target wafer by using a high-precision bonding machine.

Further, in the above step 7, the annealing temperature is 150-400° C., and the annealing time is 0.5-10 h.

Further, in the above step 7, the annealing furnace is used for annealing.

Further, in the above step 7, a dicing machine is used to perform secondary dicing according to the chip size requirement.

The present invention also provides a three-dimensional stacked integrated device, which is manufactured by the above-mentioned direct hybrid bonding process.

Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

a) The direct hybrid bonding process provided by the present invention adopts a complete process flow (glue coating, film thinning, primary scribing, activation, flip-chip pre-bonding, annealing and secondary scribing), which can realize direct hybrid bonding combine.

b) In the direct hybrid bonding process provided by the present invention, before the chip is activated, there is always a protective adhesive layer on the front of the wafer to be diced and the front of the chip to be activated. The protective adhesive layer can not only reduce the particles generated during the scribing process Pollution can also reduce the contact pollution of the chip obtained after one scribing during the transfer process, thereby effectively ensuring the cleanliness of the front side of the wafer to be diced and the front side of the chip to be activated, thereby effectively reducing the difficulty of direct hybrid bonding. Direct hybrid bonding achieved on .

c) In the direct hybrid bonding process provided by the present invention, the method of first scribing and then thinning is adopted. During one scribing, the wafer to be diced has sufficient thickness, which can reduce the edge defects caused by one scribing; at the same time , when thinning, since one scribing has been completed, there is no need to reserve enough thickness, and it can be thinned to a smaller thickness, which is suitable for the preparation of ultra-thin three-dimensional stacked integrated devices.

d) In the direct hybrid bonding process provided by the present invention, a glass carrier is used with an adhesive layer on the surface of the glass carrier, and the reverse side of the thinned wafer to be diced can be directly placed on the surface of the glass carrier to achieve The stable connection between the thinned wafer to be diced and the glass carrier does not require additional coating of an adhesive layer. In addition, when it is necessary to separate the wafer to be diced from the glass carrier, only the glass carrier is required. By curing the bonding layer on the glass carrier, the separation of the two can be achieved, thereby effectively simplifying the process flow.

e) In the direct hybrid bonding process provided by the present invention, after one scribing, particles will remain on the carrier film, and by transferring the film-attached chip to a new carrier film, on the one hand, the particle pollution brought in after one scribing can be reduced; On the other hand, during the transfer process, the film-attached chips can be screened and picked up, and known qualified chips can be selected, thereby improving the qualification rate of the three-dimensional stacked integrated device; The chips are redistributed, and the distance between two adjacent film-mounted chips is adjusted to facilitate non-contact pick-up in the subsequent flip-chip pre-bonding process.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and appended drawings.

Description of drawings

The drawings are for the purpose of illustrating specific embodiments only and are not to be considered as limitations of the invention, and like reference numerals refer to like parts throughout the drawings.

FIG. 1 is a process flow chart of the direct hybrid bonding process provided by Embodiment 1 of the present invention.

Reference signs:

1-substrate; 2-dielectric layer; 3-metal layer; 4-protective adhesive layer; 5-carrier film; 6-support ring.

Detailed ways

The preferred embodiments of the present invention will be specifically described below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of the present invention and are used together with the embodiments of the present invention to explain the principle of the present invention.

Embodiment one

This embodiment provides a direct hybrid bonding process for direct hybrid bonding from a chip to a wafer. Referring to FIG. 1, the direct hybrid bonding process includes the following steps:

Step 1: Provide a wafer to be diced and a target wafer. The structure of the wafer to be diced and the target wafer are the same, and both include a substrate 1 and a dielectric layer 2 and a metal layer 3 on the surface of the substrate 1. Define the wafer to be diced. The side of the diced wafer and the target wafer provided with the dielectric layer 2 and the metal layer 3 is the front side, and the side of the wafer to be diced and the target wafer provided with the substrate 1 is the reverse side;

Step 2: Apply a protective adhesive layer 4 (for example, photoresist) on the front surface of the wafer to be diced by using a glue applicator, and heat and cure;

Step 3: Using a blade dicing machine or a plasma dicing machine to perform dicing on the wafer to be diced obtained in step 2 to obtain a diced wafer;

Step 4: Thinning the reverse side of the diced wafer, attaching a carrier film 5 and a support ring 6 (for example, a metal ring) to the reverse side of the thinned diced wafer to obtain a film-attached chip, using an organic solvent and deionized water in sequence Cleaning, so that the protective adhesive layer 4 is removed, and multiple chips to be activated are obtained. It should be noted that deionized water is required for the last cleaning;

Step 5: Perform plasma activation on the chip to be activated and the target wafer obtained in step 4 to obtain the activated chip and the target wafer for activation;

Step 6: Perform subtractive bonding on the activation chip and the carrier film 5, reduce the bonding strength between the activation chip and the carrier film 5, perform flip-chip pre-bonding on the front side of the activation chip and the front side of the activation target wafer, and obtain the to-be-processed device;

Step 7: The devices to be processed are annealed in an annealing furnace in sequence, and a dicing machine is used to perform secondary scribing according to the chip size requirements to obtain a three-dimensional stacked integrated device.

Compared with the prior art, the direct hybrid bonding process provided in this embodiment adopts a complete process flow (glue coating, film thinning, primary scribing, activation, flip-chip pre-bonding, annealing and secondary scribing) , enabling direct hybrid bonding.

In addition, in the above-mentioned direct hybrid bonding process, before the chip is activated, there is always a protective adhesive layer 4 on the front of the wafer to be diced and the front of the chip to be activated. The protective adhesive layer 4 can not only reduce the number of particles generated during the dicing process Pollution can also reduce the contact pollution of the chip obtained after one scribing during the transfer process, thereby effectively ensuring the cleanliness of the front side of the wafer to be diced and the front side of the chip to be activated, thereby effectively reducing the difficulty of direct hybrid bonding. Direct hybrid bonding achieved on .

At the same time, in the above-mentioned direct hybrid bonding process, the method of first scribing and then thinning is adopted. During one scribing, the wafer to be diced has sufficient thickness, which can reduce the edge defects caused by one scribing; When it is thin, since one dicing has been completed, there is no need to reserve enough thickness, and it can be thinned to a smaller thickness, which is suitable for the preparation of ultra-thin three-dimensional stacked integrated devices. For example, the thickness of the diced wafer after thinning 20 to 30 μm.

In order to ensure the cleanliness of the surface of the wafer to be diced and the target wafer and the subsequent bonding strength, the following steps are also included between the above steps 1 and 2:

Pre-process the front side of the wafer to be diced and the front side of the target wafer.

Specifically, preprocessing includes the following steps:

Step a: performing mechanical chemical polishing (CMP) on the front side of the wafer to be diced and the front side of the target wafer, and appropriately increasing the roughness of the front side of the wafer to be diced and the front side of the target wafer;

Step b: organic acid (for example, citric acid) and deionized water alternately clean the front side of the wafer to be diced and the front side of the target wafer after mechanical polishing, and remove the contamination on the front side of the wafer to be diced and the front side of the target wafer Substances, it should be noted that deionized water is required for the final cleaning.

It is worth noting that in the subsequent annealing process, the volume of the metal layer 3 will expand after heating. In order to pre-reserve the expansion space of the metal layer 3, in the above step a, after the mechanochemical polishing, the metal layer 3 will expand relative to the dielectric layer. 2 is depressed, and the depth of the depression is less than 15nm, thereby basically ensuring that the metal layer 3 and the dielectric layer 2 are on the same plane after annealing.

Similarly, considering the final bonding strength and the microstructure of the bonding interface, in the above step a, after mechanochemical polishing, the surface roughness Rq of the dielectric layer 2 is less than 0.5 nm. This is because the surface roughness of the dielectric layer 2 is an important parameter that affects the final bonding strength and the microstructure of the bonding interface. If the roughness is too large, it will cause voids at the bonding interface, reduce the bonding strength, and even fail to Bond.

It should be noted that for mechanochemical polishing, different materials use different abrasive fluids and abrasive processes. Exemplarily, the material of the dielectric layer 2 is SiO ₂ , SiN, SICN or SiON, and the material of the metal layer 3 is Cu, Au or Ag.

Mechanochemical polishing is used to polish the grinding medium layer 2. The composition of the grinding liquid is calculated by volume ratio: grinding material 1, deionized water 0.5-1.5 and hydrogen peroxide 0.005-0.02, the average particle size of the grinding material is 60-200nm, the flow rate of the grinding liquid 100-500ml/min, grinding speed (upper turntable/lower turntable) 60-120/50-110RPM, grinding pressure (from edge to center): 10-1psi.

Mechanochemical polishing is used to grind the copper metal layer 3. The composition of the grinding liquid is calculated by volume ratio: grinding material 1, deionized water 5-20 and hydrogen peroxide 0.1-0.5, the average particle size of the grinding material is 30-150nm, and the grinding liquid The flow rate is 100~500ml/min, the grinding speed (upper turntable/lower turntable) is 60~120/50~110RPM, and the grinding pressure (from edge to center): 10~1psi.

In order to ensure the strength of the protective adhesive layer 4, in the above step 2, the thickness of the protective adhesive layer 4 is 5-10 μm. This is because, limiting the thickness of the protective glue layer 4 within the above-mentioned range can ensure the thickness of the photoresist layer on the one hand, effectively protect the surface of the wafer to be diced, and avoid the bumps on the surface of the wafer to be diced due to roughness. It is exposed to reduce the generation of particles in the subsequent sectioning process.

In order to further reduce the particle pollution brought in after one scribing, in step 4, the following steps are also included between attaching the carrier film 5 and the support ring 6 and removing the protective adhesive layer 4:

Step 41: performing subtractive bonding on the film-attached chip and the carrier film 5 to reduce the bonding strength between the film-attached chip and the carrier film 5;

Step 42: Provide a new carrier film 5, and transfer the film-mounted chips to the new carrier film 5 by using a mounter. It should be noted that the new carrier film 5 can also be a glass carrier.

This is because, after one scribing, particles will remain on the carrier film 5, and by transferring the film chip to a new carrier film 5, on the one hand, the particle pollution brought in after a slicing can be reduced; on the other hand, in the transfer process In the process, the film-attached chips can be screened and picked, and the known qualified chips (Known Good Die, KGD) can be selected, so as to improve the qualification rate of the prepared three-dimensional stacked integrated device; The chips are redistributed, and the distance between two adjacent film-mounted chips is adjusted to facilitate non-contact pick-up in the subsequent flip-chip pre-bonding process.

Exemplarily, after the film-attached chips are transferred to the new carrier film 5 , the pitch of the film-attached chips is 100-200 μm.

In order to simplify the process flow, in the above step 4, the carrier film 5 is a glass carrier plate. This is because the shape of the glass carrier is the same as that of the wafer to be diced, both are circular, and the shape matching degree is high, which can reduce the requirements for equipment. In order to ensure the activation rate of the plasma activation and the activity of the interface between the activation chip and the activation target wafer, in the above step 5, the plasma activation power is 50-150W, and the atmosphere is N ₂ and/or O ₂ .

In order to reduce particle contamination generated during the plasma activation process to activate the chip and activate the target wafer, between the above step 5 and step 6, the following steps are also included:

Clean the active chip front side and the active target wafer front side.

In order to reduce the pollution to the active chip and the active wafer during the flip-chip pre-bonding process, in the above step 6, the flip-chip pre-bonding includes the following steps:

Step 61: Pick up the front of the activation chip by using the Bernoulli suction method, the four-side gripping method of the suction head, or the ultra-clean direct contact with the suction head, so that the activation chip is separated from the carrier film 5;

Step 62: Pick up the reverse side of the activation chip by using the Bernoulli suction method, the four-side gripping method of the suction head, or the ultra-clean direct contact suction method, and place the activation chip on the activation target wafer;

Step 63: The activation chip is moved towards the activation target wafer, and the front side of the activation chip is flip-chip pre-bonded with the front side of the activation target wafer using a high-precision bonding machine, wherein the pre-bonding pressure can be adjusted according to the size of the activation chip , the larger the size of the activated chip, the greater the pre-bonding pressure. In addition, the use of high-precision bonding machines can also meet the needs of sub-micron hybrid bonding precision.

It should be noted that among the above-mentioned picking methods, the Bernoulli suction method is a non-contact picking method, which can avoid contamination of the activated chip by picking up, thereby ensuring the cleanliness of the front of the activated chip. Therefore, the Bernoulli suction method can be preferably used. .

In order to further improve the bonding strength between the metal layer 3 of the activated chip and the metal layer 3 of the target wafer, in the above step 7, the annealing temperature is 150-400°C, and the annealing time is 0.5-10h, so that an appropriate annealing temperature is ensured And the annealing time, can make the metal layer 3 of activation chip and the metal layer 3 of activation target wafer be fully bonded, thereby can further improve the bonding strength between the metal layer 3 of activation chip and the metal layer 3 of activation target wafer .

Embodiment two

This embodiment provides a three-dimensional stacked integrated device, which is manufactured by the direct hybrid bonding process provided in Embodiment 1.

Compared with the prior art, the beneficial effect of the three-dimensional stacked integrated device provided in this embodiment is basically the same as that of the direct hybrid bonding process provided in Embodiment 1, and will not be repeated here.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present invention can easily think of changes or Replacement should be covered within the protection scope of the present invention.

Claims (10)

1. A direct hybrid bonding process for direct hybrid bonding of a chip to a wafer, the direct hybrid bonding process comprising the steps of:

step 1: providing a wafer to be scribed and a target wafer;

step 2: coating a protective adhesive layer on the front surface of the wafer to be scribed, and heating and curing;

and step 3: carrying out primary scribing on the wafer to be scribed obtained in the step 2 to obtain a scribed wafer;

and 4, step 4: thinning the reverse side of the scribing wafer, attaching a bearing film to the reverse side of the thinned scribing wafer to obtain a film-attached chip, and cleaning to remove a protective adhesive layer to obtain a plurality of chips to be activated;

and 5: performing plasma activation on the chip to be activated and the target wafer obtained in the step (4) to obtain an activated chip and an activated target wafer;

step 6: performing bonding reduction on the activation chip and the bearing film, and performing flip-chip pre-bonding on the front surface of the activation chip and the front surface of the activation target wafer to obtain a device to be processed;

and 7: and sequentially annealing and scribing for the second time on the device to be processed to obtain the three-dimensional stacking integrated device.

2. The direct hybrid bonding process of claim 1, wherein in step 2, the thickness of the protective adhesive layer is 5 to 10 μm.

3. The direct hybrid bonding process of claim 1, wherein the step 4 of attaching the carrier film and the support ring and removing the protective adhesive layer further comprises the steps of:

step 41: performing subtractive bonding on the film chip and the carrier film;

step 42: and providing a new bearing film, and transferring the film chip to the new bearing film by using a chip mounter.

4. The direct hybrid bonding process of claim 3, wherein the pitch of the filmed chips is 100 to 200 μm after the filmed chips are transferred to a new carrier film.

5. The direct hybrid bonding process of claim 1, wherein in step 4, the carrier film is a glass carrier.

6. The direct hybrid bonding process of claims 1 to 5, wherein in step 5, the plasma activation power is 50-150W, and the atmosphere is N ₂ And/or O ₂ 。

7. The direct hybrid bonding process of any of claims 1 to 5, wherein in step 6, the flip-chip pre-bonding comprises the steps of:

step 61: picking up the front surface of the activation chip to separate the activation chip from the carrier film;

step 62: picking up the reverse side of the activation chip, and placing the activation chip above the activation target wafer;

and step 63: and moving the activation chip to the direction close to the activation target wafer, and inversely pre-bonding the front surface of the activation chip and the front surface of the activation target wafer.

8. The direct hybrid bonding process of claim 7, wherein the picking in steps 61 and 62 is performed by Bernoulli suction, four-sided tip gripping, or ultra-clean direct contact tip.

9. The direct hybrid bonding process according to any of claims 1 to 5, wherein in step 7, the annealing temperature is 150 to 400 ℃ and the annealing time is 0.5 to 10 hours.

10. A three-dimensional stacked integrated device, characterized in that it is manufactured using the direct hybrid bonding process according to any of claims 1 to 9.

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