CN115840075B - Current detection comparison circuit - Google Patents
Current detection comparison circuit Download PDFInfo
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- CN115840075B CN115840075B CN202310131504.6A CN202310131504A CN115840075B CN 115840075 B CN115840075 B CN 115840075B CN 202310131504 A CN202310131504 A CN 202310131504A CN 115840075 B CN115840075 B CN 115840075B
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- 238000001514 detection method Methods 0.000 title claims abstract description 21
- 238000003708 edge detection Methods 0.000 claims description 44
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The application discloses a current detection comparison circuit, which divides a power tube through which current flows into a plurality of power tubes, and adds a timing module, and controls the closing/opening states of the plurality of power tubes through a fixed switching period, so that the voltage difference between two ends (namely a current input end and a current output end) of the power tube can be amplified and compared, an automatic current comparison function is realized, and meanwhile, the current comparison precision is improved.
Description
Technical Field
The application relates to the technical field of circuits, in particular to a current detection comparison circuit.
Background
Portable devices in modern society are increasing, particularly with lithium batteries. When the capacity of the lithium battery is smaller, the lithium battery has the advantages of prolonging the service life of the battery to a greater extent, reducing the power consumption and improving the efficiency. For example, the TWS Bluetooth headset has a cabin battery capacity of about 400mAh, and a single headset battery capacity of about 50mAh, and besides the improvement of the structure, the working boundary of the circuit module can be further narrowed by improving the current sampling precision in the power reduction method, so that the efficiency is improved. Like in the TWS charging bin, boost function is usually integrated for charging the earphone, and the accuracy of sampling the current value of the power tube inside the Boost often determines the efficiency.
There are generally two existing schemes. The first is a single-tube single-reference scheme, as shown in fig. 1, which includes a power tube M0, an amplifier I0, a comparator I1, and a resistor R0. The working principle of the first scheme is as follows: when energy is transferred from A to B or from B to A, current is transferred from A (or B) to B (or A) through the power tube M0, and the product of the on resistance and the current is A, B differential pressure due to the fact that M0 is in a conducting state. And I0 amplifies the differential pressure of the two points A, B and sends the amplified differential pressure to an I1 comparator, and the amplified differential pressure is compared with VREF to obtain a current comparison result. In this way, when the voltage difference A, B is smaller, the accuracy will be reduced, and the output voltage I0 cannot represent the voltage difference A, B due to the fact that the output voltage I0 is close to or lower than the input offset voltage I0, so that the accuracy of the judgment result of the output of I1 cannot be ensured. For example, A, B differential pressure range is below 3mV and the input mismatch of I0 is 5mV, then I0 will amplify 8mV instead of 3mV. If it is desired to amplify 3mV, the input mismatch of I0 needs to be reduced below 0.5mV, which necessarily results in I0 being replaced from a conventional structure to a structure with a smaller input mismatch voltage, with an exponential increase in circuit difficulty and complexity.
Another solution is a single tube multi-reference solution, as shown in fig. 2. The scheme comprises a power tube M0, an amplifier I0, a comparator I1, a resistor R0 and a Switch module Switch. This scheme adds a Switch module to the scheme of fig. 2, and uses multiple reference voltages to perform sampling current comparison: when the current flowing through M0 increases, a higher VREF is selected, whereas a lower reference voltage is selected. However, the same I0 is still sampled, and A, B small voltage cannot be solved.
These two solutions are essentially one, the second one has evolved only on the first one, and do not solve the most fundamental bottleneck, nor the problem of reduced accuracy caused by the reduced differential A, B at low currents.
Disclosure of Invention
The application provides a current detection comparison circuit, which can realize the amplification comparison of the voltage difference between two ends of a power tube (namely a current input end and a current output end), realize the automatic current comparison function and improve the current comparison precision.
In a first aspect, the present application provides a current detection and comparison circuit comprising: the power supply comprises a plurality of power tubes, amplifiers, resistors, comparators, a timing module and a switch module;
one end of each power tube is electrically connected with the current input end through a first node, and the other end of each power tube is electrically connected with the current output end through a second node; the power tube is used for conducting current between the current input end and the current output end and detecting a voltage difference between the current input end and the current output end;
the first input end of the amplifier is electrically connected with the first node, the second input end of the amplifier is electrically connected with the second node, the output end of the amplifier is electrically connected with the negative input end of the comparator, and the output end of the amplifier is grounded through the resistor; the amplifier is used for amplifying the voltage difference between the current input end and the current output end;
the positive input end of the comparator is electrically connected with the reference voltage output end; the output end of the comparator is electrically connected with the input end of the timing module; the comparator is used for comparing the voltage difference between the current input end and the current output end with the reference voltage output by the reference voltage output end;
the output end of the timing module is electrically connected with the input end of the switch module; the timing module is used for timing the cycle time;
the switch module is electrically connected with the signal input end of each power tube; the switch module outputs a comparison result signal; and the switch module is used for sending a control turnover signal to the power tube so as to adjust the on-resistance of the power tube when the cycle time is met, and outputting a comparison result of the voltage difference between the current input end and the current output end and the reference voltage output by the reference voltage output end.
Optionally, the timing module includes an edge detection circuit and a pulse transmission circuit.
Optionally, an input end of the edge detection circuit is electrically connected with an output end of the comparator; the input end of the edge detection circuit is electrically connected with the output end of the pulse transmitting circuit;
the input end of the pulse transmitting circuit is electrically connected with the output end of the edge detecting circuit; the output end of the pulse transmitting circuit is electrically connected with the input end of the switch module.
Optionally, the circuit further comprises a first buffer; the output end of the comparator outputs a comparison result of the voltage difference between the current input end and the current output end and the reference voltage output by the reference voltage output end through the first buffer.
Optionally, the circuit further comprises a first and gate circuit; the first AND gate circuit comprises a first input end, a second input end, an enabling end and an output end;
the output end of the first AND gate circuit is electrically connected with the input end of the edge detection circuit, and the first output end of the pulse transmission circuit is electrically connected with the first input end of the first AND gate circuit so as to realize that the input end of the edge detection circuit is electrically connected with the first output end of the pulse transmission circuit;
the second output end of the pulse transmitting circuit is electrically connected with the first input end of the first AND gate circuit, the output end of the first AND gate circuit is electrically connected with the input end of the switch module, and the second output end of the pulse transmitting circuit is electrically connected with the input end of the switch module;
the output end of the comparator is electrically connected with the second input end of the first AND gate circuit.
Optionally, the edge detection circuit includes a first not gate, a first capacitor, a second buffer, and a first nand gate;
the input end of the first NOT circuit is electrically connected with the output end of the comparator; the output end of the first NOT circuit is grounded through the first capacitor and is connected with the input end of the second buffer; the first input end of the first NAND gate is electrically connected with the output end of the comparator, the second input end of the first NAND gate is connected with the output end of the second buffer, and the output end of the first NAND gate is electrically connected with the input end of the pulse transmitting circuit.
Optionally, the pulse sending circuit includes a second not gate circuit, a second capacitor, a third buffer and a second nand gate;
the input end of the second NOT circuit is electrically connected with the output end of the edge detection circuit; the output end of the second NOT circuit is grounded through the second capacitor and is connected with the input end of the third buffer; the first input end of the second NAND gate is electrically connected with the output end of the edge detection circuit, the second input end of the second NAND gate is connected with the output end of the third buffer,
the output end of the second NAND gate is electrically connected with the input end of the edge detection circuit; the output end of the second NAND gate is electrically connected with the input end of the switch module.
Optionally, the switch module includes: a plurality of switching units; each switch unit comprises a trigger and a NAND gate circuit;
for each switch unit, the clock signal input end of a trigger in the switch unit is electrically connected with the output end of the pulse transmitting circuit, and the Q end of the trigger in the switch unit is electrically connected with the signal input end of a power tube corresponding to the switch unit; and the signal input end of the NAND gate circuit in the switch unit is electrically connected with the Q end of the trigger in the adjacent last switch unit.
Optionally, the switch module includes: a plurality of switching units; each switch unit comprises a D-type trigger and a NAND gate circuit;
for each switch unit, the clock signal input end of the D-type trigger in the switch unit is electrically connected with the output end of the pulse transmitting circuit, and the QN end of the D-type trigger in the switch unit is electrically connected with the signal input end of the power tube corresponding to the switch unit; the first input end of the NAND gate circuit in the switch unit is electrically connected with the Q end of the D-type trigger in the adjacent last switch unit.
Optionally, the current detection comparison circuit includes n power tubes, and the switch module includes n+1 switch units.
According to the technical scheme, the application provides a current detection comparison circuit, which comprises: the power supply comprises a plurality of power tubes, an amplifier, a resistor, a comparator, a timing module and a switch module. One end of each power tube is electrically connected with the current input end through a first node, and the other end of each power tube is electrically connected with the current output end through a second node; the power tube is used for conducting current between the current input end and the current output end and detecting a voltage difference between the current input end and the current output end; the first input end of the amplifier is electrically connected with the first node, the second input end of the amplifier is electrically connected with the second node, the output end of the amplifier is electrically connected with the negative input end of the comparator, and the output end of the amplifier is grounded through the resistor; the amplifier is used for amplifying the voltage difference between the current input end and the current output end; the positive input end of the comparator is electrically connected with the reference voltage output end; the output end of the comparator is electrically connected with the input end of the timing module; the comparator is used for comparing the voltage difference between the current input end and the current output end with the reference voltage output by the reference voltage output end; the output end of the timing module is electrically connected with the input end of the switch module; the timing module is used for timing the cycle time; the switch module is electrically connected with the signal input end of each power tube; the switch module outputs a comparison result signal; and the switch module is used for sending a control turnover signal to the power tube so as to adjust the on-resistance of the power tube when the cycle time is met, and outputting a comparison result of the voltage difference between the current input end and the current output end and the reference voltage output by the reference voltage output end. Therefore, the application divides the power tube with current flowing into a plurality of power tubes, adds a timing module, and controls the closing/opening states of the plurality of power tubes through fixed switching period, so that the voltage difference between the two ends (namely the current input end and the current output end) of the power tube can be amplified and compared, the automatic current comparison function is realized, and the current comparison precision is improved.
Further effects of the above-described non-conventional preferred embodiments will be described below in connection with the detailed description.
Drawings
In order to more clearly illustrate the embodiments of the application or the prior art solutions, the drawings which are used in the description of the embodiments or the prior art will be briefly described below, it being obvious that the drawings in the description below are only some of the embodiments described in the present application, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a schematic diagram of a prior art circuit structure;
FIG. 2 is a schematic diagram of a circuit structure of the prior art;
FIG. 3 is a schematic diagram of a circuit structure of a current detection comparator circuit according to the present application;
FIG. 4 is a schematic diagram of a circuit structure of a current detection comparator circuit according to the present application;
FIG. 5 is a schematic circuit diagram of a switch module in a current detection comparator circuit according to the present application;
FIG. 6 is a schematic circuit diagram of a switch module in another current detection comparator circuit according to the present application;
fig. 7 is a schematic diagram of signals and time in a current detection and comparison circuit according to the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to specific embodiments and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Various non-limiting embodiments of the present application are described in detail below with reference to the attached drawing figures.
Referring to fig. 1, a current detection and comparison circuit according to an embodiment of the present application is shown, wherein the current detection and comparison circuit includes: the power supply comprises a plurality of power tubes (namely M1, M2, … … and Mn), an amplifier I0, a resistor R0, a comparator I1, a timing module (namely Timer) and a switching module (namely Switch Logic). Namely, the power tube is divided into M1-Mn with different proportions.
One end of each power tube is electrically connected with the current input end A through a first node J1, and the other end of each power tube is electrically connected with the current output end B through a second node J2. The power tube is used for conducting current between the current input end A and the current output end B and detecting voltage difference between the current input end A and the current output end B. It will be appreciated that a plurality of power transistors (i.e., M1, M2, … …, mn) are connected in parallel between the current input a and the current output B.
The first input end of the amplifier I0 is electrically connected with the first node J1, the second input end of the amplifier I0 is electrically connected with the second node J2, the output end of the amplifier I0 is electrically connected with the negative input end of the comparator I1, and the output end of the amplifier I0 is grounded through the resistor R0; the amplifier I0 is configured to amplify a voltage difference between the current input terminal a and the current output terminal B.
The positive input end of the comparator I1 is electrically connected with the reference voltage output end VERF; the output end of the comparator I1 is electrically connected with the input end of the timing module Timer. The comparator I1 is configured to compare a voltage difference between the current input terminal a and the current output terminal B with a reference voltage output by the reference voltage output terminal VERF.
And the output end of the timing module Timer is electrically connected with the input end of the Switch Logic of the Switch module. The timing module Timer is used for timing the cycle time.
The Switch Logic of the Switch module is electrically connected to the signal input end of each power tube (for example, the signal input end G1 of the power tube M1, the signal input ends G2 and … … of the power tube M2, and the signal input end Gn of the power tube Mn). The Switch module switches Logic to output a comparison result signal VO; and the Switch Logic of the Switch module is used for sending a control turnover signal to the power tube so as to adjust the on-resistance of the power tube when the cycle time is met, and outputting a comparison result of the voltage difference between the current input end A and the current output end B and the reference voltage output by the reference voltage output end VERF. In this way, the Timer module Timer can be used to time the Switch module Switch Logic to determine which power tube is in the on state.
In one implementation, as shown in fig. 4, the circuit further includes a first buffer I20; the output terminal of the comparator I1 outputs a comparison result VO of the voltage difference between the current input terminal a and the current output terminal B and the reference voltage output by the reference voltage output terminal VREF through the first buffer I20.
In one implementation, as shown in fig. 3, the Timer module Timer includes an Edge detection circuit (i.e., edge detection) and a Pulse transmission circuit (i.e., pulse GEN).
As shown in fig. 4, an input end of the Edge detection circuit Edge detection is electrically connected with an output end of the comparator I1; the input end of the Edge detection circuit Edge detection is electrically connected with the output end of the Pulse GEN of the Pulse sending circuit.
The input end of the Pulse GEN is electrically connected with the output end of the Edge detection circuit Edge detection; the output end of the Pulse GEN is electrically connected with the input end of the switch module.
In one implementation, as shown in fig. 4, the Edge detection circuit Edge detection may include a first not gate I2, a first capacitor C1, a second buffer I3, and a first nand gate I4.
The input end of the first NOT circuit I2 is electrically connected with the output end of the comparator I1; the output end of the first NOT circuit I2 is grounded through the first capacitor C1 and is connected with the input end of the second buffer I3; the first input end of the first NAND gate I2 is electrically connected with the output end of the comparator I1, the second input end of the first NAND gate I2 is connected with the output end of the second buffer I3, and the output end of the first NAND gate I2 is electrically connected with the input end of the Pulse GEN.
In one implementation, as shown in fig. 4, the Pulse GEN includes a second not gate I5, a second capacitor C2, a third buffer I6, and a second nand gate I7.
The input end of the second NOT circuit I5 is electrically connected with the output end of the Edge detection circuit Edge detection; the output end of the second NOT circuit I5 is grounded through the second capacitor C2 and is connected with the input end of the third buffer I6; the first input end of the second nand gate I7 is electrically connected to the output end of the Edge detection circuit Edge detection, and the second input end of the second nand gate I7 is connected to the output end of the third buffer I6. The output end of the second NAND gate I7 is electrically connected with the input end of the Edge detection circuit Edge detection; the output end of the second NAND gate I7 is electrically connected with the input end of the Switch Logic of the Switch module.
As shown in fig. 3, the Timer module Timer includes an Edge detection circuit Edge Detect and a Pulse GEN. The Edge detection circuit Edge Detect outputs a flag signal D when the Edge of the input signal (C or F) is detected, and the Pulse GEN generates a Pulse width signal E with a duration T2 according to the signal D. And the Switch Logic of the Switch module realizes the control of the power tubes M1-Mn according to the E signal. As shown in fig. 7, the delay time generated by the Edge detection circuit Edge detection is T1, and the delay time and T2 together form the total time T of the Timer module Timer. Before the voltage of the resistor R0 does not reach VREF, the timing module Timer outputs a control turnover signal Mx through a Switch Logic of the switching module every interval T time, so that the conduction impedance between the current input end A and the current output end B is changed, the differential pressure between the two ends of the current input end A and the current output end B is adjusted, and the current is amplified through the amplifier I0. This way, the voltage difference between the current input terminal a and the current output terminal B can be far higher than the input mismatch voltage VREF of the amplifier I0, so that inaccurate amplification caused by the mismatch voltage VREF is avoided, and the structural bottlenecks of fig. 1 and 2 are solved. When the voltage of the resistor R0 exceeds VREF for the first time, the comparison result signal VO is the required comparison result. The switching sequence of the power tube can set directivity according to specific application scenarios, and the application is not discussed too much here. Meanwhile, the circuit structures provided by the embodiment can be adopted for current detection and comparison of the N-type power tube and the P-type power tube. The voltage difference between the current input end A and the current output end B can be obtained by the structure regardless of the current, so that the traditional amplifier and comparator circuit can meet the function requirement without a complex and high-cost scheme.
In one implementation, as shown in fig. 5, the Switch Logic of the Switch module includes: a plurality of switching units; each switch unit comprises a trigger and a NAND gate circuit; in one implementation, if the current detection comparison circuit includes n power transistors, the switching module includes n+1 switching units.
For each switch unit, the clock signal input end of the trigger in the switch unit is electrically connected with the output end of the Pulse GEN of the Pulse transmitting circuit, the Q end of the trigger in the switch unit is electrically connected with the signal input end of the power tube corresponding to the switch unit, and the signal input end of the NAND gate circuit in the switch unit is electrically connected with the Q end of the trigger in the adjacent last switch unit, wherein the trigger in the first switch unit is not connected with the signal input end of any power tube. For example, as shown in fig. 5, the clock signal input terminal CLK of the flip-flop i1_2 in the first switch unit is electrically connected to the output terminal of the Pulse GEN of the Pulse transmitting circuit, the Q terminal of the flip-flop i1_2 in the switch unit is electrically connected to the signal input terminal of the nand gate I9 in the next adjacent switch unit, the D terminal of the flip-flop i1_2 in the first switch unit is connected to the power supply VDD, the RN terminal of the flip-flop i1_2 in the first switch unit is connected to the output terminal of the nand gate in the first switch unit, and the input terminal of the nand gate in the first switch unit receives the enable signal; the Q end of a trigger I8 in the second switch unit is electrically connected with the signal input G1 end of a power tube M1 corresponding to the switch unit, and the signal input end of a NAND gate circuit I9 in the second switch unit is electrically connected with the Q end of a trigger I1_2 in the adjacent last switch unit; the connection manner of the flip-flop and the nand gate in the other switch units is similar to that of the flip-flop and the nand gate in the second switch unit, and is not described in detail.
Fig. 5 comprises an amplifier I0, a resistor R0, a comparator I1, which enables an amplification and a comparison of the voltage difference of the current input a and the current output B. The Edge detection circuit may include a first not gate circuit I2, a first capacitor C1, a second buffer I3 and a first nand gate I4, the Pulse sending circuit Pulse GEN includes a second not gate circuit I5, a second capacitor C2, a third buffer I6 and a second nand gate I7, the Switch module Switch Logic is composed of n identical Switch units, each Switch unit is composed of a trigger (e.g. I8) and a nand gate circuit (e.g. I9), and the Q terminal of the trigger may control the signal input terminals G1 Gn of the power tubes M1 to Mn. The output signal of the comparator I1 is the final comparison result signal VO after passing through the first buffer I20. The EN signal is also present in the figure, and the Timer function is started through I1_1.
The working process of the whole example is that EN signals are low, all triggers are in a reset state, signals of G1-Gn are low, M1-Mn are in an on state, impedance between a current input end A and a current output end B is low, so that the voltage difference between the current input end A and the current output end B is small, and after the voltage difference is amplified by an amplifier I0, the voltage of an end of a resistor R0 is lower than VREF, namely, the output signal of a comparator I1 is low. In default state, the Pulse GEN outputs high level, so the input of the first and gate i1_1 is only EN high, the other two signals are both high, and the first and gate i1_1 outputs low level. When the EN signal changes from low to high, the first and gate i1_1 outputs the E signal to flip high, triggering the Q terminal of i1_2 to output the high level, and letting I8 be in the state of receiving the E signal. Meanwhile, the Edge Detect module is triggered, the I4 outputs the low Pulse width of time T1, and then returns to the high level, as in the D signal waveform of fig. 7, the rising Edge of the D signal waveform immediately triggers Pulse GEN to operate, the I7 outputs the low Pulse width of time T2, and then returns to the high level, and the signal is directly output through i1_1, as in the E signal waveform of fig. 7. The E signal is used as CLK to trigger the Q end signal G1 of the I8 to be high level, so that the M1 power tube is closed, and meanwhile, the E signal also triggers the Edge Detect module to enter into operation, and a new round of timing is repeated. If the output of I1 remains high for a time T (i.e., T1+T2), then the output signal G2 of I10 will go high, M2 will be turned off, and the next time counting is entered until the output signal VO of I1 goes low and the counting is stopped. The system can judge the current value information between the current input end A and the current output end B at the moment according to the VO and G1-Gn signals.
In one implementation, as shown in fig. 6, the switch module includes: a plurality of switching units; each switch unit comprises a D-type trigger and a NAND gate circuit; in one implementation, if the current detection comparison circuit includes n power transistors, the switching module includes n+1 switching units.
For each switch unit, the clock signal input end of the D-type trigger in the switch unit is electrically connected with the output end of the Pulse GEN, and the QN end of the D-type trigger in the switch unit is electrically connected with the signal input end of the power tube corresponding to the switch unit; the first input end of the NAND gate circuit in the switch unit is electrically connected with the Q end of the D-type trigger in the adjacent last switch unit. For example, as shown in fig. 6, the clock signal input terminal CLK of the D-type flip-flop i1_2 in the first switching unit is electrically connected to the output terminal of the Pulse GEN of the Pulse transmitting circuit, the Q terminal of the D-type flip-flop i1_2 in the switching unit is electrically connected to the signal input terminal of the nand gate I9 in the next adjacent switching unit, the D terminal of the D-type flip-flop i1_2 in the first switching unit is connected to the power supply VDD, the RN terminal of the D-type flip-flop i1_2 in the first switching unit is connected to the output terminal of the nand gate in the first switching unit, and the input terminal of the nand gate in the first switching unit receives the enable signal; the QN end of the D-type trigger I8 in the second switch unit is electrically connected with the signal input end G1 of the power tube M1 corresponding to the switch unit, the first input end of the NAND gate circuit in the second switch unit is electrically connected with the Q end of the D-type trigger I1_2 in the adjacent last switch unit, and the signal input end of the NAND gate circuit in the second switch unit receives an enabling signal; the QN end of the D-type trigger I10 in the third switch unit is electrically connected with the signal input end G2 of the power tube M2 corresponding to the switch unit, the first input end of the NAND gate circuit in the third switch unit is electrically connected with the Q end of the D-type trigger I8 in the adjacent last switch unit, and the signal input end of the NAND gate circuit in the third switch unit receives an enabling signal; the connection modes of the D-type flip-flops and the NAND gates in the other switch units are similar to those of the D-type flip-flops and the NAND gates in the second switch unit and the third switch unit, and are not described in detail.
Fig. 6 provides a detection circuit diagram suitable for an N-type power tube, in accordance with the teachings herein. The same is composed of edge_detect, pulse_gen, switch Logic, and the control signals of M1-Mn power transistors are provided by QN terminals of D-type flip-flops, unlike FIG. 5.
In one implementation, the circuit further includes a first and gate i1_1; the first AND gate circuit I1_1 comprises a first input end, a second input end, an enabling end and an output end.
The output end of the first and circuit i1_1 is electrically connected to the input end of the Edge detection circuit Edge detection, and the first output end of the Pulse GEN of the Pulse transmission circuit is electrically connected to the first input end of the first and circuit i1_1, so as to realize that the input end of the Edge detection circuit Edge detection is electrically connected to the first output end of the Pulse GEN of the Pulse transmission circuit.
The second output end of the Pulse GEN is electrically connected with the first input end of the first AND gate circuit I1_1, the output end of the first AND gate circuit I1_1 is electrically connected with the input end of the Switch Logic of the Switch module, and the second output end of the Pulse GEN is electrically connected with the input end of the Switch Logic of the Switch module; the output end of the comparator I1 is electrically connected with the second input end of the first AND gate circuit I1_1.
According to the technical scheme, the application provides a current detection comparison circuit, which comprises: the power supply comprises a plurality of power tubes, an amplifier, a resistor, a comparator, a timing module and a switch module. One end of each power tube is electrically connected with the current input end through a first node, and the other end of each power tube is electrically connected with the current output end through a second node; the power tube is used for conducting current between the current input end and the current output end and detecting a voltage difference between the current input end and the current output end; the first input end of the amplifier is electrically connected with the first node, the second input end of the amplifier is electrically connected with the second node, the output end of the amplifier is electrically connected with the negative input end of the comparator, and the output end of the amplifier is grounded through the resistor; the amplifier is used for amplifying the voltage difference between the current input end and the current output end; the positive input end of the comparator is electrically connected with the reference voltage output end; the output end of the comparator is electrically connected with the input end of the timing module; the comparator is used for comparing the voltage difference between the current input end and the current output end with the reference voltage output by the reference voltage output end; the output end of the timing module is electrically connected with the input end of the switch module; the timing module is used for timing the cycle time; the switch module is electrically connected with the signal input end of each power tube; the switch module outputs a comparison result signal; and the switch module is used for sending a control turnover signal to the power tube so as to adjust the on-resistance of the power tube when the cycle time is met, and outputting a comparison result of the voltage difference between the current input end and the current output end and the reference voltage output by the reference voltage output end. Therefore, the application divides the power tube with current flowing into a plurality of power tubes, adds a timing module, and controls the closing/opening states of the plurality of power tubes through fixed switching period, so that the voltage difference between the two ends (namely the current input end and the current output end) of the power tube can be amplified and compared, the automatic current comparison function is realized, and the current comparison precision is improved. Namely, a power tube composed of M1 and M2 … … Mn, wherein the Total Width of the power tube is consistent with M0; the Timer function consists of Edge Detect, pulse GEN and feedback channel C; edge Detect is to realize the input signal Edge detection, pulse GEN then according to Edge Detect output signal realize the Pulse width signal output; the Switch Logic realizes the control of M1-Mn; according to the application, the power tube through which current flows is divided into M1-Mn, and a timing module Timer comprising edge detect and Pulse GEN is added, and the closing/opening state of M1-Mn is controlled through a fixed switching period, so that the current value information voltage difference between the current input end A and the current output end B at two ends of the power tube can be amplified and compared, an automatic current comparison function is realized, and meanwhile, the current comparison precision is improved.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment is mainly described in a different point from other embodiments. The apparatus and system embodiments described above are merely illustrative, in which the units illustrated as separate components may or may not be physically separate. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present application without undue burden.
The above description is only of the preferred embodiments, but the scope of the application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the technical scope of the present disclosure should be included in the scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims (10)
1. A current sense compare circuit, the current sense compare circuit comprising: the power supply comprises a plurality of power tubes, amplifiers, resistors, comparators, a timing module and a switch module;
one end of each power tube is electrically connected with the current input end through a first node, and the other end of each power tube is electrically connected with the current output end through a second node; the power tube is used for conducting current between the current input end and the current output end and detecting a voltage difference between the current input end and the current output end;
the first input end of the amplifier is electrically connected with the first node, the second input end of the amplifier is electrically connected with the second node, the output end of the amplifier is electrically connected with the negative input end of the comparator, and the output end of the amplifier is grounded through the resistor; the amplifier is used for amplifying the voltage difference between the current input end and the current output end;
the positive input end of the comparator is electrically connected with the reference voltage output end; the output end of the comparator is electrically connected with the input end of the timing module; the comparator is used for comparing the voltage difference between the current input end and the current output end with the reference voltage output by the reference voltage output end;
the output end of the timing module is electrically connected with the input end of the switch module; the timing module is used for timing the cycle time;
the switch module is electrically connected with the signal input end of each power tube; the switch module outputs a comparison result signal; and the switch module is used for sending a control turnover signal to the power tube so as to adjust the on-resistance of the power tube when the cycle time is met, and outputting a comparison result of the voltage difference between the current input end and the current output end and the reference voltage output by the reference voltage output end.
2. The circuit of claim 1, wherein the timing module comprises an edge detection circuit and a pulse transmission circuit.
3. The circuit of claim 2, wherein an input of the edge detection circuit is electrically connected to an output of the comparator; the input end of the edge detection circuit is electrically connected with the output end of the pulse transmitting circuit;
the input end of the pulse transmitting circuit is electrically connected with the output end of the edge detecting circuit; the output end of the pulse transmitting circuit is electrically connected with the input end of the switch module.
4. The circuit of claim 1, wherein the circuit further comprises a first buffer; the output end of the comparator outputs a comparison result of the voltage difference between the current input end and the current output end and the reference voltage output by the reference voltage output end through the first buffer.
5. The circuit of claim 2, wherein the circuit further comprises a first and gate circuit; the first AND gate circuit comprises a first input end, a second input end, an enabling end and an output end;
the output end of the first AND gate circuit is electrically connected with the input end of the edge detection circuit, and the first output end of the pulse transmission circuit is electrically connected with the first input end of the first AND gate circuit so as to realize that the input end of the edge detection circuit is electrically connected with the first output end of the pulse transmission circuit;
the second output end of the pulse transmitting circuit is electrically connected with the first input end of the first AND gate circuit, the output end of the first AND gate circuit is electrically connected with the input end of the switch module, and the second output end of the pulse transmitting circuit is electrically connected with the input end of the switch module;
the output end of the comparator is electrically connected with the second input end of the first AND gate circuit.
6. The circuit of claim 2, wherein the edge detection circuit comprises a first not gate, a first capacitor, a second buffer, and a first nand gate;
the input end of the first NOT circuit is electrically connected with the output end of the comparator; the output end of the first NOT circuit is grounded through the first capacitor and is connected with the input end of the second buffer; the first input end of the first NAND gate is electrically connected with the output end of the comparator, the second input end of the first NAND gate is connected with the output end of the second buffer, and the output end of the first NAND gate is electrically connected with the input end of the pulse transmitting circuit.
7. The circuit of claim 2, wherein the pulse transmit circuit comprises a second not gate, a second capacitor, a third buffer, and a second nand gate;
the input end of the second NOT circuit is electrically connected with the output end of the edge detection circuit; the output end of the second NOT circuit is grounded through the second capacitor and is connected with the input end of the third buffer; the first input end of the second NAND gate is electrically connected with the output end of the edge detection circuit, the second input end of the second NAND gate is connected with the output end of the third buffer,
the output end of the second NAND gate is electrically connected with the input end of the edge detection circuit; the output end of the second NAND gate is electrically connected with the input end of the switch module.
8. The circuit of claim 2, wherein the switch module comprises: a plurality of switching units; each switch unit comprises a trigger and a NAND gate circuit;
for each switch unit, the clock signal input end of a trigger in the switch unit is electrically connected with the output end of the pulse transmitting circuit, and the Q end of the trigger in the switch unit is electrically connected with the signal input end of a power tube corresponding to the switch unit; and the signal input end of the NAND gate circuit in the switch unit is electrically connected with the Q end of the trigger in the adjacent last switch unit.
9. The circuit of claim 2, wherein the switch module comprises: a plurality of switching units; each switch unit comprises a D-type trigger and a NAND gate circuit;
for each switch unit, the clock signal input end of the D-type trigger in the switch unit is electrically connected with the output end of the pulse transmitting circuit, and the QN end of the D-type trigger in the switch unit is electrically connected with the signal input end of the power tube corresponding to the switch unit; the first input end of the NAND gate circuit in the switch unit is electrically connected with the Q end of the D-type trigger in the adjacent last switch unit.
10. The circuit according to claim 8 or 9, wherein the current detection comparison circuit comprises n power transistors, and the switching module comprises n+1 switching units.
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| CN202310131504.6A CN115840075B (en) | 2023-02-17 | 2023-02-17 | Current detection comparison circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP7577582B2 (en) * | 2021-03-22 | 2024-11-05 | ローム株式会社 | Step-down DC/DC converter, controller therefor, control method therefor, and electronic device |
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| CN106018916A (en) * | 2016-05-06 | 2016-10-12 | 北京中电华大电子设计有限责任公司 | Configurable switch voltage drop precision current detection power supply switch circuit structure |
| CN207457327U (en) * | 2017-09-30 | 2018-06-05 | 杰华特微电子（杭州）有限公司 | The current detection circuit and on-off circuit of a kind of on-off circuit |
| CN207816483U (en) * | 2017-12-06 | 2018-09-04 | 西安智多晶微电子有限公司 | Chip core temperature sensing circuit |
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