CN115834870A

CN115834870A - VESA protocol simulation verification method, VESA protocol simulation verification system, VESA protocol simulation verification equipment and storage medium

Info

Publication number: CN115834870A
Application number: CN202211214702.0A
Authority: CN
Inventors: 杨琪; 曹亮; 王新龙; 郭秦岭; 王乃冰
Original assignee: Xian Microelectronics Technology Institute
Current assignee: Xian Microelectronics Technology Institute
Priority date: 2022-09-30
Filing date: 2022-09-30
Publication date: 2023-03-21

Abstract

The invention discloses a VESA protocol simulation verification method, a VESA protocol simulation verification system, VESA protocol simulation verification equipment and a storage medium, wherein the method comprises the steps of building a simulation verification platform, initializing all components in the simulation verification platform, loading a tested piece and testing excitation; detecting the bus time sequence of the tested piece, and optimizing the time sequence error of a single pixel; detecting video parameters of a detected piece, and optimizing video parameter errors of a blanking area; detecting video frame data of a detected piece, and optimizing single-point pixel errors; detecting the video stream of the tested piece, optimizing frame dropping errors, and carrying out synchronous processing on the video frames after frame dropping; and acquiring a simulation verification result. The tolerance to the defects of the tested piece is widened according to the characteristics of the application scene of the video, partial errors of the product in the detection process are optimized, the product is allowed to pass through simulation verification with certain defects, the difficulty of product development is reduced, the research and development period can be shortened, the research and development speed is increased, and the economic benefit is improved.

Description

VESA protocol simulation verification method, VESA protocol simulation verification system, VESA protocol simulation verification equipment and storage medium

Technical Field

The invention belongs to the technical field of image processing, and relates to a VESA protocol simulation verification method, a VESA protocol simulation verification system, VESA protocol simulation verification equipment and a storage medium.

Background

Video is an information carrier frequently contacted in daily life of people, and is essentially a graphic image data stream which is played at a constant speed according to a certain frequency. The FPGA can complete the functions of image data generation, frame rate control and the like in a video system, and can also complete the functions of image data identification, key data monitoring and the like in a more complex system. When the FPGA has a problem, the video may have various errors in formats such as a dead pixel, a broken frame, and even a black screen, so that the reliability of the FPGA needs to be ensured. Simulation verification is an important link for ensuring the quality management of the FPGA. The general FPGA development process needs to be defined, designed, verified and tested in real objects from front to back in sequence, and finally is converted into a product. With the increasing complexity and scale of the design, the probability of the image processor in failure is higher and higher, the difficulty of the verification work is higher and higher, and the period is longer and longer. Therefore, the strategy and the sufficiency of the simulation verification can have great influence on the final quality and the economic benefit of the product.

VESA timing is a video protocol standard defined by the video electronics standards association and is a video protocol with very wide applicability. The authentication policy of VESA video protocols is generally strict. Namely, the DUT (device under test) needs to output the image stream strictly according to the frame rate and video format specified by the video protocol, and simultaneously, the correctness of the pixel data needs to be ensured. The verification strategy is generally defined as that the verification environment needs to examine every data output by the tested object at every clock frame by frame and pixel by pixel, and meanwhile, the stability of the frame frequency needs to be monitored. Any occurring timing or data error is considered to be a fault in the device under test.

Traditional verification strategies are based on protocol verification, and machines or algorithms are different from human recognition patterns of videos. First, humans and machines acquire data in different ways. The machine can acquire video data directly through the camera in an anthropomorphic mode, and can also directly receive and process a communication time sequence. Whereas a person can generally only obtain video information by directly observing the image on the display. Secondly, the sensitivity of human and machine to video is different, and the quality requirement of scene to video is also different. The sensitivity of the machine to video is usually at the pixel level, and the cumulative effect is significant. Because the processing of video by machines is mathematical, algorithms such as convolution, deconvolution, and pooling all process the image pixel by pixel. The human recognition accuracy is lower, and the method is a fuzzy but more intelligent recognition mode, and meanwhile, the forgetting curve is steeper. Generally, a person only needs to identify the information of the whole video or identify the key frame data.

Disclosure of Invention

The invention aims to solve the problems that in the prior art, because the image is processed pixel by pixel, the design complexity and scale of the image processor are increased continuously at present, the difficulty of performing simulation verification on the image processor is increased, and the verification period is longer and longer, and provides a VESA protocol simulation verification method, a VESA protocol simulation verification system, VESA protocol simulation verification equipment and a storage medium.

In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:

a VESA protocol simulation verification method comprises the following steps:

establishing a simulation verification platform, initializing each component in the simulation verification platform, and loading a tested piece and a test excitation;

detecting the bus time sequence of the tested piece, and optimizing the time sequence error of a single pixel;

detecting video parameters of a detected piece, and optimizing video parameter errors of a blanking area;

detecting video frame data of a detected piece, and optimizing single-point pixel errors;

detecting the video stream of the tested piece, optimizing frame dropping errors, and carrying out synchronous processing on the video frames after frame dropping;

and acquiring a simulation verification result.

The invention is further improved in that:

the bus timing of the tested piece is detected by an assertion component; the video parameters of the tested piece are detected by a MON component; the video parameters of the tested piece are detected by the MON component; the video frame data of the tested piece is detected by the SCB component; and detecting the video stream of the detected piece, and synchronizing the acquired image frame and the generated image frame through the SCB assembly.

The method for detecting the video parameters of the detected piece specifically comprises the following steps:

acquiring image data of a tested piece, and acquiring video parameters of the tested piece;

when a field synchronous falling edge is detected, starting to analyze video parameters to obtain video frame data;

when the video parameters are detected to be normal, directly outputting video frame data to the SCB assembly;

when detecting the parameter error of the blanking area in the video parameter, throwing out WARNING abnormity;

when detecting parameter ERRORs of a DE area in video parameters, throwing out ERROR abnormity, and throwing out FATAL abnormity when the ERROR abnormity occurs in continuous N frames;

and outputting the video frame data to the SCB component, and collecting the pixel stream of the next frame.

The detection of the video frame data specifically comprises the following steps:

acquiring image data acquired by the MON component, and detecting an error pixel;

inquiring whether the N frames of video before the error pixel is also the error pixel, if not, throwing out a WARNING error, and entering the comparison of the next frame; if all the previous N frames are ERROR pixels, an ERROR is thrown out firstly, then other pixels with the ERROR pixels as the upper left corner and the range as the M/DPI rectangle are inquired, if all the pixels in the range are the continuous N frames of ERROR pixels, a FATAL ERROR is thrown out, otherwise, the comparison of the next frame is carried out.

The step of performing synchronization processing on the video frames specifically comprises the following steps:

receiving video frame data output by the MON component;

detecting DE area video parameters of video frame data;

when the DE area video parameter is wrong, receiving the next video frame data;

when the video parameters in the DE area are correct, comparing displayable pixels line by line, and recording error pixels;

when the number of error pixels is less than the threshold value, checking the error pixels, automatically increasing the synchronous frame number, and synchronizing the MDL component; when the number of error pixels is larger than the threshold value, judging whether the error pixels are the last frame or not, when the error pixels are not the last frame, automatically increasing the synchronous frame number, and continuously comparing displayable pixels line by line; the last frame, a FATAL error is thrown.

The simulation verification result comprises normal, WARNING abnormity and FATAL abnormity, and when the simulation verification result is normal, the next tested piece is simulated; when the simulation verification result is WARNING abnormity, positioning and analyzing the abnormity problem; and when the simulation verification result is FATAL abnormity, the simulation verification automatically stops.

And after the simulation result is obtained, analyzing the code coverage rate and the function coverage rate of the tested piece, and if the code coverage rate and the function coverage rate are less than 100%, supplementing the test case for performing supplementary test until the code coverage rate and the function coverage rate reach 100%.

A VESA protocol emulation verification system, comprising:

the simulation verification module is used for building a simulation verification platform, initializing each component in the simulation verification platform, and loading a tested piece and test excitation;

the bus time sequence detection module is used for detecting the bus time sequence of the tested piece and optimizing the time sequence error of a single pixel;

the video parameter detection module is used for detecting the video parameters of the detected piece and optimizing the video parameter errors of the blanking area;

the video frame data detection module is used for detecting video frame data of a detected piece and optimizing single-point pixel errors;

the video stream detection module is used for detecting the video stream of the detected piece, optimizing frame dropping errors and carrying out synchronous processing on the video frames after frame dropping;

and the result output module is used for acquiring a simulation verification result.

An apparatus comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the method of any one of the preceding claims when executing the computer program.

A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the steps of the method according to any of the preceding claims.

Compared with the prior art, the invention has the following beneficial effects:

the invention provides a VESA protocol simulation verification method, which relaxes the tolerance of the defects of a tested piece according to the characteristics of the application scene of a video, optimizes partial errors of a product in the detection process, allows the product to pass the verification with certain defects, reduces the development difficulty, can shorten the research and development period, improves the research and development speed and improves the economic benefit.

And the VESA protocol simulation verification system is provided, and verification language is combined with a verification methodology frame, so that intelligent simulation of human video identification characteristics in a simulation verification platform is realized, the tolerance limit of product defects is improved on the premise of ensuring the quality of FPGA products, and the purposes of shortening the product development period and improving economic benefits are achieved.

Drawings

In order to more clearly explain the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

FIG. 1 is a flow chart of the simulation verification method of the intelligent VESA protocol based on the artificial identification feature of the invention;

FIG. 2 is a diagram of the structure of an intelligent VESA protocol simulation verification system based on artificial identification features;

FIG. 3 is a design diagram of an intelligent VESA protocol simulation verification strategy based on artificial identification features;

FIG. 4 is a schematic diagram of a timing verification strategy according to the present invention;

FIG. 5 is a flow chart of the design of the MON component of the present invention;

FIG. 6 is a flow chart of the SCB module design in the present invention;

FIG. 7 is a flow chart of a pixel comparison design in accordance with the present invention;

FIG. 8 is a schematic diagram of the design of the abnormal response of the MDL component in the present invention;

FIG. 9 is a schematic diagram of the data format design of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the embodiments of the present invention, it should be noted that if the terms "upper", "lower", "horizontal", "inner", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which is usually arranged when the product of the present invention is used, the description is merely for convenience and simplicity, and the indication or suggestion that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, cannot be understood as limiting the present invention. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.

Furthermore, the term "horizontal", if present, does not mean that the component is required to be absolutely horizontal, but may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.

In the description of the embodiments of the present invention, it should be further noted that unless otherwise explicitly stated or limited, the terms "disposed," "mounted," "connected," and "connected" should be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

The intelligent VESA video protocol verification strategy based on the artificial identification features comprises a clock timing sequence assertion design strategy, a video parameter monitoring strategy, a video data comparison strategy and a video frame synchronization mechanism. The simulation verification platform is written by SystemVerilog language, and is combined with a UVM verification methodology frame to realize simulation of human video identification characteristics. The method mainly simulates two basic characteristics of manual identification of the abnormity, including an image identification characteristic and a frame frequency identification characteristic. The image identification characteristic is that when continuous large-area color blocks in a video frame are abnormal, a person can identify the abnormality; when the patch area is small or the number of consecutive patches is small, the human cannot perceive it. The frame frequency identification characteristic is that in a continuous image stream, when a plurality of continuous frame images continuously have errors, a person can identify the abnormality; when only one frame or a few discontinuous frame dropping phenomena occur, the human cannot perceive the frame. The simulation verification platform is realized by a Mointor (MON) component, a ScoreBoard (SCB) component, a referenceModel (MDL) component and an ITEM component in a UVM frame standard model, all the components are connected in an integrated mode, and finally an intelligent VESA video protocol verification strategy for manually identifying features is realized.

And detecting the clock frequency by a clock time sequence assertion design strategy, performing exception handling when the output does not meet the frequency requirement of the display all the time, recording pixel level errors, and handing the pixel level errors to an upper-level module for processing. And detecting a pixel region and a blanking region of the output VESA time sequence by a video parameter monitoring strategy, and performing degradation processing on the abnormal data of the blanking region. And (3) detecting whether abnormal color blocks can exist in the pixel area by a video data comparison strategy, wherein the abnormal color blocks comprise single-point pixel errors and continuous block errors, performing abnormal processing on errors reaching a human eye identification threshold value, and performing degradation processing on pixel errors not reaching the threshold value.

The invention is described in further detail below with reference to the accompanying drawings:

referring to fig. 1, it is a flowchart of an intelligent VESA protocol simulation verification method based on artificial identification features, specifically including the following steps:

s1, a simulation verification platform is built, components in the simulation verification platform are initialized, and a tested piece and test excitation are loaded.

And (3) building a verification platform according to a preset structure, compiling platform components through scripts, starting the HDL simulator and running the verification platform, and initializing each component.

If the function of the tested piece is single and the rendering cost is low, the tested piece and the simulation verification platform can be loaded at the same time. And after the loading is successful, loading test case excitation at the platform excitation end, so that the excitation is directly injected into the tested piece.

If the function of the tested piece is complex and the rendering cost is high, the tested piece is not loaded at first, and only the MDL component and the necessary components in the simulation verification platform are loaded. And then loading test case excitation at an excitation end of the simulation verification platform, injecting the excitation into the MDL, and performing persistence processing on data of the MDL. After the test is finished, all the components of the tested piece and the simulation verification platform are reloaded, the MDL components are configured, and then the excitation is injected into the tested piece.

The log file and the simulated waveform window are checked while the test stimulus is loaded.

And S2, detecting the bus time sequence of the tested piece, and optimizing the time sequence error of a single pixel.

And S3, detecting the video parameters of the detected piece, and optimizing the video parameter errors of the blanking area.

S3.1, acquiring image data of the tested piece, and acquiring video parameters of the tested piece;

s3.2, when the field synchronous falling edge is detected, analyzing the video parameters to obtain video frame data;

s3.3, when the detected video parameters are normal, directly outputting video frame data to the SCB assembly;

s3.4, throwing out WARNING abnormity when detecting the parameter error of the blanking area in the video parameters;

s3.5, throwing out ERROR exception when detecting parameter ERRORs of a DE area in video parameters, and throwing out FATAL exception when ERROR exception occurs in continuous N frames;

and S3.6, outputting the video frame data to the SCB assembly, and collecting the pixel stream of the next frame.

And S4, detecting video frame data of the detected piece, and optimizing single-point pixel errors.

S4.1, acquiring image data acquired by the MON component, and detecting error pixels;

s4.2, inquiring whether the N frames of video before the error pixel is also the error pixel, if not, throwing out a WARNING error, and performing comparison of the next frame; if all the previous N frames are ERROR pixels, an ERROR is thrown out firstly, then other pixels with the ERROR pixels as the upper left corner and the range as the M/DPI rectangle are inquired, if all the pixels in the range are the continuous N frames of ERROR pixels, a FATAL ERROR is thrown out, otherwise, the comparison of the next frame is carried out.

And S5, detecting the video stream of the detected piece, optimizing frame dropping errors, and carrying out synchronous processing on the video frames after frame dropping.

S5.1, receiving video frame data output by the MON component;

s5.2, detecting the DE area video parameters of the video frame data;

s5.3, receiving the next video frame data when the video parameter in the DE area is wrong;

s5.4, when the video parameters in the DE area are correct, comparing displayable pixels line by line, and recording error pixels;

s5.5, when the number of error pixels is less than the threshold value, checking the error pixels, automatically increasing the synchronous frame number, and synchronizing the MDL component; when the number of error pixels is larger than the threshold value, judging whether the error pixels are the last frame or not, when the error pixels are not the last frame, automatically increasing the synchronous frame number, and continuously comparing displayable pixels line by line; the last frame, a FATAL error is thrown.

And S6, acquiring a simulation verification result.

If no exception exists in the simulation period, the simulation is normally finished, and the next test case simulation is carried out. If WARNING is abnormal during simulation, after simulation execution is finished, corresponding WARNING information and relevant information after persistence need to be analyzed for problem positioning and analysis. If the simulation verification result is FATAL abnormity, the simulation can be automatically stopped, a tester can perform problem positioning and analysis on site, and the use case is adjusted or redesigned according to the specific situation of the problem.

And S7, carrying out coverage rate analysis on the tested piece.

And analyzing the code coverage rate and the function coverage rate of the tested piece, and if the code coverage rate and the function coverage rate are less than 100%, performing supplementary test on the supplementary test case until the code coverage rate and the function coverage rate reach 100%.

Referring to fig. 2, which is a structural diagram of the intelligent VESA protocol simulation verification system based on the artificial identification features of the present invention, the system includes:

the bus time sequence detection module is used for detecting the bus time sequence of a detected piece and optimizing the time sequence error of a single pixel;

Referring to fig. 3, a design diagram of the simulation verification strategy of the intelligent VESA protocol based on the artificial identification features of the present invention is shown, in which the simulation verification strategy mainly aims at the output quality of the video, but not at the input features or the relationship between the excitation and the output. Therefore, the MON, SCB and MDL components are primarily designed. The VESA protocol is abstracted into four layers from bottom to top, namely a bus time sequence, video parameters, video frame data and a video stream. The assertion component detects the abnormity of the bus time sequence, the MON component detects the abnormity of the video parameters, the SCB component detects the abnormity of the video frame data, and the MON component and the SCB component both adopt a sliding window algorithm to detect the abnormity of the video stream. The simulation verification strategy in the invention is as follows: when the time sequence of the single pixel point is not satisfied, the display effect is not influenced, and the display effect is optimized at the assertion layer. The video parameter error occurs in the blanking area, does not affect the display effect, and is optimized at the MON layer. The display effect is not influenced by errors with smaller error ranges of pixel values, and the errors are optimized in the SCB layer. Besides pixel-by-pixel comparison, the SCB can also extract feature values by adopting a pattern recognition correlation algorithm, and perform deep optimization on a pixel value comparison strategy.

Referring to fig. 4, a schematic diagram of the timing verification strategy in the present invention is shown, and according to the influence on the display result, the following two timing factors are considered: the stability of the output video synchronous clock of the tested piece and whether the establishment time and the holding time of the communication of the single pixel are satisfied. The synchronous clock output by the tested piece is the basis for displaying data by the display. When the output clock does not meet the requirement, the display can display no signal or close the screen, which is obviously a false error. It is therefore necessary to design a special assertion to check the frequency of the clock signal and to throw a FATAL level exception when the frequency is out of range.

Setup and hold time errors for a single pixel generally have no effect on the display of video data. When the timing does not meet the requirements, ASSERT will FAIL, and if there is no special processing, the simulator will call the $ error function. Then the communication timing ERROR of a single pixel is optimized from ERROR level ERROR to WARNING level under the simulation verification strategy in the present invention.

Referring to fig. 5, which is a flow chart of the design of the MON component in the present invention, the main functions of the MON component are to analyze the timing sequence of the video bus, check the video parameters, collect image data, and analyze the video frame data. The image data and the video frame data are generalized video data containing blanking areas, and the analyzed video frame data are output to the SCB component. The specific working process of the MON component is as follows:

whenever a field sync falling edge is detected, parsing of the previous frame pixel stream is started, and if all parameters are correct, the video frame data is sent directly to the SCB component's queue. If any parameter is wrong, the area where the error occurred needs to be analyzed. If the blanking region parameters are in error, including field sync, field back shoulder and field front shoulder, a WARNING level error is thrown. If an ERROR occurs in the DE area, including the number of image rows, columns, row back shoulders, row syncs, and row front shoulders, an ERROR level ERROR is thrown. And then continuously checking whether the continuous N frames are in ERROR or not, and throwing a FATAL level ERROR if the ERROR level ERRORs occur in the continuous N frames. And sending the video frame data to the SCB module, and starting to acquire the next frame of pixel stream.

Referring to fig. 6, a flow chart of SCB module design in the present invention, the synchronization design is mainly to solve the frame dropping error caused by the abnormal occurrence of field signal and the frame dropping error occurred in the design itself. Frame dropping errors caused by field signal anomalies can cause the MON component to resolve to the image base parameters of the Nth and (N + 1) th frames if the field sync signal is jittered once when the MDL component expects the Nth frame, which can cause frame synchronization. Frame dropping errors occur in the design, if freezing occurs in the tested piece when the MDL component expects the Nth frame, the data of the (N + 1) th, the (N + 2) th, the (8230) th and the (N + M-1) th frames are not output, and then the data after the N + M expected by the MDL are directly output. An MDL expected data queue of N frames is maintained in the SCB component, and the frame sequence numbers of the MDL expected data queue are respectively from MDLFrameM to MDLFrameM + N from beginning to end, the received Monitor data number MonFrameN is received, and the error threshold value is N. And when the number of unmatched pixels of the MonFrameN and all frame data in the expected queue is greater than N, the tested piece is considered to be out of synchronization, and when the number of unmatched pixels of any frame data is less than N, the tested piece is in a synchronization state.

When receiving MonFramen, firstly checking whether the DE area video parameters of the video data are correct, if so, the frame is not compared, and waiting for the next frame.

If the DE area video parameters are correct, the MonFramen and the MDLFrameM are compared line by line. If the alignment is correct, the expected queue is updated with MDLFrameM +1 as the queue head.

If not, then sequentially compare MDLFrameM +1, MDLFrameM +2 backwards until MDLFrameM + N. If the expected sequence MDLFrameM + X is aligned correctly, an ERROR ERROR is thrown, and the expected queue is updated by using the MDLFrameM + X as the queue head. If none of the data in the queue matches an error, a FATAL error is thrown. The connotation logic is equivalent to that the frame skipping time interval of the tested piece cannot be larger than the recognition degree of people.

Referring to fig. 7, a flow chart of pixel comparison design in the present invention first inquires for each error pixel whether the previous N frames of images are also the same error pixel. If not, a WARNING error is thrown out, and the comparison process of the next frame is entered. If the previous N frames are all the same, an ERROR is thrown out, then other pixels in a rectangle with the pixel as the TOP LEFT corner (TOP, LEFT) and the range as M/DPI are inquired, if the pixels in the range are all continuous N frame ERROR pixels, a FATAL ERROR is thrown out, otherwise, the comparison process of the next frame is started.

In addition to pixel blob anomalies, the SCB may also employ a more intelligent comparison method. The existing algorithm level can simulate partial characteristics of artificial intelligence, a characteristic value extraction algorithm is selected, the tolerance range of the characteristic value is compared, the tolerance range can be further expanded, and a verification strategy is optimized.

Referring to fig. 8, which is a schematic diagram of the abnormal response design of the MDL component of the present invention, the MDL component mainly aims at two optimization problems: exception injection response and data persistence. For the problem of abnormal injection response, the MDL component needs to output a null frame with correct video parameters and random pixel data for the abnormal injection completion affecting the video parameters. Because the receiving object of the tested piece is a person, even if the tested piece can correctly respond to the abnormal injection and output the abnormal video frame, the display effect of the abnormal video frame can still be captured by a user, and under the verification strategy of the invention, the verification environment still throws an abnormality at the MON level or the SCB level.

Referring to fig. 9, a schematic diagram of the data format design in the present invention can be abstracted into 4 data areas according to the top-down decomposition of the VESA time sequence: VSync, VBP, active Area, and VFP. Each section is a queue of rows, and in addition to maintaining row data, the number of rows in the respective stage needs to be maintained. For row data, considering that the DE signal may have multiple abnormal flips, in addition to defining normal HBP, DE and HFP data areas, a DEN data is additionally defined to indicate the part between several DE in the same row. The HFP definition is extended to data from the last DE falling edge to the HSYNC falling edge.

In addition to abstracting the communication data, ITEM also needs to support synchronization between MDLs, MONs, SCBs. First, the expected data generated by the MDL needs to be written to the expected frame number N1. Secondly, MON needs to write in the video frame number N2 gathered, SCB needs to write in the successful synchronous frame number N3 of matching finally, if the synchronism fails, write in a NaN or-1. SCB needs to implement pixel comparison result recording, so an ErrorPixel list or a feature value is maintained in Active Area.

In the invention, an intelligent VESA protocol simulation verification method based on artificial identification features adopts SystemVerilog language and UVM verification methodology and framework. The simulation verification environment can monitor and analyze the VESA protocol, can compare expected data with actually measured result data, and records the expected data and the actually measured result data into a log. Anomalies of the tested piece can be automatically detected, and the anomalies are recorded and graded according to the verification strategy.

Compared with the traditional verification method, the verification method mainly aims to relax the tolerance of the defects of the tested piece according to the characteristics of the application scene of the video and allow the product to pass the verification with certain defects, so that the development difficulty is reduced, the development period can be shortened, and the development speed is increased. However, as market competition is increasingly intense, project development progress is a more preferential factor in some cases, and the FPGA supports repeated programming, so that slight quality problems can be repaired in a rewriting upgrading mode after products are released. In the VESA protocol product project based on the FPGA with low key level, the method can reduce the research and development cost and obviously improve the economic benefit.

An embodiment of the present invention provides a terminal device. The terminal device of this embodiment includes: a processor, a memory, and a computer program stored in the memory and executable on the processor. The processor implements the steps in the above-described embodiments of the VESA protocol simulation verification method when executing the computer program. Alternatively, the processor implements the functions of the modules/units in the above device embodiments when executing the computer program.

The computer program may be partitioned into one or more modules/units that are stored in the memory and executed by the processor to implement the invention.

The VESA protocol simulation verification device/terminal equipment can be computing equipment such as a desktop computer, a notebook computer, a palm computer and a cloud server. The VESA protocol simulation verification device/terminal equipment can include, but is not limited to, a processor and a memory.

The Processor may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, etc.

The memory can be used for storing the computer program and/or the module, and the processor can realize various functions of the VESA protocol simulation verification device/terminal equipment by running or executing the computer program and/or the module stored in the memory and calling the data stored in the memory.

The integrated module/unit of the VESA protocol simulation verification device/terminal equipment can be stored in a computer readable storage medium if the module/unit is realized in the form of a software functional unit and sold or used as an independent product. Based on such understanding, all or part of the flow of the method according to the embodiments of the present invention may also be implemented by a computer program, which may be stored in a computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method embodiments may be implemented. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, read-Only Memory (ROM), random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A VESA protocol simulation verification method is characterized by comprising the following steps:

building a simulation verification platform, initializing each component in the simulation verification platform, and loading a tested piece and test excitation;

and acquiring a simulation verification result.

2. The VESA protocol simulation verification method according to claim 1, wherein the bus timing of the tested piece is detected by an assertion component; the video parameters of the tested piece are detected by the MON component; the video parameters of the tested piece are detected by the MON component; the video frame data of the tested piece is detected by the SCB component; and detecting the video stream of the detected piece, and synchronizing the acquired image frame and the generated image frame through the SCB assembly.

3. The VESA protocol simulation verification method according to claim 2, wherein the detecting the video parameter of the tested piece specifically includes the following steps:

4. The VESA protocol simulation verification method of claim 2, wherein the detecting video frame data specifically comprises the steps of:

5. The VESA protocol simulation verification method of claim 2, wherein the synchronization processing of the video frames specifically comprises the steps of:

receiving video frame data output by the MON component;

detecting DE area video parameters of video frame data;

when the DE area video parameter is wrong, receiving the next video frame data;

6. The VESA protocol simulation verification method according to claim 1, wherein the simulation verification result includes normal, WARNING abnormal and FATAL abnormal, and when the simulation verification result is normal, the next tested piece simulation is entered; when the simulation verification result is WARNING abnormity, positioning and analyzing the abnormity problem; and when the simulation verification result is FATAL abnormity, the simulation verification automatically stops.

7. The VESA protocol simulation verification method of claim 1, wherein after obtaining the simulation result, analyzing the code coverage and the function coverage of the tested piece, if the code coverage and the function coverage are less than 100%, the supplementary test case carries out supplementary test until the code coverage and the function coverage reach 100%.

8. A VESA protocol simulation verification system is characterized by comprising:

9. An apparatus comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any of claims 1-7 when executing the computer program.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.