CN115833560A - SenseFET type full-wave inductive current sensor - Google Patents

Abstract

The invention discloses a SenseFET type full-wave inductive current sensor and relates to electronic technology. It includes a power stage, used to modulate the inductor current I _L ; a valley current sensor, used to collect the valley value inductor current signal I _L,valley and output the drain voltage VX _valley ; a peak current sensor, used to collect and output the sampling signal I _Lsen =I _L /A _L ; the peak value enable signal generator is used to generate the enable signal in the peak current sensor; the valley value enable signal generator is used to generate the enable signal in the valley value current sensor. The present invention ensures the output during the dead zone of the current sensor by setting the dead zone sampling and holding capacitor, which can reduce the slew rate requirement of the operational amplifier and the bandwidth requirement of the negative feedback closed loop, and also avoids the impact of the dead zone sampling and holding capacitor on the negative feedback closed loop bandwidth Limits, improve the sampling accuracy of I _Lsen .

Description

A SenseFET type full-wave inductive current sensor

technical field

The invention relates to electronic technology, and more specifically, it relates to a SenseFET type full-wave inductive current sensor.

Background technique

The inductance current sensor is used to collect the information of the inductance current I _L in real time, and output I _L /A _L in equal proportion to the control system, and A _L is called the sensing ratio and is a constant. Inductive current sensors are commonly used in the control system of current-mode switching inductors DC-DC to modulate and limit the amplitude of the inductor current. As a relatively independent sub-module of the control system, they are often studied separately. The SenseFET current sensor has the advantages of high integration, low loss, and controllable precision, and has attracted much research interest.

As shown in Figure 1, in the DC-DC structure, the input stage power transistors MP and MN are turned on alternately, and the conduction states of each other do not overlap, and the inductor current must flow through MP and MN. The SenseFET current sensor utilizes this One feature, the sensing inductor current is obtained by sampling the drain currents of the power transistors MP and MN respectively ^[1] . Assuming that the drain currents flowing through the power transistors MP and MN are I _L,peak and I _L,valley respectively, representing the rising phase and the falling phase of IL, that is, I _L =I _{L ,peak} +I _L,valley , through The two negative feedback closed loops G _peak and G _valley respectively make the power transistor MP and the field effect transistor MP _m1 , the power transistor MN and the field effect transistor MN _m1 two groups of current mirrors in the same bias state. At this time, if the size of the current mirror satisfies MP:MP _m1 ＝MN:MN _m1 ＝ _AL :1, then the currents of MP _m1 and MN _m1 are I _Lsen,peak ＝I _L,peak /A _L and I _Lsen,valley ＝ I _L,valley /A _L , the sensing current I _Lsen =I _L /A _L can be obtained by directly adding I _Lsen,peak and I _Lsen,valley .

There are two problems in the traditional structure of the SenseFET type current sensor:

1. The power tubes MP and MN are turned on alternately. During the stable period of the negative feedback closed-loop G _peak , the operational amplifier OPA _valley in the negative feedback closed-loop G _valley is in a saturated or cut-off state. Every time the power tube MN is turned on, the operational amplifier OPA _Valley needs to go through a start-up process, which takes a long time and has large errors during the process. The same problem will also appear at the beginning of the conduction of the power tube MP. This problem places high demands on the slew rate of OPA _peak and OPA _valley and the bandwidth of negative feedback closed-loop G _peak and G _valley .

2. There is a dead zone when the power tubes MP and MN are turned on alternately. During the dead zone, the sampling signals I _Lsen,peak and I _Lsen,valley are all 0, but I _L is not 0, and the sensing current has no output and introduce huge errors.

For the above problems, the public literature [2-8] uses a common output stage to optimize the transition process of the SenseFET current sensor during the alternate conduction period of the power transistors MP and MN. By keeping the output stage in the linear region, the op amp OPA _peak can be reduced. And the performance requirements of OPA _valley slew rate. Among them, the public literature [2-6] shares the op amp structure (that is, the op amp OPA _peak and OPA _valley are the same op amp), and adds a dead-zone sampling and holding capacitor to the output stage of the op amp to solve the problem of no output of the sensing current during the dead zone. problems, and further reduce the op amp slew rate requirements. However, the dead-zone sampling and holding capacitor appears in the negative feedback closed-loop G _peak and G _valley , which limits the bandwidth growth of the closed loop, and is not easy to quickly stabilize the negative feedback closed-loop G _peak and G _valley . Both the gain and the bandwidth of G _valley are subject to the negative feedback closed-loop G _peak , which reduces the sampling accuracy of the inductor current I _L,valley in the falling phase. However, the public literature [7,8] adopts a common output stage, but does not share the structure of the op amp, ignores the problem of no output of the sensing current during the dead zone, and only optimizes the power tube MN to the power tube MP. During the turning process of the current sensor, the sampling accuracy of I _{L, valley} is very low.

The following are the eight publications mentioned above.

[1]Man T Y, Mok P K T, Chan M.Design of Fast-Response On-Chip CurrentSensor for Current-Mode Controlled Buck Converters with MHz SwitchingFrequency[C].2007IEEE International Conference on Electron Devices and Solid-State Circuits,2007:389 -392.

[2]Zhu L, Chen B, Zheng Y, et al.AFast-Response Buck-Boost DC-DC Converter with Constructed Full-Wave Current Sensor[C].2016International Symposium on Integrated Circuits,2016.

[3]Li B, Yang J, Wu Z, et al.AFast-Response Full-Wave Current-Sensing Circuit for DC-DC Converter Operating in 10MHz Switching Frequency[C].2017International Conference on Electron Devices and Solid-State Circuits,2017 .

[4]Zhou Y, Zheng Y, Leung K N. Fast-Response Full-Wave Inductor CurrentSensor for 10MHz Buck Converter[J].Electronics Letters,2018,54(6):379-380.

[5] Zhou Y, Lin X, Yang J, et al. Adaptive-Biased Sense-FET-Based Inductor-Current Sensor for 10-MHz Buck Converter [J]. International Journal of Circuit Theory and Applications, 2020, 48(6): 953-964.

[6] Zhou Y, Cheng Q, Li J, et al.Full-Wave Sense-FET-Based Inductor-Current Sensor With Wide Dynamic Range for Buck Converters[J].IEEE Transactions on Circuits and Systems II: Express Briefs, 2022, 69(4):2041-2045.

[7] Jung-Woo H, Bai-Sun K, Jung-Hoon C, et al.AFast Response Integrated Current-Sensing Circuit for Peak-Current-Mode Buck Regulator[C].ESSCIRC2014-40th European Solid State Circuits Conference,2014: 155-8.

[8] Zhou M, Sun Z, Low Q W, et al. Multiloop Control for Fast Transient DC-DC Converter [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(1): 219-228.

Contents of the invention

The technical problem to be solved by the present invention is to provide a SenseFET type full-wave inductive current sensor aiming at the deficiencies of the prior art.

The technical scheme of the present invention is: a kind of SenseFET type full-wave inductive current sensor, comprises,

The power stage is composed of a first power transistor MP and a second power transistor MN whose drains are connected, and the drain connection terminals of the first power transistor MP and the second power transistor MN output an inductor voltage signal VX;

A valley value current sensor, including a first operational amplifier OPA _valley , a fourteenth field effect transistor M ₁₄ , a first field effect transistor M ₁ , a second field effect transistor M ₂ and a first control unit; the second field effect transistor The source of M ₂ is connected to the input terminal of the power stage, the gate of the second field effect transistor M ₂ is connected to the signal ground, the drain of the second field effect transistor M ₂ outputs the drain voltage VX _valley , and the The drain of the second field effect transistor _M2 is connected to the source of the fourteenth field effect transistor _M14 ; the gate of the fourteenth field effect transistor _M14 is connected to the output terminal of the first operational amplifier OPA _valley , The drain of the fourteenth field effect transistor M ₁₄ is connected to the positive phase input end of the first operational amplifier OPA _valley through the first control unit to form a first negative feedback closed loop G _valley ; the first control unit is also connected to the first control unit A negative phase input terminal of an operational amplifier OPA _valley is connected to control the first negative feedback closed loop G _valley to be an open loop or a closed loop; the drain of the first field effect transistor M ₁ inputs the inductance voltage signal VX, the The gate of the first field effect transistor M ₁ is input in the first control unit to be used to control the first negative feedback closed loop G _valley to be a closed loop enable signal, and the source of the first field effect transistor M ₁ is connected to the control unit;

The peak current sensor includes a second operational amplifier OPA _peak , a sixth field effect transistor M ₆ , a third field effect transistor M ₃ , a pair of mirror transistors and a second control unit; the output terminal of the second control unit is connected to the second operational amplifier The negative phase input terminal of the amplifier OPA _peak is connected for time-sharing input of the drain voltage VX _valley and the inductor voltage signal VX; and the negative phase input terminal of the second operational amplifier OPA _peak is connected with a dead zone sampling and holding capacitor C _s ; The output terminal of the second operational amplifier OPA _peak is connected to the gate of the sixth field effect transistor _M6 , and the drain of the sixth field effect transistor _M6 is connected to the positive electrode of the second operational amplifier OPA _peak through the second control unit. The phase input terminal is connected to form the second negative feedback closed loop G _peak ; the drain of the sixth field effect transistor _M6 is connected to the drain of the third field effect transistor _M3 , and the gate of the third field effect transistor _M3 The pole is connected to the signal ground, the source of the third field effect transistor _M3 is connected to the input end of the power stage; the source electrode of the sixth field effect transistor _M6 is connected to the input end of the mirror transistor pair, and the mirror transistor The output terminal of the pair outputs the sampling signal I _Lsen .

The mirror image ratio of the first power transistor MP and the second field effect transistor _M2 is _AL : 1, the mirror image ratio of the first power transistor MP and the third field effect transistor _M3 is _AL : 1, and the The mirror image ratio of the second power transistor MN and the first field effect transistor _M1 is _AL :1.

The first power transistor MP, the second field effect transistor M ₂ and the third field effect transistor M ₃ are all PMOS; the second power transistor MN and the first field effect transistor M ₁ are all NMOS.

When the first power transistor MP is turned on and the second power transistor MN is turned off, the inductor current I _L flows through the first power transistor MP, and the inductor current at this stage has a peak value I _L = _IL,peak . The first control unit controls the input terminals of the first operational amplifier OPA _valley to be grounded, so that the first operational amplifier OPA _valley works in the linear region, and the first negative feedback closed loop G _valley is an open loop. The second control unit controls the inverting input terminal of the second operational amplifier OPA _peak to input the drain voltage of the first power transistor MP, that is, the inductor voltage signal VX. Since the second negative feedback closed loop G _peak is a closed loop, so that the third field effect transistor _M3 and the first power transistor MP are in the same bias state, the leakage current of the third field effect transistor _M3 is _IL,peak /A _L , and is equal to the leakage current of the field effect transistor in the mirror tube pair, that is, I _Lsen =I _L,peak /A _L .

When the first power transistor MP is turned off and the second power transistor MN is turned on, the inductor current I _L flows through the second power transistor MN, and the inductor current at this stage is a valley value I _L = _IL,valley . The first control unit controls the first negative feedback closed-loop G _valley to be in a closed-loop state, so that the first field effect transistor _M1 and the second power transistor MN are in the same bias state, and the second field effect transistor M The drain current of ₂ is equal to the drain current of the first field effect transistor M ₁ , which is I _L,valley /A _L . The second control unit controls the inverting input terminal of the second operational amplifier OPA _peak to input the drain voltage VX _valley , and the second negative feedback closed loop G _peak formed by the second operational amplifier OPA _peak and the sixth field effect transistor _M6 makes the first The second FET _M2 and the third FET _M3 are in the same bias state, then the leakage current of the third FET _M3 is I _L,valley /A _L , that is, I _Lsen =I _L,valley /A _L.

The first control unit includes an eighth field effect transistor M ₈ , a ninth field effect transistor M ₉ , a tenth field effect transistor M ₁₀ and an eleventh field effect transistor M ₁₁ ; the ninth field effect transistor M ₉ Both the gate and the gate of the first field effect transistor _M1 are input with the second enable signal _PSn , and the source of the ninth field effect transistor _M9 is connected to the drain of the fourteenth field effect transistor _M14 , so The drain of the ninth field effect transistor _M9 is connected to the non-inverting input end of the first operational amplifier OPA _valley , and the inverting input end of the first operational amplifier OPA _valley is grounded through the eleventh field effect transistor _M11 , and The gate of the eleventh field effect transistor _M11 is connected to the input end of the power stage; the source of the first field effect transistor _M1 is connected to the drain of the eighth field effect transistor M8, and the eighth field effect transistor M1 is connected to the drain of the _eighth field effect transistor M8. The source of the field effect transistor _M8 is connected to the signal ground; the non-inverting input terminal of the first operational amplifier OPA _valley is connected to the drain of the tenth field effect transistor _M10 , and the source of the tenth field effect transistor _M10 connected to the signal ground; and the gates of the eighth field effect transistor _M8 and the tenth field effect transistor _M10 are connected to input a fifth enabling signal whose signal state is opposite to that of the second enabling signal _PSn ! PS _n .

The second control unit includes a fourth field effect transistor M ₄ , a fifth field effect transistor M ₅ and a seventh field effect transistor M ₇ ; the gate of the fourth field effect transistor M ₄ inputs a third enabling signal LVX , the source of the fourth field effect transistor _M4 inputs the inductor voltage signal VX; the gate of the fifth field effect transistor _M5 inputs the fourth enabling signal LVX _valley , and the _fifth field effect transistor M5 Source input drain voltage VX _valley ; the drains of the fourth field effect transistor _M4 and the fifth field effect transistor _M5 are connected to the inverting input terminal of the second operational amplifier OPA _peak ; the seventh field effect The gate of the transistor _M7 is connected to the signal ground, the drain of the seventh field effect transistor _M7 is connected to the positive input terminal of the second operational amplifier OPA _peak , and the source of the seventh field effect transistor _M7 is connected to the first The drains of the six field effect transistors _M6 are connected.

SenseFET type full-wave inductive current sensors also include,

Valley enable signal generator for seventh enable signal based on input! BPS _n , output the second enabling signal PS _n and the fifth enabling signal! PS _n and the fourth enabling signal LVX _valley ;

Peak enable signal generator for the sixth enable signal according to the input! BPS _p , outputting the first enabling signal PS _p and the third enabling signal LVX.

The sixth enable signal! There is a first delay t _senlop between the rising edge of the BPS _p and the falling edge of the third enabling signal LVX, and the falling edge of the third enabling signal LVX lags behind the sixth enabling signal! Rising edge of BPS _p ;

There is a second delay t _senlov between the rising edge of the second enabling signal PS _n and the falling edge of the fourth enabling signal LVX _valley , and the falling edge of the fourth enabling signal LVX _{valley lags behind the falling edge of the fourth enabling signal LVX valley} Second, the rising edge of the enable signal PS _n .

The peak enable signal generator includes a fifteenth field effect transistor M ₁₅ , a sixteenth field effect transistor M ₁₆ , a seventeenth field effect transistor M ₁₇ , an eighteenth field effect transistor M ₁₈ , a first inverter INV ₁ , the first NAND gate NAND ₁ , the first resistor R _senlop , and the first capacitor C _senlop ; the gates of the fifteenth field effect transistor M ₁₅ and the seventeenth field effect transistor M ₁₇ are all input to the sixth enabling can signal! BPS _p , the source of the fifteenth field effect transistor M ₁₅ inputs the voltage source signal V _source , the drains of the fifteenth field effect transistor M ₁₅ and the seventeenth field effect transistor M ₁₇ are connected and serve as the first The signal output terminal of the enable signal PS _p ; the source of the seventeenth field effect transistor M ₁₇ is connected to the power ground PGND; the gates of the sixteenth field effect transistor M ₁₆ and the eighteenth field effect transistor M ₁₈ Connect to the enable signal! BPS _p , the source of the sixteenth field effect transistor M ₁₆ is connected to the input voltage source signal V _source , one end of the first resistor R _senlop , one end of the first capacitor C _senlop , the sixteenth field effect transistor M ₁₆ The drains of each are connected to the input terminal of the first inverter INV ₁ , and the other terminal of the first resistor R _senlop is connected to the drain of the eighteenth field effect transistor _M18 , and the eighteenth field effect transistor _M18 The source of the first capacitor C _senlop and the other end of the first capacitor C senlop are both connected to the signal ground; the output end of the first inverter INV ₁ is connected to an input end of the first NAND gate NAND ₁ , and the first NAND gate The other input terminal of NAND ₁ inputs the sixth enabling signal! BPS _p , the output terminal of the first NAND gate NAND ₁ outputs the third enabling signal LVX.

The valley enable signal generator includes a second capacitor C _senlov , a nineteenth field effect transistor M ₁₉ , a twentieth field effect transistor M ₂₀ , a second inverter INV ₂ , a third inverter INV ₃ , The fourth inverter INV ₄ , the fifth inverter INV ₅ and the second NAND gate NAND ₂ ; the gates of the nineteenth field effect transistor M ₁₉ and the twentieth field effect transistor M ₂₀ are all input to the seventh Enable signal! BPS _n , the source of the nineteenth field effect transistor M ₁₉ inputs the voltage source signal V _source , the drains of the nineteenth field effect transistor M ₁₉ and the twentieth field effect transistor M ₂₀ are connected as the second The signal output end of the enable signal PS _n , and the drain connection ends of the nineteenth field effect transistor M ₁₉ and the twentieth field effect transistor M ₂₀ are respectively connected to the third inverter INV ₃ and the fifth inverter The input terminal of INV ₅ is connected, the source of the twentieth field effect transistor M ₂₀ is connected to the power ground PGND; the output terminal of the fifth inverter INV ₅ is used as the fifth enabling signal! The signal output end of PS _n ; the output end of the third inverter INV ₃ is connected to the input end of the fourth inverter INV ₄ , and one end of the second capacitor C _senlov is connected to the third inverter INV ₃ The output end is connected, and the other end of the second capacitor C _senlov is connected to the signal ground; the output end of the fourth inverter INV ₄ is connected to an input end of the second NAND gate NAND ₂ , and the second NAND The other input terminal of the gate NAND ₂ is connected to the output terminal of the second inverter INV ₂ , and the input terminal of the second inverter INV ₂ inputs the seventh enable signal! BPS _n , the output terminal of the second NAND gate NAND ₂ serves as the signal output terminal of the fourth enabling signal LVX _valley .

Beneficial effect

The advantages of the present invention are:

1. Compared with the SenseFET type current sensor with traditional structure, the present invention has the characteristics of common output stage and dead-zone sampling and holding capacitance. The operational amplifier OPA _peak and OPA _valley are both kept in the linear zone, and the dead-zone sampling and holding capacitance ensures that the current sensor is dead. The output during the region can reduce the slew rate requirements of OPA _peak and OPA _valley and the bandwidth requirements of negative feedback closed-loop G _peak and G _valley .

2. Compared with the SenseFET current sensor with a common output stage and a common operational amplifier structure, the negative feedback closed-loop G _peak in the present invention remains stable, which can reduce the bandwidth requirement for the negative feedback closed-loop G _peak . The negative feedback closed-loop G _peak and G _valley are relatively independent, avoiding the limitation of the negative feedback closed-loop G _peak bandwidth on the negative feedback closed-loop G _valley bandwidth. The dead zone sampling and holding capacitor is placed outside the negative feedback closed loop G _peak and G _valley , avoiding the limitation of the dead zone sampling and holding capacitor on the bandwidth of the negative feedback closed loop G _peak and G _valley .

3. Compared with the SenseFET type current sensor which has a common output stage but does not share the op-amp structure, in the present invention, the op-amp OPA _valley is maintained in the linear region, and has a dead-zone sampling and holding capacitance, which optimizes the cut-off of the power tube MP to the power tube MN The turning process of the current sensor during the conduction period improves the sampling accuracy of _IL,valley .

Description of drawings

FIG. 1 is a schematic structural diagram of a SenseFET type current sensing circuit with a traditional structure;

Fig. 2 is the SenseFET type current sensor circuit structure schematic diagram of the present invention;

Fig. 3 is the timing wave schematic diagram of enabling signal in the SenseFET type current sensor of the present invention;

Fig. 4 is a schematic structural diagram of a peak enabling signal generator circuit of the present invention;

FIG. 5 is a schematic structural diagram of a valley enabling signal generator circuit according to the present invention.

Detailed ways

Below in conjunction with embodiment, the present invention is further described, but does not constitute any restriction to the present invention, anyone makes the limited number of amendments in the scope of claims of the present invention, still within the scope of claims of the present invention.

Referring to FIG. 2 , a SenseFET type full-wave inductive current sensor of the present invention includes a power stage, a valley current sensor, a peak current sensor, a valley enabling signal generator and a peak enabling signal generator.

Among them, the power stage is used to modulate the inductor current I _L . The power stage is composed of a first power transistor MP and a second power transistor MN connected with drains. The first power transistor MP is a PMOS transistor, and the second power transistor MN is an NMOS transistor. The gate of the first power transistor MP inputs the first enabling signal PS _p , the gate of the second power transistor MN inputs the second enabling signal PS _n having the same signal state as the first enabling signal PS _p , and the first power transistor MN The substrate of the MP is connected to the source. The source of the first power transistor MP is used as the input terminal of the power stage, which receives a voltage source signal V _source , the source of the second power transistor MN is connected to the power ground PGND, and the substrate of the second power transistor MN is connected to the signal ground. The drains of the first power transistor MP and the second power transistor MN are connected to output an inductor current signal I _L , and the output inductor voltage signal is denoted as VX. The first power transistor MP and the second power transistor MN are turned on alternately, and the conduction states of each other are not overlapped. That is, there is a dead zone between the first power transistor MP and the second power transistor MN, and there is also a dead zone between the first enable signal PS _p and the second enable signal PS _n .

The valley current sensor is used to collect the valley inductor current signal I _L,valley and output the drain voltage VX _valley of the second field effect transistor M ₂ . It includes a first operational amplifier OPA _valley , a fourteenth field effect transistor M ₁₄ , a first field effect transistor M ₁ , a second field effect transistor M ₂ and a first control unit. The first control unit includes an eighth field effect transistor M ₈ , a ninth field effect transistor M ₉ , a tenth field effect transistor M ₁₀ and an eleventh field effect transistor M ₁₁ . The first FET M ₁ , the eighth FET M ₈ , the ninth FET M ₉ , the tenth FET M ₁₀ and the eleventh FET M ₁₁ are all NMOS tubes, and the second FET M ₂ and the fourteenth field effect transistor M ₁₄ are PMOS transistors. The specific circuit connection structure of the valley current sensor is as follows.

The source of the second field effect transistor _M2 is input with the voltage source signal _Vsource , its gate is connected to the signal ground, and its drain is used as the output terminal of the output drain voltage VX _valley , and is connected with the source of the fourteenth field effect transistor _M14 pole connection. The inverting input terminal of the first operational amplifier OPA _valley is connected to the drain of the eleventh field effect transistor _M11 , the source of the eleventh field effect transistor _M11 is grounded, and the gate input of the eleventh field effect transistor _M11 A voltage source signal V _source . The non-inverting input terminal of the first operational amplifier OPA _valley is respectively connected to the drains of the ninth field effect transistor M ₉ and the tenth field effect transistor M ₁₀ , the source of the tenth field effect transistor M 10 is connected to the signal ground, and the tenth field effect transistor M ₁₀ is connected to the signal ground. The gates of the effect transistor _M10 and the eighth field effect transistor _M8 are connected to input the fifth enabling signal! PS _n . The state of the gate input signal of the ninth field effect transistor _M9 and the fifth enabling signal! The second enabling signal PS _n opposite to PS _n , the source of the ninth field effect transistor _M9 is connected to the source of the first field effect transistor _M1 , the drain of the fourteenth field effect transistor _M14 and the eighth field effect transistor M14 respectively. The drain of the effect transistor _M8 is connected, and the source of the eighth field effect transistor _M8 is connected to the signal ground. The gate of the first field effect transistor M ₁ receives the second enabling signal PS _n , and the drain of the first field effect transistor M ₁ receives the inductor voltage signal VX. The gate of the fourteenth field effect transistor _M14 is connected to the output terminal of the first operational amplifier OPA _valley . The fourteenth field effect transistor M ₁₄ and the first operational amplifier OPA _valley constitute a first negative feedback closed loop G _valley .

The peak current sensor is used to collect and output a sampling signal I _Lsen . It includes a second operational amplifier OPA _peak , a sixth field effect transistor M ₆ , a third field effect transistor M ₃ , a pair of mirror transistors, a second control unit, and a dead zone sampling and holding capacitor C _s . The mirror tube pair is composed of a twelfth field effect transistor _M12 and a thirteenth field effect transistor _M13 . The second control unit includes a fourth field effect transistor M ₄ , a fifth field effect transistor M ₅ and a seventh field effect transistor M ₇ . The sixth FET M ₆ , the twelfth FET M ₁₂ and the thirteenth FET M ₁₃ are all NMOS tubes, the third FET M ₃ , the fourth FET M ₄ , and the fifth FET Both the tube M ₅ and the seventh field effect tube M ₇ are PMOS tubes. The specific circuit connection structure of the peak current sensor is as follows.

The gate of the third field effect transistor _M3 is connected to the signal ground, its source is input with the voltage source signal _Vsource , and its drain is respectively connected to the source of the seventh field effect transistor _M7 and the drain of the sixth field effect transistor _M6 . connect. The gate of the seventh field effect transistor _M7 is connected to the signal ground, and the drain thereof is connected to the non-inverting input terminal of the second operational amplifier OPA _peak . The source of the fifth field effect transistor M ₅ is connected to the drain of the second field effect transistor M ₂ , and the drain voltage VX _valley is input. The gate of the fifth field effect transistor M ₅ receives the fourth enabling signal LVX _valley . The gate of the fourth field effect transistor _M4 receives the third enable signal LVX, and the source receives the inductor voltage signal VX. The drains of the fourth FET _M4 and the fifth FET _M5 are both connected to the inverting input terminal of the second operational amplifier OPA _peak , and the inverting input terminal of the second operational amplifier OPA _peak is sampled and held in the dead zone One end of the capacitor C _s is connected, and the other end of the dead zone sampling and holding capacitor C _s is grounded.

Here, the dead zone sampling and holding capacitor C _s guarantees the output during the dead zone of the current sensor, which can reduce the slew rate requirements of the second operational amplifier OPA _peak and the first operational amplifier OPA _valley and the bandwidth of the negative feedback closed loop G _peak and G _valley need. In addition, the dead zone sampling and holding capacitor C _s is placed outside the negative feedback closed loop G _peak and G _valley , which avoids the limitation of the dead zone sampling and holding capacitor C _s on the negative feedback closed loop G _peak and G _valley bandwidth.

The output terminal of the second operational amplifier OPA _peak is connected to the gate of the sixth field effect transistor _M6 . The sixth field effect transistor M ₆ and the second operational amplifier OPA _peak constitute a second negative feedback closed loop G _peak . The source of the _sixth field effect transistor M6 is connected to the drain and gate of the twelfth field effect transistor _M12 , the gate of the thirteenth field effect transistor _M13 is connected to the gate of the twelfth field effect transistor _M12 connected, the drain of the thirteenth field effect transistor _M13 serves as the sampling output terminal of the sampling signal I _Lsen . The sources of the thirteenth field effect transistor _M13 and the twelfth field effect transistor _M12 are connected to signal ground.

In this embodiment, the mirror image ratio of the first power transistor MP and the second field effect transistor _M2 is _AL :1, the mirror image ratio of the second power transistor MN and the first field effect transistor _M1 is _AL :1, The mirror image ratio of the first power transistor MP and the third field effect transistor _M3 is _AL :1, and the mirror image ratio of the twelfth field effect transistor _M12 and the thirteenth field effect transistor _M13 is 1:1.

When the enable signal PS _p =PS _n =0, the enable signal ! PS _n = ! BPS _p = ! BPS _n =LVX _valley =1, LVX=0. At this moment, the first power transistor MP is turned on, the second power transistor MN is turned off, and the inductor current _IL flows through the first power transistor MP. The eighth field effect transistor M ₈ , the tenth field effect transistor M ₁₀ and the eleventh field effect transistor M ₁₁ are all in the conduction state, the input terminals of the first operational amplifier OPA _valley are all grounded, and its operation is in the linear region, and the first Negative feedback closed loop G _valley is an open loop. The inductor current I _L flows through the first power tube MP, and the inductor current at this stage is the peak value I _L =I _L,peak , the inverting input terminal of the second operational amplifier OPA _peak inputs the inductor voltage signal VX, the second operational amplifier OPA _peak and The second negative feedback closed loop G _peak formed by the sixth field effect transistor _M6 makes the third field effect transistor _M3 and the first power transistor MP be in the same bias state, then the leakage current of the third field effect transistor _M3 is I _{L , peak} /A _L , and is equal to the leakage current of the twelfth field effect transistor M ₁₂ and the thirteenth field effect transistor M ₁₃ , that is, I _Lsen =I _Lsen,peak =I _L,peak /A _L .

When the enable signal PS _p =PS _n =1, the enable signal ! PS _n = ! BPS _p = ! BPS _n =LVX _valley =0, LVX=1. At this moment, the first power transistor MP is turned off, and the second power transistor MN is turned on. The eighth field effect transistor M ₈ and the tenth field effect transistor M ₁₀ are in the off state, the ninth field effect transistor M ₉ is in the on state, the inductor current I _L flows through the second power transistor MN, and the inductor current is at a valley value at this stage I _L =I _{L, valley} , the first negative feedback closed loop G _valley formed by the first operational amplifier OPA _valley and the fourteenth field effect transistor M ₁₄ makes the first field effect transistor M ₁ and the first power transistor MN in the same bias state, the leakage current of the first field effect transistor M ₁ is I _L,valley / _AL , which is equal to the leakage current of the second field effect transistor M ₂ . The inverting input terminal of the second operational amplifier OPA _peak is connected to the drain voltage VX _valley , and the second negative feedback closed loop G _peak formed by the second operational amplifier OPA _peak and the sixth field effect transistor _M6 makes the third field effect transistor _M3 and the second field effect transistor _M2 are in the same bias state, then the leakage current of the third field effect transistor _M3 is I _L,valley /A _L , that is, I _Lsen =I _Lsen,valley =I _L,valley /A _L .

The present invention can reduce the slew rate requirements of the two operational amplifiers by keeping the op-amps in the peak current sensor and the valley-value current sensor in the linear region, and combining the dead-zone sampling and holding capacitance to ensure the output of the current sensor during the dead zone. By making the sampling signal I _Lsen = I _L /A _L stably output at the output terminal of the peak current sensor, the negative feedback closed loop where the peak current sensor is located is always stable, and the dead zone sampling and holding capacitor is set at the peak current sensor and the valley value current sensor respectively. In addition to the negative feedback closed loop, it avoids the limitation of the bandwidth of the two closed loops by the dead zone sampling and holding capacitor, and the combination of the two can reduce the bandwidth requirements of the two closed loops. The dead zone output of the current sensor, the slew rate of the operational amplifier and the bandwidth optimization of the closed loop can improve the accuracy of the sampling signal I _Lsen =I _L /A _L.

Referring to Fig. 3-Fig. 5, the peak enable signal generator is used to generate the enable signal in the peak current sensor, consisting of the fifteenth field effect transistor M ₁₅ , the sixteenth field effect transistor M ₁₆ , and the seventeenth field effect transistor M ₁₇ , composed of an eighteenth field effect transistor M ₁₈ , a first inverter INV ₁ , a first NAND gate NAND ₁ , a first resistor R _senlop , and a first capacitor C _senlop . It inputs the sixth enable signal! BPS _p , outputting the first enabling signal PS _p and the third enabling signal LVX. As shown in Figure 3, the sixth enabling signal! BPS _p is a signal in the driving chain of the first power transistor MP, and it is ahead of the first enable signal PS _p in timing, and its phase is opposite to that of the first enable signal PS _p , and the edge is only delayed. The third enable signal LVX is used to control the sampling and holding time of the dead zone sampling and holding capacitor C _s to the output node of the inductor voltage signal VX, and it needs to be high before the first power transistor MP is turned off, and the fourth field effect transistor is turned off M ₄ maintains the inductor voltage signal VX; and it needs to be set low after the first power transistor MP is turned on stably, and the fourth field effect transistor M ₄ is turned on to sample the inductor voltage signal VX.

In order to make the third enabling signal LVX low after the first power transistor MP is turned on stably, the sixth enabling signal! A first delay t _senlop is set between the rising edge of the BPS _p and the falling edge of the third enabling signal LVX, and the falling edge of the third enabling signal LVX lags behind the sixth enabling signal! On the rising edge of BPS _p , the first delay t _senlop is generated by the resistor R _senlop and the capacitor C _senlop . After the first power transistor MP is turned on stably, the third enable signal LVX is set low by the first delay time t _senlop .

The specific circuit structure of the peak enable signal generator in this embodiment is that the gates of the fifteenth field effect transistor M ₁₅ and the seventeenth field effect transistor M ₁₇ both input the sixth enable signal! BPS _p , the source of the fifteenth field effect transistor M ₁₅ input voltage source signal V _source , the drains of the fifteenth field effect transistor M ₁₅ and the seventeenth field effect transistor M ₁₇ are connected and used as the first enabling signal PS The signal output terminal of _p ; the source of the seventeenth field effect transistor M ₁₇ is connected to the power ground PGND; the gates of the sixteenth field effect transistor M ₁₆ and the eighteenth field effect transistor M ₁₈ are connected to the enable signal! BPS _p , the source of the sixteenth field effect transistor M ₁₆ is connected to the input voltage source signal V _source , one end of the first resistor R _senlop , one end of the first capacitor C _senlop , and the drain of the sixteenth field effect transistor M ₁₆ are all It is connected to the input end of the first inverter INV ₁ , the other end of the first resistor R _senlop is connected to the drain of the eighteenth field effect transistor M ₁₈ , the source of the eighteenth field effect transistor M ₁₈ , and the first capacitor C The other end of _senlop is connected to the signal ground; the output end of the first inverter INV ₁ is connected to an input end of the first NAND gate NAND ₁ , and the other input end of the first NAND gate NAND ₁ inputs the sixth enable Signal! BPS _p , the output end of the first NAND gate NAND ₁ outputs the third enabling signal LVX.

The valley enable signal generator is used to generate the enable signal in the valley current sensor, which consists of the second capacitor C _senlov , the nineteenth field effect transistor M ₁₉ , the twentieth field effect transistor M ₂₀ , and the second inverter INV _2. The third inverter INV ₃ , the fourth inverter INV ₄ , the fifth inverter INV ₅ and the second NAND gate NAND ₂ are composed. It inputs the seventh enable signal! BPS _n , output the second enabling signal PS _n and the fifth enabling signal! PS _n and the fourth enable signal LVX _valley . As shown in Figure 3, the seventh enabling signal! BPS _n is a signal in the driving chain of the second power transistor MN, and it is ahead of the second enabling signal PS _n in timing, and its phase is opposite to that of the second enabling signal PS _n , and the edge is only delayed. There is a dead zone between the first enabling signal PS _p and the second enabling signal PS _n , that is, the sixth enabling signal! BPS _p and seventh enable signal! There is a dead zone between BPS _n . The fifth enabling signal! PS _n and the second enabling signal PS _n only have opposite phases, and the edge delay is very small and negligible. The fourth enable signal LVX _valley is used to control the sampling and holding time of the dead zone sampling and holding capacitor C _s on the output node of the drain voltage VX _valley . It needs to be high before the second power transistor MN is turned off, and the fifth field is turned off. The effect transistor _M5 maintains the drain voltage VX _valley ; and the valley value current sensor needs to stably collect the valley value inductance current signal I _L,valley and output the drain voltage VX _valley , then set it low, turn on the fifth field effect transistor _M5 for sampling Drain voltage VX _valley .

There is a second delay t _senlov between the rising edge of the second enable signal PS _n and the falling edge of the fourth enable signal LVX _valley , and the falling edge of the fourth enable signal LVX _valley lags behind the second enable signal Rising edge of PS _n . The second delay t _senlov is generated by the second capacitor C _senlov , and the second delay t _senlov makes the fourth enable signal LVX _valley stably collect the valley value inductor current signal I _L,valley at the valley value current sensor and output the drain voltage VX _{The valley} rear is set low.

The specific circuit structure of the valley value enable signal generator in this embodiment is that the gates of the nineteenth field effect transistor M ₁₉ and the twentieth field effect transistor M ₂₀ both input the seventh enable signal! BPS _n , the source of the nineteenth field effect transistor M ₁₉ input voltage source signal V _source , the drains of the nineteenth field effect transistor M ₁₉ and the twentieth field effect transistor M ₂₀ are connected and used as the second enabling signal PS The signal output end of _n , and the drain connection ends of the nineteenth field effect transistor M ₁₉ and the twentieth field effect transistor M ₂₀ are respectively connected to the input ends of the third inverter INV ₃ and the fifth inverter INV ₅ , the source of the twentieth field effect transistor _M20 is connected to the power ground PGND. The output terminal of the fifth inverter INV ₅ serves as the fifth enabling signal! The signal output terminal of PS _n ; the output terminal of the third inverter INV ₃ is connected to the input terminal of the fourth inverter INV ₄ , and one end of the second capacitor C _senlov is connected to the output terminal of the third inverter INV ₃ , The other end of the second capacitor C _senlov is connected to the signal ground; the output end of the fourth inverter INV ₄ is connected to an input end of the second NAND gate NAND 2, and the other input end of the second NAND gate NAND ₂ is connected to the first input end of the second NAND gate NAND ₂ . The output terminals of the second inverter INV ₂ are connected, and the input terminal of the second inverter INV ₂ inputs the seventh enabling signal! BPS _n , the output terminal of the second NAND gate NAND ₂ serves as the signal output terminal of the fourth enabling signal LVX _valley .

What is described above is only the preferred embodiment of the present invention, it should be pointed out that for those skilled in the art, under the premise of not departing from the structure of the present invention, some deformations and improvements can also be made, and these will not affect the implementation of the present invention effect and utility of the patent.

Claims (8)

1. A SenseFET type full-wave inductive current sensor, comprising, The power stage is composed of a first power transistor MP and a second power transistor MN whose drains are connected, and the drain connection terminals of the first power transistor MP and the second power transistor MN output an inductor voltage signal VX; It is characterized in that it also includes, A valley value current sensor, including a first operational amplifier OPA _valley , a fourteenth field effect transistor M ₁₄ , a first field effect transistor M ₁ , a second field effect transistor M ₂ and a first control unit; the second field effect transistor The source of M ₂ is connected to the input terminal of the power stage, the gate of the second field effect transistor M ₂ is connected to the signal ground, the drain of the second field effect transistor M ₂ outputs the drain voltage VX _valley , and the The drain of the second field effect transistor _M2 is connected to the source of the fourteenth field effect transistor _M14 ; the gate of the fourteenth field effect transistor _M14 is connected to the output terminal of the first operational amplifier OPA _valley , The drain of the fourteenth field effect transistor M ₁₄ is connected to the positive phase input end of the first operational amplifier OPA _valley through the first control unit to form a first negative feedback closed loop G _valley ; the first control unit is also connected to the first control unit A negative phase input terminal of an operational amplifier OPA _valley is connected to control the first negative feedback closed loop G _valley to be an open loop or a closed loop; the drain of the first field effect transistor M ₁ inputs the inductance voltage signal VX, the The gate of the first field effect transistor M ₁ is input in the first control unit to be used to control the first negative feedback closed loop G _valley to be a closed loop enable signal, and the source of the first field effect transistor M ₁ is connected to the control unit; The peak current sensor includes a second operational amplifier OPA _peak , a sixth field effect transistor M ₆ , a third field effect transistor M ₃ , a pair of mirror transistors and a second control unit; the output terminal of the second control unit is connected to the second operational amplifier The negative phase input terminal of the amplifier OPA _peak is connected for time-sharing input of the drain voltage VX _valley and the inductor voltage signal VX; and the negative phase input terminal of the second operational amplifier OPA _peak is connected with a dead zone sampling and holding capacitor C _s ; The output terminal of the second operational amplifier OPA _peak is connected to the gate of the sixth field effect transistor _M6 , and the drain of the sixth field effect transistor _M6 is connected to the positive electrode of the second operational amplifier OPA _peak through the second control unit. The phase input terminal is connected to form the second negative feedback closed loop G _peak ; the drain of the sixth field effect transistor _M6 is connected to the drain of the third field effect transistor _M3 , and the gate of the third field effect transistor _M3 The pole is connected to the signal ground, the source of the third field effect transistor _M3 is connected to the input end of the power stage; the source electrode of the sixth field effect transistor _M6 is connected to the input end of the mirror transistor pair, and the mirror transistor The output terminal of the pair outputs the sampling signal I _Lsen . 2. A kind of SenseFET type full-wave inductive current sensor according to claim 1, is characterized in that, the mirror image ratio of described first power transistor MP and second field effect transistor M ₂ is _AL :1, and described first The mirror image ratio of the first power transistor MP and the third field effect transistor _M3 is _AL :1, and the mirror image ratio of the second power transistor MN and the first field effect transistor _M1 is _AL :1. 3. A kind of SenseFET type full-wave inductive current sensor according to claim 1 or 2, is characterized in that, described first power transistor MP, the second field effect transistor M ₂ , the 3rd field effect transistor M ₃ are PMOS; the second power transistor MN and the first field effect transistor _M1 are both NMOS. 4. A kind of SenseFET type full-wave inductive current sensor according to claim 1, is characterized in that, described first control unit comprises the eighth field effect transistor M ₈ , the ninth field effect transistor M ₉ , the tenth field effect transistor tube M ₁₀ and the eleventh field effect tube M ₁₁ ; the gate of the ninth field effect tube M ₉ and the gate of the first field effect tube M ₁ both input the second enable signal PS _n , the ninth field effect tube M 1 The source of the field effect transistor _M9 is connected to the drain of the fourteenth field effect transistor _M14 , and the drain of the ninth field effect transistor _M9 is connected to the non-inverting input terminal of the first operational amplifier OPA _valley , and the The inverting input end of the first operational amplifier OPA _valley is grounded through the eleventh field effect transistor _M11 , and the gate of the eleventh field effect transistor _M11 is connected to the input end of the power stage; the first field effect transistor M11 is connected to the input end of the power stage; The source of the transistor _M1 is connected to the drain of the eighth field effect transistor _M8 , and the source of the eighth field effect transistor _M8 is connected to signal ground; the non-inverting input terminal of the first operational amplifier OPA _valley is connected to the first The drains of the tenth field effect transistor _M10 are connected, the source of the tenth field effect transistor _M10 is connected to the signal ground; and the gates of the eighth field effect transistor _M8 and the tenth field effect transistor _M10 are connected and Input a fifth enabling signal whose signal state is opposite to that of the second enabling signal PS _n ! PS _n . 5. A kind of SenseFET type full-wave inductive current sensor according to claim 4, is characterized in that, described second control unit comprises the 4th FET _M4 , the 5th FET _M5 and the 7th FET Tube _M7 ; the gate of the fourth field effect transistor _M4 inputs the third enable signal LVX, and the source of the fourth field effect transistor _M4 inputs the inductance voltage signal VX; the fifth field effect transistor M The gate of ₅ inputs the fourth enabling signal LVX _valley , the source of the fifth field effect transistor _M5 inputs the drain voltage VX _valley ; the fourth field effect transistor _M4 , the fifth field effect transistor _M5 The drains are all connected to the inverting input end of the second operational amplifier OPA _peak ; the gate of the seventh field effect transistor _M7 is connected to the signal ground, and the drain of the seventh field effect transistor _M7 is connected to the second operational amplifier The positive input terminal of OPA _peak is connected, and the source of the seventh field effect transistor _M7 is connected with the drain of the sixth field effect transistor _M6 . 6. A kind of SenseFET type full-wave inductive current sensor according to claim 5, is characterized in that, SenseFET type full-wave inductive current sensor also comprises, Valley enable signal generator for seventh enable signal based on input! BPS _n , output the second enabling signal PS _n and the fifth enabling signal! PS _n and the fourth enabling signal LVX _valley ; Peak enable signal generator for the sixth enable signal according to the input! BPS _p , outputting the first enabling signal PS _p and the third enabling signal LVX. 7. A kind of SenseFET type full-wave inductive current sensor according to claim 6, is characterized in that, described peak enable signal generator comprises the 15th field effect transistor M ₁₅ , the 16th field effect transistor M ₁₆ , The seventeenth field effect transistor M ₁₇ , the eighteenth field effect transistor M ₁₈ , the first inverter INV ₁ , the first NAND gate NAND ₁ , the first resistor R _senlop , and the first capacitor C _senlop ; the tenth The gates of the fifth field effect transistor M ₁₅ and the seventeenth field effect transistor M ₁₇ are input with the sixth enabling signal! BPS _p , the source of the fifteenth field effect transistor M ₁₅ inputs the voltage source signal V _source , the drains of the fifteenth field effect transistor M ₁₅ and the seventeenth field effect transistor M ₁₇ are connected and serve as the first The signal output terminal of the enable signal PS _p ; the source of the seventeenth field effect transistor M ₁₇ is connected to the power ground PGND; the gates of the sixteenth field effect transistor M ₁₆ and the eighteenth field effect transistor M ₁₈ Connect to the enable signal! BPS _p , the source of the sixteenth field effect transistor M ₁₆ is connected to the input voltage source signal V _source , one end of the first resistor R _senlop , one end of the first capacitor C _senlop , the sixteenth field effect transistor M ₁₆ The drains of each are connected to the input terminal of the first inverter INV ₁ , and the other terminal of the first resistor R _senlop is connected to the drain of the eighteenth field effect transistor _M18 , and the eighteenth field effect transistor _M18 The source of the first capacitor C _senlop and the other end of the first capacitor C senlop are both connected to the signal ground; the output end of the first inverter INV ₁ is connected to an input end of the first NAND gate NAND ₁ , and the first NAND gate The other input terminal of NAND ₁ inputs the sixth enabling signal! BPS _p , the output terminal of the first NAND gate NAND ₁ outputs the third enabling signal LVX. 8. A kind of SenseFET type full-wave inductive current sensor according to claim 6, is characterized in that, described valley value enables signal generator to comprise the second capacitor C _senlov , the nineteenth field effect transistor M ₁₉ , the second Ten field effect transistors M ₂₀ , the second inverter INV ₂ , the third inverter INV ₃ , the fourth inverter INV ₄ , the fifth inverter INV ₅ and the second NAND gate NAND ₂ ; The gates of the nineteenth field effect transistor M ₁₉ and the twentieth field effect transistor M ₂₀ are both input with the seventh enabling signal! BPS _n , the source of the nineteenth field effect transistor M ₁₉ inputs the voltage source signal V _source , the drains of the nineteenth field effect transistor M ₁₉ and the twentieth field effect transistor M ₂₀ are connected as the second The signal output end of the enable signal PS _n , and the drain connection ends of the nineteenth field effect transistor M ₁₉ and the twentieth field effect transistor M ₂₀ are respectively connected to the third inverter INV ₃ and the fifth inverter The input terminal of INV ₅ is connected, the source of the twentieth field effect transistor M ₂₀ is connected to the power ground PGND; the output terminal of the fifth inverter INV ₅ is used as the fifth enabling signal! The signal output end of PS _n ; the output end of the third inverter INV ₃ is connected to the input end of the fourth inverter INV ₄ , and one end of the second capacitor C _senlov is connected to the third inverter INV ₃ The output end is connected, and the other end of the second capacitor C _senlov is connected to the signal ground; the output end of the fourth inverter INV ₄ is connected to an input end of the second NAND gate NAND ₂ , and the second NAND The other input terminal of the gate NAND ₂ is connected to the output terminal of the second inverter INV ₂ , and the input terminal of the second inverter INV ₂ inputs the seventh enable signal! BPS _n , the output terminal of the second NAND gate NAND ₂ serves as the signal output terminal of the fourth enabling signal LVX _valley .

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