CN115832065B

CN115832065B - Back contact battery and manufacturing method thereof, photovoltaic module

Info

Publication number: CN115832065B
Application number: CN202211516779.3A
Authority: CN
Inventors: 张东威; 吴帅; 李云朋; 叶枫; 方亮; 徐希翔
Original assignee: Longi Green Energy Technology Co Ltd
Current assignee: Longi Green Energy Technology Co Ltd
Priority date: 2022-11-29
Filing date: 2022-11-29
Publication date: 2025-03-07
Anticipated expiration: 2042-11-29
Also published as: WO2024114031A1; CN115832065A

Abstract

The present invention discloses a back contact cell and a manufacturing method thereof, and a photovoltaic module, which relate to the technical field of solar cells and are used to simultaneously prevent leakage at the lateral interface and the longitudinal interface of the first doped semiconductor layer and the second doped semiconductor layer. The back contact cell comprises: a silicon substrate, a first passivation layer, a first doped semiconductor layer, a second passivation layer, a second doped semiconductor layer and an insulating layer. The first passivation layer and the first doped semiconductor layer are sequentially stacked on the backlight surface of the silicon substrate. The second passivation layer and the second doped semiconductor layer are sequentially stacked on the backlight surface. The stacked second passivation layer and the second doped semiconductor layer cover a partial area of the stacked first passivation layer and the first doped semiconductor layer, and the conductivity type of the second doped semiconductor layer is opposite to that of the first doped semiconductor layer. The insulating layer is at least located between the second passivation layer and the first doped semiconductor layer, and is used to separate the second passivation layer and the first doped semiconductor layer.

Description

Back contact battery, manufacturing method thereof and photovoltaic module

Technical Field

The invention relates to the technical field of solar cells, in particular to a back contact cell, a manufacturing method thereof and a photovoltaic module.

Background

The passivation back contact solar cell refers to a solar cell with a passivation contact structure, wherein a positive electrode and a negative electrode are both positioned on the back surface of the cell, and the front surface is not shielded by a metal electrode. The passivation back contact type solar cell has the advantages of larger light absorption area, lower carrier back recombination rate and the like, so that the passivation back contact type solar cell is widely focused by photovoltaic academia and industry, and is a popular development direction of high-efficiency solar cell technology.

However, in the existing passivation back contact solar cell, when one of two types of passivation contact structures with opposite carrier collection types is covered on a partial area of the other type, the two types of passivation contact structures are difficult to separate through a thinner passivation layer, so that leakage current risk is high, and further performance of the passivation back contact solar cell is affected to be further improved.

Disclosure of Invention

The invention aims to provide a back contact battery, a manufacturing method thereof and a photovoltaic module, which are used for simultaneously preventing electric leakage at a transverse interface and a longitudinal interface of a first doped semiconductor layer and a second doped semiconductor layer, and are beneficial to improving the photoelectric conversion efficiency of the back contact battery.

In a first aspect, the invention provides a back contact cell comprising a silicon substrate, and a first passivation layer and a first doped semiconductor layer which are sequentially stacked on a backlight surface of the silicon substrate along the thickness direction of the silicon substrate. And sequentially stacking a second passivation layer and a second doped semiconductor layer which are arranged on the backlight surface along the thickness direction of the silicon substrate. Wherein the second passivation layer and the second doped semiconductor layer are stacked to cover partial areas of the first passivation layer and the first doped semiconductor layer, and the second doped semiconductor layer and the first doped semiconductor layer are opposite in conductivity type. An insulating layer disposed on the backlight surface. An insulating layer is located at least between the second passivation layer and the first doped semiconductor layer for spacing the second passivation layer from the first doped semiconductor layer.

Under the condition of adopting the technical scheme, along the thickness direction of the silicon substrate, the first passivation layer and the first doped semiconductor layer are sequentially stacked and arranged on the backlight surface. The passivation contact structure formed by the first passivation layer and the first doped semiconductor layer can realize excellent interface passivation and carrier selective collection, and is beneficial to improving the photoelectric conversion efficiency of the back contact battery. Similarly, the passivation contact structure formed by the second passivation layer and the second doped semiconductor layer also has the beneficial effects of the first passivation layer and the first doped semiconductor layer, and will not be described herein.

The second passivation layer and the second doped semiconductor layer are stacked to cover a partial region of the first passivation layer and the first doped semiconductor layer. The back contact battery provided by the invention further comprises an insulating layer arranged on the backlight surface. The insulating layer is positioned at least between the second passivation layer and the first doped semiconductor layer for spacing the second passivation layer from the first doped semiconductor layer. It is understood that the insulating layer may separate the second passivation layer and the first doped semiconductor layer not only in the thickness direction of the silicon substrate but also in a direction parallel to the backlight surface. In this case, the insulating layer can prevent carriers in the second doped semiconductor layer from entering the first doped semiconductor layer through the second passivation layer by tunneling effect, and can prevent carriers in the first doped semiconductor layer from entering the second doped semiconductor layer through the second passivation layer by tunneling effect, that is, the insulating layer can prevent carriers collected by the second doped semiconductor layer from being compounded with carriers collected by the first doped semiconductor layer with opposite conductivity types, thereby preventing electric leakage at the lateral interface and the longitudinal interface of the first doped semiconductor layer and the second doped semiconductor layer, and further being beneficial to improving the photoelectric conversion efficiency of the back contact battery.

As a possible implementation manner, the first passivation layer is a tunneling passivation layer, and the first doped semiconductor layer is a doped polysilicon layer.

In the case of adopting the above technical solution, in the actual manufacturing process, in order to form the first passivation layer and the first doped semiconductor layer only on the specific area of the backlight surface, it is necessary to perform patterning treatment on the passivation material layer for manufacturing the first passivation layer and the doped semiconductor material layer for manufacturing the first doped semiconductor layer. Compared with the mode of realizing patterning treatment by combining photoetching with wet etching and combining ink printing with wet etching, the method has the advantages that the cost of realizing patterning treatment by adopting a laser etching process is lower, and the method is more suitable for mass production. In addition, the second passivation layer and the second doped semiconductor layer which are stacked cover part of the first passivation layer and the first doped semiconductor layer which are stacked, so that the formation steps of the first passivation layer and the first doped semiconductor layer which are stacked are earlier than the formation steps of the second passivation layer and the second doped semiconductor layer which are stacked in the actual manufacturing process. Under the above circumstances, since the amorphous silicon material is easy to form polysilicon or monocrystalline silicon at high temperature, and the chemical properties of the tunneling passivation material and polysilicon are relatively stable at high temperature, compared with the intrinsic amorphous silicon layer and the doped amorphous silicon layer which are stacked, the tunneling passivation layer and the doped polysilicon layer which are stacked have smaller sensitivity to laser thermal damage at high temperature, the influence on passivation effect can be reduced during the laser film opening process, the process window is further increased, and the process difficulty is reduced, therefore, when the first passivation layer is the tunneling passivation layer, and the first doped semiconductor layer is the doped polysilicon layer, the patterning treatment can be performed on the passivation material layer for manufacturing the first passivation layer and the doped semiconductor material layer for manufacturing the first doped semiconductor layer by adopting the laser etching process, thereby ensuring that the first passivation layer and the first doped semiconductor layer have good film forming quality while reducing the manufacturing cost of the back contact battery, and being beneficial to improving the yield and the electrical property of the back contact battery.

In addition, the tunneling passivation layer and the doped polysilicon layer can be formed by adopting a low-pressure chemical vapor deposition device. And the intrinsic amorphous silicon layer and the doped amorphous silicon layer need to be deposited by using a chemical vapor deposition device. Based on this, since the cost of the low-pressure chemical vapor deposition apparatus is lower than that of the chemical vapor deposition apparatus, when the first passivation layer may also be a tunneling passivation layer and the first doped semiconductor layer may also be a doped polysilicon layer, the passivation material layer for manufacturing the first passivation layer and the doped semiconductor material layer for manufacturing the first doped semiconductor layer may be deposited by the low-pressure chemical vapor deposition apparatus, so that the manufacturing cost of the back contact battery may be reduced.

As a possible implementation manner, the second passivation layer is an intrinsic amorphous silicon layer, and the second doped semiconductor layer is a doped amorphous silicon layer.

Under the condition of adopting the technical scheme, the intrinsic amorphous silicon layer has better passivation effect than the tunneling passivation layer. Based on the above, compared with the case that the second passivation layer is a tunneling passivation layer and the second doped semiconductor layer is a doped polysilicon layer, when the second passivation layer is an intrinsic amorphous silicon layer and the second doped semiconductor layer, the recombination rate of carriers with opposite conductivity types at the interface between the silicon substrate and the second passivation layer can be further reduced, and the photoelectric conversion efficiency of the back contact cell can be further improved.

As a possible implementation manner, the back contact battery further comprises an aluminum oxide layer and a silicon nitride layer which are sequentially stacked and arranged on a light facing surface of the silicon substrate along a direction away from the silicon substrate. Or the back contact battery further comprises a silicon oxide layer and a silicon nitride layer which are sequentially stacked and arranged on a light facing surface of the silicon substrate along the direction away from the silicon substrate.

Under the condition of adopting the technical scheme, the alumina layer and the silicon nitride layer which are stacked can passivate the light facing surface, so that the recombination rate of carriers at the light facing surface is reduced, and the photoelectric conversion efficiency of the back contact battery is further improved. And moreover, the silicon nitride can play a role in antireflection, so that more light is refracted into the silicon substrate from the light-facing surface, and the utilization rate of the back contact battery to the light is further improved. On the basis, when a deposition process is adopted to form a passivation layer of amorphous silicon material on a light facing surface of a suede structure with a smaller size, epitaxial growth is easy to occur at the top of the suede structure, so that the thickness of the part of the amorphous silicon material at the top of the suede structure is larger than that of the part of the amorphous silicon material at the base of the suede structure, the thickness of each area of the passivation layer of the amorphous silicon material formed is inconsistent, the passivation effect of the passivation layer on the light facing surface is reduced, and the formation of other film layers on the light facing surface is also influenced. Compared with the passivation layer of the amorphous silicon material, the passivation layer of the aluminum oxide material is not epitaxially grown when being deposited on the light-facing surface of the small textured structure, so that the passivation effect of the passivation layer of the aluminum oxide material is better, the textured surface of the light-facing surface of the silicon substrate can be selected as the textured surface with smaller pyramid size, and the textured surface with smaller size has better light trapping effect, and the absorption of the silicon substrate to light is further improved. In addition, the above-mentioned stacked silicon oxide layer and silicon nitride layer may refer to the above-mentioned analysis of the beneficial effects of the stacked aluminum oxide layer and silicon nitride layer, and will not be described herein.

Furthermore, the aluminum oxide layer, the silicon nitride layer, and the silicon oxide layer may be formed by deposition using an atomic layer deposition apparatus. And the intrinsic amorphous silicon layer needs to be deposited by using a chemical vapor deposition device. Based on this, since the cost of the atomic layer deposition apparatus is lower than that of the chemical vapor deposition apparatus, when an aluminum oxide layer (or a silicon oxide layer) and a silicon nitride layer are formed on the light-facing surface as passivation anti-reflection layers, the aluminum oxide (or silicon oxide) and the silicon nitride layer can be formed on the light-facing surface by deposition of the atomic layer deposition apparatus, so that the manufacturing cost of the back contact cell can be reduced.

As a possible implementation, the insulating layer includes an aluminum oxide layer and a silicon nitride layer that are sequentially stacked in a direction away from the silicon substrate. Or, the insulating layer includes a silicon oxide layer and a silicon nitride layer which are sequentially stacked in a direction away from the silicon substrate.

Under the condition of adopting the technical scheme, the aluminum oxide layer, the silicon nitride layer and the silicon oxide layer all have good dielectric characteristics, so that the insulation layer is beneficial to separating the second passivation layer from the first doped semiconductor layer, the parallel resistance of the back contact battery can be further improved, and the leakage risk of the back contact battery is reduced. Furthermore, aluminum oxide, silicon nitride, and silicon oxide can also be used to fabricate a film layer with passivation and/or anti-reflection effects on the light-facing surface. Based on the above, when the insulating layer comprises the alumina layer and the silicon nitride layer which are stacked, or the silicon oxide layer and the silicon nitride layer which are stacked, the material of the insulating layer is the same as that of the passivation and antireflection layer, so that the passivation and antireflection layer can be formed on the light facing surface while the insulating layer is formed, thereby being beneficial to simplifying the manufacturing process of the back contact battery and improving the manufacturing efficiency of the back contact battery.

As a possible implementation, the thickness of the insulating layer is 75nm to 125nm. The thickness of the insulating layer is within the range, so that partial carriers possibly collected by the second doped semiconductor layer due to the small thickness of the insulating layer can be prevented from being compounded by tunneling effect sequentially penetrating through the second passivation layer and the insulating layer to the carriers collected by the first doped semiconductor layer with opposite conductivity types, and good insulating property of the insulating layer is ensured. Meanwhile, the insulating layer separates the second passivation layer from the first doped semiconductor layer along the direction of the silicon substrate, and also separates the second passivation layer from the first doped semiconductor layer along the direction parallel to the backlight surface of the silicon substrate, so that the insulating layer is located at the longitudinal juncture of the second passivation layer and the first doped semiconductor layer, and the first doped semiconductor layer and the second doped semiconductor layer are distributed above the backlight surface along the direction parallel to the backlight surface. In this case, it can be understood that when the thickness of the insulating layer is greater, the cross-sectional area of the portion of the insulating layer located at the longitudinal boundary between the second passivation layer and the first doped semiconductor layer is greater, and the surface area of the backlight surface is a constant value, so that when the thickness of the insulating layer is 75nm to 125nm, it is also possible to prevent at least one of the first doped semiconductor layer and the second doped semiconductor layer from decreasing due to the greater thickness of the insulating layer, thereby affecting the carrier collecting capability thereof, ensuring that carriers generated after photon absorption by the silicon substrate are timely guided out by the first doped semiconductor layer and the second doped semiconductor layer, and further improving the photoelectric conversion efficiency of the back contact cell.

As a possible implementation manner, the light-facing surface of the silicon substrate is a suede surface. The pile foundation width is 1 μm to 3 μm.

Under the condition of adopting the technical scheme, in a certain range, the smaller the tower base width of the suede is, the better the light trapping effect of the suede is. Based on the above, when the light-facing surface of the silicon substrate is a textured surface and the tower base width of the textured surface is 1-3 μm, the tower base width of the light-facing surface is relatively small, and the light-facing surface has a high light trapping effect. Under the circumstance, in the practical application process, the passivation reflecting layer which is made of amorphous silicon materials such as aluminum oxide, silicon oxide and the like and matched with the suede with smaller tower base width can be formed on the light-facing surface, so that more light rays can be transmitted into the silicon substrate through the light-facing surface, and the photoelectric conversion efficiency of the back contact battery is further improved.

In a second aspect, the present invention further provides a photovoltaic module, which includes the back contact battery provided in the first aspect and various implementations thereof.

The advantages of the second aspect and various implementations of the present invention may be referred to for analysis of the advantages of the first aspect and various implementations of the first aspect, and will not be described here again.

In a third aspect, the present invention also provides a method for manufacturing a back contact battery, which includes first providing a silicon substrate. Next, a first passivation layer and a first doped semiconductor layer, which are sequentially stacked on a back surface of the silicon substrate, are formed along a thickness direction of the silicon substrate. Next, an insulating layer is formed on the backlight surface. Next, a second passivation layer and a second doped semiconductor layer, which are sequentially stacked on the backlight surface, are formed along the thickness direction of the silicon substrate. Wherein the second passivation layer and the second doped semiconductor layer are stacked to cover partial areas of the first passivation layer and the first doped semiconductor layer, and the second doped semiconductor layer and the first doped semiconductor layer are opposite in conductivity type. An insulating layer is located at least between the second passivation layer and the first doped semiconductor layer for spacing the second passivation layer from the first doped semiconductor layer.

The beneficial effects of the third aspect of the present invention may be referred to as the beneficial effect analysis of the first aspect, and will not be described here again.

As one possible implementation, forming the first passivation layer and the first doped semiconductor layer in a stacked arrangement includes first sequentially forming a passivation material layer overlying the backlight surface and an intrinsic semiconductor material layer overlying the passivation material layer. Next, a diffusion process is performed on the intrinsic semiconductor material layer such that the intrinsic semiconductor material layer forms a doped semiconductor material layer, and a doped glass layer is formed on the doped semiconductor material layer. And then, removing part of the doped glass layer on the doped semiconductor material layer by adopting a laser etching process. Wherein the remaining portion of the doped glass layer forms a mask layer. And then, under the mask action of the mask layer, sequentially removing the part of the doped semiconductor material layer exposed outside the mask layer and the part of the passivation material layer exposed outside the mask layer to form a first passivation layer and a first doped semiconductor layer which are stacked.

With the above technical solution, in the practical application process, when the intrinsic semiconductor material layer located on the passivation material layer is subjected to diffusion treatment, the intrinsic semiconductor material layer is converted into a doped semiconductor material layer, and a doped glass layer is formed on the surface of the doped semiconductor material layer, and the doped glass layer may be, for example, a phosphosilicate glass layer (Phospho SILICATE GLASS, abbreviated as PSG) or a borosilicate glass layer (Boro SILICATE GLASS, abbreviated as BSG) or the like. In this case, after the laser etching process is adopted to remove a portion of the doped glass layer located on the doped semiconductor material layer, a mask layer can be formed on the remaining portion of the doped glass layer, so that patterning treatment on the doped semiconductor material layer and the passivation material layer can be realized without forming additional mask layers such as silicon nitride, the manufacturing process of the back contact battery is simplified, and meanwhile, the manufacturing cost of the back contact battery can be reduced.

As one possible implementation, the method for manufacturing the back contact cell further comprises removing the around-plated doped glass layer, the around-plated doped semiconductor material layer and the around-plated passivation material layer on the light-facing surface and the side surface of the silicon substrate after forming the first passivation layer and the first doped semiconductor layer in a stacked arrangement and before forming the insulating layer on the back surface. And then, under the mask action of the mask layer, carrying out texturing treatment on the light-facing surface of the silicon substrate so as to enable the light-facing surface to be textured. And removing the mask layer.

Under the condition of adopting the technical scheme, as described above, in the flocking process, the mask layer is obtained by performing patterning treatment on the doped glass layer formed on the doped semiconductor material layer in the diffusion process by adopting a laser etching process, and is not obtained by additionally forming the mask layer such as silicon nitride and the like through deposition and other processes after the first passivation layer and the first doped semiconductor layer which are arranged in a stacked manner are obtained, so that the manufacturing process of the back contact battery can be further simplified, and the manufacturing cost of the back contact battery can be reduced.

As a possible implementation, the thickness of the doped glass layer is 40nm to 60nm. In this case, the thickness of the doped glass layer is within the range, so that it is possible to prevent the first doped semiconductor layer and the first passivation layer located thereunder from being difficult to protect in the corresponding operation due to the poor protection effect of the mask layer formed with the remaining portion of the doped glass layer, which is caused by the small thickness of the doped glass layer, to ensure good film formation quality of the first doped semiconductor layer and the first passivation layer, and to improve the yield of the back contact cell. Meanwhile, the problems of reduced manufacturing efficiency, increased manufacturing cost and the like caused by larger thickness of the doped glass layer can be prevented, and the mass production of the back contact battery is facilitated to be improved.

As a possible implementation, the diffusion time of the diffusion treatment is 60min to 120min, and the diffusion temperature is 800 ℃ to 900 ℃. The advantages of this case are similar to those described above when the thickness of the doped glass layer is 40nm to 60nm, and reference is made to the above, and no further description is given here.

As one possible implementation, forming the first passivation layer and the first doped semiconductor layer in a stacked arrangement includes first sequentially forming a passivation material layer overlying the backlight surface and a doped semiconductor material layer overlying the passivation material layer. And then, patterning the doped semiconductor material layer and the passivation material layer by adopting a laser etching process to form a first passivation layer and a first doped semiconductor layer which are stacked. The first passivation layer is a tunneling passivation layer, and the first doped semiconductor layer is a doped polysilicon layer. The beneficial effects of the first passivation layer described above may be referred to as a tunneling passivation layer, and the first doped semiconductor layer is a beneficial effect analysis of the doped polysilicon layer, which will not be described herein.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:

FIG. 1 is a schematic longitudinal cross-sectional view of a structure of a passivation back contact solar cell according to the related art;

fig. 2 is a schematic longitudinal cross-sectional view of another structure of a passivated back contact solar cell in the related art;

fig. 3 is a schematic structural diagram of a back contact battery according to an embodiment of the present invention in a manufacturing process;

fig. 4 is a schematic diagram of a second structure in the manufacturing process of the back contact battery according to the embodiment of the invention;

fig. 5 is a schematic diagram of a third structure in the manufacturing process of a back contact battery according to an embodiment of the present invention;

Fig. 6 is a schematic structural diagram in the manufacturing process of a back contact battery according to an embodiment of the present invention;

fig. 7 is a schematic diagram showing a structure of a back contact battery in a manufacturing process according to an embodiment of the present invention;

fig. 8 is a schematic diagram of a structure in a manufacturing process of a back contact battery according to an embodiment of the present invention;

fig. 9 is a schematic diagram seventh in the manufacturing process of a back contact battery according to an embodiment of the present invention;

Fig. 10 is a schematic structural diagram eighth in the manufacturing process of a back contact battery according to an embodiment of the present invention;

fig. 11 is a schematic diagram of a structure of a back contact battery in a manufacturing process according to an embodiment of the present invention;

fig. 12 is a schematic view of a structure of a back contact battery according to an embodiment of the present invention in a manufacturing process;

fig. 13 is a schematic diagram eleven structural diagrams during a manufacturing process of a back contact battery according to an embodiment of the present invention;

Fig. 14 is a schematic diagram showing a structure of a back contact battery in the manufacturing process according to an embodiment of the present invention;

Fig. 15 is a schematic diagram of thirteenth structure in the manufacturing process of a back contact battery according to an embodiment of the present invention;

Fig. 16 is a schematic diagram showing a structure of a back contact battery in a manufacturing process according to an embodiment of the invention.

Reference numeral 11 denotes a silicon substrate, 12 denotes a passivation material layer, 121 denotes a first passivation layer, 13 denotes an intrinsic semiconductor material layer, 14 denotes a doped semiconductor material layer, 141 denotes a first doped semiconductor layer, 15 denotes a doped glass layer, 151 denotes a mask layer, 16 denotes an insulating material layer, 161 denotes an insulating layer, 17 denotes a second passivation layer, 18 denotes a second doped semiconductor layer, 19 denotes an aluminum oxide layer, 20 denotes a silicon nitride layer, 21 denotes a transparent conductive material layer, 211 denotes a first transparent conductive layer, 212 denotes a second transparent conductive layer, 22 denotes a first electrode, and 23 denotes a second electrode.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned. In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. The meaning of "a number" is one or more than one unless specifically defined otherwise.

In the description of the present invention, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, mechanically connected, electrically connected, directly connected, indirectly connected via an intervening medium, or in communication between two elements or in an interaction relationship between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.

Specifically, as shown in fig. 1 and 2, the passivation back contact solar cell in the related art generally includes a silicon substrate 11, a first passivation contact structure, and a second passivation contact structure. Wherein the first passivation contact structures and the second passivation contact structures are alternately distributed on the backlight surface along a direction parallel to the backlight surface of the silicon substrate 11. And the second passivation contact structure overlies a portion of the area of the first passivation contact structure. Specifically, in a direction away from the silicon substrate 11, the first passivation contact structure and the second passivation contact structure each include a passivation layer and a doped semiconductor layer that are sequentially stacked. Based on this, in operation of the passivated back contact solar cell, the respective type of carriers may pass through the passivation layers comprised by the first and second passivation contact structures, respectively, by tunneling effect and be conducted to the respective electrodes via the respective doped semiconductor layers comprised by the first and second passivation contact structures, thereby forming photocurrents.

However, as shown in fig. 1 and 2, in order to reduce the tunneling resistance of carriers, the passivation back contact type solar cell in the related art is designed such that the thickness of the passivation layer included in the first passivation contact structure and the second passivation contact structure is generally smaller. And the first passivation contact structure and the second passivation contact structure include doped semiconductor layers of opposite conductivity types. In this case, when the second passivation contact structure covers a partial region of the first passivation contact structure, even if an insulating layer is disposed at a longitudinal boundary of the first passivation contact structure and the second passivation contact structure along a thickness direction of the silicon substrate, the insulating layer can only space the first passivation contact structure and the second passivation contact structure in the longitudinal direction, and at a lateral boundary of the first passivation contact structure and the second passivation contact structure, the two are separated only by the passivation layer spacing (e.g., by the intrinsic semiconductor layer), whereas a thinner passivation layer has difficulty in achieving separation of carriers in the doped semiconductor layer of the first passivation contact structure and carriers in the doped semiconductor layer of the second passivation contact structure, resulting in a higher recombination rate of carriers of opposite conductivity types at the lateral boundary of the two, and thus, there is a risk of leakage, thereby affecting further improvement of performance of the passivation back contact solar cell.

In order to solve the technical problems described above, in a first aspect, an embodiment of the present invention provides a back contact battery. As shown in fig. 13, the back contact cell includes a silicon substrate 11, a first passivation layer 121, a first doped semiconductor layer 141, a second passivation layer 17, a second doped semiconductor layer 18, and an insulating layer 161.

As shown in fig. 13, the first passivation layer 121 and the first doped semiconductor layer 141 are sequentially stacked on the backlight surface of the silicon substrate 11 in the thickness direction of the silicon substrate 11. The second passivation layer 17 and the second doped semiconductor layer 18 are sequentially stacked on the backlight surface in the thickness direction of the silicon substrate 11. Wherein the second passivation layer 17 and the second doped semiconductor layer 18 which are stacked cover a partial region of the first passivation layer 121 and the first doped semiconductor layer 141 which are stacked, and the second doped semiconductor layer 18 and the first doped semiconductor layer 141 are opposite in conductivity type. The insulating layer 161 is disposed on the backlight surface. The insulating layer 161 is located at least between the second passivation layer 17 and the first doped semiconductor layer 141 for spacing the second passivation layer 17 from the first doped semiconductor layer 141.

Specifically, the silicon substrate may be an N-type silicon substrate or a P-type silicon substrate in terms of conductivity type. In terms of structure, the specific structure of the silicon substrate can be set according to actual application scenes. For example, as shown in fig. 3, the silicon substrate 11 may be a silicon substrate on which no film layer is formed and on which both the backlight surface and the light-facing surface are polished surfaces. Alternatively, as shown in fig. 13, the silicon substrate 11 may be a silicon substrate on which no film layer is formed and on which the light-facing surface is textured. Compared with the polished surface, the suede structure has a good light trapping effect, so that more light can be refracted into the silicon substrate 11 from the light-directing surface under the condition that the light-directing surface of the silicon substrate 11 is the suede, and further the photoelectric conversion efficiency of the back contact battery is improved. Specifically, in the case that the light-facing surface of the silicon substrate 11 is a textured surface, the tower base width of the textured surface may be set according to actual requirements, which is not specifically limited herein.

For the first passivation layer and the first doped semiconductor layer, the materials and thicknesses of the first passivation layer and the first doped semiconductor layer, and the doping types and doping concentrations of the doping elements in the first doped semiconductor layer may be set according to actual requirements, so long as the application to the back contact battery provided by the embodiment of the present invention is possible.

For example, the first passivation layer may be an intrinsic amorphous silicon layer and the first doped semiconductor layer may be a doped amorphous silicon layer. At this time, the first passivation layer and the first doped semiconductor layer may constitute a hetero-contact structure. Based on the above, the heterojunction structure has passivation effect superior to that of the tunneling passivation contact structure, so that the carrier recombination rate at the interface of the silicon substrate and the first passivation layer can be further reduced under the condition that the first passivation layer and the first doped semiconductor layer which are arranged in a stacked manner form the heterojunction structure, and the photoelectric conversion efficiency of the back contact battery is improved.

For another example, the first passivation layer may be a tunneling passivation layer, and the first doped semiconductor layer may be a doped polysilicon layer. In this case, in the actual manufacturing process, as shown in fig. 5 to 7, in order to form the first passivation layer 121 and the first doped semiconductor layer 141 only on a specific region of the backlight surface, it is necessary to perform patterning processing on the passivation material layer 12 for manufacturing the first passivation layer 121 and the doped semiconductor material layer 14 for manufacturing the first doped semiconductor layer 141. Compared with the mode of realizing patterning treatment by combining photoetching with wet etching and combining ink printing with wet etching, the method has the advantages that the cost of realizing patterning treatment by adopting a laser etching process is lower, and the method is more suitable for mass production. Further, as shown in fig. 13, since the second passivation layer 17 and the second doped semiconductor layer 18 which are stacked cover a partial region of the first passivation layer 121 and the first doped semiconductor layer 141 which are stacked, in the actual manufacturing process, the formation step of the first passivation layer 121 and the first doped semiconductor layer 141 which are stacked is earlier than the formation step of the second passivation layer 17 and the second doped semiconductor layer 18 which are stacked. In the above-mentioned case, since the amorphous silicon material is easy to form polysilicon or monocrystalline silicon at high temperature, and the chemical properties of the tunneling passivation material and polysilicon are relatively stable at high temperature, compared with the intrinsic amorphous silicon layer and the doped amorphous silicon layer which are stacked, the tunneling passivation layer and the doped polysilicon layer which are stacked have smaller sensitivity to laser thermal damage at high temperature, the influence on passivation effect can be reduced in the laser film opening process, the process window is further increased, and the process difficulty is reduced, so when the first passivation layer 121 is the tunneling passivation layer, and the first doped semiconductor layer 141 is the doped polysilicon layer, the laser etching process can be used to realize the patterning treatment of the passivation material layer 12 for manufacturing the first passivation layer 121 and the doped semiconductor material layer 14 for manufacturing the first doped semiconductor layer 141, thereby being capable of reducing the manufacturing cost of the back contact battery, ensuring that the first passivation layer 121 and the first doped semiconductor layer 141 have good film forming quality, and being beneficial to improving the yield and the electrical performance of the back contact battery.

Specifically, the tunneling passivation layer may include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium carbide nitride. The specific material of the tunneling passivation layer can be set according to actual requirements.

For the second passivation layer and the second doped semiconductor layer, the materials and thicknesses of the second passivation layer and the second doped semiconductor layer, and the doping types and doping concentrations of the doping elements in the second doped semiconductor layer may be set according to actual requirements. Wherein the second doped semiconductor layer and the first doped semiconductor layer are opposite in conductivity type. In this regard, in the practical application process, the second doped semiconductor may be a P-type doped semiconductor layer doped with boron or other elements, and the first doped semiconductor layer may be an N-type doped semiconductor layer doped with phosphorus or other elements. Or the second doped semiconductor layer may be an N-type doped semiconductor layer, and the first doped semiconductor layer may be a P-type doped semiconductor layer.

In addition, the second passivation layer may be a tunneling passivation layer, and the second doped semiconductor layer may be a doped polysilicon layer. Or the second passivation layer may also be an intrinsic amorphous silicon layer and the second doped semiconductor layer may also be a doped amorphous silicon layer.

It is noted that, in the case that the first passivation layer is a tunneling passivation layer, the second doped semiconductor layer is a doped polysilicon layer, and the second passivation layer is an intrinsic amorphous silicon layer, and the second doped semiconductor layer is a doped amorphous silicon layer, not only the passivation material layer for manufacturing the first passivation layer and the doped semiconductor material layer for manufacturing the first doped semiconductor layer can be patterned by using a laser etching process, so that the first passivation layer and the first doped semiconductor layer are ensured to have good film forming quality, and the process window is increased, but also the intrinsic amorphous silicon layer has a passivation effect better than that of the tunneling passivation layer. Based on the above, compared with the case that the second passivation layer is a tunneling passivation layer and the second doped semiconductor layer is a doped polysilicon layer, when the second passivation layer is an intrinsic amorphous silicon layer and the second doped semiconductor layer, the recombination rate of carriers with opposite conductivity types at the interface between the silicon substrate and the second passivation layer can be further reduced, and the photoelectric conversion efficiency of the back contact cell can be further improved.

Furthermore, the areas of the second passivation layer and the second doped semiconductor layer that are stacked and disposed and the first passivation layer and the first doped semiconductor layer that are stacked and disposed may be set according to practical application scenarios, and are not specifically limited herein.

For the insulating layer described above, the insulating layer may be a single-layer structure made of one or more insulating materials, or the insulating layer may be a multi-layer composite structure made of a plurality of insulating materials. Specifically, the specific structure of the insulating layer can be set according to actual requirements. The insulating material may be any material having insulating properties. In addition, the thickness of the insulating layer and the formation range of the insulating layer on the backlight surface may be set according to actual requirements, so long as the insulating layer is at least located between the second passivation layer and the first doped semiconductor layer, and the second passivation layer and the first doped semiconductor layer can be separated from each other by the insulating layer.

As is clear from the above, as shown in fig. 13, the insulating layer 161 may not only space the second passivation layer 17 and the first doped semiconductor layer 141 in the thickness direction of the silicon substrate 11, but also space the second passivation layer 17 and the first doped semiconductor layer 141 in a direction parallel to the backlight surface. In this case, the insulating layer 161 may prevent carriers in the second doped semiconductor layer 18 from entering the first doped semiconductor layer 141 through the second passivation layer 17 by a tunneling effect, and may prevent carriers in the first doped semiconductor layer 141 from entering the second doped semiconductor layer 18 through the second passivation layer 17 by a tunneling effect, that is, the insulating layer 161 may block carriers collected by the second doped semiconductor layer 18 from being recombined with carriers collected by the first doped semiconductor layer 141 having a conductivity type opposite to that of the first doped semiconductor layer, thereby preventing electric leakage at a lateral interface and a longitudinal interface of the first doped semiconductor layer 141 and the second doped semiconductor layer 18 at the same time, and thus being beneficial to improving the photoelectric conversion efficiency of the back contact cell.

As a possible implementation, the thickness of the insulating layer is 75nm to 125nm. In this case, the thickness of the insulating layer is within the range, so that a portion of carriers collected by the second doped semiconductor layer, which may be caused by the smaller thickness of the insulating layer, can be prevented from being sequentially combined with carriers collected by the first doped semiconductor layer having the opposite conductivity type through the second passivation layer and the insulating layer by the tunneling effect, thereby ensuring good insulating properties of the insulating layer. Meanwhile, as shown in fig. 13, the insulating layer 161 not only spaces the second passivation layer 17 from the first doped semiconductor layer 141 in the thickness direction of the silicon substrate 11, but also spaces the second passivation layer 17 from the first doped semiconductor layer 141 in a direction parallel to the backlight surface of the silicon substrate 11, so that the insulating layer 161 is located at a portion of the longitudinal boundary of the second passivation layer 17 and the first doped semiconductor layer 141, the first doped semiconductor layer 141 and the second doped semiconductor layer 18 are distributed over the backlight surface in a direction parallel to the backlight surface. In this case, it can be understood that when the thickness of the insulating layer 161 is greater, the cross-sectional area of the portion of the insulating layer 161 located at the longitudinal boundary between the second passivation layer 17 and the first doped semiconductor layer 141 is greater, and the surface area of the backlight surface is a constant value, so that when the thickness of the insulating layer 161 is 75nm to 125nm, it is also possible to prevent the cross-sectional area of one of the first doped semiconductor layer 141 and the second doped semiconductor layer 18 from being reduced due to the greater thickness of the insulating layer 161, thereby affecting the carrier collecting capability thereof, ensuring that carriers generated after the silicon substrate 11 absorbs photons are timely guided out by the first doped semiconductor layer 141 and the second doped semiconductor layer 18, and further improving the photoelectric conversion efficiency of the back contact cell.

Of course, the thickness of the insulating layer can be set to other suitable values according to different application scene requirements.

As a possible implementation, as shown in fig. 13, the back contact cell further includes an aluminum oxide layer 19 and a silicon nitride layer 20 sequentially stacked and disposed on a light-facing surface of the silicon substrate 11 in a direction away from the silicon substrate 11. Or the back contact battery further comprises a silicon oxide layer and a silicon nitride layer which are sequentially stacked and arranged on a light facing surface of the silicon substrate along the direction away from the silicon substrate.

Specifically, the thicknesses of the aluminum oxide layer, the silicon nitride layer, and the silicon oxide layer may be set according to actual requirements, and are not particularly limited herein.

Under the condition of adopting the technical scheme, the alumina layer and the silicon nitride layer which are stacked can passivate the light facing surface, so that the recombination rate of carriers at the light facing surface is reduced, and the photoelectric conversion efficiency of the back contact battery is further improved. And moreover, the silicon nitride layer can play a role in antireflection, so that more light is refracted into the silicon substrate from the light-facing surface, and the utilization rate of the back contact battery to the light is further improved. On the basis, when a deposition process is adopted to form a passivation layer of amorphous silicon material on a light facing surface of a suede structure with a smaller size, epitaxial growth is easy to occur at the top of the suede structure, so that the thickness of the part of the amorphous silicon material at the top of the suede structure is larger than that of the part of the amorphous silicon material at the base of the suede structure, the thickness of each area of the passivation layer of the amorphous silicon material formed is inconsistent, the passivation effect of the passivation layer on the light facing surface is reduced, and the formation of other film layers on the light facing surface is also influenced. Compared with the passivation layer of the amorphous silicon material, the passivation layer of the aluminum oxide material is not epitaxially grown when being deposited on the light-facing surface of the small textured structure, so that the passivation effect of the passivation layer of the aluminum oxide material is better, the textured surface of the light-facing surface of the silicon substrate can be selected as the textured surface with smaller pyramid size, and the textured surface with smaller size has better light trapping effect, and the absorption of the silicon substrate to light is further improved. In addition, the above-mentioned stacked silicon oxide layer and silicon nitride layer may refer to the above-mentioned analysis of the beneficial effects of the stacked aluminum oxide layer and silicon nitride layer, and will not be described herein. In addition, the aluminum oxide layer, the silicon nitride layer, and the silicon oxide layer may be formed by deposition using an atomic layer deposition apparatus. And the intrinsic amorphous silicon layer needs to be deposited by using a chemical vapor deposition device. Based on this, since the cost of the atomic layer deposition apparatus is lower than that of the chemical vapor deposition apparatus, when an aluminum oxide layer (or a silicon oxide layer) and a silicon nitride layer are formed on the light-facing surface as passivation anti-reflection layers, the aluminum oxide (or silicon oxide) and the silicon nitride layer can be formed on the light-facing surface by deposition of the atomic layer deposition apparatus, so that the manufacturing cost of the back contact cell can be reduced.

In addition to the silicon oxide layer, the silicon nitride layer, and the aluminum oxide layer, a material forming a film layer having passivation and antireflection functions on the light-facing surface may be provided as other suitable materials. For example, the film layer having passivation and antireflection functions formed on the light-facing surface may further include at least one of a silicon oxynitride layer, a titanium oxide layer, and a silicon oxycarbide layer.

As a possible implementation, as shown in fig. 13, the insulating layer 161 includes an aluminum oxide layer and a silicon nitride layer that are sequentially stacked in a direction away from the silicon substrate 11. Alternatively, the insulating layer 161 includes a silicon oxide layer and a silicon nitride layer which are sequentially stacked in a direction away from the silicon substrate 11.

It will be appreciated that in addition to the silicon oxide layer, the silicon nitride layer and the aluminum oxide layer, the insulating layer may be provided with other materials having the passivation and antireflection functions as described above, so that the material of the insulating layer is the same as that of the passivation and antireflection layer.

As a possible implementation, as shown in fig. 13, the light-facing surface of the silicon substrate 11 is a textured surface. And the pile has a pile foundation width of 1 μm to 3 μm.

Under the condition of adopting the technical scheme, in a certain range, the smaller the tower base width of the suede is, the better the light trapping effect of the suede is. Based on the above, when the light-facing surface of the silicon substrate is a textured surface and the tower base width of the textured surface is 1-3 μm, the tower base width of the light-facing surface is relatively small, and the light-facing surface has a high light trapping effect, so that the photoelectric conversion efficiency of the back contact battery can be further improved.

In the conventional heterojunction back-contact cell, the passivation layer formed on the light-facing surface is usually an amorphous silicon layer. Furthermore, as described above, in order to ensure the passivation effect of the amorphous silicon layer on the light-facing surface, it is generally required to form a textured structure having a relatively large tower base width. In a certain range, the larger the tower base width of the pile face is, the worse the light trapping effect of the pile face is. Accordingly, the higher the reflectivity of the light-facing surface. Therefore, the amorphous silicon passivation layer on the light-facing surface of the existing heterojunction back contact cell has poor compatibility with the suede with smaller tower base width, and the reflectivity of the light-facing surface to light is difficult to reduce while the passivation effect of the light-facing surface is improved. In this case, in the practical application process, when the intrinsic amorphous silicon layer and the doped amorphous silicon layer which are stacked are formed on the backlight surface of the back contact battery provided by the embodiment of the invention, the passivation reflection layer which is made of amorphous silicon materials such as alumina, silicon oxide and the like and matched with the suede with smaller tower base width can be formed on the light facing surface, so that the passivation effect of the backlight surface can be improved, more light rays can be transmitted into the silicon substrate through the light facing surface, and the photoelectric conversion efficiency of the back contact battery provided by the embodiment of the invention can be further improved.

In some cases, as shown in fig. 16, the back contact battery provided by the embodiment of the present invention may further include a first transparent conductive layer 211, a second transparent conductive layer 212, a first electrode 22, and a second electrode 23. The first transparent conductive layer 211 is formed at least on the first doped semiconductor layer 141, and the first electrode 22 is located on a portion of the first transparent conductive layer 211 corresponding to the first doped semiconductor layer 141, so as to conduct out carriers collected by the first doped semiconductor layer 141. The second transparent conductive layer 212 is formed on the second doped semiconductor layer 18, and the second transparent conductive layer 212 and the first transparent conductive layer 211 are insulated from each other. The second electrode 23 is positioned on the second transparent conductive layer 212 so as to guide out carriers collected by the second doped semiconductor layer 18.

The material of the first transparent conductive layer or the second transparent conductive layer can be fluorine doped tin oxide, aluminum doped zinc oxide, tin doped indium oxide, tungsten doped indium oxide, molybdenum doped indium oxide, cerium doped indium oxide, indium hydroxide and the like. The thicknesses of the first transparent conductive layer and the second transparent conductive layer may be set according to actual requirements, and are not particularly limited herein. The first electrode and the second electrode may be made of conductive materials such as silver, aluminum, copper, nickel, and the like.

In a second aspect, embodiments of the present invention further provide a photovoltaic module, where the photovoltaic module includes the back contact battery provided in the first aspect and various implementations thereof.

In a third aspect, the embodiment of the invention also provides a method for manufacturing the back contact battery. Hereinafter, the manufacturing process will be described with reference to cross-sectional views during the manufacturing process of the back contact battery shown in fig. 3 to 16. Specifically, the manufacturing method of the back contact battery comprises the following steps:

first, as shown in fig. 1, a silicon substrate 11 is provided. The specific structure of the silicon substrate 11 may be referred to as above, and will not be described herein.

In the practical application process, the doped silicon substrate can be polished in groove type cleaning equipment by adopting alkaline cleaning solution such as KOH and the like to obtain the silicon substrate. In this case, compared with the untreated bare silicon substrate, the polished back surface and the polished light-facing surface of the polished silicon substrate are both flat polished surfaces, so that the subsequent formation of a structure meeting the process requirements based on the flat polished surfaces is facilitated, and the yield of the back contact battery is improved.

As shown in fig. 7, a first passivation layer 121 and a first doped semiconductor layer 141, which are sequentially stacked on a backlight surface provided on the silicon substrate 11, are formed along a thickness direction of the silicon substrate 11. For details, the materials and thicknesses of the first passivation layer 121 and the first doped semiconductor layer 141 may be referred to as above, and will not be described herein.

Illustratively, the forming of the first passivation layer and the first doped semiconductor layer in a stacked arrangement may include the steps of sequentially forming the passivation material layer 12 covering the backlight surface and the intrinsic semiconductor material layer 13 on the passivation material layer 12 as shown in fig. 4. As shown in fig. 5, the intrinsic semiconductor material layer is subjected to a diffusion process such that the intrinsic semiconductor material layer forms a doped semiconductor material layer 14, and a doped glass layer 15 is formed on the doped semiconductor material layer 14. And then, removing part of the doped glass layer on the doped semiconductor material layer by adopting a laser etching process. Wherein the remaining portion of the doped glass layer forms a mask layer. Finally, as shown in fig. 6 and 7, under the masking action of the masking layer 151, the portion of the doped semiconductor material layer exposed outside the masking layer and the portion of the passivation material layer exposed outside the masking layer are sequentially removed, thereby forming the first passivation layer 121 and the first doped semiconductor layer 141 which are stacked.

In a practical application process, the forming process of the first passivation layer and the first doped semiconductor layer may be determined according to materials of the two. For example, in the case where the first passivation layer is a tunneling passivation layer and the first doped semiconductor layer is doped polysilicon, as shown in fig. 4, a low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, abbreviated as LPCVD) or the like may be used to sequentially form the passivation material layer 12 covering the backlight surface and the intrinsic semiconductor material layer 13 on the passivation material layer 12. In the process of forming the passivation material layer 12 and the intrinsic semiconductor material layer 13, a round-plated passivation material layer and a round-plated intrinsic semiconductor material layer are also formed on the side surface and the light-facing surface of the silicon substrate 11. Next, the intrinsic semiconductor material layer 13 is subjected to diffusion treatment by a diffusion apparatus. Specifically, as shown in fig. 5, when the intrinsic semiconductor material layer located on the passivation material layer 12 is subjected to diffusion treatment, the intrinsic semiconductor material layer is converted into the doped semiconductor material layer 14, and a doped glass layer 15 is formed on the surface of the doped semiconductor material layer 14. The processing conditions of the diffusion process may be determined according to the doping concentration of the doping element in the first doped semiconductor layer 141, the thickness and the densification degree of the doped glass layer 15 to be formed, and the actual application scenario, and are not particularly limited herein. Naturally, after diffusion treatment, the above-mentioned around-plating intrinsic semiconductor material layer is also formed into a around-plating doped semiconductor material layer, and a around-plating doped glass layer is formed on the around-plating doped semiconductor material layer. Then, after patterning the doped glass layer 15 by using a laser etching process, a mask layer may be formed on the remaining portion of the doped glass layer. The mask layer covers the doped semiconductor material layer on the part corresponding to the first doped semiconductor layer. As shown in fig. 6, under the masking action of the masking layer 151, the doped semiconductor material layer and the passivation material layer may be patterned by using a process such as laser etching, wet etching or dry etching, to form the first passivation layer 121 and the first doped semiconductor layer 141 which are stacked.

It is noted that the mask layer used in patterning the doped semiconductor material layer and the passivation material layer is obtained by patterning the doped glass layer. In other words, the patterning treatment of the doped semiconductor material layer and the passivation material layer can be realized without forming other mask layers such as silicon nitride and the like, so that the manufacturing process of the back contact battery is simplified, and the manufacturing cost of the back contact battery can be reduced.

In particular, the specific material of the doped glass layer may be determined according to the material and the doping type of the first doped semiconductor layer. For example, when the first doped semiconductor layer is an N-type doped polysilicon layer doped with phosphorus, the doped glass layer is a phosphosilicate glass layer. For another example, when the first doped semiconductor layer is a boron doped P-type doped polysilicon layer, the doped glass layer is a borosilicate glass layer.

In addition, the thickness of the doped glass layer can be set according to practical requirements, so long as the mask layer formed by the doped glass layer has a corresponding masking effect.

The doped glass layer may have a thickness of, for example, 40nm to 60nm. For example, the doped glass layer may have a thickness of 40nm, 45nm, 50nm, 55nm, or 60nm. Under the condition, the thickness of the doped glass layer is moderate, so that the problem that the first doped semiconductor layer and the first passivation layer below the doped glass layer are difficult to protect in corresponding operation due to poor protection effect of a mask layer formed by the rest part of the doped glass layer caused by the small thickness of the doped glass layer can be prevented, the first doped semiconductor layer and the first passivation layer are ensured to have good film forming quality, and the yield of the back contact battery is improved. Meanwhile, the problems of reduced manufacturing efficiency, increased manufacturing cost and the like caused by larger thickness of the doped glass layer can be prevented, and the mass production of the back contact battery is facilitated to be improved.

In addition, the diffusion time of the diffusion treatment may be 60 to 120 minutes, and the diffusion temperature may be 800 to 900 ℃. For example, the diffusion time may be 60min, 70min, 80min, 90min, 100min, 110min, or 120min. The diffusion temperature may be 810 ℃, 820 ℃, 830 ℃, 840 ℃, 850 ℃, 860 ℃, 870 ℃, 880 ℃, 890 ℃, or 900 ℃.

It is understood that the diffusion temperature and the diffusion time will affect the thickness of the doped glass layer formed during the diffusion process and the compactness of the doped glass layer. Specifically, within a certain range, the longer the diffusion time and the higher the diffusion temperature, the greater the thickness and the higher the compactness of the formed doped glass layer, and the stronger the masking action of the mask layer formed by the doped glass layer. Conversely, within a certain range, the shorter the diffusion time and the lower the diffusion temperature, the smaller the thickness and lower the compactness of the doped glass layer formed, and the weaker the masking action of the mask layer formed by the doped glass layer. In this case, when the diffusion time is 60min to 120min and the diffusion temperature is 800 ℃ to 900 ℃, it is possible to prevent the first doped semiconductor layer and the first passivation layer located thereunder from being difficult to protect in the corresponding operation due to the short diffusion time and the low diffusion temperature, ensure good film formation quality of the first doped semiconductor layer and the first passivation layer, and improve the yield of the back contact battery. Meanwhile, the problems of reduced manufacturing efficiency, increased manufacturing cost and the like caused by longer diffusion time and higher diffusion temperature can be prevented, and the mass production of the back contact battery is facilitated to be improved.

Besides performing diffusion treatment on the intrinsic semiconductor material layer to form a doped semiconductor material layer, the formation of the doped semiconductor material layer may be realized by using processes such as ion implantation or doping source coating promotion. The formation process of the proper doped semiconductor material layer can be selected according to the actual application scene requirement.

In addition, as described above, in the case where the first passivation layer is a tunneling passivation layer and the first doped semiconductor layer is a doped polysilicon layer, the doped polysilicon layer may be formed by a plasma enhanced chemical vapor deposition process in addition to the low pressure chemical vapor deposition process and the diffusion process. And in addition, the doped polysilicon layer can be crystallized in an in-situ annealing mode to reduce the stress in the doped polysilicon layer and improve the film forming quality of the doped polysilicon layer.

Furthermore, as described above, the first passivation layer may be a tunneling passivation layer, and the first doped semiconductor layer may be a doped polysilicon layer. Based on this, after sequentially forming the passivation material layer 12 covering the backlight surface and the doped semiconductor material layer 14 on the passivation material layer 12 as shown in fig. 5, the doped semiconductor material layer and the passivation material layer may be subjected to patterning treatment using a laser etching process as shown in fig. 6, to form the first passivation layer 121 and the first doped semiconductor layer 141 which are stacked. The beneficial effects of the first passivation layer 121 described above may be referred to as a tunneling passivation layer, and the first doped semiconductor layer 141 is a doped polysilicon layer, which is not described herein.

Illustratively, as described above, the light-facing surface of the silicon substrate may be a polished surface or a textured surface. In the case that the light-facing surface of the silicon substrate is textured and the mask layer is formed on the first doped semiconductor layer, after the first passivation layer and the first doped semiconductor layer are formed and stacked, and before the subsequent operation, the method for manufacturing the back contact battery further includes the step of removing the around-plated doped glass 5 layer, the around-plated doped semiconductor material layer, and the around-plated passivation material layer on the light-facing surface and the side surface of the silicon substrate 11 as shown in fig. 7. For example, a chain type cleaning apparatus may be employed, and

And removing the around-plating doped glass layer, the around-plating doped semiconductor material layer and the around-plating passivation material layer by using a roller belt or water bleaching mode. Next, as shown in fig. 8, the light-facing surface of the silicon substrate 11 is subjected to a texturing process by the mask of the mask layer 151 so that the light-facing surface is textured. Wherein the portion of the backlight surface exposed outside the mask layer 151 also

Forming a pile surface. The solution used in the texturing process and the process conditions may be determined according to the actual application scenario, and 0 is not particularly limited here. Next, as shown in fig. 9, the mask layer 151 may be removed using an HF solution. The concentration of the HF solution, and the removal time may be set according to actual requirements.

Under the condition of adopting the technical proposal, as described above, the mask layer used in the flocking process adopts the laser etching process to pattern the doped glass layer formed on the doped semiconductor material layer in the diffusion process

The first passivation layer and the first doped semiconductor layer are not stacked, but are additionally formed by depositing 5 steps to form a mask layer such as silicon nitride, thereby further simplifying the manufacturing process of the back contact battery and reducing the back contact electricity

Manufacturing cost of the pool.

It should be noted that, as described above, the back contact battery manufactured by the manufacturing method provided by the embodiment of the invention includes:

The semiconductor device comprises a silicon substrate, a first passivation layer, a first doped semiconductor layer, a second passivation layer, a second doped semiconductor layer and an insulating layer. Which is a kind of

As shown in fig. 13, the second passivation layer 17 and the second doped semiconductor layer 18 which are stacked and disposed cover a partial region of the first passivation layer 121 and the first doped semiconductor layer 141 which are stacked and disposed. And the insulating layer 161 is at least at the second passivation

Between the layer 17 and the first doped semiconductor layer 141, for spacing apart the second passivation layer 17 and the first doped semiconductor layer 141. In this case, as shown in fig. 11, after forming the first passivation layer 121 and the first doped semiconductor layer 141 which are stacked, and before forming the second passivation layer and the second doped semiconductor layer which are stacked, the method for manufacturing a back contact battery further includes the step of forming an insulating layer on the back surface.

5 Exemplary, as shown in FIG. 10, a plasma enhanced atomic layer deposition process or the like may be used to form a coating on the back

A light plane and a layer of insulating material 16 on the first doped semiconductor layer 141. Next, as shown in fig. 11, a laser etching process may be used to pattern the insulating material layer 16, so as to expose a region where the backlight surface contacts with a subsequently formed second passivation layer 17. Wherein the insulating material layer 16 covers the first passivation layer 121 and the first doped half of the stacked arrangement

Portions of the corresponding regions of the conductor layer 141 form an insulating layer. The corresponding region is a region where the first passivation layer 121 and the first 0-doped semiconductor layer 141 are stacked and the second passivation layer and the second doped semiconductor layer are stacked.

In addition, under the condition that the insulating material layer is subjected to patterning treatment by adopting a laser etching process, after exposing the area where the backlight surface is contacted with the second passivation layer formed subsequently, the surface of the area damaged by high-temperature laser etching can be cleaned and repaired by adopting a wet etching process under the mask effect of the rest part of the insulating material layer, so that the defect recombination rate of carriers at the interface is reduced, the compactness of the second passivation layer formed on the area can be improved, the passivation effect of the second passivation layer on the area is further improved, and the photoelectric conversion efficiency of the back contact battery is improved.

As shown in fig. 13, a second passivation layer 17 and a second doped semiconductor layer 18, which are sequentially stacked on the backlight surface, are formed along the thickness direction of the silicon substrate 11. Wherein the second passivation layer 17 and the second doped semiconductor layer 18 which are stacked cover a partial region of the first passivation layer 121 and the first doped semiconductor layer 141 which are stacked, and the second doped semiconductor layer 18 and the first doped semiconductor layer 141 are opposite in conductivity type. For details, the materials and thicknesses of the second passivation layer 17 and the second doped semiconductor layer 18 may be referred to above, and will not be described herein.

In a practical application process, as shown in fig. 12, a passivation material and a doped semiconductor material may be sequentially formed to cover the backlight surface and the remaining portion of the insulating material layer 16 by a chemical vapor deposition process or the like. Next, as shown in fig. 13, the passivation material and the doped semiconductor material may be subjected to patterning treatment using a process such as laser etching, so that the remaining passivation material forms the second passivation layer 17, and the remaining doped semiconductor material forms the second doped semiconductor layer 18. Finally, the remaining portion of the insulating material layer 16 may be patterned by wet etching or the like under the mask of the second doped semiconductor layer 18 to expose a portion of the first doped semiconductor layer 141. Wherein the remaining insulating material layer forms an insulating layer 161.

In some cases, as previously described, when the fabricated back contact cell further includes a first transparent conductive layer, a second transparent conductive layer, a first electrode, and a second electrode, as shown in fig. 14, a physical vapor deposition process or the like may be used to form the transparent conductive material layer 21 overlying the first doped semiconductor layer 141 and the second doped semiconductor layer 18. Next, as shown in fig. 15, an insulating trench penetrating the transparent conductive layer, the second doped semiconductor layer 18, and the second passivation layer 17 may be formed using a laser etching process or the like to space apart a portion of the transparent conductive material layer on the first doped semiconductor layer 141 from a portion of the transparent conductive material layer on the second doped semiconductor layer 18. Wherein, at least a portion of the transparent conductive material layer located on the first doped semiconductor layer 141 forms a first transparent conductive layer 211, and a portion of the transparent conductive material layer located on the second doped semiconductor layer 18 forms a second transparent conductive layer 212. Finally, as shown in fig. 16, the first electrode 22 on the first transparent conductive layer 211 and the second electrode 23 on the second transparent conductive layer 212 may be formed using a screen printing process or the like.

The invention also provides the following specific examples to further illustrate the manufacturing method of the back contact battery, which comprises the following specific operation steps:

Example 1:

And the first step is to put the N-type silicon wafer or the P-type silicon wafer into a groove type polishing and cleaning machine for polishing. Wherein the polishing solution is a KOH solution having a concentration of 5.5% to 6.5%. The temperature of the polishing solution is 81 ℃ to 87 ℃. The process time is 290s to 310s. The surface topography of the silicon substrate after the polishing process is a square structure with the size of 19-23 mu m, and the reflectivity of the backlight surface of the silicon substrate after the polishing process is 40-44%.

A second step of forming a tunnel oxide material layer on the back surface of the silicon substrate and an intrinsic polysilicon material layer on the tunnel oxide material layer in a low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, abbreviated as LPCVD) furnace. The thickness of the tunneling oxide material layer is 1.2nm to 1.8nm, and the thickness of the intrinsic polycrystalline silicon material layer is 70nm to 170nm. In addition, a round plating passivation material layer and a round plating polysilicon material layer are sequentially formed on the side surface and the light-facing surface of the silicon substrate.

And thirdly, carrying out phosphorus doping on the intrinsic polycrystalline silicon material (Poly) layer in a phosphorus diffusion furnace so that the intrinsic polycrystalline silicon material layer forms an N-type doped polycrystalline silicon material layer. The diffusion sheet resistance of the N-type doped polysilicon material layer is 70 omega/sq to 110 omega/sq. Wherein, after diffusion treatment, the phosphorus silicon glass layer is formed on the N-type doped polysilicon material layer and the winding plating polysilicon material layer.

And fourthly, patterning the part of the phosphosilicate glass layer corresponding to the backlight surface, the tunneling oxide material layer and the N-type doped polysilicon material layer by using a laser etching process to expose the area of the backlight surface corresponding to the P+ region. The remaining portion of the tunneling oxide material layer forms a first passivation layer, and the remaining portion of the N-type doped polysilicon material layer forms a first doped semiconductor layer. The portion of the phosphosilicate glass layer located on the first doped semiconductor layer forms a mask layer.

And fifthly, in a chain type cleaning machine, enabling the light facing surface of the silicon substrate to face downwards, enabling the silicon substrate to enter an HF groove, and removing the side surface and the light facing surface of the silicon substrate and the around plating passivation material layer and the around plating polysilicon material layer at normal temperature through an HF solution with the concentration of 9.5-10.5% in a roller belt type or water floating type cleaning mode. Wherein the removal time is 55s to 65s. And then, the silicon substrate with the first passivation layer, the first doped semiconductor layer and the mask layer is put into a groove type cleaning machine for alkali texturing. Wherein the texturing solution comprises KOH solution with concentration of 2.5 to 3.5 percent and texturing additive solution. The temperature of the texturing solution is 80-84 ℃ and the process time is 570-630 s. The etching amount is 0.5g to 0.7g, and the reflectivity of the light facing surface of the silicon substrate after the texturing treatment is 9 percent to 11 percent. A small suede microstructure with a tower base width of 1-3 μm facing the light surface. At this time, the P+ region of the backlight surface and the light-directing surface finish the texturing process at the same time. Finally, the mask layer is removed in an HF tank, the concentration of the HF solution is 9.5 to 10.5 percent, and the HF solution is processed for 95 to 105 seconds at normal temperature.

A sixth step of sequentially depositing an aluminum oxide layer and a silicon nitride layer on the backlight side and the light-facing side in a plasma enhanced atomic layer deposition (PLASMA ENHANCED Atomic Layer Deposition, abbreviated as PEALD) apparatus. The thickness of the aluminum oxide layer is 5nm to 15nm, and the thickness of the silicon nitride layer is 70nm to 110nm.

And seventhly, patterning the aluminum oxide layer and the silicon nitride layer on the backlight surface by using a laser to remove the parts of the aluminum oxide layer and the silicon nitride layer on the P+ region. The patterning process is designed corresponding to the silk screen pattern, and the laser type can be selected from green nanoseconds, ultraviolet picoseconds, green picoseconds and ultraviolet nanoseconds.

And eighth step, polishing process is carried out in a groove type polishing cleaner. The polishing solution is KOH solution with concentration of 5.5-6.5%, the temperature of the polishing solution is 81-87 ℃ and the process time is 170-190 s, so as to remove the laser damage generated in the seventh step. And simultaneously, polishing the laser grooving area. Finally, the treatment is carried out in HF solution at a concentration of 1% wt for 25s to 35s.

And a ninth step of sequentially forming an intrinsic amorphous silicon material layer and a boron-doped P-type doped amorphous silicon material layer which are covered on the backlight surface in chemical vapor deposition equipment. Wherein the thickness of the intrinsic amorphous silicon material layer is 5nm to 20nm, and the thickness of the P-type doped amorphous silicon material layer is 10nm to 30nm.

And a tenth step of patterning the intrinsic amorphous silicon material layer and the P-type doped amorphous silicon material layer by using a laser so that the remaining part of the intrinsic amorphous silicon material layer forms a second passivation layer and the remaining part of the P-type doped amorphous silicon material layer forms a second doped semiconductor layer. The laser type can be green nanosecond, ultraviolet picosecond, green picosecond or ultraviolet nanosecond.

Eleventh, in the chain cleaner, the backlight side of the silicon substrate is turned down into the HF tank. Wherein the concentration of the HF solution is 29 to 31 percent, and the HF solution is processed for 175 to 185 seconds at normal temperature, and the cleaning mode is a roller liquid carrying mode or a water floating mode. And removing the exposed parts of the aluminum oxide layer and the silicon nitride layer on the backlight surface after the laser etching treatment so as to expose part of the area of the first doped semiconductor layer. Finally, the waste water enters a water tank and a drying tank in sequence for cleaning and drying respectively. Wherein the aluminum oxide layer and the remaining portion of the silicon nitride layer on the backlight surface form an insulating layer.

And twelfth, forming a transparent conductive material layer covering the backlight surface in the physical vapor deposition equipment. The transparent conductive material layer has a thickness of 60nm to 100nm.

And thirteenth step, removing the partial transparent conductive material layer, the second doped semiconductor layer and the second passivation layer by using a laser etching process so as to realize insulation of the N+ region and the P+ region.

Fourteenth, the first electrode and the second electrode are formed by adopting a screen printing process and the like. The resulting structure is shown in fig. 16.

Further, the invention also provides a back contact battery manufactured by the following comparative example, and the specific operation steps are as follows:

Comparative example 1:

And a second step of forming a first silicon nitride layer covering the back surface of the silicon substrate by using a plasma enhanced chemical vapor deposition device. The first silicon nitride layer has a thickness of 190nm to 210nm and a refractive index of 2.3% to 2.5%. Wherein, the side surface and the light-facing surface of the silicon substrate are formed with a wrap-plated silicon nitride layer.

And thirdly, in a groove type cleaning machine, the silicon substrate with the first silicon nitride layer and the winding plating silicon nitride layer is put into an HF groove. Wherein the concentration of the HF solution is 0.5% to 1.5%. And processing at normal temperature for 25s to 35s to remove the wrap-around silicon nitride layer. Then, the silicon substrate with the first silicon nitride layer formed on the backlight surface enters an alkali tank for texturing treatment. The texturing solution comprises a KOH solution with a concentration of 2 to 3 percent and a texturing additive solution. The temperature of the texturing solution is 80 ℃ to 84 ℃. The process time is 760s to 800s. Then, the mixture enters a tank for bearing HNO ₃ and HF mixed solution to carry out suede smoothing treatment. The mixture ratio of the mixed solution is HNO ₃:HF=1:100. The total etching amount after the suede smoothing treatment is 1.7g to 1.9g. The reflectivity of the silicon substrate to the light surface is 11 to 13 percent. A large pile microstructure with a tower base width of 3-5 μm on the light facing surface. Finally, the first silicon nitride layer remaining on the backlight surface was removed by treating in an HF bath having a concentration of 8% wt and at normal temperature for 290s to 310 s.

And step four, sequentially forming a first intrinsic amorphous silicon material layer, a phosphorus-doped N-type doped amorphous silicon material layer, a second silicon nitride layer and a second intrinsic amorphous silicon material layer which are covered on the backlight surface in chemical vapor deposition equipment. Wherein the thickness of the first intrinsic amorphous silicon material layer is 5nm to 20nm, the thickness of the N-type doped amorphous silicon material layer is 10nm to 30nm, the thickness of the second silicon nitride layer is 170nm to 230nm, and the thickness of the second intrinsic amorphous silicon material layer is 10nm to 30nm.

And fifthly, patterning the second intrinsic amorphous silicon material layer by using a laser to expose the P+ region. The laser type can be green nanoseconds, ultraviolet picoseconds, green picoseconds and ultraviolet nanoseconds;

And a sixth step of introducing the silicon substrate formed with the first intrinsic amorphous silicon material layer, the N-type doped amorphous silicon material layer, the second silicon nitride layer and the second intrinsic amorphous silicon material layer into an HF bath in a bath cleaning apparatus, wherein the concentration of the HF solution is 7.5% to 8.5%, and treating at normal temperature for 190s to 210s to remove the exposed portion of the second silicon nitride layer. And then, an alkali tank is entered for etching treatment so as to remove the exposed parts of the first intrinsic amorphous silicon material layer and the N-type doped amorphous silicon material layer, so that the rest part of the first intrinsic amorphous silicon material layer forms a first passivation layer and the N-type doped amorphous silicon material layer forms a first doped semiconductor layer. The etching solution comprises KOH with the concentration of 0.4-0.6% and H ₂O₂ solution with the concentration of 0.1-0.2%, the temperature of the etching solution is 25 ℃, and the process time is 390-410 s.

And seventhly, sequentially forming a third intrinsic silicon material layer and a boron-doped P-type doped amorphous silicon material layer which are covered on the backlight surface in chemical vapor deposition equipment. And forming a fourth intrinsic amorphous silicon material layer and a third silicon nitride layer on the light-facing surface in sequence. Wherein the thickness of the third intrinsic amorphous silicon material layer is 5nm to 30nm, the thickness of the P-type doped amorphous silicon material layer is 10nm to 25nm, the thickness of the fourth intrinsic amorphous silicon material layer is 5nm to 20nm, and the thickness of the third silicon nitride layer is 80nm to 105nm.

And eighth step, patterning the third intrinsic silicon material layer and the P-type doped amorphous silicon material layer on the backlight surface by using a laser, so that the rest part of the third intrinsic silicon material layer forms a second passivation layer, and the rest part of the P-type doped amorphous silicon material layer forms a second doped semiconductor layer. The laser type can be green nanosecond, ultraviolet picosecond, green picosecond or ultraviolet nanosecond.

And a ninth step of removing the exposed portion of the second silicon nitride layer using an HF solution to expose a partial region of the first doped semiconductor layer and forming an insulating layer such that the portion of the second silicon nitride layer on the first doped semiconductor layer. Wherein the concentration of the HF solution is 7% to 9%, and is treated at normal temperature for 380s to 420s.

And tenth, forming a transparent conductive material layer covering the backlight surface in the chemical vapor deposition equipment. The transparent conductive material layer has a thickness of 60nm to 100nm.

And eleventh, etching the transverse junction of the first doped semiconductor layer and the second doped semiconductor layer by using a laser, and removing the partial transparent conductive material layer, the partial second passivation layer and the partial second doped semiconductor layer so that the part of the transparent conductive material layer positioned on the first doped semiconductor layer forms a first transparent conductive layer and the part of the transparent conductive material layer positioned on the second doped semiconductor layer forms a second transparent conductive layer.

And twelfth, forming the first electrode and the second electrode by adopting a screen printing process and the like. The resulting structure is shown in fig. 1.

Comparative example 2:

And forming a tunneling oxide material layer covering the back surface of the silicon substrate and an intrinsic polycrystalline silicon material layer positioned on the tunneling oxide material layer in a low-pressure chemical vapor deposition furnace. The thickness of the tunneling oxide material layer is 1.2nm to 1.8nm, and the thickness of the intrinsic polycrystalline silicon material layer is 70nm to 170nm. In addition, a round plating passivation material layer and a round plating polysilicon material layer are sequentially formed on the side surface and the light-facing surface of the silicon substrate.

And thirdly, carrying out phosphorus doping on the intrinsic polycrystalline silicon material layer in a phosphorus diffusion furnace so that the intrinsic polycrystalline silicon material layer forms an N-type doped polycrystalline silicon material layer. The diffusion sheet resistance of the N-type doped polysilicon material layer is 70 omega/sq to 110 omega/sq. Wherein, after diffusion treatment, the phosphorus silicon glass layer is formed on the N-type doped polysilicon material layer and the winding plating polysilicon material layer.

And fourthly, forming a silicon nitride layer covering the backlight surface by using plasma chemical vapor deposition. The silicon nitride layer has a thickness of 40nm to 60nm and a refractive index of 2.3% to 2.5%.

And fifthly, patterning the silicon nitride layer on the backlight surface by using a laser to expose the area of the backlight surface corresponding to the P+ region. The laser type can be green nanosecond, ultraviolet picosecond, green picosecond or ultraviolet nanosecond.

And a sixth step of introducing the formed structure into an HF tank in a tank cleaner to remove the portion of the phosphosilicate glass layer exposed to the outside of the silicon nitride of the backlight surface. The concentration of the HF solution is 0.5% to 1.5%, and is treated at normal temperature for 25s to 35s. Then, the waste water enters an alkali tank to be subjected to texturing treatment so as to perform texturing on the exposed areas of the opposite light surface and the backlight surface. The texturing solution comprises KOH at a concentration of 2.5% to 3.5% and a texturing additive solution. The temperature of the texturing solution is 80-84 ℃ and the process time is 570-630 s. The etching amount of the wool is 0.5g to 0.7g. The reflectivity of the light-facing surface after the texturing treatment is 9-11%, and the tower base width of the light-facing surface is a small suede microstructure of 1-3 mu m.

And seventhly, in the plasma enhanced atomic layer deposition equipment, an aluminum oxide layer and a silicon nitride layer which are covered on the light facing surface are sequentially formed. Wherein the thickness of the aluminum oxide layer is 5nm to 15nm, and the thickness of the silicon nitride layer is 70nm to 110nm. The exposed areas of the backlight surface were then polished by treating them in a 1% wt HF solution for 30 s.

And eighth step, forming an intrinsic amorphous silicon material layer and a boron-doped P-type doped amorphous silicon material layer which are covered on the backlight surface in sequence in chemical vapor deposition equipment. The thickness of the intrinsic amorphous silicon material layer is 5nm to 30nm, and the thickness of the P-type doped amorphous silicon layer is 10nm to 25nm.

And a ninth step of patterning the intrinsic amorphous silicon material layer and the P-type doped amorphous silicon material layer using a laser so that the remaining portion of the intrinsic amorphous silicon material layer forms a second passivation layer and the remaining portion of the P-type doped amorphous silicon material layer forms a second doped semiconductor layer. The laser type can be green nanosecond, ultraviolet picosecond, green picosecond or ultraviolet nanosecond.

And a tenth step of removing the exposed portion of the silicon nitride layer using an HF solution to expose a partial region of the first doped semiconductor layer. Wherein the concentration of the HF solution is 7% to 9%, and is treated at normal temperature for 380s to 420s.

And eleventh, forming a transparent conductive material layer covering the backlight surface in the physical vapor deposition equipment. The transparent conductive material layer has a thickness of 60nm to 100nm.

And a twelfth step of removing the partial transparent conductive material layer, the second doped semiconductor layer and the second passivation layer by using a laser etching process so as to realize insulation of the N+ region and the P+ region.

And thirteenth step, forming the first electrode and the second electrode by adopting a screen printing process and the like. The resulting structure is shown in fig. 2.

Among them, table 1 tests the back contact batteries manufactured by the above example 1, comparative example 1 and comparative example 2, and compares the parameters of the above three back contact batteries.

TABLE 1 comparison of parameters of the back contact batteries fabricated in example 1, comparative example 1 and comparative example 2

As shown in fig. 16, in the back contact battery manufactured in embodiment 1, the insulating layer 161 is located at least between the second passivation layer 17 and the first doped semiconductor layer 141. Also, the insulating layer 161 includes an aluminum oxide layer and a silicon nitride layer in a direction away from the silicon substrate 11. In the back contact battery manufactured in comparative example 1, as shown in fig. 1, the insulating layer 161 of silicon nitride material was formed only at the longitudinal boundary of the first doped semiconductor layer 141 and the second passivation layer 17. As shown in fig. 2, in the back contact battery manufactured in comparative example 2, a doped glass layer and an insulating layer 161 on the doped glass layer are formed only at the longitudinal boundary of the first doped semiconductor layer 141 and the second passivation layer 17. Based on this, it can be seen from table 1 that the parallel resistance and the short-circuit current of the back-contact battery manufactured in example 1 are higher than those of the back-contact batteries manufactured in comparative examples 1 and 2, respectively, and the open-circuit voltage of the back-contact battery manufactured in example 1 is smaller than those of the back-contact batteries manufactured in comparative examples 1 and 2, thereby facilitating reduction of the leakage risk of the back-contact battery, and further, the conversion efficiency of the back-contact battery manufactured in example 1 is higher than those of the back-contact batteries manufactured in comparative examples 1 and 2.

In the back contact battery manufactured in example 1, as shown in fig. 16, an aluminum oxide layer and a silicon nitride layer on the aluminum oxide layer were formed in this order on the light-facing surface in a direction away from the silicon substrate. In the back contact cell manufactured in comparative example 1, as shown in fig. 1, an amorphous silicon passivation layer and a silicon nitride layer on the amorphous silicon passivation layer were sequentially formed on the light facing surface in a direction away from the silicon substrate. Because of this, the amorphous silicon passivation layer on the light-facing surface has parasitic absorption due to the light absorption property of the amorphous silicon, resulting in a reduction of light incident into the silicon substrate. Also, as described above, the amorphous silicon passivation layer is difficult to match with the light facing surface having the small textured structure, and the aluminum oxide layer may match with the light facing surface of the small textured structure. In this case, as can be seen from table 1, the light-directing surface tower base width and the light-directing surface reflectivity of the back-contact battery manufactured in example 1 are smaller than the light-directing surface tower base width and the light-directing surface reflectivity corresponding to the back-contact battery manufactured in comparative example 1, respectively, so as to facilitate enhancement of the light trapping effect of the light-directing surface, so that more light is incident into the silicon substrate, and finally, the conversion efficiency of the back-contact battery manufactured in example 1 is greater than the conversion efficiency corresponding to the back-contact battery manufactured in comparative example 1.

Further, as shown in fig. 16, in the back contact cell manufactured in embodiment 1, the first passivation layer 121 and the first doped semiconductor layer 141 form a tunneling passivation contact structure. The second passivation layer 17 and the second doped semiconductor layer 18 constitute a hetero-contact structure. In contrast, in the back contact cell manufactured in comparative example 1, as shown in fig. 1, the first passivation layer 121 and the first doped semiconductor layer 141 constitute a hetero contact structure. While the second passivation layer 17 and the second doped semiconductor layer 18 also constitute a hetero-contact structure. Based on this, as described above, the chemical properties of the tunneling passivation contact structure are more stable at high temperature than the hetero-contact structure, so that the passivation effect on the tunneling passivation contact structure is smaller after the laser film opening process. Also, as can be seen from table 1, the n+ region laser process window of the back contact cell manufactured in example 1 is larger than the corresponding n+ region laser process window of the back contact cell manufactured in comparative example 1.

From the foregoing, it can be seen from table 1 that the back contact battery manufactured in example 1 has a higher fill factor than the back contact batteries manufactured in comparative examples 1 and 2, i.e., the quality of the back contact battery manufactured in example 1 is superior to that of the back contact batteries manufactured in comparative examples 1 and 2.

In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.

The embodiments of the present disclosure are described above. These examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.

Claims

1. A back contact battery, comprising: a silicon substrate,

A first passivation layer and a first doped semiconductor layer are sequentially stacked on the backlight surface of the silicon substrate along the thickness direction of the silicon substrate;

A second passivation layer and a second doped semiconductor layer are sequentially stacked on the backlight surface along the thickness direction of the silicon substrate; wherein the stacked second passivation layer and the second doped semiconductor layer cover a portion of the stacked first passivation layer and the first doped semiconductor layer, and the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types;

An insulating layer disposed on the backlight surface; the insulating layer is at least located between the second passivation layer and the first doped semiconductor layer, and is used to separate the second passivation layer from the first doped semiconductor layer; the insulating layer extends from the sidewalls of the stacked first passivation layer and the first doped semiconductor layer to the silicon substrate, contacts the silicon substrate, and extends in a direction away from the first doped semiconductor layer; the stacked second passivation layer and the second doped semiconductor layer at least cover the portion of the insulating layer that contacts the silicon substrate;

A passivation anti-reflection layer is arranged on the light-facing surface of the silicon substrate; the material of the insulating layer is the same as that of the passivation anti-reflection layer; the insulating layer includes at least two layers, and the material of the insulating layer has passivation and anti-reflection functions.

2 . The back contact cell according to claim 1 , wherein the first passivation layer is a tunneling passivation layer, and the first doped semiconductor layer is a doped polysilicon layer.

3 . The back contact cell according to claim 2 , wherein the second passivation layer is an intrinsic amorphous silicon layer, and the second doped semiconductor layer is a doped amorphous silicon layer.

4. The back contact cell according to claim 1, characterized in that the back contact cell further comprises: an aluminum oxide layer and a silicon nitride layer stacked in sequence on the light-facing surface of the silicon substrate in a direction away from the silicon substrate; or

The back contact cell further comprises: a silicon oxide layer and a silicon nitride layer which are sequentially stacked on the light-facing surface of the silicon substrate in a direction away from the silicon substrate.

5. The back contact cell according to any one of claims 1 to 4, characterized in that, along a direction away from the silicon substrate, the insulating layer comprises an aluminum oxide layer and a silicon nitride layer stacked in sequence; or

Along a direction away from the silicon substrate, the insulating layer includes a silicon oxide layer and a silicon nitride layer stacked in sequence.

6 . The back-contact battery according to claim 1 , wherein the thickness of the insulating layer is 75 nm to 125 nm.

7 . The back contact cell according to claim 1 , wherein the light-facing surface of the silicon substrate is a velvet surface; and the width of the tower base of the velvet surface is 1 μm to 3 μm.

8. A photovoltaic module, characterized by comprising a back contact cell as claimed in any one of claims 1 to 7.

9. A method for manufacturing a back contact battery, comprising:

Providing a silicon substrate;

Forming a first passivation layer and a first doped semiconductor layer sequentially stacked on a backlight surface of the silicon substrate along a thickness direction of the silicon substrate;

An insulating layer is formed on the backlight surface; and a passivation anti-reflection layer is formed on the light-facing surface of the silicon substrate; the material of the insulating layer is the same as that of the passivation anti-reflection layer; the insulating layer includes at least two layers, and the material of the insulating layer has passivation and anti-reflection functions;

A second passivation layer and a second doped semiconductor layer are formed and stacked in sequence on the backlight surface along the thickness direction of the silicon substrate; wherein the stacked second passivation layer and the second doped semiconductor layer cover partial areas of the stacked first passivation layer and the first doped semiconductor layer, and the conductivity types of the second doped semiconductor layer and the first doped semiconductor layer are opposite; the insulating layer is at least located between the second passivation layer and the first doped semiconductor layer, and is used to separate the second passivation layer and the first doped semiconductor layer; the insulating layer extends from the side walls of the stacked first passivation layer and the first doped semiconductor layer to the silicon substrate, contacts the silicon substrate, and extends in a direction away from the first doped semiconductor layer; the stacked second passivation layer and the second doped semiconductor layer at least cover the portion of the insulating layer that contacts the silicon substrate.

10. The method for manufacturing a back contact battery according to claim 9, characterized in that forming the first passivation layer and the first doped semiconductor layer in a stacked arrangement comprises:

sequentially forming a passivation material layer covering the backlight surface and an intrinsic semiconductor material layer located on the passivation material layer;

Performing diffusion treatment on the intrinsic semiconductor material layer so that the intrinsic semiconductor material layer forms a doped semiconductor material layer, and forming a doped glass layer on the doped semiconductor material layer;

Using a laser etching process, a portion of the doped glass layer located on the doped semiconductor material layer is removed; wherein the remaining portion of the doped glass layer forms a mask layer;

Under the masking effect of the mask layer, the portion of the doped semiconductor material layer exposed outside the mask layer and the portion of the passivation material layer exposed outside the mask layer are removed in sequence to form the first passivation layer and the first doped semiconductor layer which are stacked.

11. The method for manufacturing a back contact cell according to claim 10, characterized in that the thickness of the doped glass layer is 40 nm to 60 nm; and/or,

The diffusion time of the diffusion treatment is 60 minutes to 120 minutes, and the diffusion temperature is 800° C. to 900° C.

12. The method for manufacturing a back-contact battery according to claim 10, characterized in that after forming the first passivation layer and the first doped semiconductor layer in a stacked arrangement and before forming the insulating layer on the backlight surface, the method for manufacturing a back-contact battery further comprises:

Removing the wrap-around doped glass layer, the wrap-around doped semiconductor material layer and the wrap-around passivation material layer located on the light-facing surface and the side surface of the silicon substrate;

Under the masking action of the mask layer, a texturing process is performed on the light-facing surface of the silicon substrate so that the light-facing surface is a texturing surface;

The mask layer is removed.

13. The method for manufacturing a back contact battery according to any one of claims 9 to 12, characterized in that forming the first passivation layer and the first doped semiconductor layer in a stacked arrangement comprises:

sequentially forming a passivation material layer covering the backlight surface and a doped semiconductor material layer located on the passivation material layer;

The doped semiconductor material layer and the passivation material layer are patterned by laser etching process to form the first passivation layer and the first doped semiconductor layer which are stacked; wherein the first passivation layer is a tunneling passivation layer, and the first doped semiconductor layer is a doped polysilicon layer.