CN115831868B - Method for manufacturing semiconductor device - Google Patents
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- CN115831868B CN115831868B CN202310015417.4A CN202310015417A CN115831868B CN 115831868 B CN115831868 B CN 115831868B CN 202310015417 A CN202310015417 A CN 202310015417A CN 115831868 B CN115831868 B CN 115831868B
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000000758 substrate Substances 0.000 claims abstract description 103
- 238000005530 etching Methods 0.000 claims abstract description 26
- 238000004140 cleaning Methods 0.000 claims abstract description 18
- 239000000126 substance Substances 0.000 claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 4
- 239000012459 cleaning agent Substances 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 8
- 238000002360 preparation method Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 146
- 238000002955 isolation Methods 0.000 description 12
- 239000000463 material Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
The invention provides a preparation method of a semiconductor device, which comprises the steps of providing a substrate, wherein the substrate comprises a Core region and an IO region; etching to remove a part of the thickness of the substrate of the IO region so as to enable the surfaces of the substrate of the IO region and the Core region to have a height difference; forming a first oxide layer on the substrate of the IO region and the Core region; etching to remove the first oxide layer on the substrate of the Core region; and forming a second oxide layer on the substrate of the Core region by adopting a chemical cleaning process, wherein the surfaces of the first oxide layer on the IO region and the second oxide layer on the Core region are flush, and the thickness of the first oxide layer is larger than that of the second oxide layer. The invention can avoid the deformation and defect of the film layer caused by the height difference, thereby improving the yield of the device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor device.
Background
In the manufacturing process of a semiconductor device, a substrate is often divided into different regions, such as an IO region (input-output region) and a Core region (Core region), and the thicknesses of gate oxide layers required for the respective IO region and Core region are different. In the prior art, gate oxide layers with different thicknesses are generally formed on the surfaces of the substrate in the IO region and the Core region by using a mask process, and the gate oxide layers with different thicknesses can cause the surfaces of the IO region and the Core region to generate a height difference, and then in the subsequent preparation processes, such as the processes of a high-K dielectric layer, titanium nitride, amorphous silicon, nitride, oxide and the like, the film layer generated by stress in each process can deform due to the height difference, and the defect risk is associated, so that the product yield is affected.
Disclosure of Invention
The invention aims to provide a preparation method of a semiconductor device, which avoids film deformation and defects caused by height difference, thereby improving the yield of the device.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a Core region and an IO region;
etching to remove a part of the thickness of the substrate of the IO region so as to enable the surfaces of the substrate of the IO region and the Core region to have a height difference;
forming a first oxide layer on the substrate of the IO region and the Core region;
etching to remove the first oxide layer on the substrate of the Core region; the method comprises the steps of,
and forming a second oxide layer on the substrate of the Core region by adopting a chemical cleaning process, wherein the surfaces of the first oxide layer on the IO region and the second oxide layer on the Core region are flush, and the thickness of the first oxide layer is larger than that of the second oxide layer.
Optionally, before etching to remove a part of the thickness of the substrate in the IO region, a third oxide layer is formed on the surfaces of the substrate in the IO region and the Core region.
Optionally, the step of etching to remove a portion of the thickness of the substrate in the IO region includes:
forming a first patterned photoresist layer on the Core region substrate;
etching to remove a third oxide layer on the substrate of the IO region, and etching to remove a part of the substrate of the IO region; the method comprises the steps of,
and removing the first patterned photoresist layer and removing the third oxide layer on the Core region substrate.
Optionally, the thickness of the substrate of the IO region is 650-750 angstroms after etching and removing.
Optionally, an ISSG process is used to form the first oxide layer on the IO region and the Core region of the substrate.
Optionally, the thickness of the first oxide layer is 800-900 angstroms.
Optionally, the cleaning agent of the chemical cleaning process comprises ozone water.
Optionally, the thickness of the second oxide layer is 100-200 angstroms.
Optionally, the second oxide layer includes an o—h bond.
Optionally, after forming the second oxide layer on the Core region substrate using a chemical cleaning process, forming a high-K dielectric layer on the first oxide layer and the second oxide layer is further included.
In the method for manufacturing the semiconductor device, a substrate is provided, wherein the substrate comprises a Core region and an IO region; etching to remove the substrate of the IO region with partial thickness so as to enable the surface of the substrate of the IO region and the surface of the substrate of the Core region to have a height difference; forming a first oxide layer on the substrate of the IO region and the Core region; etching to remove the first oxide layer on the substrate in the Core region; and forming a second oxide layer on the substrate in the Core region by adopting a chemical cleaning process, wherein the surfaces of the first oxide layer on the IO region and the second oxide layer on the Core region are flush, and the thickness of the first oxide layer is larger than that of the second oxide layer. According to the invention, the thicknesses of the oxide layers on the surfaces of the substrates of the Core area and the IO area are required to be different, the height difference is formed on the surfaces of the substrates of the IO area and the Core area, and then the second oxide layer is formed on the substrate of the Core area by utilizing a chemical cleaning process, so that the thickness of the first oxide layer is larger than that of the second oxide layer, the first oxide layer on the IO area is flush with the surface of the second oxide layer on the Core area, the height difference between the surfaces of the first oxide layer and the second oxide layer is reduced, the difficulty of the subsequent preparation process is reduced, and the deformation and defects of the film layer caused by the height difference are avoided, thereby improving the yield of the device.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
Fig. 2 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention after a substrate is provided.
Fig. 3 is a schematic cross-sectional view of a semiconductor device after etching a substrate in an IO region according to an embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention after removing a first patterned photoresist layer.
Fig. 5 is a schematic cross-sectional view of a semiconductor device after forming a first oxide layer according to an embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention after etching to remove a first oxide layer in a Core region.
Fig. 7 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention after removing the second patterned photoresist layer.
Fig. 8 is a schematic cross-sectional view of a semiconductor device after forming a second oxide layer according to an embodiment of the present invention.
Fig. 9 is a schematic cross-sectional view of a semiconductor device after forming a high-K dielectric layer and a metal gate in accordance with an embodiment of the present invention.
Wherein, the reference numerals are as follows:
10-a substrate; 11-Core zone; a 12-IO region; a 20-trench isolation structure; 31-a third oxide layer; 32-a first oxide layer; 33-a second oxide layer; 41-a first patterned photoresist layer; 42-a second patterned photoresist layer; a 50-high-K dielectric layer; 60-metal gate; 70-interlayer dielectric layer.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to this embodiment. Referring to fig. 1, the present invention provides a method for manufacturing a semiconductor device, including:
step S1: providing a substrate, wherein the substrate comprises a Core region and an IO region;
step S2: etching to remove the substrate of the IO region with partial thickness so as to enable the surface of the substrate of the IO region and the surface of the substrate of the Core region to have a height difference;
step S3: forming a first oxide layer on the substrate of the IO region and the Core region;
step S4: etching to remove the first oxide layer on the substrate in the Core region;
step S5: and forming a second oxide layer on the substrate in the Core region by adopting a chemical cleaning process, wherein the first oxide layer on the IO region is flush with the surface of the second oxide layer on the Core region, and the thickness of the first oxide layer is larger than that of the second oxide layer.
Fig. 2 is a schematic cross-sectional view of a semiconductor device according to the present embodiment after a substrate is provided; fig. 3 is a schematic cross-sectional view of a semiconductor device according to the present embodiment after etching a substrate in an IO region; fig. 4 is a schematic cross-sectional view of the semiconductor device according to the present embodiment after the first patterned photoresist layer is removed; fig. 5 is a schematic cross-sectional view of a semiconductor device according to the present embodiment after a first oxide layer is formed; fig. 6 is a schematic cross-sectional view of the semiconductor device according to the present embodiment after etching to remove the first oxide layer in the Core region; fig. 7 is a schematic cross-sectional view of the semiconductor device according to the present embodiment after removing the second patterned photoresist layer; fig. 8 is a schematic cross-sectional view of a semiconductor device according to the present embodiment after forming a second oxide layer; fig. 9 is a schematic cross-sectional view of a semiconductor device according to the present embodiment after forming a high-K dielectric layer and a metal gate. The following describes the method for manufacturing the semiconductor device according to this embodiment in detail with reference to fig. 2 to 9.
Referring to fig. 2, step S1 is performed: the substrate 10 is provided, and the material of the substrate 10 includes one or more of silicon, germanium, gallium, nitrogen or carbon. A number of trench isolation structures 20 are formed in the substrate 10, the substrate 10 being divided into different regions by the trench isolation structures 20 such that the substrate 10 comprises a Core region 11 and an IO region 12. Since the Core region 11 and the IO region 12 are different in voltage withstand performance, the thicknesses of the gate oxide layers of the Core region 11 and the IO region 12 are different, and in general, the voltage withstand value of the Core region 11 is lower than that of the IO region 12.
Further, since the sacrificial oxide layer is formed on the surface of the substrate 10 in order to prevent contamination or damage to the surface of the substrate 10 during the formation of the trench isolation structure 20 or other previous processes, that is, the third oxide layer 31 is formed on the substrate 10 in the Core region 11 and the IO region 12, the third oxide layer 31 may also extend to cover the trench isolation structure 20, and the thickness of the third oxide layer 31 is not limited herein.
Referring to fig. 3, step S2 is performed: forming a first patterned photoresist layer 41 on the Core region 11 and the IO region 12, the first patterned photoresist layer 41 exposing the third oxide layer 31 on the IO region 12; further, the third oxide layer 31 on the IO region 12 is etched away by a dry etching process, and the substrate 10 of the IO region 12 having a partial thickness is etched away by a dry etching process continuously, so that the surfaces of the substrate 10 of the IO region 12 and the Core region 11 have a height difference. In the present embodiment, the thickness of the substrate 10 from which the IO region 12 is etched and removed may be 650 to 750 angstroms, but is not limited to this range, and is particularly related to the device withstand voltage.
Further, referring to fig. 4, the first patterned photoresist layer 41 is removed by an ashing process, and the third oxide layer 31 on the Core region 11 is etched by a wet etching process.
Referring to fig. 5, step S3 is performed: a first oxide layer 32 is formed on the substrate of the IO region 12 and the Core region 11 using an ISSG process (in situ vapor growth process), and the first oxide layer 32 also extends to cover the trench isolation structure 20. Because the principle of the ISSG process is that oxygen and hydrogen are introduced, an oxidation reaction is formed on the surface of the substrate 10 under a high-temperature environment to form a first oxide layer 32 with better quality, the material filled in the trench isolation structure 20 is different from the material of the substrate 10, the material filled in the trench isolation structure 20 generally comprises silicon oxide, and part of the material filled in the trench isolation structure 20 is oxidized in the process, so that the thickness of the first oxide layer 32 formed on the surface of the trench isolation structure 20 is smaller than the thickness of the first oxide layer 32 on the substrate of the IO region 12 and the Core region 11. In the present embodiment, the thickness of the first oxide layer 32 on the substrate of the IO region 12 and the Core region 11 may be 800 angstroms to 900 angstroms, but is not limited to this range, and is particularly related to the device withstand voltage; the thickness of the first oxide layer 32 on the surface of the trench isolation structure 20 is not limited, but after performing the ISSG process, the surface of the first oxide layer 32 on the surface of the trench isolation structure 20 is substantially flush with the surface of the first oxide layer 32 on the substrate of the IO region 12 (the thickness difference is small) because the surface of the substrate 10 of the IO region 12 and the Core region 11 has a height difference.
Referring to fig. 6, step S4 is performed: forming a second patterned photoresist layer 42 over the Core region 11 and the IO region 12, the second patterned photoresist layer 42 exposing the first oxide layer 32 over the Core region 11; further, the first oxide layer 32 on the Core region 11 is etched away using a dry etching process to reveal the surface of the substrate 10.
Further, referring to fig. 7, an ashing process is used to remove the second patterned photoresist layer 42.
Referring to fig. 8, step S5 is performed: a chemical cleaning process is used to form a second oxide layer 33 on the substrate 10 in the Core region 11, with the first oxide layer 32 on the io region 12 and the second oxide layer 33 on the Core region 11 being flush (substantially flush) in surface. The second oxide layer 33 of the target thickness is formed by controlling the cleaning time of the chemical cleaning process such that the surfaces of the first oxide layer 32 on the IO region 12 and the second oxide layer 33 on the Core region 11 are flush, and the thickness of the first oxide layer 32 on the IO region 12 is greater than the thickness of the second oxide layer 33 on the Core region 11. In this embodiment, the cleaning agent of the chemical cleaning process includes ozone water, the ozone water reacts with the substrate 10 of the Core region 11 to form the second oxide layer 33, the second oxide layer 33 formed by the chemical cleaning process is rich in O-H bonds (hydrogen bonds), the O-H bonds are beneficial to the deposition of the subsequent film layer, and the film layer can be tightly connected with the second oxide layer 33, so that the defect generation is reduced; the thickness of the second oxide layer 33 may be 100 to 200 angstroms, but is not limited to this range, and is specifically related to the device withstand voltage and the thickness of the first oxide layer 32 on the IO region 12. In this embodiment, since the thicknesses of the oxide layers on the surfaces of the substrate in the Core region and the IO region are different (the thickness of the first oxide layer on the IO region is different from the thickness of the second oxide layer on the Core region), by making the surfaces of the substrate in the IO region and the Core region have a height difference, and then forming the second oxide layer on the substrate in the Core region by using a chemical cleaning process, the thickness of the first oxide layer on the IO region is greater than the thickness of the second oxide layer on the Core region, and the surface of the first oxide layer on the IO region is flush with the surface of the second oxide layer on the Core region, so that the height difference between the surfaces of the first oxide layer and the second oxide layer is reduced, the difficulty of the subsequent preparation process is reduced, and the deformation and defects of the film layer caused by the height difference are avoided, thereby improving the yield of the device.
Further, referring to fig. 9, after forming the second oxide layer 33 on the substrate 10 in the Core region 11 by using a chemical cleaning process, a high K dielectric layer 50 is further formed on the first oxide layer 32 and the second oxide layer 33. Specifically, an interlayer dielectric layer 70 is formed on the IO region 12 and the Core region 11, and a plurality of openings (not labeled in the figure) are formed by etching the interlayer dielectric layer 70, wherein the plurality of openings respectively expose a first oxide layer 32 on the IO region 12 and a second oxide layer 33 on the Core region 11; furthermore, the high-K dielectric layer 50 is deposited on the inner wall (sidewall and bottom) of the opening, and since the Core region 11 is used as a Core region and is generally used for logic operation, the requirement on the structural connection characteristic of the Core region 11 is higher, so that the logic operation speed is faster, the second oxide layer 33 is rich in O-H bonds, the high-K dielectric layer 50 can be tightly connected with the second oxide layer 33, and the defect generation of the Core region 11 is reduced; and filling a metal material in the opening to form the metal gate 60.
In summary, in the method for manufacturing a semiconductor device provided by the present invention, a substrate is provided, the substrate including a Core region and an IO region; etching to remove the substrate of the IO region with partial thickness so as to enable the surface of the substrate of the IO region and the surface of the substrate of the Core region to have a height difference; forming a first oxide layer on the substrate of the IO region and the Core region; etching to remove the first oxide layer on the substrate in the Core region; and forming a second oxide layer on the substrate in the Core region by adopting a chemical cleaning process, wherein the surfaces of the first oxide layer on the IO region and the second oxide layer on the Core region are flush, and the thickness of the first oxide layer is larger than that of the second oxide layer. According to the invention, the thicknesses of the oxide layers on the surfaces of the substrates of the Core area and the IO area are required to be different, the height difference is formed on the surfaces of the substrates of the IO area and the Core area, and then the second oxide layer is formed on the substrate of the Core area by utilizing a chemical cleaning process, so that the thickness of the first oxide layer is larger than that of the second oxide layer, the first oxide layer on the IO area is flush with the surface of the second oxide layer on the Core area, the height difference between the surfaces of the first oxide layer and the second oxide layer is reduced, the difficulty of the subsequent preparation process is reduced, and the deformation and defects of the film layer caused by the height difference are avoided, thereby improving the yield of the device.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (8)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a Core region and an IO region;
etching to remove a part of the thickness of the substrate of the IO region so as to enable the surfaces of the substrate of the IO region and the Core region to have a height difference;
forming a first oxide layer on the substrate of the IO region and the Core region, wherein the surface of the first oxide layer on the IO region is higher than the surface of the substrate of the Core region;
etching to remove the first oxide layer on the substrate of the Core region;
forming a second oxide layer on the substrate of the Core region by adopting a chemical cleaning process, wherein the second oxide layer comprises O-H bonds, the surfaces of the first oxide layer on the IO region and the second oxide layer on the Core region are flush, and the thickness of the first oxide layer is larger than that of the second oxide layer; the method comprises the steps of,
and forming a high-K dielectric layer on the first oxide layer and the second oxide layer.
2. The method of manufacturing a semiconductor device according to claim 1, wherein a third oxide layer is formed on surfaces of the IO region and the Core region substrate before etching to remove a part of the thickness of the IO region substrate.
3. The method of manufacturing a semiconductor device according to claim 2, wherein the step of etching away the substrate of the IO region having a partial thickness comprises:
forming a first patterned photoresist layer on the Core region substrate;
etching to remove a third oxide layer on the substrate of the IO region, and etching to remove a part of the substrate of the IO region; the method comprises the steps of,
and removing the first patterned photoresist layer and removing the third oxide layer on the Core region substrate.
4. The method for manufacturing a semiconductor device according to claim 1 or 3, wherein a thickness of the substrate from which the IO region is etched is 650 to 750 angstroms.
5. The method of manufacturing a semiconductor device according to claim 1, wherein the first oxide layer is formed on the substrate of the IO region and the Core region using an ISSG process.
6. The method of manufacturing a semiconductor device according to claim 5, wherein a thickness of the first oxide layer is 800 angstroms to 900 angstroms.
7. The method of manufacturing a semiconductor device according to claim 1 or 5, wherein the cleaning agent of the chemical cleaning process includes ozone water.
8. The method of manufacturing a semiconductor device according to claim 7, wherein a thickness of the second oxide layer is 100 angstroms to 200 angstroms.
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