CN115831752A - Semiconductor device and preparation method thereof - Google Patents

Abstract

The present application provides a semiconductor device and a manufacturing method thereof, the device comprising: a second part of the substrate; a cavity layer located on one side of the second part of the substrate; a stack of nanosheets located on the side of the cavity layer away from the second part of the substrate layer; the nanosheet stack layer includes a stack of multiple nanosheets; the nanosheets are formed from a semiconductor material; the stack of nanosheets forms a plurality of conductive channels; wraparound gates around the nanosheet stack; source and drain The electrodes are located at both ends of the nanosheet stack; the material of the source and drain electrodes is a semiconductor material doped with conductive elements. Therefore, by setting the cavity layer in the present application, the influence of the parasitic channel effect at the bottom can be avoided, thereby reducing the influence of leakage current and gate capacitance, and further improving the electrical performance of the device. It can well solve the influence brought by the self-heating effect in the stacked nanosheets. The effect of leakage-induced barrier lowering is effectively reduced, and parameters such as subthreshold slope and on-off ratio are improved.

Description

A kind of semiconductor device and its preparation method

technical field

The present application relates to the field of semiconductor technology, in particular to a semiconductor device and a manufacturing method thereof.

Background technique

With the continuous shrinking of the transistor feature size, the device performance is improved through the continuous introduction of new materials, new processes and new structures, while reducing the impact of the short channel effect caused by the shrinking size. The structure of the device has changed from a two-dimensional planar CMOS (Complementary Metal Oxide Semiconductor) device to a three-dimensional FinFET (Fin Field-Effect Transistor, Fin Field-Effect Transistor) structure, and now the mainstream Nanowire /Nanosheet Nanowire/Nanosheet Gate-Round Transistor.

The gate-all-round transistor is considered to be one of the most promising next-generation devices under the 3nm technology node to replace FinFET devices and achieve mass production. The gate-all-around device effectively increases Weff (Effective gatewidth)/footprint (package size), improves the control ability of the gate to the channel, can effectively suppress the short channel effect, and improve the current driving ability of the device.

At present, the research progress of Nanosheet-GAAFET (Nanosheet-Gate-all-around Field-Effect Transistor, nanosheet-all-around gate field-effect transistor) has attracted extensive attention from academia and industry. Through continuous optimization of the process flow and key processes, the exploration of new structures based on this structure is also a popular research direction for new CMOS devices.

Nanosheet-GAAFET can improve the performance of the device by stacking the number of nanosheets. The novel device structure is well compatible with the current mainstream FinFET process. However, since NSFET (Nanosheet Field-Effect Transistor, Nanosheet Field Effect Transistor) and FinFET have unavoidable parasitic channels under their intrinsic channels, there are parasitic capacitances and leakage currents in the parasitic channels, resulting in poor electrical performance of the device. degradation, but also brings great challenges to the scaling of transistors. Since the parasitic channel of NSFET is wider, the effect of the parasitic channel on it is more significant. How to reduce the influence of the parasitic channel has become a problem that cannot be ignored.

Contents of the invention

In view of this, the purpose of the present application is to provide a method that can avoid the influence of the bottom parasitic channel effect, thereby reducing the influence of leakage current and gate capacitance, and can further increase the electrical performance of the device.

In order to achieve the above object, the application has the following technical solutions:

In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, including:

providing an initial substrate;

Injecting an inert gas into the initial substrate, annealing to form a cavity layer, so as to divide the initial substrate into a first part of the substrate and a second part of the substrate;

On the surface of the first part of the substrate opposite to the void layer and away from the void layer, epitaxially grow a superlattice stack; the superlattice stack is alternately stacked by first semiconductor layers and second semiconductor layers form;

Etching the superlattice stack to form a plurality of fins;

depositing a dummy gate on the fin;

Etching both ends of the fin to the surface of the initial substrate, and epitaxially growing source and drain at both ends of the fin after etching, the material of the source and drain is a semiconductor material doped with conductive elements;

removing the dummy gate, etching away the first semiconductor layer, and realizing the channel release of the nanosheets of the second semiconductor layer, and the stack formed by the nanosheets constitutes a plurality of conductive channels;

Forming a wrap-around gate that wraps around the stack of nanosheets;

Etching removes the first portion of the substrate.

In a possible implementation manner, the etching to remove the first part of the substrate includes:

Etching forms at least one etching via hole connected to the cavity layer, and etching and removing the first part of the substrate through the etching via hole.

In a possible implementation manner, the etching to remove the first part of the substrate includes:

The first portion of the substrate is etched away using wet etching.

In a possible implementation manner, after removing the first part of the substrate by etching, further include:

Filling the first part of the substrate and the cavity layer with a gas and/or liquid medium having a dielectric constant less than or equal to a preset threshold.

In a possible implementation manner, the etching the superlattice stack to form a plurality of fins includes:

A first sidewall is set on the superlattice stack; and the superlattice stack is etched using the first sidewall as a mask to form the plurality of fins.

In a second aspect, an embodiment of the present application provides a semiconductor device, including:

the second part of the substrate;

a cavity layer located on one side of the second portion of the substrate;

A nanosheet stack layer located on a side of the cavity layer away from the second part of the substrate; the nanosheet stack layer includes a stack formed by a plurality of nanosheets; the nanosheet is formed of a semiconductor material; the nanosheet The stack formed constitutes a plurality of conductive channels;

a wraparound gate surrounding the nanosheet stack;

The source and drain electrodes are located at both ends of the nanosheet stack layer; the material of the source and drain electrodes is a semiconductor material doped with conductive elements.

In a possible implementation manner, the method further includes: shallow trench isolation between the cavity layer and the surrounding gate.

In a possible implementation manner, it further includes: an isolation layer located on a side of the source and drain away from the cavity layer.

In a possible implementation manner, the method further includes: a second sidewall located between the isolation layer and the surrounding gate.

In a possible implementation manner, the type of the device includes: a positive channel nanosheet surrounding gate field effect transistor or a negative channel nanosheet surrounding gate field effect transistor.

Compared with the prior art, the present application has the following beneficial effects:

An embodiment of the present application provides a semiconductor device and a manufacturing method thereof, the device comprising: a second part of the substrate; a cavity layer located on the side of the second part of the substrate; a nanometer layer located on the side of the cavity layer away from the second part of the substrate The sheet stack layer; the nanosheet stack layer includes a stack formed by a plurality of nanosheets; the nanosheet is formed of a semiconductor material; the stack formed by the nanosheet forms a plurality of conductive channels; a wrap-around gate around the nanosheet stack layer; The source and drain electrodes are located at both ends of the nanosheet stack; the material of the source and drain electrodes is a semiconductor material doped with conductive elements. Therefore, by setting the cavity layer in the present application, the influence of the parasitic channel effect at the bottom can be avoided, thereby reducing the influence of leakage current and gate capacitance, and further improving the electrical performance of the device. It can well solve the influence brought by the self-heating effect in the stacked nanosheets. The effect of leakage-induced barrier lowering is effectively reduced, and parameters such as subthreshold slope and on-off ratio are improved.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are For some embodiments of the present application, those skilled in the art can also obtain other drawings based on these drawings without creative effort.

FIG. 1 shows a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

2-13 show cross-sectional views of various structures in the manufacturing process of a semiconductor device provided by the embodiment of the present application;

FIG. 14 shows a cross-sectional view of a semiconductor device provided by an embodiment of the present application;

FIG. 15 shows a top view of a semiconductor device provided by an embodiment of the present application.

Detailed ways

In order to make the above-mentioned purpose, features and advantages of the present application more obvious and understandable, the specific implementation manners of the present application will be described in detail below in conjunction with the accompanying drawings.

In the following description, a lot of specific details are set forth in order to fully understand the application, but the application can also be implemented in other ways different from those described here, and those skilled in the art can do it without violating the content of the application. By analogy, the present application is therefore not limited by the specific embodiments disclosed below.

As described in the background technology, as the feature size of transistors continues to shrink, device performance is improved by continuously introducing new materials, new processes and new structures, while reducing the impact of the short channel effect caused by size shrinking. The structure of the device has changed from a two-dimensional planar CMOS (Complementary Metal Oxide Semiconductor) device to a three-dimensional FinFET (Fin Field-Effect Transistor, Fin Field-Effect Transistor) structure, and now the mainstream Nanowire /Nanosheet nanowire/nanosheet gate-around transistor.

The gate-all-round transistor is considered to be one of the most promising next-generation devices under the 3nm technology node to replace FinFET devices and achieve mass production. The gate-all-around device effectively increases Weff (Effective gatewidth)/footprint (package size), improves the control ability of the gate to the channel, can effectively suppress the short channel effect, and improve the current driving ability of the device.

At present, the research progress of Nanosheet-GAAFET (Nanosheet-Gate-all-around Field-Effect Transistor, nanosheet-all-around gate field-effect transistor) has attracted extensive attention from academia and industry. Through continuous optimization of the process flow and key processes, the exploration of new structures based on this structure is also a popular research direction for new CMOS devices.

Nanosheet-GAAFET can improve the performance of the device by stacking the number of nanosheets. The novel device structure is well compatible with the current mainstream FinFET process. However, since NSFET (Nanosheet Field-Effect Transistor, Nanosheet Field Effect Transistor) and FinFET have unavoidable parasitic channels under their intrinsic channels, there are parasitic capacitances and leakage currents in the parasitic channels, resulting in poor electrical performance of the device. degradation, but also brings great challenges to the scaling of transistors. Since the parasitic channel of NSFET is wider, the effect of the parasitic channel on it is more significant. How to reduce the influence of the parasitic channel has become a problem that cannot be ignored.

In addition, how to effectively reduce the leakage-induced barrier lowering effect and improve parameters such as subthreshold slope and on-off ratio are also technical problems to be solved in this field.

In order to solve the above technical problems, an embodiment of the present application provides a semiconductor device and a manufacturing method thereof. The device includes: a second part of the substrate; a cavity layer located on one side of the second part of the substrate; A stack of nanosheets on one side of the substrate; the stack of nanosheets includes a stack of multiple nanosheets; the nanosheet is formed of a semiconductor material; the stack of nanosheets forms a plurality of conductive channels; surrounding the stack of nanosheets The surrounding gate; the source and drain are located at both ends of the nanosheet stack; the material of the source and drain is a semiconductor material doped with conductive elements. Therefore, by setting the cavity layer in the present application, the influence of the parasitic channel effect at the bottom can be avoided, thereby reducing the influence of leakage current and gate capacitance, and further improving the electrical performance of the device. It can well solve the influence brought by the self-heating effect in the stacked nanosheets. The effect of leakage-induced barrier lowering is effectively reduced, and parameters such as subthreshold slope and on-off ratio are improved.

Referring to Figure 1, it is a flow chart of a method for manufacturing a semiconductor device provided by the embodiment of the present application, including:

S101: providing an initial substrate.

In the embodiment of the present application, as shown in FIG. 2, the initial substrate 0 can be prepared first, and the initial substrate 0 can be a semiconductor substrate, such as a Si substrate, a Ge substrate, a SiGe substrate, an SOI (insulator Silicon On Insulator) or GOI (Germanium On Insulator, Germanium On Insulator), etc. In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP or SiC, etc., or a stacked structure, such as Si/SiGe, etc., or other Epitaxial structure, such as SGOI (silicon germanium on insulator), etc. In this embodiment, the initial substrate 0 is a bulk silicon substrate.

Specifically, the initial substrate 0 is a part of a semiconductor wafer suitable for forming one or more semiconductor devices. When a bulk silicon substrate is used, a highly doped well is formed in the bulk silicon substrate by implanting impurities, diffusing, and annealing area to achieve the desired well depth. Among them, for P (positive, positive) type FET, the above-mentioned highly doped well region is an N well, and the implanted impurities are n-type impurity ions, such as phosphorus (P) ions; for N (negative, negative) type FET, the above-mentioned high The doped well region is a P well, and the implanted impurities are p-type impurity ions, such as boron (B) ions.

S102: Injecting an inert gas into the initial substrate, and annealing to form a cavity layer, so as to divide the initial substrate into a first partial substrate and a second partial substrate.

In the embodiment of the present application, as shown in FIG. 3, an inert gas, such as ammonia, can be injected into the initial substrate, and annealed in a high-temperature inert gas environment to form a cavity layer 1, so as to divide the initial substrate into the first part Substrate 0' and second part substrate 0".

A silicon dioxide layer 11 is grown on the surface of the first part of the substrate 0'.

S103: Epitaxially grow a superlattice stack on the surface of the first part of the substrate opposite to the void layer and away from the void layer; the superlattice stack consists of a first semiconductor layer and a second semiconductor layer Alternate layers are formed.

In the embodiment of the present application, as shown in FIG. 4 , the silicon dioxide (SiO2) on the surface of the first part of the substrate 0' is removed, and multiple periods of the first semiconductor layer 51 are epitaxially grown on the first part of the substrate 0'. The superlattice structure of the second semiconductor layer 52 is laminated; the thickness of the first semiconductor layer 51 in the superlattice structure can be set to 3-100nm, and the thickness of the second semiconductor layer 52 can be set to 1-50nm, and finally produced The thickness of the nanosheet will directly determine the height and electrostatic properties of the nanosheet channel.

Wherein, the above-mentioned first semiconductor layer 51/second semiconductor layer 52 superlattice can be Si/SiGe stacked layer, SiGe/Si stacked layer, SiGe/Ge stacked layer, Ge/SiGe stacked layer, Si/Ge stacked layer or Ge /Si stack.

S104: Etching the superlattice stack to form a plurality of fins.

In the embodiment of the present application, as shown in FIG. 5 , in a possible implementation manner, first sidewalls 61 may be provided on the superlattice stack; The lattice is stacked to form multiple fins.

Specifically, a nanoscale first sidewall 61 device can be formed using a self-aligned sidewall transfer (SIT, Self aligned sidewall transfer) process, and the material of the first sidewall 61 can be silicon nitride (SiNX). The specific formation process To: cover a layer of sacrificial layer 62 on the superlattice stack, the sacrificial layer can specifically be polycrystalline silicon (PolySi, p-si) or amorphous silicon (a-si), etch away part of the sacrificial layer 62, deposit nitride Silicon (SiNx) layer, and then use anisotropic etching to etch away the remaining sacrificial layer 62, so that it only remains on the superlattice stack with multiple periodic silicon nitride (SiNx) first sidewalls (spacers) ) 61, the silicon nitride (SiNx) first sidewall 61 plays the role of a hard mask (Hard Mask) in photolithography.

As shown in FIG. 6 , the epitaxially grown superlattice stack can be formed into a plurality of periodically distributed fins through an etching process.

Specifically, etching is performed using the first sidewall 61 as a mask to form fins with a superlattice stack structure. The upper part of the fin is the conductive channel region formed by the superlattice stack, and the lower part is the first part of the substrate 0', forming the fin as shown in Figure 6.

The fin includes not only a superlattice stack structure, but also a single crystal silicon structure that penetrates deep into the substrate. The etching process may be a dry etching process, and in one embodiment, reactive ion etching (Reactive ion etching, RIE) may be used. The fins will be used to form horizontal nanosheets of one or more n-FETs and/or p-FETs.

It should be noted that although FIG. 6 shows one fin, it should be understood that any suitable number and shape of fins can be used in the embodiments of the present application. The height of the fin is about 10nm-400nm, and the width is about 1-100nm.

As shown in FIG. 7 , the first sidewall 61 is removed by etching, and then a shallow trench isolation (shallow trench isolation, STI) region 7 may be formed between two adjacent fins. First, the dielectric insulating material is deposited, then planarized, for example, by CMP (chemical mechanical polish, chemical mechanical polishing) process, and then the dielectric insulating material is selectively etched back to expose the three-dimensional fin structure, thereby adjacent to the fin sheet to form the shallow trench isolation region 7 .

The upper surface of the shallow trench isolation region 7 is generally flush with the interface between the superlattice stack structure in the fin and the single crystal silicon substrate, and may also be higher or lower than the interface level. The shallow trench isolation region 7 can be formed of suitable dielectric materials, such as silicon dioxide (SiO2), silicon nitride (SiNx) and the like. The function of the shallow trench isolation region 7 is to separate transistors on adjacent fins. The shallow trench isolation region 7 exposes the bottommost first semiconductor layer 51 of the superlattice stack.

S105: Depositing a dummy gate on the fin.

In the embodiment of the present application, as shown in FIG. 8 , dummy gates 8 can be formed on the exposed fins in the direction perpendicular to the fin lines (ie, the BB' direction). Thermal oxidation, chemical vapor deposition, Dummy gates 8 are formed by processes such as sputtering. The dummy gate 8 spans the superlattice stack on the upper part of the fin, and a plurality of dummy gates 8 are periodically distributed along the fin line direction.

The material used for the dummy gate 8 may be polysilicon (PolySi, p-si) or amorphous silicon (a-si).

S106: Etching both ends of the fin to the surface of the initial substrate, and epitaxially growing source and drain at both ends of the fin after etching, the material of the source and drain is a semiconductor material doped with conductive elements.

In the embodiment of the present application, as shown in FIG. 9 , silicon nitride or doped silicon oxide material may be deposited on both sides of each dummy gate 8 and etched to form the second sidewall 9 .

Then, as shown in FIG. 10, the two ends of the fin can be etched to the initial substrate surface, and the source and drain electrodes 41/42 are epitaxially grown at both ends of the fin after etching, and the material of the source and drain electrodes 41/42 is doped and conductive. elements of semiconductor materials.

Specifically, semiconductor materials such as SiGe or Si can be deposited and heavily doped. For P-type semiconductor devices, the doping element is B or BF2, and for N-type semiconductor devices, the doping element is P/As to form heavy doping. Source and drain 41/42. Low-temperature rapid thermal annealing is used for the source and drain electrodes 41/42 to activate the impurities.

S107: removing the dummy gate, etching away the first semiconductor layer, and realizing channel release of the nanosheets of the second semiconductor layer, and the stack formed by the nanosheets constitutes a plurality of conductive channels.

In the embodiment of the present application, as shown in FIG. 11 , an isolation layer 10 may be deposited on the source and drain electrodes 41 / 42 , and the material of the isolation layer 10 may be an oxide such as silicon dioxide.

Then, through a selective etching or etching process, the aforementioned polysilicon (PolySi, p-si) or amorphous

The dummy gate 8 formed of silicon (a-si) is etched or etched away, that is, the dummy gate 8 is removed.

Subsequently, as shown in FIG. 12 , the first semiconductor layer 51 in the superlattice stack is selectively etched to release the channel of the nanosheet 2 (nanosheet). Etching/corroding the conductive channel region exposed by the fins to remove each layer of the first semiconductor layer 51, the first semiconductor layer 51 is a sacrificial layer, and releasing the nanosheets 2 formed by the second semiconductor layer.

The width range of the nanosheets 2 is 1-100nm, the thickness range is 1-50nm, and the interval between the nanosheets 2 is 3-100nm.

In one embodiment, for both P-type and N-type FETs, the sacrificial layers are both SiGe layers, and the SiGe layer is selectively removed while the Si layer is retained to form a Si horizontally stacked nanosheet stack device. An etchant that selectively etches SiGe at a faster rate relative to Si may be used in the selective removal process. In one embodiment, the conventional wet process is used to isotropically etch the sacrificial layer to release the nanosheet channel, thereby forming the nanosheet conductive channel.

In another embodiment, for P-type and N-type FETs, channel release is performed separately.

For a P-type FET, the sacrificial layer is a Si layer, the Si layer is selectively removed, and the SiGe layer is retained to form a SiGe horizontally stacked nanosheet stack device. An etchant that selectively etches Si at a faster rate relative to SiGe may be used in the selective removal process. In one embodiment, the conventional wet process is used to isotropically etch the sacrificial layer to release the nanosheet channel, thereby forming the nanosheet conductive channel.

For N-type FETs, the sacrificial layer is a SiGe layer, the SiGe layer is selectively removed, and the Si layer is retained to form a Si horizontally stacked nanosheet stack device. An etchant that selectively etches SiGe at a faster rate relative to Si may be used in the selective removal process. In one embodiment, the conventional wet process is used to isotropically etch the sacrificial layer to release the nanosheet channel, thereby forming the nanosheet conductive channel. The second semiconductor nanosheets 2 are laminated to form a stacked layer of nanosheets.

Next, as shown in FIG. 12 , a high-K dielectric layer 12 is deposited such that the high-K dielectric layer 12 surrounds the surface of the nanosheet stack and covers the surface of the second sidewall 9 . The high-k dielectric layer 12 may have a dielectric constant higher than about 6.0, and the material of the high-k dielectric layer 12 may be one of HfO2, HfSiOx, HfON, HfSiON, HfAlOx, HfLaOx, Al2O3, ZrO2, ZrSiOx, Ta2O5 or La2O3 one or a combination of several.

S108 : forming a wrap-around gate to wrap around the nanosheet stack.

In the embodiment of the present application, as shown in FIG. 13 , the metal gate 3 is deposited in the space formed by the dummy gate 8 and outside the high-K dielectric layer 12 to form a multi-layer high-K/metal gate structure.

The metal gate 3 includes a multilayer structure of a covering layer, a barrier layer, a work function layer, and a filling layer. Film structures with different effective work functions can be formed by selective photolithography and etching to adjust the device threshold. Generally, the metal gate 3 is formed by chemical vapor deposition, physical vapor deposition and other processes.

Metal gate 3 materials are TaC, TaN, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAl, TiAlC, TiAlN, PtSix, Ni3Si, Pt, Ru, Ir , Mo, Ti, Al, W, Co, Cr, Au, Cu, Ag, HfRu or RuOx one or a combination of several.

As shown in FIG. 13 , the metal gate 3 fills the space after the dummy gate 8 is removed. Afterwards, perform chemical mechanical polishing on the structure of the high-K dielectric layer 12 and the metal gate 3 to planarize them, and remove excess high-K dielectric layer 12 and metal gate 3 materials exposed on the surface of the dielectric layer outside the space of the dummy gate 8 . Wherein, the high-K dielectric layer 12 and the metal gate 3 fill the space of the original first semiconductor layer 51 to form a ring gate structure, that is, a surrounding gate, which surrounds the nanosheet 2 .

S109: Etching and removing the first part of the substrate.

In the embodiment of the present application, see FIG. 15 , which is a top view of a semiconductor device provided in the embodiment of the present application, including a device region, a wet-etched Si substrate region, an etched via hole, and an Si substrate region.

A-A' is the direction along the fin line and the center line of the fin, and the line BB' is the direction perpendicular to the fin line and the center line of the fin. Figures 2-14 are based on A-A' and BB' Schematic cross-section of two lines.

Referring to FIG. 14 , at least one etching via hole connected to the void layer may be formed by etching, and the first part of the substrate is etched and removed through the etching via hole. Optionally, the first part of the substrate may be removed by wet etching.

For example, wet etching can be used to selectively remove the bulk silicon material, that is, the first part of the substrate, by adjusting the etching selectivity ratio of the Si substrate to SiGe and SiO2. That is, by increasing the etching layout, etching via holes from top to bottom are formed, and then wet etching is used to selectively remove the sub-Fin parasitic channel and the bulk silicon material under the STI.

In the embodiment of the present application, by adding a SON (silicon on nothing) substrate structure, the speed of selective removal by wet etching can be accelerated. By controlling the time and rate of wet etching, the thickness of bulk silicon material removed can be controlled.

Optionally, after etching and removing the first part of the substrate, further comprising:

Filling the first part of the substrate and the void layer with a gas and/or liquid medium with a dielectric constant less than or equal to a preset threshold can well solve the impact of the self-heating effect in the stacked nanosheets.

The embodiment of the present application combines the conventional Nanasheet-GAAFET preparation method on the SON substrate to reduce the influence of the parasitic channel effect at the bottom by forming the SON substrate structure, and can increase the electrical performance of the device.

The present application provides a method for manufacturing a semiconductor device. The device prepared by the method includes: a second part of the substrate; a cavity layer on the side of the second part of the substrate; Nanosheet stack; the nanosheet stack includes a stack of nanosheets; the nanosheets are formed from a semiconductor material; the stack of nanosheets forms a plurality of conductive channels; a wraparound gate around the nanosheet stack ; The source and drain electrodes are located at both ends of the nanosheet stack; the material of the source and drain electrodes is a semiconductor material doped with conductive elements. Therefore, by setting the cavity layer in the present application, the influence of the parasitic channel effect at the bottom can be avoided, thereby reducing the influence of leakage current and gate capacitance, and further improving the electrical performance of the device. It can well solve the influence brought by the self-heating effect in the stacked nanosheets. The effect of leakage-induced barrier lowering is effectively reduced, and parameters such as subthreshold slope and on-off ratio are improved.

Exemplary device

Referring to FIG. 14, it is a schematic diagram of a semiconductor device provided by the embodiment of the present application, including:

Second part substrate 0";

A cavity layer 1 located on one side of the second part of the substrate 0";

The nanosheet stack layer located on the side of the hollow layer 1 away from the second part of the substrate 0"; the nanosheet stack layer includes a stack formed by a plurality of nanosheets 2; the nanosheet 2 is formed of a semiconductor material ; The stack formed by the nanosheet 2 constitutes a plurality of conductive channels;

Surrounding the surrounding grid 3 surrounding the stacked layer of the nanosheet 2;

The source and drain electrodes 41/42 are located at both ends of the nanosheet stack; the material of the source and drain electrodes 41/42 is a semiconductor material doped with conductive elements.

In a possible implementation manner, it further includes: a shallow trench isolation 7 located between the cavity layer 1 and the surrounding gate 3 .

In a possible implementation manner, it further includes: an isolation layer 10 located on a side of the source and drain electrodes 41 / 42 away from the cavity layer 1 .

In a possible implementation manner, it further includes: a second spacer 9 located between the isolation layer 10 and the surrounding gate 3 .

In a possible implementation manner, the type of the device includes: a positive channel nanosheet surrounding gate field effect transistor or a negative channel nanosheet surrounding gate field effect transistor.

An embodiment of the present application provides a semiconductor device, the device comprising: a second part of the substrate; a cavity layer located on one side of the second part of the substrate; a nanosheet stack layer located on the side of the cavity layer away from the second part of the substrate; The stack of nanosheets includes a stack of multiple nanosheets; the nanosheets are formed of semiconductor materials; the stack of nanosheets forms a plurality of conductive channels; the surrounding gate around the stack of nanosheets; the source and drain, Located at both ends of the nanosheet stack; the source and drain materials are semiconductor materials doped with conductive elements. Therefore, by setting the cavity layer in the present application, the influence of the parasitic channel effect at the bottom can be avoided, thereby reducing the influence of leakage current and gate capacitance, and further improving the electrical performance of the device. It can well solve the influence brought by the self-heating effect in the stacked nanosheets. The effect of leakage-induced barrier lowering is effectively reduced, and parameters such as subthreshold slope and on-off ratio are improved.

Each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, as for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for relevant parts, please refer to part of the description of the method embodiment.

The above descriptions are only the preferred embodiments of the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any person familiar with the art, without departing from the scope of the technical solution of the application, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the application, or to modify the equivalent of equivalent changes Example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application that do not deviate from the content of the technical solution of the present application still fall within the protection scope of the technical solution of the present application.

Claims (10)

1. A method for preparing a semiconductor device, comprising: providing an initial substrate; Injecting an inert gas into the initial substrate, annealing to form a cavity layer, so as to divide the initial substrate into a first part of the substrate and a second part of the substrate; On the surface of the first part of the substrate opposite to the void layer and away from the void layer, epitaxially grow a superlattice stack; the superlattice stack is alternately stacked by first semiconductor layers and second semiconductor layers form; Etching the superlattice stack to form a plurality of fins; depositing a dummy gate on the fin; Etching both ends of the fin to the surface of the initial substrate, and epitaxially growing source and drain at both ends of the fin after etching, the material of the source and drain is a semiconductor material doped with conductive elements; removing the dummy gate, etching away the first semiconductor layer, and realizing the channel release of the nanosheets of the second semiconductor layer, and the stack formed by the nanosheets constitutes a plurality of conductive channels; Forming a wrap-around gate that wraps around the stack of nanosheets; Etching removes the first portion of the substrate. 2. The method according to claim 1, wherein the etching to remove the first part of the substrate comprises: Etching forms at least one etching via hole connected to the cavity layer, and etching and removing the first part of the substrate through the etching via hole. 3. The method according to claim 2, wherein the etching to remove the first part of the substrate comprises: The first portion of the substrate is etched away using wet etching. 4. The method according to claim 1, further comprising: after etching and removing the first part of the substrate: Filling the first part of the substrate and the cavity layer with a gas and/or liquid medium having a dielectric constant less than or equal to a preset threshold. 5. The method according to claim 1, wherein said etching said superlattice stack to form a plurality of fins comprises: A first sidewall is set on the superlattice stack; and the superlattice stack is etched using the first sidewall as a mask to form the plurality of fins. 6. A semiconductor device, characterized in that, comprising: the second part of the substrate; a cavity layer located on one side of the second portion of the substrate; A nanosheet stack layer located on a side of the cavity layer away from the second part of the substrate; the nanosheet stack layer includes a stack formed by a plurality of nanosheets; the nanosheet is formed of a semiconductor material; the nanosheet The stack formed constitutes a plurality of conductive channels; a wraparound gate surrounding the nanosheet stack; The source and drain electrodes are located at both ends of the nanosheet stack layer; the material of the source and drain electrodes is a semiconductor material doped with conductive elements. 7 . The device according to claim 6 , further comprising: shallow trench isolation between the cavity layer and the surrounding gate. 8. The device according to claim 6, further comprising: an isolation layer located on a side of the source and drain away from the cavity layer. 9. The device according to claim 8, further comprising: a second spacer located between the isolation layer and the surrounding gate. 10 . The device according to claim 6 , wherein the type of the device comprises: a positive channel nanosheet surrounding gate field effect transistor or a negative channel nanosheet surrounding gate field effect transistor. 11 .

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