CN115831710A - Method for reducing silicon substrate defects to suppress warping of silicon-based gallium nitride epitaxial wafer - Google Patents

Abstract

The invention discloses a method for reducing defects of a silicon substrate to inhibit warping of a silicon-based gallium nitride epitaxial wafer, which comprises the following steps: s1, preparing an 8-inch heavily-doped borosilicate single crystal rod by adopting a Czochralski method; s2, sequentially carrying out line cutting, chamfering, thinning, polishing and cleaning on the monocrystalline rod to obtain a polished wafer; s3, carrying out rapid heat treatment on the polished wafer to obtain an annealed polished wafer; s4, detecting and comparing Oxygen Induced Stacking Faults (OISF) on the surfaces and the sections of the annealed polishing sheets and the unannealed polishing sheets; s5, growing GaN epitaxial layers on the surfaces of the annealed polished wafer and the non-annealed polished wafer, and comparing and analyzing the warping of the epitaxial wafers to obtain corresponding experimental results; and S6, comparing and analyzing the surface appearances of the GaN epitaxial layers grown on the surfaces of the annealed polishing piece and the unannealed polishing piece in the S5 to obtain corresponding experimental results. According to the method, the 8-inch silicon substrate is subjected to rapid heating and cooling treatment in the argon atmosphere, OISF in the silicon substrate is eliminated, and the consistency of the silicon substrate is improved.

Description

Method for reducing silicon substrate defects to suppress warping of silicon-based gallium nitride epitaxial wafer

technical field

The invention relates to the technical field of semiconductors, in particular to a method for reducing oxygen-induced stacking faults (OISF) in silicon substrates by performing rapid thermal treatment (RTP) on 8-inch silicon (Si) polished wafer substrates, thereby reducing silicon-based Gallium Nitride (GaN) Warpage (BOW) Method.

Background technique

GaN-on-silicon power devices have a higher breakdown voltage, higher power density and higher energy conversion efficiency than silicon power devices, and the market size in the field of PD fast charging is growing rapidly. Shows growing application prospects.

The specifications of GaN epitaxial materials grown on silicon substrates are the key to determining the performance of power devices. Compared with 6-inch products, 8-inch epitaxial products will be the mainstream products in the future because they can reduce device costs by 30-40%. However, the 8-inch epitaxial material has a large warpage and is prone to surface cracks, resulting in a low device manufacturing yield, which seriously hinders the reduction of device cost.

The warping and surface cracking of GaN-on-Si epitaxial wafers are mainly caused by lattice mismatch and thermal mismatch between Si and GaN. In order to suppress the warping of the epitaxial wafer, it is necessary to increase the hardness of the silicon substrate. The method of doping a large amount of boron (B) in the silicon substrate is generally used in the industry to increase the hardness of the silicon substrate. In the boron-doped silicon single crystal, due to Boron atoms can promote the precipitation of native oxygen, that is, the formation of silicon-oxygen compounds (SiO _x ), so that oxygen-induced stacking faults (OISF) are generated according to the following mechanism: oxygen is the most important unintentional doping in Czochralski silicon single crystals. The impurity is introduced by the quartz crucible during the crystal growth process. The oxygen atoms will react with the silicon atoms during the crystal cooling process to form SiO _x . The volume of SiO _x is larger than that of silicon atoms, which will make the adjacent SiO _x Silicon atoms lose their positions and become interstitial silicon, and a large amount of interstitial silicon gathers in the silicon substrate to form OISF. Since the formation of OISF in heavily doped boron-silicon single crystal is inevitable, in order to ensure the uniformity of the substrate, the industry uses the entire OISF single crystal as the substrate of silicon-based gallium nitride. However, due to the difference in heat dissipation rate (thermal history) between the center and edge of the single crystal, the radial distribution of OISF on the silicon substrate is not uniform, resulting in inconsistent scales of thermal expansion and contraction of various parts of the substrate during the epitaxial process. Cracks occur. In addition, the presence of OISF reduces the hardness of the silicon substrate, leading to greater warping of the epiwafer. Cracks and warpage on the surface of the epitaxial wafer will lead to a significant drop in the yield of the device manufacturing process, thereby increasing the cost of the device.

Contents of the invention

The invention adopts a method for reducing silicon substrate defects to suppress warping of silicon-based gallium nitride epitaxial wafers. The principle is: on the one hand, during the heating process of the RTP process, a large amount of OISF formed by the accumulation of interstitial silicon diffuses to the surface of the silicon substrate, so that the OISF in the silicon wafer is ablated; on the other hand, during the thermal process of the RTP process, the silicon A large number of vacancies will be generated inside the substrate, and some of the vacancies will combine with the interstitial silicon that constitutes the OISF to ablate. Due to OISF ablation, the RTP-treated silicon substrate is harder, which can effectively reduce the warpage of the epitaxial wafer. In addition, after OISF ablation, there is no OISF in the center and edge of the silicon substrate, and the radial consistency is significantly enhanced. The expansion and contraction of the center and edge tend to be the same during the thermal process, avoiding cracks on the surface of the epitaxial wafer.

A method for reducing silicon substrate defects to suppress warpage of silicon-based gallium nitride epitaxial wafers, characterized in that it comprises the following steps:

S1. Prepare 8-inch heavily doped borosilicate single crystal rod by Czochralski method;

S2. Carrying out wire cutting, chamfering, thinning, polishing and cleaning of the single crystal rod in sequence to obtain a polished sheet;

S3, performing rapid heat treatment on the polished sheet to obtain an annealed polished sheet;

S4, detect the OISF of the surface and cross section of the annealed polished sheet and the non-annealed polished sheet, and compare;

S5. GaN epitaxial layer was grown on the surface of the annealed polished wafer and the non-annealed polished wafer, and the warpage of the epitaxial wafer was compared and analyzed, and the corresponding experimental results were obtained;

S6. Comparing and analyzing the surface morphology of the GaN epitaxial layer grown on the surface of the annealed polished wafer and the non-annealed polished wafer in S5, and obtaining corresponding experimental results.

Preferably, the OISF of the surface and cross section of the silicon substrate after heat treatment is compared with that of the untreated silicon substrate, so as to confirm the effect of heat treatment on eliminating OISF in the silicon substrate.

Preferably, the gallium nitride epitaxial layer is grown on the surface of the heat-treated silicon substrate and the untreated silicon substrate, and the warpage and surface morphology of the epitaxial wafer are compared to confirm the warpage and surface morphology of the epitaxial wafer on different substrates. influence of appearance.

Preferably, in S1, silicon block and boron particles are used as raw materials to pull an 8-inch silicon single crystal at a pulling speed of 35-50 mm h ^-1 .

Preferably, in the S3, the polishing sheet is heated to 1200-1300°C, kept at a constant temperature for 5-30 seconds and then cooled down, the argon flow rate is maintained at 10-50 slm throughout the process, and the heating rate and cooling rate are both 30-70°C/s.

Compared with the prior art, the beneficial effects of the present invention are: compared with the existing 8-inch substrate products, the present invention has no significant increase in cost, OISF ablation on the surface and inside of the substrate, increased hardness of the substrate, and radial consistency enhanced.

With the annealed and polished wafer prepared by the invention as the substrate, the prepared epitaxial wafer has no cracks on the surface, which improves the yield rate of the epitaxy process. With the prepared annealed polished wafer of the present invention as the substrate, the warpage (BOW) of the prepared epitaxial wafer is controlled at about 40 μm, which is lower than that of the epitaxial wafer (about 80 μm) prepared with the non-annealed polished wafer as the substrate, improving The serious warpage problem of the 8-inch silicon-based GaN epitaxial wafer was solved, which is conducive to improving the yield rate of the device manufacturing process.

Description of drawings

Fig. 1 is the experimental result table of embodiment one.

Fig. 2 is the experimental result table of embodiment two.

Detailed ways

The following clearly and completely describes the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Embodiment one:

A method for reducing silicon substrate defects to suppress warping of silicon-based gallium nitride epitaxial wafers, comprising the following steps:

S1. Using silicon blocks and boron particles as raw materials, pull down an 8-inch silicon single crystal in a thermal field, and control the pulling speed at 45-50mmh ^-1 . The content is 14-22ppma, the resistivity is 0.005-0.01Ω·cm,

S2. Carrying out wire cutting, chamfering, thinning, polishing and cleaning of the single crystal rod in sequence to obtain a polished sheet with a thickness of 1130-1170 μm;

S3. Perform rapid heat treatment with BEST/Mattson Helios C200 annealing furnace to obtain annealed polished sheet. The process is as follows: argon gas is introduced into the chamber, the flow rate of argon gas is 30slm, and the temperature of the chamber is raised to 1250°C, and the heating rate is 50°C. /s, keep the temperature for 5 seconds and then cool down, the cooling rate is 50°C/s;

S4. Thermally oxidize the polished wafer in S2 and the annealed polished wafer in S3 at 1150°C for 2 hours, then corrode, and observe and compare the surface and cross-section with a microscope. The results show that the surface of the silicon wafer after RTP and There is no abnormality in the cross section, indicating that the rapid thermal treatment process in S3 ablated the OISF in the silicon substrate;

S5. GaN epitaxial layer was grown on the surface of the polished sheet in S2 and the annealed polished sheet in S3, and the warpage of the epitaxial layer was measured. The results showed that the warpage of the GaN epitaxial layer on the surface of the polished sheet was 80 μm, and the warpage of the GaN epitaxial layer on the surface of the annealed polished sheet It is 40um, indicating that the rapid heat treatment process in S3 suppresses the warping of GaN epitaxial wafers;

S6. Use a microscope to detect the surface morphology of the GaN epitaxial layer grown on the surface of the annealed polished sheet and the non-annealed polished sheet in S5. The results show that there are cracks on the surface of the non-annealed polished sheet and no cracks on the surface of the annealed polished sheet, indicating that in S3 The rapid thermal treatment process helps to avoid cracks on the surface of GaN-on-Si.

This example shows a method for reducing the defects of the silicon substrate and suppressing the warpage of the silicon-based GaN epitaxial wafer by performing RTP heat treatment on the 8-inch silicon substrate. Silicon single crystal polished wafer, the experimental equipment is BEST/Mattson Helios C200 annealing furnace, through heat treatment, the OISF in the silicon substrate is ablated, the warping of the silicon-based gallium nitride epitaxial wafer is suppressed, and surface cracks are avoided.

Embodiment two:

The difference from Embodiment 1 is that:

1. In the process of pulling silicon single crystal, the pulling speed of this embodiment is 35-40mm h ^-1 ;

2. Since OISF is more likely to be generated at a low pulling speed, the OISF density of the polished silicon substrate in this embodiment is higher.

A method for reducing silicon substrate defects to suppress warping of silicon-based gallium nitride epitaxial wafers by performing RTP heat treatment on an 8-inch silicon substrate, comprising the following steps:

S1. Using silicon blocks and boron particles as raw materials, pull down an 8-inch silicon single crystal in a thermal field, and control the pulling speed at 35-40mmh ^-1 . The content is 14-22ppma, the resistivity is 0.005-0.01Ω·cm,

S2. Carrying out wire cutting, chamfering, thinning, polishing and cleaning of the single crystal rod in sequence to obtain a polished sheet with a thickness of 1130-1170 μm;

S3. Perform rapid heat treatment with BEST/Mattson Helios C200 annealing furnace to obtain annealed polished sheet. The process is as follows: argon gas is introduced into the chamber, the flow rate of argon gas is 30slm, and the temperature of the chamber is raised to 1250°C, and the heating rate is 50°C. /s, keep the temperature for 5 seconds and then cool down, the cooling rate is 50°C/s;

S4. Thermally oxidize the polished wafer in S2 and the annealed polished wafer in S3 at 1150°C for 2 hours, then corrode, and observe and compare the surface and cross-section with a microscope. The results show that the surface of the silicon wafer after RTP and There is no abnormality in the cross-section, indicating that the rapid heat treatment process in S3 ablated the OISF in the silicon substrate when the silicon single crystal pulling speed was low and the OISF density was high;

S5. GaN epitaxial layer was grown on the surface of the polished sheet in S2 and the annealed polished sheet in S3, and the warpage of the epitaxial layer was measured. The results showed that the warpage of the GaN epitaxial layer on the surface of the polished sheet was 80 μm, and the warpage of the GaN epitaxial layer on the surface of the annealed polished sheet It is 40um, indicating that the rapid heat treatment process in S3 suppresses the warping of GaN epitaxial wafers;

S6. Use a microscope to detect the surface morphology of the GaN epitaxial layer grown on the surface of the annealed polished sheet and the non-annealed polished sheet in S5. The results show that there are cracks on the surface of the non-annealed polished sheet and no cracks on the surface of the annealed polished sheet, indicating that in S3 The rapid thermal treatment process helps to avoid cracks on the surface of GaN-on-Si.

This example shows a method for reducing the defects of the silicon substrate and suppressing the warpage of the silicon-based GaN epitaxial wafer by performing RTP heat treatment on the 8-inch silicon substrate. Silicon single crystal polished wafer, the experimental equipment is BEST/Mattson Helios C200 annealing furnace, through heat treatment, the OISF in the silicon substrate is ablated, the warping of the silicon-based gallium nitride epitaxial wafer is suppressed, and surface cracks are avoided.

Claims (5)

1. A method for reducing silicon substrate defects to suppress warping of silicon-based gallium nitride epitaxial wafers, characterized in that, comprising the following steps: S1. Prepare an 8-inch heavy-doped borosilicate single crystal rod by the Czochralski method; S2. Carrying out wire cutting, chamfering, thinning, polishing and cleaning of the single crystal rod in sequence to obtain a polished sheet; S3, performing rapid heat treatment on the polished sheet to obtain an annealed polished sheet; S4, detect the OISF of the surface and cross section of the annealed polished sheet and the non-annealed polished sheet, and compare; S5. GaN epitaxial layer was grown on the surface of the annealed polished wafer and the non-annealed polished wafer, and the warpage of the epitaxial wafer was compared and analyzed, and the corresponding experimental results were obtained; S6. Comparing and analyzing the surface morphology of the GaN epitaxial layer grown on the surface of the annealed polished wafer and the non-annealed polished wafer in S5, and obtaining corresponding experimental results. 2. The method for reducing silicon substrate defects to suppress warping of silicon-based GaN epitaxial wafers according to claim 1, characterized in that: the surface and cross-section of the heat-treated silicon substrate and the untreated silicon substrate are carried out. Comparison of OISF in order to confirm the effect of heat treatment on eliminating OISF in silicon substrates. 3. The method for reducing silicon substrate defects to suppress warping of silicon-based gallium nitride epitaxial wafers according to claim 1, characterized in that: the heat-treated silicon substrate and the untreated silicon substrate undergo surface growth GaN epitaxial layer, and compare the warpage and surface topography of the epitaxial wafer to confirm the influence of different substrates on the warpage and surface topography of the epitaxial wafer. 4. The method for reducing silicon substrate defects to suppress warping of silicon-based gallium nitride epitaxial wafers according to claim 1, characterized in that: in said S1, silicon blocks and boron particles are used as raw materials to draw 8-inch Silicon single crystal, the casting speed is 35-50mm h ^-1 . 5. The method for reducing silicon substrate defects to suppress warping of silicon-based gallium nitride epitaxial wafers according to claim 1, characterized in that: in said S3, the polished wafers are heated to 1200-1300 °C, and the temperature is constant for 5- Cool down after 30 seconds, keep the argon flow rate at 10-50slm throughout the process, and the heating and cooling rates are both 30-70°C/s.

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