CN115831040A - Pixel island, display device and light field display device - Google Patents

Abstract

The present disclosure provides a pixel island, a display device and a light field display device. The pixel island includes: a driving layer including a power pad, a data pad, a clock pad and a chip select pad, and a logic processing circuit and a plurality of pixel circuits, and the power pad is used for the logic processing circuit and the pixel circuit to supply power, the data pad is used to provide data voltage to the pixel circuit, and the logic processing circuit is used to provide the clock signal according to the clock pad and the chip select signal of the chip select pad A gate control signal is provided to the pixel circuit; a plurality of sub-pixels are electrically connected to the pixel circuit in a one-to-one correspondence.

Description

Pixel island, display device and light field display device

technical field

The present disclosure belongs to the field of display technology, and in particular relates to a pixel island, a display device and a light field display device.

Background technique

This section is intended to provide a background or context to the implementations that are recited in the claims. The descriptions herein are not admitted to be prior art by inclusion in this section.

In the related art, a huge number of LED chips are transferred to the driving backplane, so as to obtain a display panel for light field display. The transfer and die-bonding process takes a long time and has a low yield rate, resulting in high cost of the display panel.

Contents of the invention

The present disclosure provides a pixel island, a display device and a light field display device.

The present disclosure provides the following technical solutions: a pixel island, comprising:

The driving layer includes a power supply pad, a data pad, a clock pad and a chip select pad, and includes a logic processing circuit and a plurality of pixel circuits, and the power supply pad is used for the logic processing circuit and the pixel circuit power supply, the data pad is used to provide data voltage to the pixel circuit, and the logic processing circuit is used to supply the pixel circuit with the clock signal of the clock pad and the chip select signal of the chip select pad Provide gate control signals;

a plurality of sub-pixels, and the plurality of sub-pixels are electrically connected to the pixel circuit in a one-to-one correspondence.

In some embodiments, the logic processing circuit is configured to: during the period when the chip select signal is maintained at a valid voltage, sequentially under the excitation of the rising edge and the falling edge of the clock signal provided by the clock pad A gate control signal provided to the pixel circuit is generated.

In some embodiments, the plurality of sub-pixels are divided into sub-pixels of multiple colors, the sub-pixels of the same color are distributed in the same rectangular area extending along the first direction, and the sub-pixels of different colors are arranged along the second direction , the first direction and the second direction are parallel to and intersect two directions in which the driving layer is located.

In some embodiments, the light emitted by the sub-pixels is collimated light.

In some embodiments, the number of the data pads is equal to the number of color types of the sub-pixels, and each data pad is used to receive a data voltage of a sub-pixel of one color.

In some embodiments, the sub-pixels include: LEDs.

The present disclosure provides the following technical solutions: a display panel, including a driving backplane and a plurality of the aforementioned pixel islands, the driving backplane includes a plurality of power lines, a plurality of chip selection signal lines extending along a third direction, and a clock signal line, a plurality of data lines extending in a fourth direction, the third direction and the fourth direction are two directions parallel to and intersecting the plane where the display panel is located, and the power line is used to The power supply pad of the pixel island provides a power supply voltage. The chip select signal line is used to provide a chip select signal to the chip select pad of the pixel island, and the clock signal line is used to provide a clock pad to the pixel island. Clock signals are provided, and the data lines are used to provide data voltages to data pads of the pixel islands.

In some embodiments, in the display panel, sub-pixels of the same color are distributed in the same rectangular area extending along the third direction, and sub-pixels of different colors are periodically arranged along the fourth direction.

In some embodiments, a column of the pixel islands arranged along the fourth direction is correspondingly connected to one or more of the data lines.

The present disclosure provides the following technical solutions: a display device, including: a source driver chip, a gate driver chip, and the aforementioned display panel, the source driver chip is used to drive the data lines, and the gate driver chip Used to drive the chip select signal line and the clock signal line.

The present disclosure provides the following technical solutions: a light field display device, comprising: a source driver chip, a gate driver chip, and the aforementioned display panel, the source driver chip is used to drive the data lines, and the gate driver chip The driving chip is used to drive the chip selection signal line and the clock signal line; the light field display device also includes a lens structure arranged on the light output surface of the display panel.

In some embodiments of the present disclosure, the transfer process of the single LED chip to the display substrate is replaced by the transfer process of the pixel island and the display substrate. The workload of the transfer process is greatly reduced. Further, the quality inspection of a single LED chip is replaced by the quality inspection of a pixel island, which is easier to operate due to its larger volume. Further, when a single sub-pixel or a pixel circuit of a single sub-pixel is faulty, only one pixel island needs to be scrapped or replaced without scrapping the entire display panel. This also helps to reduce the overall manufacturing cost of the display device.

Description of drawings

FIG. 1 is a top view of a pixel island according to an embodiment of the disclosure.

FIG. 2 is a schematic diagram of the distribution of sub-pixels in a single LED chip in the pixel island shown in FIG. 1 .

FIG. 3 is a circuit diagram of a driving layer in a pixel island according to an embodiment of the present disclosure.

4 is a cross-sectional view of a pixel island of an embodiment of the present disclosure.

FIG. 5 is a schematic diagram of the connection relationship of some structures in the display device according to the embodiment of the present disclosure.

FIG. 6 is a driving timing diagram of a pixel island according to an embodiment of the present disclosure.

FIG. 7 is a variant of the driving layer in the pixel island of the embodiment of the present disclosure.

FIG. 8 is a schematic structural diagram of a light field display device provided by an embodiment of the present disclosure.

Wherein, the reference signs are: R, red LED chip; G, green LED chip; B, blue LED chip; R1 to RN, independently controlled light-emitting areas in the red LED chip; VDD, VSS, power supply voltage; RST , EM, Gate1, Gate2, GateT, gate control signal; C1, capacitor; M1 to M7, transistor; SCS, chip select signal; CLK, clock signal; Data, data voltage; DataR, red sub-pixel data voltage; DataG, Green sub-pixel data voltage; DataB, blue sub-pixel data voltage; 1, base layer; 2, circuit layer; 3, sub-pixel; P1, P2, power pad; P5, data pad; P3, chip select pad ; P4, clock pad; LED1, light-emitting diode; L1, data line; L2, chip selection signal line; L3, clock signal line; IC1, source driver chip; IC2, gate driver chip; I, pixel island; 200 , Lens structure.

Detailed ways

The present disclosure will be further described below in conjunction with the embodiments shown in the accompanying drawings.

FIG. 1 is a top view of a pixel island according to an embodiment of the disclosure. FIG. 2 is a schematic diagram of the distribution of sub-pixels in a single LED chip in the pixel island shown in FIG. 1 . FIG. 3 is a circuit diagram of a driving layer in a pixel island according to an embodiment of the present disclosure. 4 is a cross-sectional view of a pixel island of an embodiment of the present disclosure.

Referring to FIG. 1 to FIG. 4 , embodiments of the present disclosure provide a pixel island. The pixel island independently packages or combines a plurality of sub-pixels, pixel circuits of the plurality of sub-pixels, and a driving circuit of the pixel circuits into an independent product. The display substrate only needs to provide power signal, chip select signal, clock signal and data voltage to the pixel island to drive the sub-pixels in the pixel island to light up sequentially or simultaneously. The preparation process of the display panel is simplified to the connection process of the pixel island and the display substrate, which greatly reduces the workload of the transfer and crystal bonding process. The workload of detecting the pixel island yield is low, and the reliability of the pixel island is stable. This helps to improve the efficiency of display panel manufacturing, and also helps to improve the yield rate of the display panel.

Referring to FIG. 4 , the driving layer in the pixel island includes a base layer 1 and a circuit layer 2 . The material of the base layer 1 is, for example, semiconductor materials such as silicon and gallium arsenide, or flexible insulating materials such as polyimide. Pixel circuits and logic processing circuits are arranged in the circuit layer 2 . The sub-pixel 3 is, for example, an independently controllable light-emitting area in a single LED chip.

Referring to FIG. 1 , a single red LED chip R has multiple light emitting regions that can be driven independently, thereby forming multiple red sub-pixels. A single green LED chip G has multiple light emitting regions that can be driven independently, thereby forming multiple green sub-pixels. A single blue LED chip B has multiple light emitting regions that can be driven independently, thereby forming multiple blue sub-pixels.

In some other embodiments, a single LED chip includes a single independently controllable light-emitting area, that is, a single LED chip forms a sub-pixel.

A single LED chip is manufactured on the driving layer by, for example, transfer and die-bonding processes. The pixel islands are then encapsulated. The pixel islands are thus used to prepare display panels. It is also possible to directly connect the pixel island to the display substrate without encapsulation after the single LED chip is transferred to the driving layer. Specifically, a bonding or soldering process may be used to realize the electrical connection between the power supply pad, the data pad, the clock pad, the chip select pad and the exposed wiring on the display substrate.

It should be noted that the sub-pixels are not limited to be formed by LED chips. In some other embodiments, the sub-pixels in the pixel island may also be formed by organic light emitting diodes or quantum dot light emitting diodes.

The power pad P1 is for example used to receive the first power supply voltage VDD, and the power supply substrate P2 is used for example to receive the second power supply voltage VSS. The first power supply voltage VDD is, for example, a positive power supply voltage, and the second power supply voltage VSS is, for example, a negative power supply voltage. The power pads P1, P2 are used to supply power to logic processing circuits and pixel circuits. The number of power pads is not limited to two. In some other embodiments, the pixel circuit also needs a half voltage (the median voltage of the high-level power supply voltage and the low-level power supply voltage). Correspondingly, the pixel island also includes a pad (not shown in the figure) for receiving half voltage.

The data pad P5 is used to provide a data voltage to the pixel circuit. The magnitude of the data voltage directly determines the brightness of the sub-pixels driven by the pixel circuit. The logic processing circuit is used to provide gate control signals to the pixel circuits according to the clock signal on the clock pad P4 and the chip select signal on the chip select pad P3.

Power pads P1 , P2 , data pad P5 , chip select pad P3 and clock pad P4 are arranged on the surface of the base layer 1 away from the circuit layer 2 . Power pads P1 , P2 , data pads P5 , chip select pads P3 and clock pads P4 are electrically connected to circuit layer 2 through vias penetrating base layer 1 , for example. In these embodiments, the light output direction of the sub-pixel is, for example, the direction in which the base layer 1 points to the circuit layer 2 .

In other embodiments, the power pads P1 , P2 , data pads P5 , chip select pads P3 and clock pads P4 are disposed on the surface of the circuit layer 2 away from the base layer 1 . The power pads P1 , P2 , data pads P5 , chip select pads P3 and clock pads P4 extend beyond the sub-pixel 3 along the direction from the base layer 1 to the circuit layer 2 , for example. In these embodiments, the light emitting direction of the sub-pixel 3 is, for example, the direction in which the circuit layer 2 points to the base layer 1 .

The present disclosure is not limited to how the sub-pixels and the driving layer are specifically packaged and the mechanical structure design of the power supply pads, data pads, clock pads and chip select pads.

The plurality of sub-pixels in the pixel island are electrically connected to the pixel circuits in a one-to-one correspondence.

FIG. 3 exemplarily shows two pixel circuits in a pixel island. The pixel circuit includes seven P-type transistors M1 to M7, a capacitor C1, and a light emitting diode LED1. The two ends of the capacitor C1 respectively receive the power supply voltage and connect to the gate of the transistor M1. The gate of the transistor M3 receives the gate control signal EM, the first terminal of the transistor M3 receives the power supply voltage VDD, and the second terminal of the transistor M3 is connected to the first terminal of the transistor M7 and the transistor M1. The second electrode of the transistor M7 receives the data voltage Data, and the gate of the transistor M7 receives the gate control signals Gate1 and Gate2. The second pole of the transistor M1 is connected to the first pole of the transistor M2 and the first pole of the transistor M7. The second pole of the transistor M2 is connected to the gate of the transistor M1, and the gate of the transistor M2 receives gate control signals Gate1 and Gate2. The gate of the transistor M4 receives the gate control signal EM, the second pole of the transistor M4 is connected to the anode of the light-emitting diode LED1, and the cathode of the light-emitting diode LED1 receives the power supply voltage VSS. Both the gate of the transistor M5 and the gate of the transistor M6 receive the gate control signal RST, and the first electrodes of the transistor M5 and the transistor M6 both receive the power supply voltage VSS. The second pole of the transistor M5 is connected to the gate of the transistor M1. The second pole of the transistor M6 is connected to the anode of the light emitting diode LED1.

Observe the pixel circuit on the left side of Figure 3, when the gate control signal RST is a low-level voltage, one end of the capacitor C1 (that is, the gate of the transistor M1) is written into the power supply voltage VSS, and the transistor M6 is turned on and emits light The anode voltage of diode LED1 is reset. When the gate control signal Gate1 is at a low level voltage, the corresponding transistor M7 is turned on, and the data voltage is written into the gate of the transistor M1 after threshold compensation. When the gate control signal EM is at a low level voltage, the transistors M3 and M4 are turned on, and the gate voltage of the transistor M1 controls the current of the light-emitting diode LED1 , thereby controlling the brightness of the light-emitting diode LED1 .

Observe the pixel circuit on the right side of Figure 3, when the gate control signal RST is at a low level voltage, one end of the capacitor C1 (that is, the gate of the transistor M1) is written into the power supply voltage VSS, and the transistor M6 is turned on and emits light The anode voltage of diode LED2 is reset. When the gate control signal Gate2 is at a low level voltage, the corresponding transistor M7 is turned on, and the data voltage is written into the gate of the transistor M1 after threshold compensation. When the gate control signal EM is at a low level voltage, the transistors M3 and M4 are turned on, and the gate voltage of the transistor M1 controls the current of the light-emitting diode LED1 , thereby controlling the brightness of the light-emitting diode LED2 .

The transistors in the above pixel circuits are all P-type transistors, and the effective voltage of the gate voltage is a low-level voltage. In some other embodiments, the transistors of the pixel circuit are all N-type transistors, and the effective voltage of the gate voltage thereof is a high level voltage.

The logic processing circuit provides gate control signals to each pixel circuit, so that each pixel circuit receives the data voltage Data in sequence.

In some embodiments, the logic processing circuit is configured to: during the period when the chip select signal maintains a valid voltage, under the stimulation of the rising edge and falling edge of the clock signal provided by the clock pad, sequentially generate Gate control signal.

In other words, when the chip select signal maintains a valid voltage, each jump edge of the clock signal will trigger a jump edge of the gate control signal. In this way, the frequency of the clock signal can be appropriately lowered by making full use of the jump edge information of the clock signal.

In some other embodiments, the logic processing circuit is configured to: during the period when the chip select signal maintains a valid voltage, under the excitation of the rising edge of the clock signal provided by the clock pad, sequentially generate the gates provided to the pixel circuit control signal. The frequency of the clock signal needs to be appropriately increased to shorten the data writing time of all sub-pixels in the pixel island.

The logic processing circuit is configured to: during the period when the chip select signal maintains a valid voltage, under the excitation of the falling edge of the clock signal provided by the clock pad, sequentially generate the gate control signal provided to the pixel circuit. . The frequency of the clock signal needs to be appropriately increased to shorten the data writing time of all sub-pixels in the pixel island.

FIG. 6 is a driving timing diagram of a pixel island according to an embodiment of the present disclosure. Referring to FIG. 3 and FIG. 6 , in an exemplary embodiment, the working sequence of the logic processing circuit is as follows.

The high-level voltage of the chip select signal SCS is an effective voltage, and the data voltage required by each sub-pixel in the pixel island is sequentially written into each sub-pixel during the period when the chip select signal is at a high-level voltage. During the low-level voltage period of the chip select signal SCS, each sub-pixel maintains a light-emitting state. The detailed working sequence is as follows.

At the moment of the first rising edge of the clock signal CLK after the rising edge of the chip select signal SCS, the voltage of the gate control signal EM provided to each pixel circuit in the pixel island is set to a high level voltage. The transistors M3 and M4 in all pixel circuits in the pixel island are in an off state.

At the subsequent falling edge of the clock signal CLK, the voltages of the gate control signal RST provided to each pixel circuit in the pixel island are all set to a low level voltage. The gate voltages of the transistors M1 and the anode voltages of the light emitting diodes LED1 , LED2 . . . of all pixel circuits in the pixel island are reset.

At the moment of the second rising edge of the clock signal CLK after the rising edge of the chip select signal SCS, the voltage of the gate control signal RST provided to each pixel circuit in the pixel island is set to a high level voltage.

At the falling edge of the subsequent clock signal CLK, the gate control signal Gate1 provided to the first pixel circuit is set to a low level voltage.

At the moment of the third rising edge of the clock signal CLK after the rising edge of the chip select signal SCS, the gate control signal Gate1 provided to the first pixel circuit is set to a high level voltage. During the period when the gate control signal Gate1 supplied to the first pixel circuit remains at a low level, the transistor M7 in the first pixel circuit is turned on, and the gate of the transistor M1 of the pixel circuit is written into data voltage.

At the falling edge of the subsequent clock signal CLK, the gate control signal Gate2 provided to the second pixel circuit is set to a low level voltage.

At the moment of the fourth rising edge of the clock signal CLK after the rising edge of the chip select signal SCS, the gate control signal Gate2 provided to the first pixel circuit is set to a high level voltage. During the period when the gate control signal Gate2 supplied to the second pixel circuit is kept at a low level, the transistor M7 in the second pixel circuit is turned on, and the gate of the transistor M1 of the pixel circuit is written into data voltage.

In this way, after the pixel voltage is written to all the pixel circuits in the pixel island in sequence, the chip select signal SCS provided to the pixel island is set to a low level voltage (in this embodiment as an invalid voltage) at the falling edge of the first clock signal CLK , and set the gate control signal EM provided to all pixel circuits in the pixel island to a low-level voltage (effective voltage in this embodiment), so that all sub-pixels in the pixel island enter a light-emitting state.

In some other embodiments, the logic control circuit lights up the sub-pixels in the same pixel island sequentially or time-sharingly. The present disclosure does not limit the lighting timing of each sub-pixel in the pixel island.

The present disclosure does not limit the specific implementation form of the logic control circuit. For example, the circuit form of the logic control circuit can be designed by means of a state transition diagram. Another example is a logic control circuit that includes a counter and a mapping table. The mapping relationship between the counting result of the counter and the gate control signal received by each pixel circuit is recorded in the mapping table. As the counting result of the counter increases, the state of each gate control signal received by each pixel circuit also changes. Another example is that the logic control circuit includes a counter and multiple arithmetic circuits for obtaining each gate control signal. Each arithmetic circuit is used to map a specific counting result to a specific high level state (digital 1) or low level state (digital 0).

In some embodiments, the multiple sub-pixels are divided into sub-pixels of multiple colors, the sub-pixels of the same color are distributed in the same rectangular area extending along the first direction, and the sub-pixels of different colors are arranged along the second direction, the second The first direction and the second direction are parallel to and intersect with the plane where the driving layer is located.

In the embodiment shown in FIG. 1 , a single pixel island contains multiple red LED chips R, and the multiple red LED chips R are evenly distributed in a rectangular area extending along the first direction. Due to the limited size of the rectangular area along the first direction, a plurality of red LED chips R are arranged in dislocation. If the size of the rectangular area along the first direction is large enough, a plurality of red LED chips R are arranged in a row along the first direction.

Referring to FIG. 2 , each red LED chip R integrates N sub-pixels R1 , R2 . . . RN.

In some other embodiments, a single pixel island contains one red LED chip R, and N sub-pixels R1, R2...RN are integrated in the red LED chip R.

In some other embodiments, a single pixel island contains multiple red LED chips R, and a single red LED constitutes a red sub-pixel.

In some other embodiments, the sub-pixels in a single pixel island are organic light emitting diodes or quantum dot light emitting diodes.

In some embodiments, the light emitted by the sub-pixels is collimated light. For example collimating structures (not shown) may be provided in the pixel islands. The collimating structure is eg a lens structure. The collimation structure is also, for example, a black matrix. The present disclosure does not limit how to control the light emitting direction of the sub-pixels.

In some embodiments, the number of data pads is equal to the number of color types of sub-pixels, and each data pad receives a data voltage of a sub-pixel of one color.

FIG. 7 is a variant of the driving layer in the pixel island of the embodiment of the present disclosure. Referring to FIG. 7 , in these embodiments, the pixel island includes three data pads for respectively receiving the data voltage DataR of the red subpixel, the data voltage DataG of the green subpixel, and the data voltage DataG of the blue subpixel. Correspondingly, in the display panel, the pixel islands are connected to three data lines. Such a design can reduce the data writing time consumption of the pixel island.

FIG. 5 is a schematic diagram of the connection relationship of some structures in the display device according to the embodiment of the present disclosure.

Referring to FIG. 5 , an embodiment of the present disclosure provides a display panel, including a driving backplane P and a plurality of aforementioned pixel islands I. The driving backplane P includes a plurality of power lines (not shown), extending along a third direction. A plurality of chip selection signal lines L2 and clock signal lines L3, a plurality of data lines L1 extending along the fourth direction, power lines are used to provide power supply voltage to the power supply pads of the pixel island, the third direction and the fourth direction are parallel to In the two intersecting directions of the plane where the display panel is located, the chip selection signal line L2 is used to provide a chip selection signal to the chip selection pad of the pixel island, and the clock signal line L3 is used to provide a clock signal to the clock pad of the pixel island, The data line L1 is used to provide data voltages to the data pads of the pixel islands.

Specifically, in the embodiment shown in FIG. 5 , the third direction is perpendicular to the fourth direction. The pixel islands 1 are arranged in an array along the third direction and the fourth direction.

It should be noted that the extension of the data line L1 along the fourth direction means that the entire section of the data line L1 excluding the section of the fan-out area extends along the fourth direction. Sections of the data line L1 other than the section in the fan-out area are, for example, straight lines, or, for example, serpentine lines.

The top view boundary of the pixel island 1 is also not limited to a rectangular shape. In some other embodiments, the top view boundary of the pixel island 1 is, for example, a regular hexagon.

In some embodiments, in the display panel, sub-pixels of the same color are distributed in the same rectangular area extending along the third direction, and sub-pixels of different colors are periodically arranged along the fourth direction.

In other words, the first direction in FIG. 1 and the third direction in FIG. 5 are the same direction. Specifically, in the display panel shown in FIG. 5 , the red LED chips R in a row of pixel islands arranged along the third direction are distributed in a rectangular area extending along the third direction; The green LED chips G in the island are distributed in a rectangular area extending along the third direction; the blue LED chips B in a row of pixel islands arranged along the third direction are distributed in a rectangular area extending in the third direction. In the display panel shown in FIG. 5 , along the fourth direction, the area where the red sub-pixels are located, the area where the green sub-pixels are located, and the area where the blue sub-pixels are located are periodically arranged.

It should be noted that the present disclosure does not specifically limit the arrangement of the pixel islands in the display panel.

In the display panel of some embodiments of the present disclosure, when the refresh frequency is 60 Hz, the data writing time of all pixel islands should be less than 16.67 ms. Each LED chip R, G or B includes Q sub-pixels, and has Q data writing periods. Limited by the low-temperature polysilicon process level, the shortest period of a data write is 0.8us. Assume that the pixel island includes a red LED chip R, a blue LED chip G and a green LED chip B, and then it is assumed that the pixel island has a data pad. Then the data writing time of one pixel island is 3*Q*0.8us. If it is assumed that there are M rows of pixel islands arranged along the third direction in the display panel, then the total data writing time of the display panel is 3*Q*M*0.8us. It should satisfy 3*Q*M*0.8us<16.67ms. This limits the resolution of the display panel.

In order to improve the resolution of the display panel, in some embodiments, multiple data pads can be arranged in the pixel island. Correspondingly, a column of pixel islands arranged along the fourth direction in the display panel is correspondingly connected to a plurality of data lines.

Referring to FIG. 5 , based on the same inventive concept, an embodiment of the present disclosure also provides a display device, including: a source driver chip IC1 , a gate driver chip IC2 , and the aforementioned display panel P. The source driver chip IC1 is used for The data line L1 in the display panel P is driven, and the gate driving chip IC2 is used to drive the chip selection signal line L2 and the clock signal line L8.

The display device can be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

FIG. 8 is a schematic structural diagram of a light field display device provided by an embodiment of the present disclosure.

Referring to FIG. 8 , based on the same inventive concept, an embodiment of the present disclosure further provides a light field display device, including: a source driver chip IC1, a gate driver chip IC2, and the aforementioned display panel, and the source driver chip IC1 uses For driving the data line L1, the gate driver chip IC2 is used for driving the chip select signal line L2 and the clock signal line L3; the light field display device further includes a lens structure 200 disposed on the light emitting surface of the display panel P.

FIG. 8 exemplarily shows a lens structure 200 in a light field display device. A plurality of lens structures 200 respectively cover a row of pixel islands I arranged along the fourth direction.

The present disclosure does not limit the design manner of the lens structure 200 , and those skilled in the art can make settings according to the conventional design manner of the light field display device.

Each embodiment in the present disclosure is described in a progressive manner, the same and similar parts of the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments.

The protection scope of the present disclosure is not limited to the above-mentioned embodiments, and it is obvious that those skilled in the art can make various changes and modifications to the present disclosure without departing from the scope and spirit of the present disclosure. If these changes and modifications belong to the scope of the claims of the present disclosure and their equivalent technologies, the intent of the present disclosure is to also include these changes and modifications.

Claims (11)

1. A pixel island, characterized in that it comprises: The driving layer includes a power supply pad, a data pad, a clock pad and a chip select pad, and includes a logic processing circuit and a plurality of pixel circuits, and the power supply pad is used for the logic processing circuit and the pixel circuit power supply, the data pad is used to provide data voltage to the pixel circuit, and the logic processing circuit is used to supply the pixel circuit with the clock signal of the clock pad and the chip select signal of the chip select pad Provide gate control signals; a plurality of sub-pixels, and the plurality of sub-pixels are electrically connected to the pixel circuit in a one-to-one correspondence. 2. The pixel island according to claim 1, wherein the logic processing circuit is configured to: during the period when the chip select signal maintains a valid voltage, on the rising edge and the falling edge of the clock signal The gate control signals provided to the pixel circuits are sequentially generated under the excitation of . 3. The pixel island according to claim 1, wherein the plurality of sub-pixels are divided into sub-pixels of multiple colors, and the sub-pixels of the same color are distributed in the same rectangular area extending along the first direction, The sub-pixels of different colors are arranged along a second direction, and the first direction and the second direction are parallel to and intersect two directions on which the driving layer is located. 4. The pixel island according to claim 1, wherein the light emitted by the sub-pixels is collimated light. 5. The pixel island according to claim 2, wherein the number of the data pads is equal to the number of color types of the sub-pixels, and each data pad is used to receive data of a sub-pixel of one color Voltage. 6. The pixel island according to claim 1, wherein the sub-pixels comprise: LEDs. 7. A display panel, characterized in that it comprises a driving backplane and a plurality of pixel islands according to any one of claims 1 to 6, the driving backplane comprises a plurality of power lines extending along the third direction A plurality of chip select signal lines and clock signal lines, a plurality of data lines extending along the fourth direction, the power lines are used to provide power supply voltage to the power pads of the pixel island, the third direction and the The fourth direction is two directions parallel to and intersecting the plane where the display panel is located, the chip selection signal line is used to provide a chip selection signal to the chip selection pad of the pixel island, and the clock signal line is used to The data line is used to provide a clock signal to the clock pad of the pixel island, and the data line is used to provide a data voltage to the data pad of the pixel island. 8. The display panel according to claim 7, wherein in the display panel, sub-pixels of the same color are distributed in the same rectangular area extending along the third direction, and sub-pixels of different colors arranged periodically along the fourth direction. 9 . The display panel according to claim 7 , wherein a column of the pixel islands arranged along the fourth direction is correspondingly connected to one or more of the data lines. 10. A display device, characterized in that it comprises: a source driver chip, a gate driver chip, and the display panel according to any one of claims 7 to 9, the source driver chip is used to drive the The data line, the gate driver chip is used to drive the chip select signal line and the clock signal line. 11. A light field display device, comprising: a source driver chip, a gate driver chip, and a display panel according to any one of claims 7 to 9, the source driver chip being used for The data line is driven, and the gate driver chip is used to drive the chip select signal line and the clock signal line; the light field display device further includes a lens structure arranged on the light output surface of the display panel.

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