CN115826278A - A kind of array substrate and display panel - Google Patents

Abstract

The present application discloses an array substrate, which includes a plurality of pixel driving circuits and a plurality of lead-out voltage lines, and the plurality of pixel driving circuits are arranged in an array along a first direction and a second direction; wherein, in the first direction, at least Part of the adjacent two pixel driving circuits are arranged mirror-symmetrically, and a light-transmitting area is formed between the two pixel driving circuits arranged mirror-symmetrically; in the second direction, a plurality of pixel driving circuits located in the same column form a pixel column; At least a part of the lead-out voltage lines extends between the two pixel columns where the two pixel drive circuits arranged in mirror image symmetry are located, and the lead-out voltage lines are provided with isolation regions at positions corresponding to the light-transmitting regions. The light-transmitting area is set corresponding to the photosensitive element, so that the optical sensor in the photosensitive element can accurately sense the ambient light, so that the photosensitive element can control the display panel to adjust the screen brightness according to the ambient light, improve the user's visual experience and save power.

Description

A kind of array substrate and display panel

technical field

The present application relates to the field of display technology, in particular to an array substrate and a display panel.

Background technique

At present, the display panel is more and more widely used, and at the same time, the display panel has more and more functions, so that the display panel develops towards an intelligent direction. In the array substrate, a photosensitive element can be arranged on the side of the backlight surface to obtain the brightness in the external environment, so that the array substrate can adjust the luminous brightness according to the ambient brightness, which is convenient for users to use.

Therefore, it is necessary to improve the structure of the array substrate, so that the array substrate has a light-transmitting area, so that the photosensitive element can sense the brightness in the external environment, and then provide a basis for controlling the brightness of the array substrate.

Contents of the invention

The present application mainly provides a light-transmitting area on the array substrate, so that light can pass through the array substrate and reach the optical sensor area of the photosensitive element.

In order to solve the above technical problems, a technical solution adopted by this application is to provide an array substrate, which includes a plurality of pixel driving circuits and a plurality of lead-out voltage lines; wherein, the plurality of pixel driving circuits are Arranged in an array; wherein, in the first direction, at least part of the adjacent two pixel drive circuits are mirror-symmetrically arranged, and a light-transmitting area is formed between the two mirror-symmetrically arranged pixel drive circuits.

In the second direction, a plurality of pixel driving circuits located in the same column form a pixel column; at least part of the drawn-out voltage lines extend between the two pixel columns where the two pixel driving circuits arranged in mirror image symmetry are located, and the drawn-out voltage lines are in the corresponding The position of the light-transmitting area is provided with a partition area. By arranging a partition area at the position where the drawn voltage line corresponds to the light-transmitting area, the light-transmitting area of the light-transmitting area is not affected by the drawn-out voltage line, thereby ensuring the light transmittance of the array substrate.

Wherein, an lead-out voltage line is provided between the pixel columns where a group of two pixel drive circuits arranged in mirror image symmetry are located. By arranging the lead-out voltage lines between the pixel columns where two pixel drive circuits are arranged symmetrically in a mirror image, the space of the array substrate is fully used to route the lead-out voltage lines, so as to increase the line density in the array substrate and improve the array performance. The degree of integration of the substrate.

Wherein, the array substrate further includes: a plurality of reference voltage lines, which extend along the first direction and are electrically connected to the pixel driving circuit; wherein, one lead-out voltage line is electrically connected to one reference voltage line. By electrically connecting the lead-out voltage line and the reference voltage line, the lead-out voltage line leads out the signal of the reference voltage line, which is beneficial to realizing uniform voltage of the array substrate.

Preferably, the reference voltage line includes a first reference voltage line, a second reference voltage line, and a third reference voltage line, and the lead voltage line and one of the first reference voltage line, the second reference voltage line, and the third reference voltage line electrical connection. The design of three reference voltage lines is beneficial to maintain the stability of the pixel circuit.

Wherein, in the first direction, the array substrate includes a plurality of extraction voltage lines, and the plurality of extraction voltage lines are electrically connected to the plurality of reference voltage lines alternately in sequence.

Between adjacent pixel columns where two pixel drive circuits are arranged mirror-symmetrically, lead voltage lines connected to different reference voltage lines can be sequentially arranged, and the lead voltage lines and the reference voltage lines are designed in a grid pattern. By sequentially connecting the lead-out voltage line and the reference voltage line, the signal of each reference voltage line is drawn out, so that uniform voltage and current uniformity of the pixel circuit in the array substrate are realized.

Wherein, the array substrate further includes a plurality of data lines extending along the second direction, and the data lines adjacent to the light-transmitting area are bent along the periphery of the light-transmitting area. By bending the data lines adjacent to the light-transmitting area along the periphery of the light-transmitting area, the size of the area of the light-transmitting area can be controlled so that the design of the light-transmitting area meets requirements.

Wherein, the lead-out voltage line and the first reference voltage line are located on different metal layers; and/or, the lead-out voltage line and the second reference voltage line are located on different metal layers; and/or, the lead-out voltage line and the third reference voltage line are located on Different metal layers; by setting the reference voltage line and the lead-out voltage line on different metal layers, the routing design in the array substrate is optimized.

Preferably, the lead-out voltage line, the first reference voltage line, the second reference voltage line and the third reference voltage line are located on different metal layers; by setting the reference voltage line and the lead-out voltage line on different metal layers, the array substrate The transmission of voltage signals in different layers is beneficial to realize the voltage stability of the pixel circuit.

Preferably, the metal layer where the first reference voltage line is located is located between the third reference voltage line and the metal layer where the lead-out voltage line is located, and the metal layer where the second reference voltage line is located is located away from the metal layer where the third reference voltage line is located. One side of the reference voltage line. By setting different reference voltage lines and lead-out voltage lines on different metal layers, the wiring design in the array substrate is optimized, the efficiency and density of wiring design are improved, and the integration degree of the array substrate is improved.

Wherein, the shape of the light-transmitting area is the same as that of the photosensitive element below the light-transmitting area. The diffraction pattern of the light-transmitting area is made to be the same as the shape of the photosensitive element, and the sensitivity of the photosensitive element is improved.

Preferably, the shape of the photosensitive element and the light-transmitting area is circular. A circle is a shape that can be easily designed for the photosensitive element and the light-transmitting region.

Wherein, the pixel driving circuit includes a charging circuit, a light emitting circuit and a reset circuit. Among them, the charging circuit is used to charge the driving transistor and write data; the light emitting circuit responds to the signal of the light emitting control signal to realize the light emitting of the light emitting element; the reset circuit resets the transistor in the pixel driving circuit, and the reset circuit includes a plurality of reference voltage line.

Wherein, the reset circuit includes a first reference voltage line, a second reference voltage line and a third reference voltage line, wherein the first reference voltage line is connected to the gate of the drive transistor, and is used to reset the gate of the drive transistor; The second reference voltage line is connected to the anode of the light-emitting element, and is used to reset the anode of the light-emitting element; the third reference voltage line is connected to the drain of the driving transistor, and is used to reset the source of the driving transistor;

Preferably, the charging circuit includes a data line, a second transistor, a driving transistor and a third transistor, the drain of the second transistor is connected to the data line, the source of the second transistor is connected to the drain of the driving transistor, and the source of the driving transistor is connected to the first The sources of the three transistors and the drain of the third transistor are connected to the gate of the driving transistor; the charging circuit is used to implement data writing and charging to the driving transistor.

Preferably, the light-emitting circuit includes a high power supply voltage line, a light-emitting control signal, a fifth transistor, a driving transistor, a sixth transistor, and a light-emitting element; the source of the fifth transistor is connected to the high power supply voltage line, and the gate of the fifth transistor is connected to the light-emitting control signal. signal, the drain of the fifth transistor is connected to the drain of the driving transistor, the source of the driving transistor is connected to the source of the sixth transistor, the gate of the sixth transistor is connected to the light-emitting control signal, and the drain of the sixth transistor is connected to the anode of the light-emitting element . The light emission of the light emitting element is controlled by the light emitting circuit.

In order to solve the above technical problem, another technical solution adopted by the present application is to provide a display panel, including the array substrate in the above embodiment.

The beneficial effect of the present application is that at least part of the adjacent two pixel drive circuits in the array substrate are arranged in mirror symmetry, and a light-transmitting area is formed between the two pixel drive circuits arranged in mirror symmetry. In addition, at least part of the lead-out voltage lines extends between the two pixel columns where the two pixel drive circuits arranged in mirror image symmetry are located, and the lead-out voltage lines are provided with isolation regions at positions corresponding to the light-transmitting regions. The light-transmitting area is set corresponding to the photosensitive element. The optical sensor in the photosensitive element can accurately sense the ambient light, so that the photosensitive element can control the display panel to adjust the screen brightness according to the ambient light, improve the user's visual experience, and save the use of the array substrate. The power of the display panel.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the application. For those skilled in the art, other drawings can also be obtained based on these drawings without creative effort. in:

FIG. 1 is a schematic structural view of an embodiment of an array substrate of a display panel of the present application;

FIG. 2 is a schematic structural view of another embodiment of the array substrate of the display panel of the present application;

FIG. 3 is a schematic circuit diagram of an embodiment of a pixel driving circuit in the present application.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only part of the embodiments of the application, not all of them. Based on the implementation manners in this application, all other implementation manners obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

Please refer to Figure 1, Figure 1 is a schematic structural diagram of an embodiment of the array substrate of the display panel of the present application; the present application provides an array substrate, which includes multiple pixel drive circuits and multiple lead-out voltage lines Vref', The circuits are arranged in an array along the first direction X and the second direction Y; wherein, in the first direction X, at least partially adjacent two pixel drive circuits are arranged in mirror symmetry, and the two pixel drive circuits arranged in mirror symmetry A light-transmitting area 1 is formed between the circuits; in the second direction Y, a plurality of pixel driving circuits located in the same column form a pixel column; The pixel columns extend, and the lead-out voltage line Vref' is provided with an isolating area at a position corresponding to the light-transmitting area 1 .

In the present application, at least part of the adjacent two pixel drive circuits are arranged mirror-symmetrically, and a light-transmitting region 1 is formed between the two pixel-driving circuits arranged mirror-symmetrically, and the light-transmitting region 1 is mainly composed of adjacent and mirror-image Part of the symmetrical pixel driving circuit is formed together, so that the number of pixel driving circuits on the array substrate does not need to be reduced, and the resolution of the display panel using the array substrate is guaranteed without affecting the display effect of the display panel. In addition, the design of the array substrate in this application includes the lead-out voltage line Vref', and at least part of the lead-out voltage line Vref' extends between the two pixel columns where the two pixel drive circuits arranged in mirror image symmetry, so that the lead-out voltage line Vref' Extending in the second direction Y makes the voltage in the display panel relatively uniform, further ensuring the uniformity of current in the display panel and the stability of the pixel circuit. In this application, by setting the light-transmitting area 1 between the pixel drive circuits arranged in mirror image symmetry, the light-transmitting area 1 is set corresponding to the photosensitive element, the optical sensor in the photosensitive element can accurately sense the ambient light, so that the photosensitive element can The control display panel adjusts the brightness of the screen according to the ambient light so as to improve the user's visual experience and save the power of the display panel using the array substrate.

Wherein, an extraction voltage line Vref' is provided between the pixel columns where a group of two pixel driving circuits arranged in mirror image symmetry are located. The extracted voltage line Vref' is arranged between the pixel columns where the two pixel driving circuits arranged in mirror image symmetry are located, because the pixel columns provided with the extracted voltage line Vref' are adjacently arranged, and the pixel driving circuits in the adjacent pixel columns It is mirror-symmetrical, so that there is enough space between adjacent pixel columns to set the lead-out voltage line Vref', and setting the lead-out voltage line Vref' between adjacent pixel columns will not affect other wiring designs in the array substrate , no resistance interference.

In addition, the array substrate further includes a plurality of reference voltage lines Vref, the reference voltage lines Vref extend along the first direction X, and are electrically connected to the pixel driving circuit; wherein, one lead-out voltage line Vref' is electrically connected to one reference voltage line Vref; The English corresponding to the voltage line Vref is Voltage reference (abbreviated as Vref), and the reference voltage line Vref in this application refers to a voltage in the circuit that can be kept constant regardless of load, power supply, temperature drift, time, etc. A voltage value used as a reference point when measuring a voltage value. Vref can be used in voltage regulators in power supply systems, analog-to-digital converters and digital-to-analog converters.

Preferably, the reference voltage line Vref includes a first reference voltage line Vref 1, a second reference voltage line Vref 2 and a third reference voltage line Vref 3, between the pixel columns where a group of mirror-symmetrically arranged two pixel driving circuits are located. The lead-out voltage line Vref' provided between them is electrically connected to one of the first reference voltage line Vref 1 , the second reference voltage line Vref 2 , and the third reference voltage line Vref 3 . In the pixel driving circuit of the present application, there are three reference voltage lines Vref, which are respectively the first reference voltage line Vref 1, the second reference voltage line Vref 2 and the third reference voltage line Vref3, and each reference voltage line Vref is respectively connected to Different transistors are connected. Wherein, the first reference voltage line Vref 1 is connected to the source electrode Source of the fourth transistor T4, the second reference voltage line Vref 2 is connected to the drain electrode Drain of the seventh transistor T7, and the third reference voltage line Vref 3 is connected to the eighth transistor T8 The source of the Source is connected.

Please refer to FIG. 2. FIG. 2 is a schematic structural diagram of another embodiment of the array substrate of the display panel of the present application; in the first direction X, the array substrate includes a plurality of lead-out voltage lines Vref', and the multiple lead-out voltage lines Vref' and A plurality of reference voltage lines Vref are electrically connected alternately in sequence. Because the lead-out voltage line Vref' is electrically connected to one of the first reference voltage line Vref1, the second reference voltage line Vref2, and the third reference voltage line Vref3. In addition, the lead-out voltage line Vref' is arranged between a group of pixel columns where two pixel drive circuits arranged in mirror symmetry are located, and adjacent rows where two pixel drive circuits arranged in mirror symmetry arranged in sequence in the first direction X are located. Between the pixel columns, the arrangement order of adjacent pixel columns can be followed, so that the lead-out voltage line Vref' is sequentially connected to one of the first reference voltage line Vref 1, the second reference voltage line Vref 2 and the third reference voltage line Vref 3 electrical connection. That is, between adjacent pixel columns where two pixel drive circuits are arranged in mirror-image symmetry, lead-out voltage lines Vref' connected to different reference voltage lines Vref can be sequentially arranged, so that the lead-out voltage line Vref' and the reference voltage line Vref is a grid design. In the first direction X, between the adjacent pixel columns where the first group of mirror-symmetrically arranged two pixel drive circuits are located, the lead-out voltage line Vref' is connected to the first reference voltage line Vref 1; in the second group Between adjacent pixel columns, the drawn voltage line Vref' is connected to the second reference voltage line Vref 2; between the third group of adjacent pixel columns, the drawn voltage line Vref' is connected to the third reference voltage line Vref 3, Then alternate settings in this order.

It can be understood that, in other embodiments, between the first group of adjacent pixel columns, the lead-out voltage line Vref' is connected to the second reference voltage line Vref 2 or the third reference voltage line Vref 3; Between the adjacent pixel columns, the lead-out voltage line Vref' is connected to the third reference voltage line Vref3 or the first reference voltage line Vref1; between the third group of adjacent pixel columns, the lead-out voltage line Vref' is connected to the first reference voltage line Vref' The reference voltage line Vref 1 or the second reference voltage line Vref 2 are connected, and then alternately set in this order.

In the above-mentioned embodiments, the grid design of the lead voltage line Vref' and the reference voltage line Vref can be realized, wherein the reference voltage line Vref extends along the first direction X, and the lead voltage line Vref' extends along the second direction Y. Since the lead-out voltage line Vref' is sequentially connected to different reference voltage lines Vref, for the first reference voltage line Vref 1, the first reference voltage line Vref 1 extends along the first direction X, and the lead-out line connected to the first reference voltage line Vref 1 The voltage line Vref' extends along the second direction Y, and the first reference voltage line Vref 1 and the lead-out voltage line Vref' in the corresponding circuit structure have a network structure in the array substrate. Similarly, it can be known that the second reference voltage line Vref 2 and its corresponding voltage line Vref' in the circuit structure also have a mesh structure in the array substrate, and the third reference voltage line Vref 3 and its corresponding circuit structure's voltage line Vref' are also in the array The substrate has a network structure. When the reference voltage line Vref and the lead-out voltage line Vref' have a network structure in the array substrate, the reference voltage is more balanced and uniform, and the pixel circuit is stabilized.

Wherein, in one embodiment, the lead-out voltage line Vref' and the first reference voltage line Vref 1 are located on different metal layers; in one embodiment, the lead-out voltage line Vref' and the second reference voltage line Vref 2 are located on different metal layers layer; in one embodiment, the lead-out voltage line Vref' and the third reference voltage line Vref3 are located in different metal layers; when the reference voltage line Vref and the lead-out voltage line Vref' are set in different layers, the lead-out voltage line Vref can be effectively realized 'The lead-out of the signal in the reference voltage line Vref.

Preferably, the lead voltage line Vref', the first reference voltage line Vref 1, the second reference voltage line Vref 2 and the third reference voltage line Vref 3 are respectively located in different metal layers; when the lead voltage line Vref', the first reference voltage line When the line Vref1, the second reference voltage line Vref 2, and the third reference voltage line Vref 3 are located on different metal layers, the best routing design method can be obtained in the array substrate, and the integration of the routing design in the array substrate can be improved. , rationally arrange the routing setting space in the array substrate.

Preferably, the metal layer where the first reference voltage line Vref 1 is located is located between the metal layer where the third reference voltage line Vref 3 and the lead-out voltage line Vref' are located, and the metal layer where the second reference voltage line Vref 2 is located is located in the third reference voltage line Vref'. The metal layer where the voltage line Vref 3 is located is away from the side of the first reference voltage line Vref 1 . Combining with the connection relationship of different reference voltage lines Vref in the circuit, the best way to set the reference voltage line Vref is obtained.

In one embodiment, the array substrate includes a first metal layer M1 , a second metal layer M2 , a third metal layer M3 and a fourth metal layer M4 .

In one embodiment, the lead-out voltage line Vref' is electrically connected to one of the first reference voltage line Vref1, the second reference voltage line Vref2, and the third reference voltage line Vref3. The lead-out voltage line Vref' is located in the fourth metal layer M4; the first reference voltage line Vref 1 is located in the third metal layer M3, and the connection between the first reference voltage line Vref 1 and the lead-out voltage line is realized by opening a hole in the flat layer and filling the hole with conductive material Electrical connection of Vref';

In one embodiment, the second reference voltage line Vref 2 is located on the first metal layer M1, and the connection between the second reference voltage line Vref 2 and the extraction voltage line Vref' is realized through the conduction vias connecting the second reference voltage line Vref 2 and the extraction voltage line Vref'. Electrical connection of line Vref';

In one embodiment, the second reference voltage line Vref 2 on the first metal layer M1 is connected to the third metal layer M3 through a hole, and then through a conductive hole between the third metal layer M3 and the fourth metal layer M4. The second reference voltage line signal Vref 2 is transmitted to the fourth metal layer M4 through the hole, so as to realize the electrical connection between the second reference voltage line Vref 2 and the lead-out voltage line Vref';

In one embodiment, the third reference voltage line Vref 3 is located on the second metal layer M2, and the connection between the third reference voltage line Vref 3 and the extraction voltage line Vref' is realized through a conduction via connecting the third reference voltage line Vref 3 and the extraction voltage line Vref'. The electrical connection of the line Vref', the conduction hole first connects the third reference voltage line Vref 3 located in the second metal layer M2 and the third metal layer M3, and then passes through the conduction between the third metal layer M3 and the fourth metal layer M4. The signal of the third reference voltage line Vref 3 is transmitted to the fourth metal layer M4 through the hole, so as to realize the electrical connection between the third reference voltage line Vref 3 and the lead-out voltage line Vref′.

The array substrate further includes: a plurality of data lines Data extending along the second direction Y, and the data lines Data adjacent to the light-transmitting area 1 are bent along the periphery of the light-transmitting area. In the prior art, the data line Data in the array substrate is designed as a straight line. When the data line Data is designed as a straight line, the data line Data in each pixel drive circuit is also designed in two adjacent pixel drive circuits that are mirror-symmetrical. They are arranged adjacently, and since the pixel driving circuits in the array substrate are arranged in an array along the first direction X, the light-transmitting regions 1 cannot be designed between adjacent data lines Data. However, in the present application, the light-transmitting region 1 is designed in the adjacent mirror image pixel driving circuit, and the data line Data adjacent to the light-transmitting region 1 is curved along the periphery of the light-transmitting region 1 . The area of the light-transmitting region 1 can be expanded, and at the same time, the area of the light-transmitting region 1 can be controlled by controlling the bending degree of the data line Data on the periphery of the light-transmitting region 1, so that the area of the light-transmitting region 1 and the light transmittance of the array substrate meet client needs.

Preferably, the data line Data is connected to the second transistor T2. Specifically, the semiconductor layer where the second transistor T2 is located (that is, the P-Si layer) is first connected to the third metal layer M3 through the first via hole, and then the second transistor T2 is connected to the third metal layer M3. The metal layer M3 passes through the planarization layer through the second via hole to reach the fourth metal layer M4 where the data line Data is located, so as to realize the electrical connection between the data line Data and the second transistor T2, and the first via hole and the second via hole pass through the third via hole. The metal layer M3 is connected; the light-transmitting region 1 is disposed adjacent to the first via hole and the second via hole. And the first via hole and the second via hole avoid the area of the light-transmitting region 1 . In the routing of the array substrate, the first via hole and the second via hole are close to the drain Drain of the second transistor T2 , and further, the first via hole and the second via hole are away from the edge of the light-transmitting region 1 . In one embodiment, the data line Data is connected to the drain Drain of the second transistor T2, so that the second transistor T2 has a data writing function.

In one embodiment, a zigzag design is adopted for the source of the second transistor T2 in the array substrate, so that in the first direction X, the light-transmitting region 1 is located at the drain of the second transistor T2 in the adjacent pixel driving circuit. Meanwhile, the height of the gate Gate of the second transistor T2 in the second direction Y is lowered. The height of the light-transmitting region 1 in the second direction Y is enlarged, and the area of the light-transmitting region 1 is increased. In the prior art, the source and drain of the second transistor T2 are designed to be parallel to the second direction Y. In this application, the source of the second transistor T2 is designed with a broken line, so that the source of the second transistor T2 The electrode Source and the drain Drain are no longer parallel to the second direction Y, and when the adjacent pixel driving circuits are designed with mirror symmetry, the distance between the drains of the second transistor T2 in the adjacent pixel driving circuits becomes larger . Create conditions for setting the light-transmitting region 1 in the first direction X in the adjacent mirror-symmetrically designed pixel drive circuit, and in the second direction Y, reduce the height of the gate Gate of the second transistor T2, but although it reduces The height of the gate Gate of the second transistor T2 still ensures the width-to-length ratio of the gate Gate, so that the function of the gate Gate is not damaged. Set light-transmitting zone 1 above to create conditions.

In one embodiment, the array substrate further includes a first scan line S1 and a second scan line S2 , which are arranged at intervals and extend along the first direction X. In the second direction Y, the transparent region 1 is located between the first scan line S1 and the second scan line S2. In the second direction Y, the first scanning line S1 and the second scanning line S2 surround the light-transmitting region 1 .

In one embodiment, the shape of the light-transmitting region 1 is the same as the shape of the photosensitive element positioned below the light-transmitting region 1; trapezoidal, common trapezoidal, etc., and can be circular, elliptical, etc. In another embodiment, the light-transmitting region 1 can have a special shape. When the shape of the light-transmitting region 1 is the same as that of the photosensitive element below the light-transmitting region 1, the diffraction pattern of the shape of the light-transmitting region 1 matches the pattern of the photosensitive element, which can improve the sensitivity of the optical sensor in the photosensitive element.

Preferably, the shapes of the photosensitive element and the light-transmitting region 1 are circular. When the shape of the photosensitive element is circular and the shape of the light-transmitting area 1 is also circular, external light passing through the circular light-transmitting area will have a circular diffraction pattern. When the shape of the diffraction pattern is consistent with the shape of the photosensitive element, The sensitivity of the optical sensor in the photosensitive element can be improved. In one embodiment, the first scanning line S1 and the second scanning line S2 located on both sides of the light-transmitting region 1 in the second direction Y are arc-shaped (not shown in the figure), so that the light-transmitting region 1 has a circular shape. shaped shape. In one embodiment, the initial scan line S0 is located at the first gate layer G1, the first scan line S1 is located at the second gate layer G2, and the second scan line S2 is located at the first metal layer M1. Through the design of different layers of scanning lines, the wiring design of the array substrate is optimized.

Preferably, the pixel driving circuit includes a pixel driving circuit for blue sub-pixels, a pixel driving circuit for red sub-pixels and a pixel driving circuit for green sub-pixels. Among them, by changing the pixel driving circuit of the blue sub-pixel, the pixel driving circuit of the blue sub-pixel and the pixel driving circuit of the adjacent sub-pixel are mirror-symmetrically arranged. The display effect of the display panel is less affected. It is not limited here, and may be adjusted according to actual conditions.

Please refer to FIG. 3 . FIG. 3 is a schematic structural diagram of another embodiment of the array substrate of the display panel of the present application. The array substrate in this application includes a plurality of pixel driving circuits and a plurality of lead-out voltage lines Vref', wherein the pixel driving circuit includes a charging circuit, a light emitting circuit and a reset circuit, wherein the charging circuit is used for charging and writing data to the driving transistor T1 input; the light-emitting circuit responds to the light-emitting control signal EM to realize the light-emitting of the light-emitting element; the reset circuit resets the transistor in the pixel driving circuit, and the reset circuit includes a plurality of reference voltage lines Vref.

Further, the reset circuit includes a first reference voltage line Vref 1, a second reference voltage line Vref 2 and a third reference voltage line Vref 3, wherein the first reference voltage line Vref 1 is connected to the gate Gate of the drive transistor T1 for To reset the gate Gate of the driving transistor T1; the second reference voltage line Vref 2 is connected to the anode of the light emitting element for resetting the anode of the light emitting element; the third reference voltage line Vref 3 is connected to the drain Drain of the driving transistor T1 Connected to reset the source of the drive transistor T1; the first reference voltage line Vref1 and the third reference voltage line Vref3 double reset the drive transistor T1, the reset effect is good, easy to control, and the operation of the drive transistor T1 is improved. The stability and accuracy of the display panel can achieve the effect of uniform display.

Preferably, the charging circuit includes a data line Data, a second transistor T2, a driving transistor T1 and a third transistor T3, the drain of the second transistor T2 is connected to the data line Data, and the source of the second transistor T2 is connected to the drain of the driving transistor Drain, the source Source of the driving transistor T1 is connected to the source Source of the third transistor T3, and the drain Drain of the third transistor T3 is connected to the gate Gate of the driving transistor T1; in the charging circuit, the signal of the data line Data passes through the second The drain Drain of the transistor T2 then flows out through the source Source of the second transistor T2 to the drain Drain of the drive transistor T1, then flows out through the source Source of the drive transistor T1 to the source Source of the third transistor T3, and then passes through the third The drain Drain of the transistor T3 reaches the gate Gate of the driving transistor T1 to charge and write data to the driving transistor T1 .

Preferably, the light emitting circuit includes a high power supply voltage line ELVDD, a light emission control signal EM, a fifth transistor T5, a driving transistor T1, a sixth transistor T6 and a light emitting element; the source of the fifth transistor T5 is connected to the high power supply voltage line ELVDD, and the fifth transistor T5 is connected to the high power supply voltage line ELVDD, and the fifth transistor T5 The gate Gate of the fifth transistor T5 is connected to the light emission control signal EM, the drain of the fifth transistor T5 is connected to the drain Drain of the driving transistor T1, the source of the driving transistor T1 is connected to the source of the sixth transistor T6, and the sixth transistor The gate Gate of T6 is connected to the light emitting control signal EM, and the drain Drain of the sixth transistor T6 is connected to the anode of the light emitting element. In the light emitting circuit, the gates of the fifth transistor T5 and the sixth transistor T6 are both connected to the light emitting control signal EM, and the fifth transistor T5 and the sixth transistor T6 are turned on in response to the signal sent by the light emitting control signal EM.

Further, the pixel driving circuit in this application has an 8T1C structure, that is, the pixel driving circuit in this application includes 8 transistors and 1 storage capacitor. in:

The first transistor T1 (or the driving transistor T1) may be electrically connected between the high power supply voltage ELVDD supply and the light emitting element (or may be between the first node N1 and the second node N2), and may respond to the third node N3 The voltage at the third node is turned on.

The second transistor T2 is used for data writing, and the second transistor T2 (or switching transistor) may be electrically connected between the data line Data and the first node N1, and may be turned on in response to a signal of the second scan signal S2 .

The third transistor T3 is used for threshold compensation, the third transistor T3 may be electrically connected between the second node N2 and the fourth node N4, and may be turned on by the second scan signal S2'. That is, the second transistor T2 and the third transistor T3 may transmit a data signal to the third node N3 in response to the second scan signal S2'. The storage capacitor Cst may be electrically connected between the high power supply voltage ELVDD supply and the third node N3, and may store a data signal supplied to the third node N3.

The fourth transistor T4 is used to reset the gate Gate of the driving transistor T1, the fourth transistor T4 can be electrically connected between the fourth node N4 and the supply of the first reference voltage line Vref1, and can respond to the first scanning line S1 The signal is turned on. Here, the storage capacitor Cst may be initialized to charge (or have) a voltage. In one embodiment, the third transistor T3 and the fourth transistor T4 are made of Indium Gallium Zinc Oxide (IGZO), which has a small leakage current during operation and improves the stability of the pixel circuit. Other transistors can be made of Low Temperature Poly-Silicon (LTPS).

The fifth transistor T5 is used to control the light emitting element to emit light in the light emitting stage, the fifth transistor T5 may be electrically connected between the high power supply voltage ELVDD supply and the first node N1, and may be turned on in response to the light emitting control signal EM.

The sixth transistor T6 is used to control the light-emitting element to emit light in the light-emitting stage, the sixth transistor T6 may be electrically connected between the second node N2 and the fifth node N5, and may be turned on in response to the light-emitting control signal EM. That is, the fifth transistor T5 and the sixth transistor T6 may form a current path supplied from the high power voltage line ELVDD to the light emitting element in response to the light emitting control signal EM.

The seventh transistor T7 is used to reset the light emitting element, the seventh transistor T7 can be electrically connected between the second reference voltage line Vref2 supply and the fifth node N5, and can be turned on in response to the signal of the initial scanning line S0 . That is, the seventh transistor T7 may form a bypass path (or a bypass route) between the fifth node N5 and the supply of the second voltage line Vref2 in response to the initial scan signal S0. Wherein, the light emitting element EL may be an organic light emitting diode EL.

The eighth transistor T8 is used to reset the source of the driving transistor T1, and shares a gate line with the seventh transistor T7. The eighth transistor T8 may be electrically connected between the first node N1 and the third reference voltage line Vref3, and may be turned on in response to the initial scan signal S0. Reset the source Source of the drive transistor T1.

The organic light emitting diode EL may be electrically connected between the fifth node N5 and the low power supply voltage ELVSS supply. Similarly, the anode of the organic light emitting diode EL can be electrically connected to the fifth node N5, and the cathode of the organic light emitting diode EL can be electrically connected to the low power supply voltage ELVSS. The organic light emitting diode EL may emit light based on a current (ie, a driving current) transferred through the driving transistor T1. The organic light emitting diode EL cooperates with a storage capacitor Cst, which can be represented as a parasitic capacitor electrically connected in parallel with the organic light emitting diode EL, as shown in FIG. 3 .

The present application also provides a display panel, which includes the array substrate in the above embodiments. This embodiment provides an array substrate, which can be applied to the following display panels, such as electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, smart bracelets, smart watches, super personal Mobile or fixed terminals such as computers and navigators. The array substrate may be an organic light-emitting diode (Organic Light-Emitting Diode, referred to as OLED) array substrate, a micro light-emitting diode (Micro Light-Emitting Diode, referred to as Micro LED or μLED) array substrate, or a liquid crystal (Liquid Crystal Display, referred to as LCD) array substrate.

The above is only the implementation of the application, and does not limit the patent scope of the application. Any equivalent structure or equivalent process conversion made by using the specification and drawings of the application, or directly or indirectly used in other related technologies fields, are all included in the scope of patent protection of this application in the same way.

Claims (10)

1. An array substrate, comprising:

a plurality of pixel driving circuits arranged in an array along a first direction and a second direction; in the first direction, at least part of two adjacent pixel driving circuits are arranged in a mirror symmetry mode, and a light-transmitting area is formed between the two pixel driving circuits arranged in the mirror symmetry mode;

a plurality of lead-out voltage lines in which the plurality of pixel driving circuits located in the same column form a pixel column in the second direction; at least part draw forth the voltage line and be two that mirror symmetry set up pixel drive circuit place two extend between the pixel row, just draw forth the voltage line and be in corresponding the position in printing opacity district is provided with the partition region.

2. The array substrate of claim 1,

and one leading-out voltage wire is arranged between the pixel columns where the two pixel driving circuits are arranged in mirror symmetry.

3. The array substrate of claim 2, further comprising:

a plurality of reference voltage lines extending in the first direction and electrically connected to the pixel driving circuit; wherein one of the lead-out voltage lines is electrically connected to one of the reference voltage lines;

preferably, the reference voltage lines include a first reference voltage line, a second reference voltage line, and a third reference voltage line, and the lead-out voltage line is electrically connected to one of the first reference voltage line, the second reference voltage line, and the third reference voltage line.

4. The array substrate of claim 3,

in the first direction, the array substrate comprises a plurality of extraction voltage lines, and the extraction voltage lines are sequentially and alternately electrically connected with the reference voltage lines;

two that adjacent and be mirror symmetry setting between the pixel row at pixel drive circuit place, can set gradually with the difference the voltage line of drawing forth that the reference voltage line links to each other, draw forth the voltage line with the reference voltage line is the latticed design.

5. The array substrate of claim 1, further comprising:

and the data lines extend along the second direction, and the data lines adjacent to the light transmission area are bent along the periphery of the light transmission area.

6. The array substrate of claim 4,

the leading-out voltage line and the first reference voltage line are located in different metal layers; and/or the leading-out voltage line and the second reference voltage line are positioned in different metal layers; and/or the leading-out voltage line and the third reference voltage line are located in different metal layers;

preferably, the pull-out voltage line, the first reference voltage line, the second reference voltage line, and the third reference voltage line are located in different metal layers, respectively;

preferably, the metal layer where the first reference voltage line is located between the third reference voltage line and the metal layer where the drawn-out voltage line is located, and the metal layer where the second reference voltage line is located on a side, away from the first reference voltage line, of the metal layer where the third reference voltage line is located.

7. The array substrate of claim 1,

the shape of the light-transmitting area is the same as that of the photosensitive element positioned below the light-transmitting area;

preferably, the photosensitive element and the light-transmitting region are circular in shape.

8. The array substrate of claim 2, wherein the pixel driving circuit comprises:

a charging circuit; for charging the drive transistor and writing data;

a light emitting circuit; realizing light emission of the light emitting element in response to a signal of the light emission control signal;

and the reset circuit resets the transistors in the pixel driving circuit and comprises a plurality of reference voltage lines.

9. The array substrate of claim 8,

the reset circuit comprises a first reference voltage line, a second reference voltage line and a third reference voltage line, wherein the first reference voltage line is connected with the gate of the driving transistor and is used for resetting the gate of the driving transistor;

the second reference voltage line is connected with the anode of the light-emitting element and is used for resetting the anode of the light-emitting element;

the third reference voltage line is connected with the drain electrode of the driving transistor and is used for resetting the source electrode of the driving transistor;

preferably, the charging circuit includes a data line, a second transistor, the driving transistor and a third transistor, a drain of the second transistor is connected to the data line, a source of the second transistor is connected to a drain of the driving transistor, a source of the driving transistor is connected to a source of the third transistor, and a drain of the third transistor is connected to a gate of the driving transistor;

preferably, the light emitting circuit includes a high power voltage line, a light emission control signal, a fifth transistor, the driving transistor, a sixth transistor, and the light emitting element; a source of the fifth transistor is connected to the high power voltage line, a gate of the fifth transistor is connected to the emission control signal, a drain of the fifth transistor is connected to a drain of the driving transistor, a source of the driving transistor is connected to a source of the sixth transistor, a gate of the sixth transistor is connected to the emission control signal, and a drain of the sixth transistor is connected to an anode of the light emitting element.

10. A display panel, comprising:

an array substrate as claimed in any one of claims 1 to 9.

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