CN115801003B - Multi-step analog-to-digital converter and implementation method thereof - Google Patents

Abstract

The invention discloses a multi-step analog-to-digital converter and its implementation method, which improves the structure of the incremental zoom-type analog-to-digital converter, and adopts the noise-shaping successive approximation analog-to-digital converter to refine the analog-to-digital converter; Includes: a multi-bit digital ramp ADC with digital prediction, a multi-bit multi-order noise-shaping successive approximation ADC, and a configurable floating voltage-domain amplifier. The present invention adopts the working mode of one-time sampling and multiple conversions, and configures the quantization process of the analog-to-digital converter as one rough quantization followed by multiple fine quantizations; With high input bandwidth and low data output delay, it can adapt to a variety of IoT application scenarios.

Description

A multi-step analog-to-digital converter and its realization method

technical field

The invention belongs to the technical field of integrated circuit design, and relates to the design technology of an analog-to-digital converter integrated circuit, in particular to a high-energy-efficiency and high-precision multi-step analog-to-digital converter structure and an implementation method thereof.

Background technique

In recent years, emerging applications such as the Internet of Things have put forward stricter requirements on the accuracy and energy efficiency of analog-to-digital converters (ADCs). Especially in the application of mobile devices, the energy-efficient successive approximation analog-to-digital converter (SARADC) is limited by the thermal noise of the comparator, which often reduces the accuracy of the entire system, while the high-precision Sigma-DeltaADC consumes A lot of energy, creating a bottleneck for the battery life of the device. At the same time, Sigma-DeltaADC requires a complex digital processing circuit, and the long data delay makes it impossible to obtain the quantization result of the input analog signal in real time, which is not conducive to the integration in the system. In order to solve the problem that ADCs are difficult to balance high precision and high energy efficiency, some new ADC structures such as zoom ADC (Zoom ADC) and noise shaping successive approximation analog-to-digital converter (NoiseShapingSARADC) have been proposed by designers in recent years. propose.

ZoomADC is a multi-step analog-to-digital converter. It uses low-power SARADC in the first stage and high-precision Sigma-Delta ADC in the second stage. Two-step refinement. After the coarse quantization is completed, the reference level range of the second-stage Sigma-DeltaADC is adjusted according to the coarse quantization result of the first-stage SARADC, so that the input signal falls within the reduced reference level range, thereby greatly reducing the Sigma-DeltaADC The input signal size of the loop filter in the DeltaADC reduces the power consumption of the loop filter and achieves energy-efficient refinement. However, in order to achieve high precision, the existing traditional ZoomADC requires a high oversampling rate, so that the second-stage Sigma-DeltaADC performs multiple conversions, but each conversion will destroy the residual voltage value stored on the first-stage SARADC, and resampling is required. In order to recover the residual voltage, the above-mentioned existing methods introduce a large number of repeated sampling operations to the quantization process of ZoomADC, resulting in a very slow conversion speed. Usually, only approximately constant or low-frequency input signals can be quantized, and it is difficult to adapt to various application scenarios. .

The existing NoiseShaping SARADC uses low-power SARADC as the quantizer of Sigma-DeltaADC, and utilizes the characteristics of SARADC that can perform multi-bit quantization, which greatly reduces its oversampling rate and improves the input bandwidth and applicability of the system. However, due to the absence of the first-level coarse quantization, the existing NoiseShaping SARADC usually requires a higher-order loop filter to meet the high-precision requirements at a lower oversampling rate, which significantly increases hardware overhead and design complexity.

Therefore, it is still very challenging to design ADCs that can be applied to emerging applications such as the Internet of Things and take into account high energy efficiency and high precision.

Contents of the invention

Aiming at the problems existing in the above prior art, the present invention provides a high-energy-efficiency and high-precision multi-step analog-to-digital converter and its implementation method. The proposed multi-step analog-to-digital converter circuit is a new type of incremental scaling mode The digital converter (Incremental ZoomADC) circuit, which uses the noise shaping successive approximation analog-to-digital converter (NoiseShapingSARADC) to carry out the second level of refinement in the scaling analog-to-digital converter (Zoom ADC), and the designed analog-to-digital converter adopts The working method of sampling once and converting multiple times can take into account high energy efficiency and high precision, and it also has medium input bandwidth and low data output delay, which can adapt to a variety of IoT application scenarios.

The present invention defines the following term names and corresponding English names:

Incremental Zoom ADC (IncrementalZoomADC);

Noise Shaping Successive Approximation Analog-to-Digital Converter (NoiseShapingSARADC)

Digital slope analog-to-digital converter (DigitalSlopeADC);

MSB (MostSignificantBit, most significant bit);

LSB ( Least Significant Bit, least significant bit);

The present invention proposes a multi-step analog-to-digital converter, which adopts NoiseShapingSARADC for fine quantization in the ZoomADC system in structure, and proposes to do one sampling in the ZoomADC system, then perform a rough quantization, and then perform multiple fine quantization conversions , to achieve the effect of one sampling and multiple conversions. Thereby, the quantization accuracy of the ZoomADC system is improved, and the power consumption of the fine quantization stage in the ZoomADC system is reduced. The present invention designs a novel NoiseShapingSARADC implementation method, which can reduce the hardware overhead and power consumption of the NoiseShapingSAR ADC. The present invention adopts a multi-stage digital prediction technology on the basis of the DigitalSlopeADC, and designs a DigitalSlopeADC with the multi-stage digital prediction technology, thereby reducing the capacitor switching power consumption in the DigitalSlopeADC. The invention improves based on the floating voltage domain amplifier, designs a configurable floating voltage domain amplifier, can configure the floating voltage domain amplifier according to different amplifier noise requirements, and reduces the power consumption of the floating voltage domain amplifier.

Technical scheme of the present invention is:

A kind of multi-step analog-to-digital converter, i.e. incremental scaling type analog-to-digital converter; The present invention improves this ADC structure on the form of incremental scaling type analog-to-digital converter, and main improvement is to adopt Noise Shaping SAR ADC to do this The refinement of various forms of ADC. The incremental scaling type analog-to-digital converter of the present invention comprises: a DigitalSlopeADC with digital prediction of a multi-bit, a NoiseShapingSARADC of a multi-bit multi-order and a configurable floating voltage domain amplifier; The DigitalSlopeADC with digital prediction of a multi-bit is used as the ADC system The first stage is the first step of coarse quantization; the multi-bit and multi-stage NoiseShapingSARADC is used as the second stage of the ADC system to perform the second step of fine quantization; a configurable floating voltage domain amplifier is embedded in the second stage to eliminate sampling noise And perform signal amplification between coarse quantization and fine quantization. in,

The multi-bit DigitalSlopeADC with digital prediction and the multi-bit multi-stage NoiseShapingSARADC share the same digital-to-analog converter (DAC) part. The DAC part is composed of two parts connected by the top plate of the capacitor array with different encoding methods. The two parts correspond to the Two ADCs are used, the one corresponding to DigitalSlopeADC is called coarse quantization DAC, and the one corresponding to NoiseShapingSARADC is called fine quantization DAC.

In specific implementation, the multi-bit DigitalSlopeADC with digital prediction is a 6-bit DigitalSlopeADC with 2nd-order digital prediction; the multi-bit multi-stage NS-SARADC is a 7-bit 2nd-order NS-SARADC.

The components in the incremental scaling analog-to-digital converter system proposed by the present invention are described in detail below:

A． Multi-bit DigitalSlopeADC with digital prediction;

During specific implementation, the present invention designs and adopts the Digital Slope ADC with second-order digital prediction to carry out coarse quantization, including four parts of sampling circuit, coarse quantization DAC, comparator and digital logic, and digital logic part is in existing DigitalSlope ADC The digital predictor (such as first-order, second-order or multi-order digital predictor) of the present invention is added on the basis of the digital logic, in order to adapt to the needs of multi-order digital predictors, the coarse quantization in the DigitalSlope ADC with multi-order digital prediction The DAC section is thermometer coded.

After the sampling circuit finishes sampling the input signal, the multi-bit DigitalSlopeADC with digital prediction begins to perform coarse quantization. The process is as follows: firstly, use the results of the last two coarse quantizations to perform second-order digital prediction on the input signal sampled this time, and the first negative time and the result of the 0th coarse quantization is considered to be zero, so that the second-order digital prediction of the first and second coarse quantization can also be performed. After the prediction result is obtained, the prediction result is first applied to the coarse quantization DAC; the subsequent Coarse quantization continues on the basis of the prediction result; use a comparator to compare the voltage on the top plate of the DAC with zero, and change the prediction result by one LSB according to the comparison result, that is, switch 1 unit capacitance in the coarse quantization DAC, every The process of comparing first and then switching is repeated every cycle. After a few cycles, the comparison result of the comparator is reversed (for example, the comparison result of the comparator in the previous few cycles is always positive, and the current comparison result becomes negative, which means a reversal occurs) , stop and get the result of this rough quantization.

Through analysis and simulation, in an ADC system with an oversampling rate of 8, using the 6-bit DigitalSlopeADC with second-order digital prediction of the present invention, after applying the prediction result to the coarse quantization DAC, only 6 unit capacitors need to be switched at most. That is, the rough quantization of the analog-to-digital converter can be completed in 6 cycles. Compared with the existing ZoomADC that uses SARADC for coarse quantization, it needs to switch all the capacitors in the coarse quantization DAC once and the switching direction is uncertain; in the specific implementation of the present invention, DigitalSlopeADC is combined with second-order digital prediction to improve, with two The Digital Slope ADC with high-order digital prediction only needs to switch the capacitor corresponding to the input signal, which greatly reduces the switching number and switching power consumption of the coarse quantization DAC.

B． Multi-bit and multi-order NoiseShapingSARADC

During specific implementation, the present invention designs and adopts the second-order NoiseShapingSARADC to perform fine quantization, which includes four parts of fine quantization DAC, comparator, loop filter and digital logic, and the loop filter part adopts the present invention to propose a A new loop filter implementation, the fine quantization DAC part adopts binary code.

After the coarse quantization is completed, the top plates of the coarse quantization DAC and the fine quantization DAC are the residual voltage of the coarse quantization; first, the residual voltage is amplified and added to the output voltage of the loop filter during the fine quantization process, The summing input comparator is compared with zero, and a capacitor in the refinement DAC is switched according to the comparison result. The process of first amplifying, then comparing and then switching is repeated every cycle. After 7 cycles, 7 capacitors in the refinement DAC are Capacitors are switched sequentially from large to small to complete this refinement. A loop filter update is triggered after each refinement.

The loop filter is a multi-order FIR filter (Finite Impulse Response, finite-length unit impulse response filter), and a second-order FIR filter can be used, which adopts the implementation method proposed by the present invention as follows: After the last refinement and the last refinement, the input of the loop filter is extracted and stored in two delay capacitors: delay capacitor 1 and delay capacitor 2, and delay capacitor 1 and delay capacitor 2 during this refinement The single-cycle delay of the last input signal to the loop filter and the double-cycle delay of the last input signal to the loop filter are saved respectively. Use the voltage values stored on the delay capacitor 1 and delay capacitor 2 to obtain the output of the loop filter during this refinement: connect the two capacitors in series to achieve two input signals on the loop filter The addition between the single-cycle delay and the double-cycle delay, when adding, also needs to multiply the single-cycle delay of the loop filter’s last input signal by a coefficient 2, which will save the last time of the loop filter The delay capacitor for the single-cycle delay of the input signal is split into two parts, and then the two capacitors are connected in series, and the final addition result is the output of the loop filter.

Two capacitors connected in series are connected to the output terminal of the configurable floating voltage domain amplifier in the form of capacitor stacking, and the addition of the output result of the loop filter and the output result of the configurable floating voltage domain amplifier is realized in this refinement process .

When the loop filter is updated after the refinement is completed, the input signal of the current cycle of the loop filter is extracted and saved to the third delay capacitor (delay capacitor 3) by the buffer, and the delay capacitor 3 is used for the next refinement. and the voltage value stored on the delay capacitor 1 to obtain a new loop filter output. After the next refinement is completed, the buffer is used to extract the input signal of the current period of the loop filter and save it on the delay capacitor 2, and use the voltage values stored on the delay capacitor 2 and delay capacitor 3 to obtain new loop filter output, and so on.

Compared with the existing loop filter implementation, the implementation of the loop filter proposed by the present invention can not only achieve high robustness and high precision noise shaping effect, but also can easily Extending the filter order to higher order reduces loop filter power consumption and hardware overhead.

C． Configurable Floating Voltage Domain Amplifier Design

The configurable floating voltage domain amplifier structure includes a power supply capacitor, a load capacitor, an amplifying tube, and a binary capacitor array; wherein, the power supply capacitor includes the first part of the power supply capacitor, the second part of the power supply capacitor, and the third part of the power supply capacitor; the load capacitor includes the first part of the load capacitor and the second part of the load capacitor and noise canceling capacitor;

The working process of the incremental scaling analog-to-digital converter of the present invention includes: a sampling stage, a coarse quantization stage, a fine quantization stage and an update loop filter stage; wherein the sampling stage, the fine quantization stage and the update loop filter stage are The three stages require the amplifier to have the same gain, but they have different requirements on the noise level of the amplifier. Among them, the sampling stage requires the smallest noise of the amplifier, followed by the update loop filter stage, and the fine quantization stage can tolerate Larger amplifier noise. When working, the configurable floating voltage domain amplifier proposed by the present invention includes:

In the sampling stage, the sampling noise is eliminated through the amplifier and the noise elimination capacitor, and the power supply capacitor is configured as the sum of the first part of the power supply capacitor, the second part of the power supply capacitor and the third part of the power supply capacitor; the load capacitor is configured as the first part of the load capacitor, the second part of the power supply capacitor The two parts of the load capacitor and the noise elimination capacitor are added together, so that the power consumption of the amplifier is the largest and the noise is the smallest;

In the refinement stage, the comparator noise is suppressed by amplifying the residual voltage, the power supply capacitor is configured as the first part of the power supply capacitor, and the load capacitor is configured as the first part of the load capacitor, so that the power consumption of the amplifier is the smallest and the noise is the largest;

In the update stage of the loop filter, the noise of the loop filter is suppressed by amplifying the residual voltage and the charge conservation on the capacitor DAC is ensured. The power supply capacitor is configured as the addition of the first part of the power supply capacitor and the second part of the power supply capacitor, and the load capacitor is configured as Add the first part of the load capacitance and the second part of the load;

Furthermore, another additional binary capacitor array is added and connected in parallel with the power supply capacitor, which is used to fine-tune the size of the power supply capacitor of the three-stage amplifier and calibrate the gain of the amplifier.

Compared with the non-configurable amplifier in the prior art solution, which needs to be designed to meet the minimum noise requirement, the configurable floating voltage domain amplifier of the present invention configures the parameters of the floating voltage domain amplifier for different noise requirements, and the amplifier power consumption Lower, which is beneficial to improve the energy efficiency of the ADC system.

The above-mentioned incremental scaling type analog-to-digital converter of the present invention configures the quantization process of the incremental ZoomADC to perform multiple fine quantization after a rough quantization; the implementation method includes the following steps:

1) Prepare a multi-bit DigitalSlopeADC, including four parts: sampling circuit, DAC, comparator and digital logic, and improve it based on the structure of the Digital Slope ADC. By adding multi-stage digital prediction elements to the digital logic part of the DigitalSlopeADC, a multi-bit Digital Slope ADC with digital prediction;

Structurally, a multi-bit Digital Slope ADC with multi-stage digital prediction is used for rough quantization;

2) Prepare a multi-bit and multi-order NoiseShapingSARADC, including four parts: DAC, loop filter, comparator and digital logic, among which the loop filter part adopts the new loop filter implementation method proposed by the present invention.

Use multi-bit multi-level NS-SAR ADC for fine quantization;

3) The multi-bit digital ramp analog-to-digital converter with digital prediction and the multi-bit, multi-order noise-shaping successive approximation analog-to-digital converter share the same digital-to-analog converter (DAC) component, which consists of two parts with different codes The top plate of the capacitor array is connected in the same way; among them, the digital-to-analog converter corresponding to the multi-bit digital ramp-type analog-to-digital converter with digital prediction is a coarse quantization digital-to-analog converter, which corresponds to the successive approximation analog-to-digital converter for noise shaping The digital-to-analog converter used by the converter is a fine-grained digital-to-analog converter;

4) Design and prepare a configurable floating voltage domain amplifier, that is, improve on the basis of the existing floating voltage domain amplifier; by splitting the power supply capacitance and load capacitance of the floating voltage domain amplifier into multiple parts, and in the digital logic of the amplifier Some control elements with multiple configurations are added to configure the power supply capacitor configuration and load capacitor, increase the configurable attributes of the amplifier, and configure it into different modes in different working stages according to different amplifier noise requirements.

A floating voltage domain amplifier is used for amplification between coarse quantization and fine quantization and sampling noise elimination.

5) The multi-bit Digital Slope ADC with multi-level digital prediction is used as the first-level ADC, the multi-bit multi-level NoiseShapingSARADC is used as the second-level ADC, and the first-level and second-level ADCs are performed through the top plate of the DAC component Connected, configurable floating voltage domain amplifier is embedded in the second-stage ADC, placed between the DAC and the loop filter, which is the improved IncrementalZoomADC.

Compared with prior art, the beneficial effect of the present invention:

The present invention provides an incremental scaling analog-to-digital converter, which uses multi-bit, multi-order NoiseShapingSARADC to carry out fine quantization in Zoom ADC. Compared with the traditional Zoom analog-to-digital converter, the analog-to-digital converter designed by the present invention can Taking into account high energy efficiency and high precision, it also has medium input bandwidth and low data output delay, and can adapt to a variety of IoT application scenarios.

Compared with the existing traditional ZoomADC, which requires re-sampling to restore the residual voltage after each fine-quantization, the incremental analog-to-digital converter proposed by the present invention can perform multiple fine-quantization after one coarse quantization without re-sampling , that is, one sampling and multiple conversions, which saves a lot of sampling operations, improves the input bandwidth of the system and greatly eases the requirements on the input drive circuit.

Compared with the existing implementation methods, the Noise Shaping SAR implementation method proposed by the present invention can not only achieve a stable noise shaping effect, but also reduce the hardware overhead and power consumption of the NS-SAR ADC.

The DigitalSlopeADC with multi-stage digital prediction technology proposed by the invention can reduce the capacitor switching power consumption in the existing DigitalSlopeADC.

Compared with the existing floating voltage domain amplifier, the configurable floating voltage domain amplifier proposed by the present invention can be configured into multiple modes according to different amplifier noise requirements, thereby reducing the power consumption of the floating voltage domain amplifier.

Description of drawings

Fig. 1 is the structural representation of the incremental scaling type analog-to-digital converter of the present invention;

in, is the input signal; For the sampling signal, the input signal is sampled when it is set high; It is a coarse quantization signal, and it will be coarse quantized when it is set high; It is a fine quantization signal, when it is set high, it will perform fine quantization; It is a reset signal, and it resets the system when it is set high.

FIG. 2 is a working sequence diagram of the incremental scaling analog-to-digital converter of the present invention.

FIG. 3 is a schematic circuit diagram of the incremental scaling analog-to-digital converter of the present invention.

FIG. 4 is a schematic diagram of the working process of the incremental scaling analog-to-digital converter of the present invention.

FIG. 5 is a schematic diagram of the working principle of the loop filter in the incremental scaling analog-to-digital converter of the present invention.

FIG. 6 is a circuit diagram of a configurable floating voltage domain amplifier in the ADC of the present invention.

Detailed ways

The present invention will be further described through specific embodiments below in conjunction with the accompanying drawings, but the scope of the present invention will not be limited in any way.

The incremental ZoomADC (incremental scaling analog-to-digital converter) proposed by the present invention includes a coarse quantization ADC and a fine quantization ADC, wherein the realization of the coarse quantization ADC is improved based on the DigitalSlopeADC (digital slope analog-to-digital converter), and the design into a multi-bit DigitalSlopeADC with second-order digital prediction. The fine quantization ADC is realized by NoiseShapingSARADC, and the coarse quantization ADC and the fine quantization ADC share a capacitor (DAC). The incremental scaling analog-to-digital converter structure proposed by the present invention not only has the technical advantages of NoiseShapingSARADC high energy efficiency and multi-bit quantization, but also utilizes the coarse quantization and reference level range adjustment technology in ZoomADC, and does not require high-order loops Filters can meet the high-precision requirements of analog-to-digital conversion.

As shown in Figure 1 and Figure 2, when the incremental ZoomADC of the present invention is specifically implemented, the first stage is a 6-bit DigitalSlopeADC for coarse quantization, the second stage is a 7-bit NoiseShapingSARADC for fine quantization, and a floating voltage domain amplifier Do inter-stage signal amplification and sampling noise elimination. DigitalSlopeADC and NoiseShapingSARADC share a DAC part. In a complete analog-to-digital conversion process of the incremental ZoomADC of the present invention, at first DigitalSlopeADC is to the input signal Sampling is performed and the sampling noise is eliminated with a floating voltage domain amplifier, and then the DigitalSlopeADC performs the first coarse quantization on the sampled input signal. After the rough quantization is completed, the floating voltage domain amplifier performs interstage amplification and uses NoiseShapingSARADC to perform 4 fine quantizations to achieve one sampling Subsequent multiple refinement transformations. This process is repeated eight times, and a total of 8 samples, 8 coarse quantizations, and 32 fine quantizations are performed to obtain 32 quantization results, and the 32 quantization results are processed by a sampling filter to obtain an analog-to-digital conversion result.

The ADC system circuit and working process of the present invention are shown in Figure 3 and Figure 4, and the whole ADC system includes the following 4 working stages:

1) Sampling stage:

exist When the level is high, the sampling switch is closed to connect the bottom plate of the DAC to the input signal on, the top plate is connected to the common mode level on, the amplifier and capacitor reset. exist time is set to low level, the DAC top plate switch is turned off, and the input signal and the first sampling noise Fixed on the DAC, and trigger the amplifier to start amplifying. exist time is asserted low, the sampling switch and capacitor switch off, the arrive Constantly changing input signal and the first sampling noise amplified and sampled to a capacitive Above, the sampling of the input signal and the elimination of sampling noise are completed.

2) Rough quantization stage:

After the sampling is completed, firstly according to the coarse quantization results of the last two sampling periods and The second-order prediction is performed on the input signal value of this sampling period, and the prediction result is , switches the bottom plate voltage in the DAC corresponding to the predicted number of units of capacitance. The comparator is then triggered to compare the top plate voltage of the DAC, and switch the bottom plate voltage of one unit capacitor in the DAC every conversion cycle according to the comparison result. After comparing several conversion cycles and detecting that the comparison result is reversed, perform another comparison and switch the compensation capacitor with a size of 0.5 unit capacitance in the DAC to complete the coarse quantization and obtain the coarse quantization result of this sampling period .

3) Refinement stage

In each conversion cycle of the refinement stage, the amplifier is first triggered to amplify the residual voltage on the top plate of the DAC, and the amplified signal is superimposed on the noise elimination capacitor After passing through the FIR filter, it is input to the comparator, and the bottom plate voltage of the corresponding bit in the DAC is switched according to the comparison result to complete a conversion cycle, and the process is repeated 7 times to complete a refinement.

4) Loop filter update stage

The loop filter is realized by a second-order FIR filter, in the first In sub-refinement, the capacitor in the filter and Save the feedback signal after the last refinement is completed ,capacitance and Save the feedback signal after the last refinement is completed , the capacitor and connected in parallel, and with a capacitor and Reverse concatenation, you can get output of the second-order FIR filter. complete the first After the second refinement, the FIR filter needs to be updated once. First, the amplifier is triggered to amplify the residual voltage on the top plate of the DAC after the refinement is completed, and the amplified signal is superimposed on the capacitor And after passing through the FIR filter, the feedback signal after the refinement is completed , which is held by the buffer in the capacitive and On, and carry out the capacitive circular shift operation, use the capacitive and replacement capacitor and position, with a capacitor and replacement capacitor and position, with a capacitor and replacement capacitor and position, you can complete the first Secondary loop filter update. In the next refinement, that is, the In the second refinement, the first The output value of the FIR filter feedback after the second update is updated as , complete the first The feedback signal after sub-refinement is saved in the capacitor through the buffer and , and move the capacitor position cyclically again. The second-order FIR filter can be updated by repeating the operation of saving the feedback signal and shifting the capacitance after each refinement.

After the loop filter is updated, reset the DAC bottom plate voltage corresponding to the finer ADC.

In the four working stages of the ADC system of the present invention, the amplifier is used in the sampling stage, the refinement stage and the loop filter update stage, and the amplifier of the present invention adopts a configurable floating voltage domain amplifier structure as shown in Figure 6 implementation, where the supply capacitor Contains the first part of the supply capacitor , the second part of the power supply capacitor and the third part of the supply capacitor Three parts, load capacitance then contains the first part of the load capacitance and the second part of the load capacitance two parts. During the sampling phase, the amplifier is most sensitive to noise, so the supply capacitor is configured as , the load capacitance is configured as , the power consumption of the amplifier is the largest and the noise is the smallest; in the refinement stage, the noise of the amplifier will be shaped to tolerate larger noise, so the power supply capacitor is configured as , the load capacitance is configured as , the amplifier consumes the least power and is the most noisy; during the update phase of the loop filter, the amplifier has moderate noise and power consumption, and the supply capacitor is configured as , the load capacitance is configured as . An additional binary capacitor array is added and connected in parallel with the power supply capacitor to fine-tune the size of the power supply capacitor of the three-stage amplifier and calibrate its gain. After a factory calibration, the amplifier gain can meet the design requirements.

It should be noted that the purpose of the disclosed embodiments is to help further understanding of the present invention, but those skilled in the art can understand that various replacements and modifications are possible without departing from the scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the protection scope of the present invention is subject to the scope defined in the claims.

Claims (9)

1. A multi-step analog-to-digital converter is characterized in that the structure of an incremental scaling analog-to-digital converter is improved, and a noise shaping successive approximation type analog-to-digital converter (Noise Shaping SAR ADC) is adopted for fine quantization of the analog-to-digital converter; comprising the following steps: a multi-bit digital ramp analog-to-digital converter (digital slopeADC) with digital prediction, a multi-bit multi-order noise shaping successive approximation analog-to-digital converter, and a configurable floating voltage domain amplifier; realizing one-time sampling and multiple conversion, namely performing one-time coarse quantization after one-time sampling, and performing multiple-time fine quantization conversion;

the multi-bit digital slope analog-to-digital converter with digital prediction is used as a first stage of the multi-step analog-to-digital converter and is used for performing first-step coarse quantization; the multi-bit multi-order noise shaping successive approximation type analog-to-digital converter is used as a second stage of the multi-step analog-to-digital converter and is used for performing second-step fine quantization; a configurable floating voltage domain amplifier embedded in the second stage for removing sampling noise and performing signal amplification between coarse quantization and fine quantization;

the multi-bit digital slope analog-to-digital converter with digital prediction and the multi-bit multi-order noise shaping successive approximation analog-to-digital converter share the same digital-to-analog converter component, and the component is formed by connecting two parts of capacitor array top polar plates adopting different coding modes; the digital-to-analog converter used for the digital slope analog-to-digital converter with digital prediction is a coarse quantization digital-to-analog converter, and the digital-to-analog converter used for the noise shaping successive approximation analog-to-digital converter is a fine quantization digital-to-analog converter;

A. the digital ramp type analog-to-digital converter with digital prediction comprises: a sampling circuit section, a coarse quantization digital-to-analog converter section, a comparator section, and a digital logic section; wherein the digital logic portion incorporates a multi-order digital predictor; the coarse quantization digital-to-analog converter part adopts thermometer coding;

B. the multi-bit multi-order noise shaping successive approximation type analog-to-digital converter comprises a fine quantization digital-to-analog converter part, a comparator part, a loop filter part and a digital logic part; wherein the loop filter part adopts a novel loop filter; the fine quantization digital-to-analog converter part adopts binary coding;

the novel loop filter is a multi-order finite length unit impulse response filter, and the order of the filter can be expanded to a higher order by only one buffer; the method specifically comprises the following steps:

extracting and storing the input of the loop filter after the last fine quantization and the last fine quantization are completed on two delay capacitors, wherein the two delay capacitors respectively store single-period delay of the last input signal of the loop filter and double-period delay of the last input signal of the loop filter;

the output of the loop filter at the current fine quantization is obtained by using the voltage values stored on the two delay capacitors: the two capacitors are connected in series through the capacitor, the single-period delay and the double-period delay of the two input signals on the loop filter are added, the single-period delay of the last input signal of the loop filter is multiplied by a set coefficient, the delay capacitor which holds the single-period delay of the last input signal of the loop filter is split, and the capacitors are connected in series; the addition result is the output of the loop filter;

C. the configurable floating voltage domain amplifier structure comprises a power supply capacitor, a load capacitor, an amplifying tube and a binary capacitor array; the power supply capacitor comprises a first part of power supply capacitor, a second part of power supply capacitor and a third part of power supply capacitor; the load capacitor comprises a first partial load capacitor, a second partial load capacitor and a noise elimination capacitor;

the configurable floating voltage domain amplifier can be configured with noise of different sizes while realizing gains of the same size at different stages of the working process of the incremental scaling analog-to-digital converter; the configurable floating voltage domain amplifier, in operation, comprises:

in the sampling stage, sampling noise is eliminated through an amplifier and a noise elimination capacitor, and a power supply capacitor is configured to be added up by a first part of power supply capacitor, a second part of power supply capacitor and a third part of power supply capacitor; the load capacitor is configured to be added by the first partial load capacitor, the second partial load capacitor and the noise elimination capacitor, so that the power consumption of the amplifier is maximum and the noise is minimum;

in the fine quantization stage, the residual voltage is amplified to inhibit the noise of the comparator, the power supply capacitor is configured as a first part of power supply capacitor, and the load capacitor is configured as a first part of load capacitor, so that the power consumption of the amplifier is minimum and the noise is maximum;

in the loop filter updating stage, loop filter noise is suppressed by amplifying the residual voltage, and conservation of charge of a capacitor in the digital-to-analog converter is ensured, a power supply capacitor is configured to be added by a first part of power supply capacitor and a second part of power supply capacitor, and a load capacitor is configured to be added by a first part of load capacitor and a second part of load.

2. The multi-step analog-to-digital converter of claim 1, wherein the multi-bit band digitally predicted digital ramp analog-to-digital converter is a 6-bit band 2-order digital prediction; the multi-bit, multi-order noise shaping successive approximation analog-to-digital converter is 7 bits, 2 orders.

3. A method for realizing a multi-step analog-to-digital converter is characterized by designing a multi-step analog-to-digital converter, namely an incremental scaling analog-to-digital converter, configuring the quantization process of the analog-to-digital converter into one-time sampling, performing one-time coarse quantization, and performing multiple-time fine quantization, namely one-time sampling and multiple-time conversion, wherein repeated sampling is not needed between the fine quantization; the implementation method comprises the following steps:

1) Preparing a multi-bit digital slope type analog-to-digital converter with digital prediction;

the structure of the digital slope analog-to-digital converter is improved, and a multi-order digital prediction element is added to a digital logic part in the digital slope analog-to-digital converter to prepare the digital slope analog-to-digital converter with multi-bit digital prediction, wherein the digital slope analog-to-digital converter comprises a sampling circuit, a digital-to-analog converter, a comparator and digital logic and is used for coarse quantization;

2) Preparing a multi-bit and multi-step noise shaping successive approximation type analog-to-digital converter for fine quantization, wherein the multi-bit and multi-step noise shaping successive approximation type analog-to-digital converter comprises a digital-to-analog converter, a loop filter, a comparator and a digital logic part; wherein the loop filter part adopts a novel loop filter; the novel loop filter specifically comprises:

extracting and storing the input of the loop filter after the last fine quantization and the last fine quantization are completed on two delay capacitors, wherein the two delay capacitors respectively store single-period delay of the last input signal of the loop filter and double-period delay of the last input signal of the loop filter;

the output of the loop filter at the current fine quantization is obtained by using the voltage values stored on the two delay capacitors: the two capacitors are connected in series through the capacitor, the single-period delay and the double-period delay of the two input signals on the loop filter are added, the single-period delay of the last input signal of the loop filter is multiplied by a set coefficient, the delay capacitor which holds the single-period delay of the last input signal of the loop filter is split, and the capacitors are connected in series; the addition result is the output of the loop filter;

3) The multi-bit digital slope analog-to-digital converter with digital prediction and the multi-bit multi-order noise shaping successive approximation analog-to-digital converter share the same digital-to-analog converter component, and the component is formed by connecting two parts of capacitor array top polar plates adopting different coding modes; the digital-to-analog converter used for the digital slope analog-to-digital converter with digital prediction is a coarse quantization digital-to-analog converter, and the digital-to-analog converter used for the noise shaping successive approximation analog-to-digital converter is a fine quantization digital-to-analog converter;

4) Designing and preparing a configurable floating voltage domain amplifier; the method is used for amplifying and sampling noise elimination between coarse quantization and fine quantization;

an improvement over existing floating voltage domain amplifiers; the power supply capacitor and the load capacitor of the floating voltage domain amplifier are divided into a plurality of parts, and a plurality of configuration control elements are added into the digital logic part of the amplifier, so that the configuration of the power supply capacitor and the load capacitor is carried out, the configurable property of the amplifier is increased, and the power supply capacitor and the load capacitor are configured into different modes in different working stages according to different noise requirements of the amplifier;

5) Connecting a digital slope analog-to-digital converter with multi-bit and multi-order digital prediction and a multi-bit and multi-order noise shaping successive approximation analog-to-digital converter through a top polar plate of a digital-to-analog converter component; the configurable floating voltage domain amplifier is embedded in the multi-bit and multi-order noise shaping successive approximation type analog-digital converter and is arranged between the digital-analog converter and the loop filter, so that the improved incremental scaling type analog-digital converter is obtained.

4. A method for implementing a multi-step analog-to-digital converter as defined in claim 3, wherein after the sampling circuit samples the input signal, the multi-bit digital ramp analog-to-digital converter with digital prediction performs a coarse quantization process comprising:

firstly, performing second-order digital prediction on the sampled input signal by using the result of the previous two times of coarse quantization;

the result of the first and zeroth coarse quantization is zero;

after obtaining the prediction result, firstly applying the prediction result to a coarse quantization digital-to-analog converter;

coarse quantization is then performed: comparing the voltage on the top polar plate of the coarse quantization digital-to-analog converter with zero by using a comparator, and changing a prediction result by one LSB according to the comparison result, namely switching 1 unit capacitor in the coarse quantization digital-to-analog converter;

repeating the process of comparing and switching once in each period;

after a few periods, the comparison result of the comparator is overturned, the operation is stopped, and the result of the current coarse quantization is obtained.

5. The method of claim 4, wherein the top plates of the coarse digital-to-analog converter and the fine digital-to-analog converter are both coarse quantized residual voltages after coarse quantization.

6. The method of implementing a multi-step analog-to-digital converter of claim 5, wherein the residual voltage is first amplified and the output voltage of the loop filter during the current fine quantization is added, and the added input comparator is compared with zero;

switching one capacitor in the fine quantization digital-to-analog converter according to the comparison result;

repeating the process of amplifying, comparing and switching once in each period;

after a plurality of periods, the capacitance in the fine quantization digital-to-analog converter is sequentially switched from large to small, so that the fine quantization is completed;

the loop filter update is triggered after each fine quantization is completed.

7. A method of implementing a multi-step analog-to-digital converter as claimed in claim 3, wherein the configurable floating voltage domain amplifier is operative to include:

in the sampling stage, sampling noise is eliminated through an amplifier and a noise elimination capacitor, and a power supply capacitor is configured to be added up by a first part of power supply capacitor, a second part of power supply capacitor and a third part of power supply capacitor; the load capacitor is configured to be added by the first partial load capacitor, the second partial load capacitor and the noise elimination capacitor, so that the power consumption of the amplifier is maximum and the noise is minimum;

in the fine quantization stage, the residual voltage is amplified to inhibit the noise of the comparator, the power supply capacitor is configured as a first part of power supply capacitor, and the load capacitor is configured as a first part of load capacitor, so that the power consumption of the amplifier is minimum and the noise is maximum;

in the loop filter update phase, loop filter noise is suppressed and conservation of charge on the capacitor DAC is ensured by amplifying the residual voltage, the supply capacitor is configured as a first partial supply capacitor and a second partial supply capacitor added, and the load capacitor is configured as a first partial load capacitor and a second partial load added.

8. The method of implementing a multi-step analog-to-digital converter of claim 1, wherein two capacitors connected in series are connected to the output of the configurable floating voltage domain amplifier in a stacked manner to effect addition of the loop filter output result to the amplifier output result during the current fine quantization.

9. The method for implementing a multi-step analog-to-digital converter of claim 8, wherein when the loop filter is updated after the current fine quantization is completed, the buffer is used to extract and store the input signal of the loop filter in the present period onto the third delay capacitor, and the voltage values stored on the third delay capacitor and the first delay capacitor are used to obtain a new loop filter output in the next fine quantization; and after the next fine quantization is finished, the buffer is used for extracting and storing the input signal of the loop filter in the period of the loop filter on the second delay capacitor, and the voltage values stored on the second delay capacitor and the third delay capacitor are used for obtaining a new loop filter output in the next fine quantization.

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