CN115766526A - Test method, device and electronic equipment for switch physical layer chip - Google Patents

Abstract

The invention provides a method and a device for testing a physical layer chip of a switch and electronic equipment, wherein the method comprises the following steps: configuring each PHY port of a physical layer PHY chip to be in a loopback state through a management data clock MDC interface and a management data input/output MDIO interface; and obtaining a port test result of each PHY port by carrying out linear speed flow test on each PHY port, wherein the port test result is used for indicating whether the PHY port passes the test or not. According to the invention, each PHY port of the PHY chip can be configured to be in a loopback state through the MDC interface and the MDIO interface, so that linear speed flow test can be carried out on each PHY port, test case data sent to each PHY port of the PHY chip in the test process can be analyzed through loopback of the PHY chip, the port test result of each PHY port can be obtained, an external jig is not required in the test process, and the test efficiency can be improved.

Description

Test method, device and electronic equipment for switch physical layer chip

technical field

The invention relates to the technical field of computers, in particular to a test method, device and electronic equipment for a switch physical layer chip.

Background technique

The physical layer (Physical Layer, PHY) of the switch processes the data of the media access control layer (Media Access Control, MAC), converts the parallel data into serial data, encodes according to the rules of the physical layer, and then turns it into an analog signal to send the data out , and can realize part of the Carrier Sense Multiple Access/Collision Detection (CSMA/CD) function with collision detection, which is an important part of the switch. With the development of network technology, the use of PHY chips on switches is increasing.

The PHY port test technology in the related art mostly uses external fixtures (such as optical modules, eload and other fixtures), and connects the sending (tx) port and receiving (rx) port of each lane through a DC blocking capacitor, and then conducts traffic Test, the test efficiency is low.

Contents of the invention

Aiming at the problems existing in the prior art, embodiments of the present invention provide a test method, device and electronic equipment for a physical layer chip of a switch.

In a first aspect, the present invention provides a method for testing a physical layer chip of a switch, comprising: configuring each PHY port of the physical layer PHY chip to be in a loopback state through a management data clock MDC interface and a management data input and output MDIO interface;

By performing a wire-speed flow test on each PHY port, a port test result of each PHY port is obtained, and the port test result is used to indicate whether the PHY port passes the test.

Optionally, according to a method for testing a switch physical layer chip provided by the present invention, the port test results of each PHY port are obtained by performing a wire-speed flow test on each PHY port, including:

Obtain the connection status of each PHY port;

If it is determined that the connection state of each PHY port is a connection establishment state, then send the test case data to each PHY port through the sending TX port of the MAC of the medium access control layer;

Receive the loopback data of each PHY port through the receiving RX port of the MAC;

Based on the test case data, the loopback data of each PHY port and the connection state monitoring data of each PHY port, the port test results of each PHY port are obtained.

Optionally, according to a method for testing a physical layer chip of a switch provided by the present invention, the data of each PHY port is obtained based on the test case data, the loopback data of each PHY port, and the connection status monitoring data of each PHY port. Port test results, including:

Based on the test case data and the loopback data of each PHY port, determine the difference information of the number of sending and receiving packets of each PHY port and the error packet information of each PHY port;

Based on the connection state monitoring data of each PHY port, the difference information of the number of sent and received packets, and the error packet information, it is judged whether each PHY port has passed the test, and the port test result of each PHY port is obtained.

Optionally, according to the test method of a switch physical layer chip provided by the present invention, after the port test results of each PHY port are obtained by performing a wire-speed flow test on each PHY port, it also includes:

When the port test result of the target PHY port indicates that the target PHY port has failed the test, based on the connection status monitoring data of the target PHY port, the difference information of the number of sending and receiving packets, and the error packet information, determine the target failure keyword;

Obtain a target fault diagnosis instruction based on the target fault keyword and a fault table, the fault table is used to characterize the mapping relationship between the fault keyword and the fault diagnosis instruction, and the fault diagnosis instruction is used to assist in the diagnosis of a PHY port;

Obtaining fault diagnosis information of the target PHY port by executing the target fault diagnosis instruction;

The target PHY port is any PHY port of the PHY chip.

Optionally, according to a method for testing a physical layer chip of a switch provided in the present invention, after the acquisition of the fault diagnosis information of the target PHY port, it further includes:

Determine the fault reporting information of the target PHY port based on the connection state monitoring data of the target PHY port, the difference information of the number of sending and receiving packets, error packet information, and fault diagnosis information;

Sending the fault report information of the target PHY port to the server.

Optionally, according to a method for testing a switch physical layer chip provided by the present invention, it also includes:

Through the MDC interface and the MDIO interface, poll multiple registers of the PHY chip to obtain storage values of the multiple registers, the multiple registers include interrupt registers, control registers and status registers;

Based on the reference value of each register and the storage value of each register, determine the operation status information of the PHY chip, where the operation status information is used to indicate whether the PHY chip has a fault.

Optionally, according to a method for testing a physical layer chip of a switch provided in the present invention, after the determination of the operating state information of the PHY chip, it further includes:

In the case where the running state information indicates that the PHY chip is faulty, the storage values of each register are configured as reference values of each register.

In a second aspect, the present invention also provides a test device for a physical layer chip of a switch, comprising:

The first configuration module is used to configure each PHY port of the physical layer PHY chip to be in a loopback state through the management data clock MDC interface and the management data input and output MDIO interface;

The test module is used to obtain the port test result of each PHY port by performing a wire-speed flow test on each PHY port, and the port test result is used to indicate whether the PHY port passes the test.

In a third aspect, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and operable on the processor. When the processor executes the program, any of the above-mentioned The test method of the physical layer chip of the switch is described.

In a fourth aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method for testing a physical layer chip of a switch as described above is implemented.

The test method, device and electronic equipment of the physical layer chip of the switch provided by the present invention can configure each PHY port of the PHY chip to be in a loopback state through the MDC interface and the MDIO interface, and then can perform a line-speed flow test on each PHY port, and test The test case data sent to each PHY port of the PHY chip during the process can be looped back through the PHY chip, and then the loopback data of each PHY port can be analyzed, and the port test results of each PHY port can be obtained. The port test results can indicate the PHY port Whether the test is passed or not, the test process does not need to use external fixtures, which can improve the test efficiency.

Description of drawings

In order to more clearly illustrate the present invention or the technical solutions in the prior art, the accompanying drawings that need to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings in the following description are the present invention. For some embodiments of the invention, those skilled in the art can also obtain other drawings based on these drawings without creative effort.

Fig. 1 is the schematic flow sheet of the test method of switch physical layer chip provided by the present invention;

Fig. 2 is a schematic diagram of the hardware connection structure of the wire-speed flow test provided by the present invention;

Fig. 3 is the structural representation of the testing device of switch physical layer chip provided by the present invention;

Fig. 4 is a schematic structural diagram of an electronic device provided by the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention , but not all examples. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

FIG. 1 is a schematic flow chart of a test method for a physical layer chip of a switch provided by the present invention. As shown in FIG. 1 , the subject of the test method for a physical layer chip of a switch may be an electronic device. The method includes:

Step 101, configure each PHY port of the physical layer PHY chip to be in a loopback state through the management data clock MDC interface and the management data input and output MDIO interface;

Specifically, in order to improve test efficiency, each PHY port of the PHY chip can be configured to be in a loopback state through a management data clock (Management Data Clock, MDC) interface and a management data input and output (Management Data Input Output, MDIO) interface. The test case data sent by each PHY port of the PHY chip can be looped back through the PHY chip.

It is understandable that through the MDC interface and the MDIO interface, each port of the PHY chip can be configured as a Lineinternal loopback, so that the traffic can be sent from the MAC port tx, then loop back through the PHY chip, and return to the MAC port rx, thereby The implementation does not rely on external fixtures for testing.

In step 102, the port test result of each PHY port is obtained by performing a wire-speed flow test on each PHY port, and the port test result is used to indicate whether the PHY port passes the test.

Specifically, after configuring each PHY port of the PHY chip to be in the loopback state, each PHY port can be tested for wire-speed traffic, and the test case data can be sent to each PHY port of the PHY chip during the test, and the test case data is used for Each PHY port is tested, and the loopback data of each PHY port can be analyzed through the loopback of the PHY chip, and the port test result of each PHY port can be obtained. The port test result can indicate whether the PHY port has passed the test.

For example, the PHY chip can include 3 PHY ports, which are port A, port B and port C respectively. Through the MDC interface and MDIO interface, port A, port B and port C can be configured to be in the loopback state. Port A, port B, and port C send test case data, and through the loopback of the PHY chip, the loopback data of port A, port B, and port C can be analyzed, and the port test results of each PHY port can be obtained.

The test method of switch physical layer chip provided by the present invention, through MDC interface and MDIO interface, each PHY port of PHY chip can be configured as the loopback state, and then each PHY port can be carried out wire-speed flow test, in the test process, send to PHY chip The test case data sent by each PHY port of the PHY chip can be looped back through the PHY chip, and then the loopback data of each PHY port can be analyzed, and the port test results of each PHY port can be obtained. The port test results can indicate whether the PHY port has passed the test. The process does not need to use external fixtures, which can improve the test efficiency.

Optionally, the present invention provides a method for testing a switch physical layer chip, wherein the port test results of each PHY port are obtained by performing a wire-speed flow test on each PHY port, including:

Obtain the connection status of each PHY port;

If it is determined that the connection state of each PHY port is a connection establishment state, then send the test case data to each PHY port through the sending TX port of the MAC of the medium access control layer;

Receive the loopback data of each PHY port through the receiving RX port of the MAC;

Based on the test case data, the loopback data of each PHY port and the connection state monitoring data of each PHY port, the port test results of each PHY port are obtained.

Specifically, after each PHY port of the PHY chip is configured to be in the loopback state, the connection (Link) state of each PHY port can be obtained, and it is judged whether the connection state of each PHY port is in the connection establishment state (Link up). The connection status of the PHY port is the connection establishment state, then the test case data can be sent to each PHY port through the sending TX port of the MAC, and the test case data is used to test each PHY port, and then through the receiving RX port of the MAC, you can Receive the loopback data of each PHY port, and then based on the test case data, the loopback data of each PHY port and the connection status monitoring data of each PHY port, the test situation of the PHY port can be analyzed, and the port test of each PHY port can be obtained result.

For example, the PHY chip may include two PHY ports, namely port A and port B. Through the MDC interface and the MDIO interface, port A and port B may be configured to be in a loopback state, and then it may be determined whether port A and port B are both in the loopback state. Link up, if it is determined that both port A and port B are in Link up, then send the test case data to port A and port B through the sending TX port of the MAC, and then receive the data of port A and port B through the receiving RX port of the MAC Loopback data, and then based on the test case data, the loopback data of port A and port B, and the connection status monitoring data of port A and port B, the test situation of port A and port B can be analyzed, and each PHY port can be obtained port test results.

Optionally, Fig. 2 is a schematic diagram of the hardware connection structure of the wire-speed flow test provided by the present invention, as shown in Fig. 2, the PHY chip can be connected to the CPU through the KR bus of the central processing unit (Central Processing Unit, CPU), and the PHY chip Can include physical medium attachment (Physical Medium Attachment, PMA) sublayer, physical medium dependent (Physical Medium Dependent, PMD) sublayer, physical coding sublayer (Physical Coding Sublayer, PCS), serializer (Serializer) and deserializer (De-Serializer). As shown in Figure 2, each PHY port of the PHY chip can be configured to be in the loopback state, and then the Lanconf tool can be combined with the Lanconf tool to perform line-speed sending and receiving packet testing on each PHY port, and count the number of sending and receiving packets and error packets of each port in real time Count and so on.

Therefore, after each PHY port of the PHY chip is configured to be in the loopback state, the test case data is sent to each PHY port through the TX port of the MAC, and the loopback data of each PHY port is received through the RX port of the MAC, which can realize the The automatic test of each PHY port, and the test process does not need to use external fixtures, which can improve the test efficiency.

Optionally, the present invention provides a method for testing a physical layer chip of a switch, wherein the port test of each PHY port is obtained based on the test case data, the loopback data of each PHY port, and the connection status monitoring data of each PHY port. Results, including:

Based on the test case data and the loopback data of each PHY port, determine the difference information of the number of sending and receiving packets of each PHY port and the error packet information of each PHY port;

Based on the connection state monitoring data of each PHY port, the difference information of the number of sent and received packets, and the error packet information, it is judged whether each PHY port has passed the test, and the port test result of each PHY port is obtained.

Specifically, by comparing the number of packets of the test case data and the number of packets of the loopback data, the difference information of the number of packets sent and received can be determined, and the loopback data can be checked (for example, Cyclic Redundancy Check (CRC)) The error packet information can be obtained, and then based on the connection status monitoring data of each PHY port, the difference information of the number of sent and received packets, and the error packet information, it can be judged whether each PHY port has passed the test, and then the port test result of each PHY port can be obtained.

Optionally, for a certain PHY port, if the connection state monitoring data indicates that the connection state of the PHY port changes to a disconnected state (Link down) during the test, it can be determined that the PHY port fails the test.

Optionally, for a certain PHY port, if the information about the difference in the number of sent and received packets indicates that the number of packets of the test case data is different from the number of packets of the loopback data, it can be determined that the PHY port has failed the test.

Optionally, for a certain PHY port, if the error packet information indicates that one or more data packets in the loopback data fail the check, it may be determined that the PHY port fails the test.

Optionally, for a certain PHY port, if the following three conditions are met at the same time, it can be determined that the PHY port has failed the test:

The first condition, the connection state monitoring data indicates that the connection state of the PHY port during the test is the connection establishment state;

The second condition, the information about the difference in the number of sent and received packets indicates that the number of packets of the test case data is the same as the number of packets of the loopback data;

The third condition is that the error packet information indicates that during the process of verifying the loopback data, all data packets in the loopback data pass the verification.

Therefore, by judging whether each PHY port has passed the test based on the connection status monitoring data of each PHY port, the difference information of the number of sent and received packets, and the error packet information, the automatic test of each PHY port can be realized, and the test process does not need to use external fixtures. Can improve test efficiency.

Optionally, the present invention provides a test method for a physical layer chip of a switch, after the port test results of each PHY port are obtained by performing a wire-speed flow test on each PHY port, it also includes:

When the port test result of the target PHY port indicates that the target PHY port has failed the test, based on the connection status monitoring data of the target PHY port, the difference information of the number of sending and receiving packets, and the error packet information, determine the target failure keyword;

Obtain a target fault diagnosis instruction based on the target fault keyword and a fault table, the fault table is used to characterize the mapping relationship between the fault keyword and the fault diagnosis instruction, and the fault diagnosis instruction is used to assist in the diagnosis of a PHY port;

Obtaining fault diagnosis information of the target PHY port by executing the target fault diagnosis instruction;

The target PHY port is any PHY port of the PHY chip.

Specifically, in order to obtain the cause of the failure of the PHY port, the port test results of each PHY port can be analyzed. If the port test result of the target PHY port of the PHY chip indicates that the target PHY port has failed the test, then the data can be monitored based on the connection status, sending and receiving packets. Quantity difference information and error packet information, extracting fault keywords to obtain target fault keywords used to characterize target PHY port fault conditions, and then query in the fault table based on target fault keywords to obtain target fault keywords The matching target fault diagnosis command can further execute the target fault diagnosis command to diagnose the target PHY port and obtain the fault diagnosis information of the target PHY port.

It can be understood that the fault table can represent the mapping relationship between fault keywords and fault diagnosis instructions, based on the target fault keywords, by querying in the fault table, the target fault diagnosis instructions matching the target fault keywords can be obtained. By analyzing historical test data, keywords can be extracted for various fault scenarios of PHY ports, and fault keywords can be obtained, which can represent a type of fault scenarios of PHY ports. For various fault scenarios of the PHY port, each fault diagnosis instruction can be pre-configured, and a fault diagnosis instruction can perform fault diagnosis for a type of fault scenario to assist in the diagnosis of the PHY port.

For example, the connection status monitoring data indicates that during the test, the connection status of the target PHY port changes from Link up to Link down, then the target fault keyword can include "abnormal connection status", and then based on this keyword, in the fault table Query, the target fault diagnosis instruction matching the keyword ("abnormal connection state") can be obtained.

For example, for the target PHY port, if the information on the difference in the number of sent and received packets indicates that the number of packets of the test case data is different from the number of packets of the loopback data, then the target fault keyword may include "the number of sent and received packets is inconsistent", and then based on the keyword , query in the fault table, and the target fault diagnosis instruction matching the keyword ("inconsistent number of sent and received packets") can be obtained.

For example, for the target PHY port, if the error packet information indicates that one or more data packets in the loopback data have not passed the check, the target fault keyword may include "CRC error occurs", and then based on this keyword, the Query in the table to obtain the target fault diagnosis instruction matching the keyword ("CRC error occurred").

For example, the target fault keyword may include "CRC error occurs", and the target fault diagnosis instruction matching this keyword may be for fault diagnosis in CRC error scenarios, and the target fault diagnosis instruction may obtain eye diagrams, bathtubs for the target PHY port Curve, CTLE parameters and Decision Feedback Equalizer (Decision Feedback Equalier, DFE) parameters, and then based on the preset range value, can judge the eye diagram, bathtub curve, continuous-time linear equalizer (Continuous-time linear equalizer, CTLE) parameters and DFE parameters Whether it is within the preset range, the fault diagnosis information of the target PHY port can be obtained.

Therefore, in the case that the PHY port fails the test, the target fault diagnosis instruction can be obtained by querying the fault table, and the fault diagnosis information can be obtained by running the target fault diagnosis instruction, which can automatically diagnose the fault of the PHY port, and the test process does not need to use External fixtures can improve test efficiency.

Optionally, the present invention provides a method for testing a physical layer chip of a switch, after the acquisition of the fault diagnosis information of the target PHY port, further comprising:

Determine the fault reporting information of the target PHY port based on the connection state monitoring data of the target PHY port, the difference information of the number of sending and receiving packets, error packet information, and fault diagnosis information;

Sending the fault report information of the target PHY port to the server.

Specifically, after obtaining the fault diagnosis information of the target PHY port, the information of the target PHY port can be collected, and the connection state monitoring data, the difference information of the number of sent and received packets, the error packet information and the fault diagnosis information can be packaged into the fault report information, and then can Send the fault reporting information of the target PHY port to the server.

Therefore, by sending the fault report information of the PHY port to the server, the server can collect and comprehensively analyze the fault information of each PHY chip.

Optionally, the present invention provides a method for testing a physical layer chip of a switch, further comprising:

Through the MDC interface and the MDIO interface, poll multiple registers of the PHY chip to obtain storage values of the multiple registers, the multiple registers include interrupt registers, control registers and status registers;

Based on the reference value of each register and the storage value of each register, determine the operation status information of the PHY chip, where the operation status information is used to indicate whether the PHY chip has a fault.

Specifically, in order to monitor the running status of the PHY chip in real time, multiple registers of the PHY chip can be polled through the MDC interface and the MDIO interface to obtain the storage values of multiple registers, and then the reference value of each register and the storage value of each register can be Values are compared to determine the operational status information of the PHY chip.

It can be understood that, in related technologies, the detection of the running state of the PHY chip is generally performed by sending code streams during the link idle phase, and the real-time performance is low. The invention polls a plurality of registers of the PHY chip through the MDC interface and the MDIO interface, and can monitor the running state of the PHY chip in real time.

For example, the stored value of the interrupt register (such as serdes interrupt register) can be compared with the reference value of the interrupt register, and if it is determined that the stored value of the interrupt register is different from the reference value of the interrupt register, it can be determined that the PHY chip is faulty.

For example, the stored value of the control register may be compared with the reference value of the control register, and if it is determined that the stored value of the control register is different from the reference value of the control register, it may be determined that the PHY chip is faulty.

For example, the stored value of the status register can be compared with the reference value of the status register, and if it is determined that the stored value of the status register is different from the reference value of the status register, it can be determined that the PHY chip is faulty.

Therefore, by polling multiple registers of the PHY chip through the MDC interface and the MDIO interface, real-time monitoring of the operating status of the PHY chip can be realized, and the test process does not need to use external fixtures, which can improve test efficiency.

Optionally, the present invention provides a method for testing a physical layer chip of a switch, after said determining the operating status information of said PHY chip, further comprising:

In the case where the running state information indicates that the PHY chip is faulty, the storage values of each register are configured as reference values of each register.

Specifically, after determining the operating status information of the PHY chip, it can be determined whether the PHY chip is faulty. If it is determined that the PHY chip is faulty, the PHY chip can be reset by configuring the storage value of each register as a reference value of each register. In order to restore the PHY chip to a normal operating state.

Optionally, the PHY chip debug tool that can run in the background of the switch can enable a thread to poll the PHY chip Serdes interrupt register, control register or status register, etc. through the MDC interface and MDIO interface. If there is an exception, it will automatically intervene and rewrite the register Value reconfiguration.

Therefore, in the case of a failure of the PHY chip, by configuring the storage value of each register as a reference value of each register, automatic intervention can be realized, with high real-time performance, and the impact of failure on business can be reduced.

The test method of switch physical layer chip provided by the present invention, through MDC interface and MDIO interface, each PHY port of PHY chip can be configured as the loopback state, and then each PHY port can be carried out wire-speed flow test, in the test process, send to PHY chip The test case data sent by each PHY port of the PHY chip can be looped back through the PHY chip, and then the loopback data of each PHY port can be analyzed, and the port test results of each PHY port can be obtained. The port test results can indicate whether the PHY port has passed the test. The process does not need to use external fixtures, which can improve the test efficiency.

The following is an optional example of the present invention, but not as a limitation of the present invention.

The CPU 10GBASE-KR makes a QSFP port through the PHY chip, configures the port as 4x10G, and records it as port1, port2, port3, and port4, and performs an automated test at a high temperature (about 45 degrees Celsius), which may include the following steps 401 to 403:

Step 401, configure internal loopback on all four ports of the PHY chip.

In step 402, it is detected that the port can link up normally after the loopback is configured, and the Lanconf tool is called to perform a transmit and receive test, and the port count is counted in real time.

Optionally, during the test, the real-time detection program running in the background finds by polling that the value of the LIVELNKSTAT1_00x20028 register is abnormal, the value is 0xFF0F, compared with the normal value, and written back to 0xFF87.

Step 403, according to the statistical information in step 402, it is determined that a CRC error occurs in port1 during the test, and the test program checks the fault table to find the fault diagnosis command "TRAFFIC_CRC" through the log (log) keyword "traffic crc occurred" According to the fault diagnosis instruction, firstly, through the MDC interface and the MDIO interface dump register (dump register refers to exporting and transferring the data of the register into a file or static form), obtain the Port1 eye diagram, determine that the eye height is small, and analyze the bathtub curve certainty If the jitter is large, then analyze the port CTLE or DFE and other training parameters to determine that there is a large difference compared with the normal port, and then determine that the initial value of CTLE is unreasonable, and return the result and collected information to the server.

The present invention configures the internal loopback on the PHY chip and combines the Lanconf tool to realize the automatic test of the PHY port without relying on other tooling fixtures, and the test program can automatically collect information and automatically analyze the cause of test failure by checking the fault table. Compared with traditional testing methods, it can reduce the cost of tooling, reduce manpower, and avoid damage to the environment that is not analyzed in time. The real-time polling of the PHY chip registers through the background program can detect the running status of the PHY chip in real time, and can automatically intervene without the user feeling, and will not affect the normal business.

The test device for the switch physical layer chip provided by the present invention is described below, and the test device for the switch physical layer chip described below and the test method for the switch physical layer chip described above can be referred to each other correspondingly.

Fig. 3 is a schematic structural diagram of a test device for a switch physical layer chip provided by the present invention. As shown in Fig. 3 , the device includes: a first configuration module 301 and a test module 302, wherein:

The first configuration module 301 is used to configure each PHY port of the physical layer PHY chip to be in a loopback state through the management data clock MDC interface and the management data input and output MDIO interface;

The test module 302 is configured to obtain a port test result of each PHY port by performing a wire-speed flow test on each PHY port, and the port test result is used to indicate whether the PHY port passes the test.

The test device of the switch physical layer chip provided by the present invention can configure each PHY port of the PHY chip to be in a loopback state through the MDC interface and the MDIO interface, and then can carry out a line-speed flow test to each PHY port, and send data to the PHY chip during the test. The test case data sent by each PHY port of the PHY chip can be looped back through the PHY chip, and then the loopback data of each PHY port can be analyzed, and the port test results of each PHY port can be obtained. The port test results can indicate whether the PHY port has passed the test. The process does not need to use external fixtures, which can improve the test efficiency.

Optionally, the test module is specifically used for:

Obtain the connection status of each PHY port;

If it is determined that the connection state of each PHY port is a connection establishment state, then send the test case data to each PHY port through the sending TX port of the MAC of the medium access control layer;

Receive the loopback data of each PHY port through the receiving RX port of the MAC;

Based on the test case data, the loopback data of each PHY port and the connection state monitoring data of each PHY port, the port test results of each PHY port are obtained.

Optionally, the test module is specifically used for:

Based on the test case data and the loopback data of each PHY port, determine the difference information of the number of sending and receiving packets of each PHY port and the error packet information of each PHY port;

Based on the connection state monitoring data of each PHY port, the difference information of the number of sent and received packets, and the error packet information, it is judged whether each PHY port has passed the test, and the port test result of each PHY port is obtained.

Optionally, the device further includes a fault diagnosis module, after obtaining the port test results of each PHY port by performing a wire-speed flow test on each PHY port, the fault diagnosis module is used for:

When the port test result of the target PHY port indicates that the target PHY port has failed the test, based on the connection status monitoring data of the target PHY port, the difference information of the number of sending and receiving packets, and the error packet information, determine the target failure keyword;

Obtain a target fault diagnosis instruction based on the target fault keyword and a fault table, the fault table is used to characterize the mapping relationship between the fault keyword and the fault diagnosis instruction, and the fault diagnosis instruction is used to assist in the diagnosis of a PHY port;

Obtaining fault diagnosis information of the target PHY port by executing the target fault diagnosis instruction;

The target PHY port is any PHY port of the PHY chip.

Optionally, the device further includes a sending module, after the acquisition of the fault diagnosis information of the target PHY port, the sending module is configured to:

Determine the fault reporting information of the target PHY port based on the connection state monitoring data of the target PHY port, the difference information of the number of sending and receiving packets, error packet information, and fault diagnosis information;

Sending the fault report information of the target PHY port to the server.

Optionally, the device also includes a running state monitoring module, and the running state monitoring module is used for:

Through the MDC interface and the MDIO interface, poll multiple registers of the PHY chip to obtain storage values of the multiple registers, the multiple registers include interrupt registers, control registers and status registers;

Based on the reference value of each register and the storage value of each register, determine the operation status information of the PHY chip, where the operation status information is used to indicate whether the PHY chip has a fault.

Optionally, the device further includes a second configuration module, after the determination of the operation state information of the PHY chip, the second configuration module is configured to:

In the case where the running state information indicates that the PHY chip is faulty, the storage values of each register are configured as reference values of each register.

The test device of the switch physical layer chip provided by the present invention can configure each PHY port of the PHY chip to be in a loopback state through the MDC interface and the MDIO interface, and then can carry out a line-speed flow test to each PHY port, and send data to the PHY chip during the test. The test case data sent by each PHY port of the PHY chip can be looped back through the PHY chip, and then the loopback data of each PHY port can be analyzed, and the port test results of each PHY port can be obtained. The port test results can indicate whether the PHY port has passed the test. The process does not need to use external fixtures, which can improve the test efficiency.

FIG. 4 is a schematic structural diagram of an electronic device provided by the present invention. As shown in FIG. 4, the electronic device may include: a processor (processor) 410, a communication interface (Communications Interface) 420, a memory (memory) 430 and a communication bus 440, Wherein, the processor 410 , the communication interface 420 , and the memory 430 communicate with each other through the communication bus 440 . The processor 410 can call the logical instructions in the memory 430 to execute the test method of the physical layer chip of the switch, for example, the method includes:

Through the management data clock MDC interface and the management data input and output MDIO interface, configure each PHY port of the physical layer PHY chip to be in the loopback state;

By performing a wire-speed flow test on each PHY port, a port test result of each PHY port is obtained, and the port test result is used to indicate whether the PHY port passes the test.

In addition, the above logic instructions in the memory 430 may be implemented in the form of software function units and be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the essence of the technical solution of the present invention or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program codes. .

On the other hand, the present invention also provides a computer program product. The computer program product includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can Execute the test method of the physical layer chip of the switch provided by each of the above methods, for example, the method includes:

Through the management data clock MDC interface and the management data input and output MDIO interface, configure each PHY port of the physical layer PHY chip to be in the loopback state;

By performing a wire-speed flow test on each PHY port, a port test result of each PHY port is obtained, and the port test result is used to indicate whether the PHY port passes the test.

In yet another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it is implemented to perform the test method for the physical layer chip of the switch provided by the above methods, For example the method includes:

Through the management data clock MDC interface and the management data input and output MDIO interface, configure each PHY port of the physical layer PHY chip to be in the loopback state;

By performing a wire-speed flow test on each PHY port, a port test result of each PHY port is obtained, and the port test result is used to indicate whether the PHY port passes the test.

The device embodiments described above are only illustrative, and the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in One place, or it can be distributed to multiple network elements. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. It can be understood and implemented by those skilled in the art without any creative efforts.

Through the above description of the implementations, those skilled in the art can clearly understand that each implementation can be implemented by means of software plus a necessary general hardware platform, and of course also by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the prior art can be embodied in the form of software products, and the computer software products can be stored in computer-readable storage media, such as ROM/RAM, magnetic discs, optical discs, etc., including several instructions to make a computer device (which may be a personal computer, server, or network device, etc.) execute the methods described in various embodiments or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (10)

1. A method for testing a switch physical layer chip, characterized in that it comprises: Through the management data clock MDC interface and the management data input and output MDIO interface, configure each PHY port of the physical layer PHY chip to be in the loopback state; By performing a wire-speed flow test on each PHY port, a port test result of each PHY port is obtained, and the port test result is used to indicate whether the PHY port passes the test. 2. according to the test method of the described switch physical layer chip of claim 1, it is characterized in that, described by carrying out wire-speed flow test to each PHY port, obtain the port test result of each PHY port, comprising: Obtain the connection status of each PHY port; If it is determined that the connection state of each PHY port is a connection establishment state, then send the test case data to each PHY port through the sending TX port of the MAC of the medium access control layer; Receive the loopback data of each PHY port through the receiving RX port of the MAC; Based on the test case data, the loopback data of each PHY port and the connection state monitoring data of each PHY port, the port test results of each PHY port are obtained. 3. according to the test method of the described switch physical layer chip of claim 2, it is characterized in that, described based on the loopback data of described test case data, each PHY port and the connection status monitoring data of each PHY port, obtain each PHY port Port test results, including: Based on the test case data and the loopback data of each PHY port, determine the difference information of the number of sending and receiving packets of each PHY port and the error packet information of each PHY port; Based on the connection state monitoring data of each PHY port, the difference information of the number of sent and received packets, and the error packet information, it is judged whether each PHY port has passed the test, and the port test result of each PHY port is obtained. 4. according to the testing method of switch physical layer chip described in any one of claim 1-3, it is characterized in that, after described by carrying out wire-speed flow test to each PHY port, after obtaining the port test result of each PHY port, also include: When the port test result of the target PHY port indicates that the target PHY port has failed the test, based on the connection status monitoring data of the target PHY port, the difference information of the number of sending and receiving packets, and the error packet information, determine the target failure keyword; Obtain a target fault diagnosis instruction based on the target fault keyword and a fault table, the fault table is used to characterize the mapping relationship between the fault keyword and the fault diagnosis instruction, and the fault diagnosis instruction is used to assist in the diagnosis of a PHY port; Obtaining fault diagnosis information of the target PHY port by executing the target fault diagnosis instruction; The target PHY port is any PHY port of the PHY chip. 5. the test method of switch physical layer chip according to claim 4, is characterized in that, after the fault diagnosis information of described target PHY port of described acquisition, also comprise: Determine the fault reporting information of the target PHY port based on the connection state monitoring data of the target PHY port, the difference information of the number of sending and receiving packets, error packet information, and fault diagnosis information; Sending the fault report information of the target PHY port to the server. 6. according to the testing method of switch physical layer chip described in any one of claim 1-3, it is characterized in that, also comprising: Through the MDC interface and the MDIO interface, poll multiple registers of the PHY chip to obtain storage values of the multiple registers, the multiple registers include interrupt registers, control registers and status registers; Based on the reference value of each register and the storage value of each register, determine the operation status information of the PHY chip, where the operation status information is used to indicate whether the PHY chip has a fault. 7. according to the test method of switch physical layer chip described in claim 6, it is characterized in that, after described determining the operation state information of described PHY chip, also comprise: In the case where the running state information indicates that the PHY chip is faulty, the storage values of each register are configured as reference values of each register. 8. A test device for a switch physical layer chip, characterized in that it comprises: The first configuration module is used to configure each PHY port of the physical layer PHY chip to be in a loopback state through the management data clock MDC interface and the management data input and output MDIO interface; The test module is used to obtain the port test result of each PHY port by performing a wire-speed flow test on each PHY port, and the port test result is used to indicate whether the PHY port passes the test. 9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and operable on the processor, wherein the processor according to claim 1 is implemented when executing the program. The test method for the switch physical layer chip described in any one of to 7. 10. A non-transitory computer-readable storage medium on which a computer program is stored, wherein when the computer program is executed by a processor, the physical layer chip of the switch according to any one of claims 1 to 7 is implemented. Test Methods.

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