CN115766351A - Digital front-end processing device, signal processing method and antenna equipment - Google Patents

Abstract

The disclosure provides a digital front-end processing device, a signal processing method of the digital front-end processing device, and antenna equipment, and belongs to the technical field of integrated circuits. The digital front-end processing device of the present disclosure is configured to process radio frequency signals transmitted by N transmission links between the baseband and the antenna unit, where N≥1, and N is an integer; in the N transmission links Each includes at least one sub-link; wherein, an equalizer and a channel evaluation unit are configured on the sub-link; the digital front-end processing device also includes a microprocessor; for any of the sub-links, the The channel evaluation unit is configured to evaluate the transmission channel of the radio frequency signal it receives, and send the evaluation result to the microprocessor, so that the microprocessor determines the filter coefficient according to the evaluation result; The equalizer is configured to filter the radio frequency signal according to the filter coefficient determined by the microprocessor.

Description

Digital front-end processing device, signal processing method, and antenna device

technical field

The disclosure belongs to the technical field of integrated circuits, and in particular relates to a digital front-end processing device, a signal processing method of the digital front-end processing device, and antenna equipment.

Background technique

In recent years, with the rapid development of integrated circuits and system-on-chip (SOC), high integration, ultra-wideband, and low power consumption have always been the direction of people's efforts, among which the conversion of analog signals to digital signals is the most important. Due to the complexity of the environment, the conversion of analog signals to digital signals requires multiple processing. As an electronic device that can adjust the amplification of electrical signals of various frequency components, the equalizer compensates for the analog signal by adjusting various electrical signals of different frequencies. Insufficient or saturated sampling.

Existing analog compensation and equalization solutions are only used to compensate the deviation of filter bandwidth caused by process deviation and temperature change, or require complex circuits to achieve bandwidth calibration. When using analog circuits to implement equalizers, it is difficult to guarantee performance; using software to implement equalization functions and algorithms requires high time costs.

Contents of the invention

The present invention aims to solve at least one of the technical problems in the prior art, and provides a digital front-end processing device, a signal processing method of the digital front-end processing device, and an antenna device.

In the first aspect, an embodiment of the present disclosure provides a digital front-end processing device configured to process radio frequency signals transmitted by N transmission links between the baseband and the antenna unit, where N≥1, And N is an integer; each of the N transmission links includes at least one sub-link; wherein, the sub-link is configured with an equalizer and a channel evaluation unit; the digital front-end processing device also includes a microprocessor device;

For any of the sub-links, the channel evaluation unit on it is configured to evaluate the transmission channel of the radio frequency signal it receives, and send the evaluation result to the microprocessor, so that the The microprocessor determines filter coefficients according to the evaluation result; the equalizer is configured to filter the radio frequency signal according to the filter coefficients determined by the microprocessor.

Wherein, the sub-link includes a sending link; the sending link includes a signal compensation unit,

The signal compensation unit is configured to initially compensate the radio frequency signal and send it to the equalizer, and the signal compensation unit is multiplexed as the channel evaluation unit in the transmission chain.

Wherein, the transmission link further includes a DC offset compensation unit;

The DC offset compensation unit is configured to perform DC offset compensation on the radio frequency signal filtered by the equalizer, and send the DC offset compensated radio frequency signal.

Wherein, the sub-link also includes a receiving link; the receiving link also includes a DC offset compensation unit;

The DC offset compensation unit is configured to perform DC offset compensation on the radio frequency signal and send it to the channel evaluation unit.

Wherein, the receiving chain includes a signal compensation unit,

The signal compensation unit is configured to perform tracking compensation on the radio frequency signal, and send the tracking compensated radio frequency signal.

Wherein, the sub-link also includes a feedback link; the feedback link also includes a DC offset compensation unit;

The DC offset compensation unit is configured to perform DC offset compensation on the radio frequency signal and send it to the channel evaluation unit.

Wherein, the feedback link further includes a signal compensation unit;

The signal compensation unit is configured to perform tracking compensation on the radio frequency signal, and send the tracking compensated radio frequency signal.

Wherein, the equalizer includes a time domain synchronization module, a storage module and a filter module;

The time domain synchronization module is configured to synchronize the equalizer with the time domain of the microprocessor according to the received time domain synchronization signal sent by the microprocessor;

The storage module is configured to receive and store the filter coefficient sent by the microprocessor when detecting the edge change of the request signal sent by the microprocessor;

The filter module is configured to filter the radio frequency signal according to the filter coefficients stored in the storage module under the control of the enable signal.

Wherein, the filter module includes a first accumulator, a multiplier, a second accumulator, a first computing unit and a second computing unit;

The first accumulator is configured to receive a radio frequency signal and accumulate part of the radio frequency signal;

The multiplier is used to multiply the radio frequency signal input to the filter module and the filter coefficient;

The second accumulator is configured to accumulate the results output by the multiplier;

The first computing unit is configured to round off the radio frequency signal output by the second accumulator, and transmit the calculation result to the second computing unit;

The second operation unit is configured to perform a saturation operation on the radio frequency signal output by the first operation unit, and output it.

Wherein, the transmission link includes two sub-links, respectively the first sub-link and the second sub-link; the radio frequency signal transmitted by the first sub-link is the same as that transmitted by the second sub-link The RF signal is orthogonal.

In the second aspect, the embodiment of the present disclosure also provides a signal processing method of a digital front-end processing device, the signal processing method of the digital front-end processing device includes any one of the above-mentioned digital front-end processing devices for the connection between the baseband and the antenna unit The radio frequency signals transmitted by the N transmission links are processed; wherein, the processing of the radio frequency signals transmitted by any sub-link of each of the N transmission links includes:

Evaluate the transmission channel of the radio frequency signal received by the channel evaluation unit, and feed back the evaluation result to the microprocessor;

the microprocessor determines filter coefficients according to the evaluation result;

The equalizer filters the radio frequency signal according to the filter coefficient determined by the microprocessor.

Wherein, the sub-link includes a sending link; the sending link includes a signal compensation unit, and the signal compensation unit is multiplexed as the channel evaluation unit in the sending link; in the equalizer pair Before the radio frequency signal is filtered, it also includes:

The RF signal is initially compensated by the signal compensation unit and sent to the equalizer microprocessor.

Wherein, the transmission link also includes a DC offset compensation unit; after the equalizer filters the radio frequency signal, it also includes:

Perform DC offset compensation on the RF signal filtered by the equalizer through the DC offset compensation unit, and send the DC offset compensated RF signal.

Wherein, the sub-link includes a receiving link; the receiving link includes a DC offset compensation unit; before the equalizer filters the radio frequency signal, it also includes:

Perform DC offset compensation on the radio frequency signal through the DC offset compensation unit, and send it to the channel assessment unit; the channel assessment unit performs channel assessment on the radio frequency signal received by the input signal terminal, and sends The radio frequency signal is transmitted to the equalizer through the output signal terminal, and at the same time, the channel evaluation unit feeds back the evaluation result to the microprocessor through the feedback signal terminal.

Wherein, the receiving chain also includes a signal compensation unit; after the equalizer filters the radio frequency signal, it also includes:

The radio frequency signal is tracked and compensated by the signal compensation unit, and the tracked and compensated radio frequency signal is sent.

Wherein, the sub-link is a feedback link; the feedback link includes a DC offset compensation unit; before the equalizer filters the radio frequency signal, it also includes:

Perform DC offset compensation on the radio frequency signal through the DC offset compensation unit, and send it to the channel assessment unit; the channel assessment unit performs channel assessment on the radio frequency signal received by the input signal terminal, and sends The radio frequency signal is transmitted to the equalizer through the output signal terminal, and at the same time, the channel evaluation unit feeds back the evaluation result to the microprocessor through the feedback signal terminal.

Wherein, the feedback link also includes a signal compensation unit; after the equalizer filters the radio frequency signal, it also includes:

The radio frequency signal is tracked and compensated by the signal compensation unit, and the tracked and compensated radio frequency signal is sent.

In a third aspect, an embodiment of the present disclosure further provides an antenna device, where the antenna device includes any one of the digital front-end processing devices described above.

Description of drawings

FIG. 1 is a schematic diagram of a connection structure of an equalizer according to an embodiment of the disclosure.

FIG. 2 is a schematic diagram of a transmission link connection structure according to an embodiment of the present disclosure.

FIG. 3 is a schematic diagram of a transmission link connection structure according to an embodiment of the present disclosure.

FIG. 4 is a schematic diagram of a receiving link connection structure according to an embodiment of the disclosure.

FIG. 5 is a schematic diagram of a feedback link connection structure according to an embodiment of the present disclosure.

FIG. 6 is a flowchart of a signal processing method of a digital front-end processing device according to an embodiment of the disclosure.

FIG. 7 is a flowchart of a signal processing method of a digital front-end processing device in a transmission link according to an embodiment of the present disclosure.

Fig. 8 is a flow chart of the work of each module of the equalizer in the transmission link according to the embodiment of the present disclosure.

FIG. 9 is a flowchart of filtering performed by an equalizer in a transmission link according to an embodiment of the present disclosure.

FIG. 10 is a flowchart of a signal processing method of a digital front-end processing device in a receiving chain according to an embodiment of the present disclosure.

Fig. 11 is a flowchart of the work of each module of the equalizer in the receiving chain according to the embodiment of the present disclosure.

FIG. 12 is a flowchart of filtering performed by an equalizer in a receiving chain according to an embodiment of the present disclosure.

Detailed ways

In order to enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by those skilled in the art to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Likewise, words like "a", "an" or "the" do not denote a limitation of quantity, but mean that there is at least one. "Comprising" or "comprising" and similar words mean that the elements or items appearing before the word include the elements or items listed after the word and their equivalents, without excluding other elements or items. Words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right" and so on are only used to indicate the relative positional relationship. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

When the radio frequency signal transceiver device communicates between devices, it usually uses three transmission links: the receiving transmission link for receiving the radio frequency signal sent by the external device through the antenna, the sending transmission link for sending the radio frequency signal and the communication link for The transmitted signal is verified by the feedback transmission link. Taking signal transmission as an example, the transmission process of the signal transmission transmission link includes radio frequency signal input, signal analog-to-digital conversion, digital logic operation processing of the converted digital signal and filtering of the signal, and transmission of the filtered signal to the multimedia The layer converts the data format, transmits the converted data signal to the physical layer, modulates the digital signal to obtain the time domain and frequency domain of the signal, and finally converts it into an analog signal for transmission through the antenna. The receiving process of the receiving transmission link is opposite to the sending process of the sending transmission link, and will not be repeated here.

In the process of transmitting and receiving radio frequency signals, it is necessary to perform digital logic operations and filter processing on the received and transmitted signals to improve the quality of signal transmission and reception, among which filtering is an important part. Taking low-pass filtering as an example, when performing low-pass filtering on a received or transmitted signal, the low-pass filtered signal may experience in-band roll-off, resulting in poor final signal quality.

In view of this, an embodiment of the present disclosure provides a digital front-end processing device, which can equalize and compensate the signal while filtering the radio frequency signal. In the prior art, it is very difficult to implement an equalizer with an analog circuit, and the performance is difficult to guarantee; using software to realize the equalization function and algorithm has a high time cost; the digital front-end processing device in the present disclosure includes a filter coefficient through a microprocessor Adjustment, combined with the circuit to realize the technical solution of filtering the radio frequency signal and compensating the radio frequency signal. At the same time, it also discloses a signal processing method of the digital front-end processing device to realize filtering the radio frequency signal and compensating possible amplitude roll-off at the same time.

The digital front-end processing device according to the embodiment of the present disclosure will be described in detail below in combination with specific embodiments and descriptions of drawings.

In the first aspect, the embodiment of the present disclosure discloses a digital front-end processing device. As shown in FIG. 1, the digital front-end processing device is configured to perform radio frequency signals transmitted by N transmission links between the baseband and the antenna unit. Processing, N≥1, and N is an integer; each of the N transmission links includes at least one sub-link. Wherein, an equalizer 10 and a channel evaluation unit 12 are arranged on the sub-link; the digital front-end processing device also includes a microprocessor 11 . For any sub-link, the channel evaluation unit 12 on it is configured to evaluate the transmission channel of the radio frequency signal it receives, and send the evaluation result to the microprocessor 11, so that the microprocessor 11 according to the evaluation As a result, filter coefficients are determined; the equalizer 10 is configured to filter the radio frequency signal according to the filter coefficients determined by the microprocessor 11 .

It should be noted that, in the embodiment of the present disclosure, the microprocessor 11 and the equalizer 10 are connected by an advanced high-performance bus (AHB). The connection method and the type of the connection line are adjusted, which are not further limited in the present disclosure.

In the digital front-end processing device of the embodiment of the present disclosure, since the microprocessor 11 generates filter coefficients according to the channel evaluation results, and the equalizer 10 filters the radio frequency signals according to the filter coefficients, the analog circuit is combined with software to implement the radio frequency signal. Operations of filtering, compensation and equalization. The difficulty of filtering, compensating and equalizing the radio frequency signal is reduced, and the effect of signal processing is improved. At the same time, when the equalizer 10 is used as a low-pass filter, the problem of in-band roll-off of the amplitude of the radio frequency signal during low-pass filtering is also solved, and the signal quality of the processed final radio frequency signal is improved.

In some examples, the N transmission links between the baseband and the antenna unit can perform processing such as sending and receiving and feeding back radio frequency signals. For example: in the embodiment of the present disclosure, the transmission link includes three paths, that is, N is 3, and the three transmission links are respectively used for sending, receiving, and feedback; each transmission link may include multiple sub-links. As shown in FIG. 2 , in the embodiment of the present disclosure, the transmission link includes three paths, namely, a sending path, a receiving path, and a feedback path, and each transmission link includes two sub-links as an example for illustration. The two sub-links included in each transmission link are respectively the first sub-link and the second sub-link; the radio frequency signal transmitted by the first sub-link is exactly the same as the radio frequency signal transmitted by the second sub-link pay. It is understandable that before the radio frequency signal enters the data front-end processing device, the radio frequency signal is vector-decomposed, and the original radio frequency signal is decomposed into two vector signals with the same frequency and the same peak amplitude but a phase difference of 90 degrees. Afterwards, transmission is performed through the first sub-link and the second sub-link respectively. For example: IQ modulated data can be divided into two channels, carrier modulation is performed respectively, and the two channels of carrier waves are orthogonal to each other. I is In-phase (in-phase), Q is Quadrature (quadrature), and IQ modulation is to divide the signal input to the filter into two channels for modulation. In the embodiment of the present disclosure, the radio frequency signal transmitted by the first sub-link is an in-phase signal, and the radio frequency signal transmitted by the second sub-link is an orthogonal signal. During the whole signal sending and receiving process, it is necessary to convert the radio frequency signal from an analog signal to a digital signal, so the radio frequency signal in this article is a digital signal unless otherwise specified. The transmission link can be changed during actual configuration. In this disclosure, only IQ modulation is used as a preferred implementation solution, and other modulation methods can also be used. There can be one or more sub-links. The specific structure of each sub-link when the sub-links in the embodiments of the present disclosure are a sending link, a receiving link and a feedback link will be described below respectively.

The first example: as shown in FIG. 3 , when the sub-link is a sending link, the sending link not only includes the above-mentioned equalizer 10 , but also includes a signal compensation unit 13 and/or a DC offset compensation unit 14 . In the embodiment of the present disclosure, it is taken as an example that the transmission link includes the signal compensation unit 13 and the DC offset compensation unit 14 at the same time.

Wherein, the signal compensation unit 13 is configured to initially compensate the radio frequency signal and send it to the equalizer 10 . At the same time, the signal compensation unit 13 is multiplexed as the channel evaluation unit 12 in the transmission link, that is, the signal compensation unit 13 can evaluate the channel.

Specifically, the signal compensation unit 13 has an input signal terminal, an output signal terminal and a feedback signal terminal, and the input signal terminal of the signal compensation unit 13 is used to receive a radio frequency signal as a signal input signal terminal of a digital front-end processing device, and the signal compensation unit 13 The output signal terminal is connected to the equalizer 10 , and the feedback signal terminal of the signal compensation unit 13 is connected to the microprocessor 11 . The input signal end of the signal compensation unit 13 receives the radio frequency signal, and the signal compensation unit 13 initially compensates the received radio frequency signal, and sends the compensated radio frequency signal to the equalizer 10, and simultaneously performs channeling according to the compensated radio frequency signal. Evaluate, and output the channel evaluation result to the microprocessor 11 through the feedback signal terminal.

Wherein, the DC offset compensation unit 14 is configured to perform DC offset compensation on the radio frequency signal filtered by the equalizer 10, and send the DC offset compensated radio frequency signal.

Specifically, the DC offset compensation unit 14 includes an input signal terminal and an output signal terminal, the input signal terminal of the DC offset compensation unit 14 is connected to the equalizer 10, and the output signal terminal of the DC offset compensation unit 14 is used as a digital front-end processing device. Output signal terminal.

The reason why the DC offset compensation unit 14 is provided is that the amplitude of the RF signal output by the equalizer 10 after filtering according to the filter coefficient sent by the microprocessor 11 will drop to a certain extent, so it needs to pass through the DC offset compensation unit 14 The decreased signal amplitude is compensated to increase the overall signal amplitude, and the compensated radio frequency signal is sent out of the digital front-end processing device.

The second example: as shown in FIG. 4, when the sub-link is a receiving link, the receiving link not only includes the above-mentioned equalizer 10, but also includes a DC offset compensation unit 14 and/or a signal compensation unit 13. In the embodiment of the present disclosure, it is taken that the receiving chain includes both the signal compensation unit 13 and the DC offset compensation unit 14 as an example.

Wherein, the DC offset compensation unit 14 is configured to perform DC offset compensation on the radio frequency signal and send it to the channel evaluation unit 12 .

Specifically, the DC offset compensation unit 14 includes an input signal terminal and an output signal terminal, the input signal terminal of the DC offset compensation unit 14 is used as the input signal terminal of the digital front-end processing device, and the output signal terminal of the DC offset compensation unit 14 is connected to the channel The evaluation unit 12 is connected.

The reason why the DC offset compensation unit 14 is set is because during the signal receiving process, the signal received by the antenna may suffer a certain loss, and its amplitude will have a certain decline, so the DC offset compensation unit 14 needs to be used to compensate for the decreased signal amplitude. value to increase the overall signal amplitude, and transmit the compensated radio frequency signal to the channel evaluation unit 12.

Specifically, the channel evaluation unit 12 has an input signal terminal, an output signal terminal and a feedback signal terminal, the input signal terminal of the signal compensation unit 13 is used to receive the radio frequency signal compensated by the DC offset compensation unit 14, and the output signal of the signal compensation unit 13 The terminal is connected to the equalizer 10, and the feedback signal terminal of the signal compensation unit 13 is connected to the microprocessor 11. The channel evaluation unit 12 performs channel evaluation according to the received RF signal compensated by the DC offset compensation unit 14, transmits the evaluated RF signal to the equalizer 10 through the output signal terminal, and generates a channel evaluation result at the same time, and sends it through the feedback signal terminal to the microprocessor 11.

Wherein, the signal compensation unit 13 is configured to track and compensate the radio frequency, and send the track-compensated radio frequency signal.

Specifically, the signal compensation unit 13 has an input signal end and an output signal end, the input signal end of the signal compensation unit 13 is connected to the equalizer 10, and the output signal end of the signal compensation unit 13 is used to send a radio frequency signal, as a digital front-end processing device Signal output signal terminal.

The reason why the signal compensation unit 13 is provided is that the amplitude of the radio frequency signal output by the equalizer 10 after filtering according to the filter coefficient sent by the microprocessor 11 will have certain fluctuations, so the signal compensation unit 13 needs to be used to compensate for excessive or If the signal amplitude is too low, the overall signal amplitude tends to be stable, and the compensated radio frequency signal is sent out of the digital front-end processing device.

The third example: as shown in Figure 5, when the sub-link is a feedback link, the feedback link not only includes the above-mentioned equalizer 10, but also includes a DC offset compensation unit 14 and/or a signal compensation unit 13, in this In the disclosed embodiment, the feedback link includes both the signal compensation unit 13 and the DC offset compensation unit 14 as an example.

Wherein, the DC offset compensation unit 14 is configured to perform DC offset compensation on the radio frequency signal and send it to the channel evaluation unit 12 .

Specifically, the DC offset compensation unit 14 includes an input signal terminal and an output signal terminal, the input signal terminal of the DC offset compensation unit 14 is used as the input signal terminal of the digital front-end processing device, and the output signal terminal of the DC offset compensation unit 14 is connected to the channel The evaluation unit 12 is connected.

The reason why the DC offset compensation unit 14 is set is because during the signal receiving process, the signal received by the antenna may suffer a certain loss, and its amplitude will have a certain decline, so the DC offset compensation unit 14 needs to be used to compensate for the decreased signal amplitude. value to increase the overall signal amplitude, and transmit the compensated radio frequency signal to the channel evaluation unit 12. Specifically, the channel evaluation unit 12 has an input signal terminal, an output signal terminal and a feedback signal terminal, the input signal terminal of the signal compensation unit 13 is used to receive the radio frequency signal compensated by the DC offset compensation unit 14, and the output signal of the signal compensation unit 13 The terminal is connected to the equalizer 10, and the feedback signal terminal of the signal compensation unit 13 is connected to the microprocessor 11. The channel evaluation unit 12 performs channel evaluation according to the received RF signal compensated by the DC offset compensation unit 14, transmits the evaluated RF signal to the equalizer 10 through the output signal terminal, and generates a channel evaluation result at the same time, and sends it through the feedback signal terminal to the microprocessor 11.

Wherein, the signal compensation unit 13 is configured to track and compensate the radio frequency, and send the track-compensated radio frequency signal.

Specifically, the signal compensation unit 13 has an input signal end and an output signal end, the input signal end of the signal compensation unit 13 is connected to the equalizer 10, and the output signal end of the signal compensation unit 13 is used to send a radio frequency signal, as a digital front-end processing device Signal output signal terminal.

The reason why the signal compensation unit 13 is provided is that the amplitude of the radio frequency signal output by the equalizer 10 after filtering according to the filter coefficient sent by the microprocessor 11 will have certain fluctuations, so the signal compensation unit 13 needs to be used to compensate for excessive or If the signal amplitude is too low, the overall signal amplitude tends to be stable, and the compensated radio frequency signal is sent out of the digital front-end processing device.

It should be noted that the above-mentioned filter coefficients can be one piece of data or a set of data. When the filter coefficient is a set of data, the number of coefficients included in the set of data is related to the filtering order realized by the equalizer 10 and the use of the actual product. Correspondingly, the form of the filter coefficients and the number of coefficients specifically included are not further limited here.

In some examples, the equalizer 10 in the embodiment of the present disclosure may specifically include a time-domain synchronization module, a storage module and a filter module regardless of any situation in which the sub-links are connected. Wherein, the time domain synchronization module is configured to synchronize the equalizer 10 with the time domain of the microprocessor 11 by receiving the time domain synchronization signal sent by the microprocessor 11; the storage module is configured to detect the request sent by the microprocessor 11 The edge of the signal changes, the filter coefficient data is received and the filter coefficient is stored; the filter module is configured to filter the radio frequency signal according to the filter coefficient stored in the storage module under the control of the enable signal. The microprocessor 11 will send a request signal to the equalizer 10, but the clock domains of the equalizer 10 and the microprocessor 11 are different, so it is necessary to adjust the clock domains of the equalizer 10 and the microprocessor 11 to be consistent, usually the microprocessor The first and second request signals sent by 11 are used as clock synchronization signals to synchronize the clock domains of equalizer 10 and microprocessor 11 . After the clock domain synchronization of equalizer 10 and microprocessor 11, equalizer 10 can receive the request signal of microprocessor 11, and microprocessor 11 sends request signal to equalizer 10, when equalizer 10 detects the edge of request signal When changing, the microprocessor 11 will send the filter coefficient data to the equalizer 10, and the equalizer 10 will register the filter coefficient in the equalizer 10 after receiving the filter coefficient data. The aforementioned edge change can be understood as that when the equalizer 10 detects that the request signal changes from 1 to 0 or from 0 to 1, it can receive the filter coefficient data sent by the control unit. The above-mentioned registration only plays the role of caching. When the equalizer 10 uses the stored filter coefficients to perform the radio frequency signal, the stored filter coefficients will become invalid. When filtering is required next time, new filter coefficients will be stored. , at this time the equalizer 10 can directly load the newly registered filter coefficients. The filter module automatically filters the radio frequency signal according to the filter coefficients stored in the storage module under the control of the enable signal. The way that the equalizer 10 detects the edge of the request signal can reduce the difficulty of the software design of the microprocessor 11, and it is also unnecessary to add a counter in the equalizer 10, which reduces the complexity of the device.

It should be noted that the signals received, sent and fed back are continuous signals; during the receiving process, due to the different distances between the signal source of the external signal and the receiving device and the environment in which the signal propagates, the quality of the signal will be affected; similarly, During the sending process, the distance of the target object and the actual environment are also different, so the sent signal needs to be adjusted. The radio frequency signal enters the digital front-end processing device in the form of a continuous signal. When the radio frequency signal passes through the digital front-end processing device, the signal does not need to be filtered, equalized and compensated. evaluation to determine whether compensation is required. Therefore, a request signal is required to instruct the equalizer 10, and at the same time, different filter coefficients are loaded to the equalizer 10 according to different situations. When there is no need to filter, compensate and equalize the radio frequency signal, the equalizer 10 can be directly skipped, or the signal compensation unit 13 and the DC offset compensation unit 14 can be skipped, thereby reducing certain power consumption.

In some examples, the equalizer 10 includes a first accumulator, a multiplier, a second accumulator, a first computing unit, and a second computing unit; the first accumulator is configured to receive a radio frequency signal, and accumulate a part of the radio frequency signal ; The multiplier is used to multiply and calculate the radio frequency signal input to the filter module and the filter coefficient; the second accumulator is configured to accumulate the results output by the multiplier; the first computing unit is configured to output the second accumulator The radio frequency signal is rounded off, and the calculation result is transmitted to the second operation unit; the second operation unit is configured to perform saturation operation on the radio frequency signal output by the first operation unit, and obtain the final filtering result of the equalizer 10 . In the embodiment of the present disclosure, the equalizer 10 is used as a tenth-order low-pass filter as an example, wherein the radio frequency signal that has been converted into a data signal includes X ₁ -X ₁₀ , and the signal data is sequentially input into the accumulator; each All signals correspond to filter coefficients. The filter coefficients input to the equalizer 10 are A ₁ -A ₁₀ . Since the filter coefficients are symmetrical in the middle, the two ends are equal, that is to say, A ₁ =A ₁₀ , A ₂ =A ₉ , A ₃ =A ₈ , A ₄ =A ₇ and A ₅ =A ₆ . Therefore, in the microprocessor 11, only 5 filter coefficients are required, and Y ₁ , Y ₂ , Y ₃ , Y ₄ and Y ₅ . The flow process that the equalizer 10 processes the signal is:

S1: Accumulate radio frequency signals, X ₁ +X ₁₀ , X ₂ +X ₉ , X ₃ +X ₈ , X ₄ +X ₇ , X ₅ +X ₆ .

S2: Multiply the accumulated result by the filter coefficient, Y ₁ ×(X ₁ +X ₁₀ ), Y ₂ ×(X ₂ +X ₉ ), Y ₃ ×(X ₃ +X ₈ ), Y ₄ ×( X ₄ +X ₇ ), Y ₅ ×(X ₅ +X ₆ ).

S3: Accumulate the multiplied five sets of data again to obtain the result after filtering and processing the radio frequency signal.

Compared with the method of directly multiplying the RF signal and the filter coefficient and then accumulating, the calculation method implemented by the above module can reduce the complex calculation process; and in the final accumulation process, the above process only needs to accumulate five Data, directly multiplying the RF signal and the filter coefficient will get ten data, so the final accumulation process is also more optimized. It should be noted that the amount of signal data and the filter order corresponding to the equalizer 10 can be adjusted according to actual signals and actual usage conditions.

Since the radio frequency signal is a digital signal in the digital front-end processing device, it will be processed in the form of data. The first operation unit outputs the data output by the second accumulator for further processing, and when the data bit width of the signal output by the second accumulator is too large, part of the data bit width is reduced to reduce power consumption. The second calculation unit sets the signal range, specifically, sets the maximum and minimum values of the signal data bit width, and further compensates the radio frequency signal to prevent the received or transmitted radio frequency signal from being too large or too small.

In the second aspect, the embodiment of the present disclosure provides a signal processing method of a digital front-end processing device. As shown in FIG. 6, the device includes using any of the above-mentioned digital front-end processing devices to transmit The radio frequency signal transmitted by the link is processed; wherein, the processing of the radio frequency signal transmitted by any sub-link in each of the N transmission links includes:

S01, the microprocessor 11 evaluates the transmission channel of the radio frequency signal through the channel evaluation unit 12, generates an evaluation result, and feeds back the evaluation result to the microprocessor 11.

S02 , the microprocessor 11 obtains the corresponding filter coefficients according to the channel evaluation result and the pre-stored corresponding relationship between the channel evaluation results and the filter coefficients, and sends it to the equalizer 10 .

S03. The equalizer 10 filters the radio frequency signal according to the filter coefficient.

Combine analog circuits with software to implement filtering, compensation and equalization of radio frequency signals. The difficulty of filtering, compensating and equalizing the radio frequency signal is reduced, and the effect of signal processing is improved. At the same time, when the equalizer 10 is used as a low-pass filter, the problem of in-band roll-off of the amplitude of the radio frequency signal during low-pass filtering is also solved, and the signal quality of the processed final radio frequency signal is improved.

In the embodiment of the present disclosure, the transmission link includes three paths, that is, N is 3, which are respectively the sending path, the receiving path, and the feedback path, and each transmission link includes two sub-links as an example for illustration.

In the embodiment of the present disclosure, the sub-links may include a transmitting link, a receiving link, and a feedback link. The signal processing methods of the receiving link and the feedback link are the same, and the signal processing method will be described below only by taking the example that the sub-link may include the transmitting link and the receiving link.

The first example: as shown in Figure 7, when the sub-link is a transmission link, the sub-link includes a signal compensation unit 13, an equalizer 10, and a DC offset compensation unit 14; wherein, the signal compensation unit 13 multiplexes is the channel estimation unit 12 in the sending link. The method specifically includes the following steps:

S11. The signal compensation unit 13 receives a radio frequency signal, and performs initial compensation on the radio frequency signal.

It should be noted that the radio frequency signal received by the signal compensation unit 13 in step S11 is a digital signal. In some examples, the signal compensation unit 13 receives the radio frequency signal and performs initial compensation on the radio frequency signal, including: the signal compensation unit 13 initially compensates the amplitude of the received signal, and the amplitude of the radio frequency signal to be sent is too high Or the part of the signal that is too low is compensated, so that the overall amplitude of the radio frequency signal tends to be stable.

S12 , the signal compensation unit 13 performs channel assessment according to the initially compensated radio frequency signal, and feeds back the channel assessment result to the microprocessor 11 , and sends the initially compensated radio frequency signal to the equalizer 10 .

S13 , the microprocessor 11 determines the corresponding filter coefficients according to the channel evaluation result fed back by the signal compensation unit 13 and the corresponding relationship between the channel evaluation result and the filter coefficient stored in it, and sends it to the equalizer 10 .

In some examples, in step S13, the corresponding relationship between the pre-stored channel assessment result and the filter coefficient may be a mapping table, or a preset algorithm, that is, the filter coefficient is calculated according to the channel assessment result through a corresponding algorithm. .

S14 , the equalizer 10 compensates the radio frequency signal according to the filter coefficient determined by the microprocessor 11 .

In some examples, equalizer 10 includes a time domain synchronization module, a storage module and a filtering module. As shown in Figure 8, step S14 may specifically include:

S141 , the time domain synchronization module synchronizes its own time domain with the time domain of the microprocessor 11 according to receiving the time domain synchronization signal sent by the microprocessor 11 .

S142. Receive the request signal sent by the microprocessor 11, and when an edge change of the request signal of the microprocessor 11 is detected, receive the microprocessor filter coefficient and store it in the storage module.

It should be noted that the storage only acts as a buffer. When the equalizer 10 uses the stored filter coefficients to perform the radio frequency signal, the stored filter coefficients will become invalid. When filtering is required next time, new filter coefficients will be stored. coefficient, at this time the equalizer 10 can directly load the newly registered filter coefficient.

S143. Under the control of the enable signal, the filter module filters the radio frequency signal according to the filter coefficients stored in the storage module.

It should be noted that the reason why the filter module needs to perform filter control under the control of the enable signal is because the radio frequency signal is a continuous signal during transmission, and it is not necessary to filter this continuous signal all the time. The equalizer 10 needs to carry out filter processing only when specific or needs to adjust the radio frequency signal, so an enable signal is set, and when the equalizer 10 does not need to work for a long time, the enable signal can be turned off to make the equalizer 10 stop working, reducing The power consumption of the entire digital front-end processing device is reduced.

In some examples, the filtering module may include a first adder, a multiplier, a second adder, a first operation unit, and a second operation unit. As shown in Figure 9, step S143 may specifically include:

S1431. The radio frequency signal received at the input signal end of the equalizer 10 is accumulated in the first accumulator for the first time, for example, the first and last signals are accumulated in pairs.

S1432. The multiplier multiplies the filter coefficient loaded into the equalizer 10 by the radio frequency signal after the first accumulation.

S1433. The second accumulator accumulates the multiplied radio frequency signals again to obtain a radio frequency signal.

S1434. The first operation unit performs rounding operation on the radio frequency signal after the above steps.

S1435. The second calculation unit performs saturation calculation on the radio frequency signal after the above steps to obtain the final radio frequency signal filtered by the equalizer 10 .

It should be noted that the first computing unit and the second computing unit are used to limit the bit width of the radio frequency signal converted into a mathematical signal, and the rounding operation will process the radio frequency signal exceeding a certain amount, reduce its bit width, and reduce the Power consumption; the saturation operation further limits the bit width range of the radio frequency signal, and processes the radio frequency signal with too high or too low bit width, so that the bit width of the radio frequency signal is controlled within a certain range. In the embodiments of the present disclosure, no further limitation is made on the bit width of the radio frequency signal, and persons in the relevant technical field may adjust it according to actual usage conditions.

S15. The DC offset compensation unit 14 performs DC offset compensation on the radio frequency signal filtered by the equalizer 10, and sends the DC offset compensated radio frequency signal.

In some examples, step S15 may specifically include: the DC offset compensation unit 14 compensates the amplitude of the filtered radio frequency signal to increase the amplitude to a certain extent before outputting. The reason why the amplitude is compensated is that the amplitude of the RF signal output by the equalizer 10 after filtering according to the filter coefficient sent by the microprocessor 11 will have a certain decrease, so it needs to be compensated by the DC offset compensation unit 14 The decreased signal amplitude increases the overall signal amplitude, and the compensated radio frequency signal is used as the output of the digital front-end processing device.

Second example: when the sub-link is a receiving link, the sub-link includes a DC offset compensation unit 14 , a channel evaluation unit 12 , an equalizer 10 and a signal compensation unit 13 . As shown in Figure 10, the method specifically includes the following steps:

S21. The DC offset compensation unit 14 performs DC offset compensation on the radio frequency signal.

In some examples, step S21 may specifically include: the DC offset compensation unit 14 performs DC offset compensation on the amplitude of the radio frequency signal to increase the amplitude to a certain extent. The reason why the amplitude is compensated is that during the signal receiving process, the signal received by the antenna may suffer a certain loss, and its amplitude will drop to a certain extent, so it is necessary to compensate the dropped signal amplitude through the DC offset compensation unit 14 , to increase the overall signal amplitude, and then transmit the radio frequency signal after the DC offset compensation to the channel evaluation unit 12 .

S22 , the channel assessment unit 12 performs channel assessment according to the DC offset-compensated RF signal, feeds back the channel assessment result to the microprocessor 11 , and sends the DC offset-compensated RF signal to the equalizer 10 .

S23. The microprocessor 11 determines the corresponding filter coefficients according to the channel evaluation results fed back by the channel evaluation unit 12 and the pre-stored channel evaluation results and filter coefficients, and sends them to the equalizer 10.

In some examples, in step S23, the correspondence between the pre-stored channel assessment results and filter coefficients can be a mapping table, or a preset algorithm, that is, the filter coefficients are calculated according to the channel assessment results through corresponding algorithms .

S24 , the equalizer 10 compensates the radio frequency signal according to the filter coefficient determined by the microprocessor 11 .

In some examples, equalizer 10 includes a time domain synchronization module, a storage module and a filtering module. As shown in Figure 11, step S14 may specifically include:

S241 , the time domain synchronization module synchronizes its own time domain with the time domain of the microprocessor 11 according to receiving the time domain synchronization signal sent by the microprocessor 11 .

S242. Receive the request signal sent by the microprocessor 11, and when an edge change of the request signal of the microprocessor 11 is detected, receive the microprocessor filter coefficient and store it in the storage module.

It should be noted that the storage only acts as a buffer. When the equalizer 10 uses the stored filter coefficients to perform the radio frequency signal, the stored filter coefficients will become invalid. When filtering is required next time, new filter coefficients will be stored. coefficient, at this time the equalizer 10 can directly load the newly registered filter coefficient.

S243. Under the control of the enable signal, the filter module filters the radio frequency signal according to the filter coefficients stored in the storage module.

It should be noted that the reason why the filter module needs to perform filter control under the control of the enable signal is because the radio frequency signal is a continuous signal during transmission, and it is not necessary to filter this continuous signal all the time. The equalizer 10 needs to carry out filter processing only when specific or needs to adjust the radio frequency signal, so an enable signal is set, and when the equalizer 10 does not need to work for a long time, the enable signal can be turned off to make the equalizer 10 stop working, reducing The power consumption of the entire digital front-end processing device is reduced.

In some examples, the filtering module may include a first adder, a multiplier, a second adder, a first operation unit, and a second operation unit. As shown in Figure 12, step S243 may specifically include:

S2431. The radio frequency signal received at the input signal end of the equalizer 10 is accumulated in the first accumulator for the first time, for example, the first and last signals are accumulated in pairs.

S2432. The multiplier performs a multiplication operation on the filter coefficient loaded into the equalizer 10 and the radio frequency signal after the first accumulation.

S2433. The second accumulator accumulates the multiplied radio frequency signals again to obtain a radio frequency signal.

S2434. The first operation unit performs rounding operation on the radio frequency signal after the above steps.

S2435. The second calculation unit performs saturation calculation on the radio frequency signal after the above steps, and obtains the final radio frequency signal filtered by the equalizer 10 .

It should be noted that the first computing unit and the second computing unit are used to limit the bit width of the radio frequency signal converted into a mathematical signal, and the rounding operation will process the radio frequency signal exceeding a certain amount, reduce its bit width, and reduce the Power consumption; the saturation operation further limits the bit width range of the radio frequency signal, and processes the radio frequency signal with too high or too low bit width, so that the bit width of the radio frequency signal is controlled within a certain range. In the embodiments of the present disclosure, no further limitation is made on the bit width of the radio frequency signal, and persons in the relevant technical field may adjust it according to actual usage conditions.

S25. The signal compensation unit 13 receives the radio frequency signal, and performs tracking compensation on the radio frequency signal.

It should be noted that the radio frequency signal received by the signal compensation unit 13 in step S25 is a digital signal. In some examples, the signal compensation unit 13 receives the radio frequency signal and performs tracking compensation on the radio frequency signal, including: the signal compensation unit 13 performs tracking compensation on the amplitude of the received signal, and the amplitude of the radio frequency signal to be received is too high Or the part of the signal that is too low is compensated, so that the overall amplitude of the radio frequency signal tends to be stable, and the compensated radio frequency signal is used as the output of the digital front-end processing device.

In a third aspect, an embodiment of the present disclosure further provides an antenna device, which includes any one of the above-mentioned digital front-end processing devices. Of course, the antenna device also includes a baseband and an antenna unit; the baseband and the antenna unit are connected by N transmission links, each of which is equipped with a digital front-end processing device. Wherein, the antenna unit may include N antenna modules, and the N antenna modules are connected to the N transmission links in one-to-one correspondence.

Since the antenna device in the embodiments of the present disclosure includes any of the above-mentioned digital front-end processing devices, the operations of filtering, compensating and equalizing radio frequency signals can be implemented by combining analog circuits with software. The difficulty of filtering, compensating and equalizing the radio frequency signal is reduced, and the effect of signal processing is improved. At the same time, when the equalizer is used as a low-pass filter, the problem of in-band roll-off of the amplitude of the radio frequency signal during low-pass filtering is also solved, and the signal quality of the processed final radio frequency signal is improved.

It can be understood that, the above embodiments are only exemplary embodiments adopted for illustrating the principle of the present invention, but the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims (18)

1. A digital front-end processing device is configured to process radio frequency signals transmitted by N transmission links between a baseband and an antenna unit, wherein N is more than or equal to 1, and N is an integer; each of the N transmission links comprises at least one sub-link; wherein, an equalizer and a channel evaluation unit are configured on the sub-link; the digital front-end processing device also comprises a microprocessor;

for any sub-link, the channel evaluation unit on the sub-link is configured to evaluate a transmission channel of the radio frequency signal received by the sub-link and feed back an evaluation result to the microprocessor, so that the microprocessor determines a filter coefficient according to the evaluation result; the equalizer is configured to filter the radio frequency signal according to the filter coefficients determined by the microprocessor.

2. The digital front-end processing device of claim 1, wherein the sub-link comprises a transmit link; the transmission chain comprises a signal compensation unit,

the signal compensation unit is configured to perform initial compensation on the radio frequency signal and send the radio frequency signal to the equalizer, and the signal compensation unit is multiplexed as the channel estimation unit in the sending link.

3. The digital front-end processing device of claim 2, wherein the transmit chain further comprises a dc offset compensation unit;

the DC offset compensation unit is configured to perform DC offset compensation on the RF signal filtered by the equalizer and send the RF signal after DC offset compensation.

4. The digital front-end processing device of claim 1, wherein the sub-link further comprises a receive link; the receiving chain also comprises a direct current offset compensation unit;

the direct current offset compensation unit is configured to perform direct current offset compensation on the radio frequency signal and send the radio frequency signal to the channel estimation unit.

5. The digital front-end processing device of claim 4, wherein the receive chain includes a signal compensation unit,

the signal compensation unit is configured to perform tracking compensation on the radio frequency signal and transmit the tracking compensated radio frequency signal.

6. The digital front-end processing device of claim 1, wherein the sublinks further comprise a feedback link; the feedback link further comprises a DC offset compensation unit;

the direct current offset compensation unit is configured to perform direct current offset compensation on the radio frequency signal and send the radio frequency signal to the channel estimation unit.

7. The digital front-end processing device of claim 6, wherein the feedback link further comprises a signal compensation unit;

the signal compensation unit is configured to perform tracking compensation on the radio frequency signal and transmit the tracking compensated radio frequency signal.

8. The digital front-end processing apparatus of any of claims 1-7, wherein the equalizer comprises a time domain synchronization module, a storage module, and a filtering module;

the time domain synchronization module is configured to synchronize the equalizer with the time domain of the microprocessor according to the received time domain synchronization signal sent by the microprocessor;

the storage module is configured to receive and store the filter coefficient sent by the microprocessor when detecting the edge change of the request signal sent by the microprocessor;

the filtering module is configured to filter the radio frequency signal according to the filter coefficient stored in the storage module under the control of an enable signal.

9. The digital front-end processing device of claim 8, wherein the filtering module comprises a first accumulator, a multiplier, a second accumulator, a first arithmetic unit, and a second arithmetic unit;

the first accumulator is configured to receive the radio frequency signal and accumulate part of the radio frequency signal;

the multiplier is used for multiplying the radio frequency signal input into the filtering module by the filtering coefficient;

the second accumulator is configured to accumulate the result output by the multiplier;

the first operation unit is configured to round the radio frequency signal output by the second accumulator and transmit the calculation result to the second operation unit;

the second operation unit is configured to perform saturation operation on the radio frequency signal output by the first operation unit and output the radio frequency signal.

10. The digital front-end processing device according to claim 1, wherein the transmission link comprises two sub-links, a first sub-link and a second sub-link; the radio frequency signal transmitted by the first sublink is orthogonal to the radio frequency signal transmitted by the second sublink.

11. A signal processing method of a digital front-end processing device, wherein the signal processing method of the digital front-end processing device comprises the steps of processing radio-frequency signals transmitted by N transmission links between a baseband and an antenna unit by using the digital front-end processing device as claimed in any one of claims 1 to 10; wherein the processing of the radio frequency signal transmitted by any one sublink of each of the N transmission links comprises:

the channel evaluation unit evaluates the transmission channel of the received radio frequency signal and feeds back the evaluation result to the microprocessor;

the microprocessor determines a filter coefficient according to the evaluation result;

and the equalizer filters the radio frequency signal according to the filter coefficient determined by the microprocessor.

12. The signal processing method of a digital front-end processing device according to claim 11, wherein the sub-link comprises a transmission link; the transmission link comprises a signal compensation unit, and the signal compensation unit is multiplexed as the channel estimation unit in the transmission link; before the equalizer filters the radio frequency signal, the method further comprises:

and performing initial compensation on the radio frequency signal through the signal compensation unit, and sending the radio frequency signal to the equalizer microprocessor.

13. The signal processing method of the digital front-end processing device according to claim 12, wherein the transmission chain further comprises a dc offset compensation unit; after the step of filtering the radio frequency signal by the equalizer, the method further comprises:

and performing direct current offset compensation on the radio frequency signal filtered by the equalizer through the direct current offset compensation unit, and sending the radio frequency signal subjected to the direct current offset compensation.

14. The signal processing method of a digital front-end processing device according to claim 11, wherein the sub-link comprises a receiving link; the receiving chain comprises a direct current offset compensation unit; before the step of filtering the radio frequency signal by the equalizer, the method further comprises:

performing direct current offset compensation on the radio frequency signal through the direct current offset compensation unit, and sending the radio frequency signal to the channel evaluation unit; the channel evaluation unit carries out channel evaluation on the radio-frequency signals received by the input signal end and transmits the radio-frequency signals to the equalizer through the output signal end, and meanwhile, the channel evaluation unit feeds back evaluation results to the microprocessor through the feedback signal end.

15. The signal processing method of a digital front-end processing device according to claim 14, wherein the receiving chain further comprises a signal compensation unit; after the step of filtering the radio frequency signal by the equalizer, the method further comprises:

and tracking and compensating the radio frequency signal through the signal compensation unit, and sending the radio frequency signal after tracking and compensating.

16. The signal processing method of a digital front-end processing device according to claim 11, wherein the sub-link is a feedback link; the feedback link comprises a DC offset compensation unit; before the step of filtering the radio frequency signal by the equalizer, the method further comprises:

performing direct current offset compensation on the radio frequency signal through the direct current offset compensation unit, and sending the radio frequency signal to the channel evaluation unit; the channel evaluation unit carries out channel evaluation on the radio-frequency signals received by the input signal end and transmits the radio-frequency signals to the equalizer through the output signal end, and meanwhile, the channel evaluation unit feeds back evaluation results to the microprocessor through the feedback signal end.

17. The signal processing method of the digital front-end processing device of claim 16, wherein the feedback link further comprises a signal compensation unit; after the step of filtering the radio frequency signal by the equalizer, the method further comprises:

and tracking and compensating the radio frequency signal through the signal compensation unit, and sending the radio frequency signal after tracking and compensating.

18. An antenna device, wherein the antenna device comprises the digital front-end processing apparatus of any one of claims 1-10.

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