CN115765638A - 6-18GHz power amplifier combining active matching and passive matching and implementation method - Google Patents
6-18GHz power amplifier combining active matching and passive matching and implementation method Download PDFInfo
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Abstract
The invention discloses a 6-18GHz power amplifier combining active matching and passive matching, which comprises a passive input matching network, an active input matching network, a passive interstage matching network, an active interstage matching network, a passive output matching network, an active output matching network, a first transistor and a second transistor, wherein the active input matching network is connected with the active interstage matching network; and the impedance positions of the first transistor and the second transistor are accurately controlled by adopting a mode of combining active matching and passive matching. The implementation method of the invention firstly carries out preliminary matching on the impedance position of the transistor through the passive matching circuit, reduces the matching difficulty, and realizes accurate control on the impedance position through active matching to correct the fundamental wave impedance position and the harmonic wave impedance position on the basis. The invention solves the problem that the impedance of the transistor in the traditional ultra-wideband power amplifier can not be ideally matched at all frequency points, and finally improves the overall efficiency of the 6-18GHz power amplifier.
Description
Technical Field
The invention relates to a microwave power amplifier, in particular to a 6-18GHz power amplifier combining active matching and passive matching and a realization method thereof.
Background
The power amplifier is a main energy consumption element of the receiving and transmitting link, and the power consumption of the receiving and transmitting link can be effectively reduced by improving the efficiency of the power amplifier. In accordance with the demands of integration and miniaturization, it is generally required that the power amplifier operates not at a certain frequency point but in a wide band range. How to realize larger output power and higher gain in a broadband, especially in an ultra-wideband range, and ensure as high efficiency as possible at the same time is a hot issue of research in academia and industry.
The traditional ultra-wideband power amplifier is a fixed passive matching circuit structure no matter in a distributed circuit topology or a reactance matching circuit topology. From the Foster reactance theorem, it is known that the matching position of a conventional passive matching circuit rotates clockwise with frequency in a smith chart. However, according to the Load-Pull test result, the optimal impedance point of the transistor rotates counterclockwise with the frequency. Therefore, the impedance of the existing ultra-wideband power amplifier transistor cannot be perfectly matched at all frequency points, and the efficiency of the ultra-wideband power amplifier is further limited.
Disclosure of Invention
The purpose of the invention is as follows: the invention discloses a 6-18GHz power amplifier combining active matching and passive matching and a realization method thereof, wherein the 6-18GHz power amplifier can enable the impedance of a transistor to be ideally matched at all frequency points and improve the efficiency of the power amplifier.
The technical scheme is as follows: the power amplifier comprises a passive input matching network, an active input matching network, a passive interstage matching network, an active interstage matching network, a passive output matching network, an active output matching network, a first transistor and a second transistor;
the input end of the passive input matching network is connected with the radio frequency input end, and the input end of the active input matching network is connected with the output end of the passive input matching network; the grid electrode of the first transistor is connected with the output end of the active input matching network; the source electrode of the first transistor is grounded;
the input end of the passive interstage matching network is connected with the drain electrode of the first transistor; the input end of the active interstage matching network is connected with the output end of the passive interstage matching network; the grid electrode of the second transistor is connected with the output end of the active interstage matching network; the source electrode of the second transistor is grounded;
the input end of the passive output matching network is connected with the drain electrode of the second transistor; the input end of the active output matching network is connected with the output end of the passive output matching network; the radio frequency output end is connected with the output end of the active output matching network;
the control signal of the active input matching network is a first control signal; the control signal of the active interstage matching network is a second control signal; the control signal of the active output matching network is a third control signal;
the input signal of the radio frequency input end is an input signal source; the first control signal, the second control signal and the third control signal are all the combination of output signals of a first signal source, a second signal source, … … and an nth signal source; n is a positive integer and is not less than 3;
the output signal frequency of the input signal source is f 0 (ii) a The first signal source outputs a signal with a frequency f 0 (ii) a The frequency of the output signal of the second signal source is 2f 0 (ii) a … …; the output signal frequency of the nth signal source is nf 0 。
Further, the passive input matching network comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first microstrip line, a second microstrip line, a third microstrip line, a fourth microstrip line, a first capacitor, a second capacitor and a third capacitor; one end of the first resistor is connected with the radio frequency input end; the other end of the first resistor is connected with one end of the second resistor and one end of the third resistor respectively; the other end of the third resistor is connected with one end of the first microstrip line; the other end of the first microstrip line is grounded; the other end of the second resistor is connected with one end of the first capacitor; the other end of the first capacitor is connected with one end of the second capacitor and one end of the second microstrip line respectively; the other end of the second capacitor is grounded; the other end of the second microstrip line is connected with one end of the third microstrip line and one end of the fourth resistor respectively; the other end of the third microstrip line is connected with one end of a fifth microstrip line in the active input matching network; the other end of the fourth resistor is connected with one end of the fourth microstrip line; the other end of the fourth microstrip line is respectively connected with the grid bias voltage and one end of the third capacitor; the other end of the third capacitor is grounded;
the active input matching network comprises a fifth microstrip line, a sixth microstrip line and a seventh microstrip line, and one end of the fifth microstrip line is connected with one end of a third microstrip line in the passive input matching network; the other end of the fifth microstrip line is connected with one end of the sixth microstrip line and one end of the seventh microstrip line respectively; the other end of the sixth microstrip line is connected with the grid electrode of the first transistor; the other end of the seventh microstrip line is connected with the first control signal.
Further, the passive inter-stage matching network comprises an eighth microstrip line, a ninth microstrip line, a tenth microstrip line, an eleventh microstrip line, a twelfth microstrip line, a thirteenth microstrip line, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a fifth resistor and a sixth resistor; one end of the eighth microstrip line is connected with the drain electrode of the first transistor; the other end of the eighth microstrip line is connected with one end of the ninth microstrip line and one end of the tenth microstrip line respectively; the other end of the ninth microstrip line is respectively connected with the drain bias voltage and one end of the fourth capacitor; the other end of the fourth capacitor is grounded; the other end of the tenth microstrip line is connected with one end of a fifth capacitor; the other end of the fifth capacitor is connected with one end of the sixth capacitor, one end of the seventh capacitor and one end of the fifth resistor respectively; the other end of the sixth capacitor is grounded; the other end of the seventh capacitor is connected with the other end of the fifth resistor and is respectively connected with one end of the eighth capacitor and one end of the eleventh microstrip line; the other end of the eighth capacitor is grounded; the other end of the eleventh microstrip line is connected with one end of the twelfth microstrip line and one end of the sixth resistor respectively; the other end of the twelfth microstrip line is connected with one end of a fourteenth microstrip line in the active interstage matching network; the other end of the sixth resistor is connected with one end of a thirteenth microstrip line; the other end of the thirteenth microstrip line is respectively connected with the gate bias voltage and one end of the ninth capacitor; the other end of the ninth capacitor is grounded;
the active interstage matching network comprises a fourteenth microstrip line, a fifteenth microstrip line and a sixteenth microstrip line, wherein one end of the fourteenth microstrip line is connected with one end of a twelfth microstrip line in the passive input matching network; the other end of the fourteenth microstrip line is connected with one end of the fifteenth microstrip line and one end of the sixteenth microstrip line respectively; the other end of the fifteenth microstrip line is connected with the gate of the second transistor; the other end of the sixteenth microstrip line is connected with a second control signal.
Further, the passive output matching network comprises a seventeenth microstrip line, an eighteenth microstrip line, a nineteenth microstrip line, a twentieth microstrip line, a twenty-first microstrip line, a tenth capacitor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor and a fourteenth capacitor; one end of the seventeenth microstrip line is connected with the drain electrode of the second transistor; the other end of the seventeenth microstrip line is connected with one end of the eighteenth microstrip line and one end of the nineteenth microstrip line respectively; the other end of the eighteenth microstrip line is connected with the drain bias voltage and one end of the tenth capacitor respectively; the other end of the tenth capacitor is grounded; the other end of the nineteenth microstrip line is connected with one end of an eleventh capacitor and one end of a twelfth capacitor respectively; the other end of the eleventh capacitor is grounded; the other end of the twelfth capacitor is connected with one end of the twentieth microstrip line and one end of the twenty-first microstrip line respectively; the other end of the twentieth microstrip line is grounded; the other end of the twenty-first microstrip line is connected with one end of a thirteenth capacitor and one end of a fourteenth capacitor respectively; the other end of the thirteenth capacitor is grounded; the other end of the fourteenth capacitor is connected with one end of a twenty-second microstrip line in the active output matching network;
the active output matching network comprises a twenty-second microstrip line, a twenty-third microstrip line and a twenty-fourth microstrip line, and one end of the twenty-second microstrip line is connected with one end of a fourteenth capacitor in the passive output matching network; the other end of the twenty-second microstrip line is connected with one end of a twenty-third microstrip line and one end of a twenty-fourth microstrip line respectively; the other end of the twenty-third microstrip line is connected with the radio frequency output end; the other end of the twenty-fourth microstrip line is connected with a third control signal.
The implementation method of the 6-18GHz power amplifier combining active matching and passive matching adopts a mode combining the active matching and the passive matching to accurately control the impedance positions of a first transistor and a second transistor: firstly, impedance positions of two transistors are primarily matched through a passive matching circuit, so that the matching difficulty is reduced; and further correcting the impedance position through active matching, wherein the correction comprises fundamental impedance position correction and harmonic impedance position correction. The method comprises the following steps:
A 1 : selecting a process approach according to the required working frequency range; selecting the final total gate width of the power amplifier according to the required output power and the power density of the selected process path; determining the stage number of the power amplifier according to the required gain; determining an interstage drive ratio according to gain compression characteristics of the selected process path device;
A 2 : the first transistor (pHEMT) is determined by Load Pull and Source Pull tests or simulations 1 ) Determining a second fundamental load impedance, a second harmonic load impedance, a second third harmonic load impedance, a second fundamental source impedance, a second harmonic source impedance, and a second third harmonic source impedance of the second transistor;
A 3 : under the premise of ensuring that the insertion loss of the passive output matching network is small, a second transistor (pHEMT) is arranged 2 ) The fundamental load impedance of (a) is matched to a circular region near the output load impedance;
A 4 : on the premise of ensuring that the insertion loss of the passive interstage matching network is small, matching the first fundamental wave load impedance of the first transistor to a circular area near the second fundamental wave source impedance of the second transistor;
A 5 : on the premise of ensuring that the insertion loss of the passive input matching network is small, matching first fundamental wave source impedance Z1_ S1 of the first transistor to a circular area near input load impedance;
A 6 : in step A 3 On the basis, the second fundamental wave load impedance of the second transistor is strictly matched from a circular region near the output load impedance through injecting a third control signal into the active output matching networkTo the output load impedance point;
A 7 : in step A 4 On the basis, injecting a second control signal into the active interstage matching network, and strictly matching the first fundamental wave load impedance of the first transistor to the second fundamental wave source impedance of the second transistor from a circular region near the second fundamental wave source impedance of the second transistor;
A 8 : in step A 5 On the basis, injecting a first control signal into an active input matching network, and strictly matching first fundamental wave source impedance of a first transistor from a circular region near the input load impedance to an input load impedance point;
A 9 : according to step A 3 Step A 8 The designed matching network completes the integration and optimization of the schematic diagram and the layout.
Further, step A 6 And injecting a third control signal into the active output matching network to enable the second harmonic load impedance and the second third harmonic load impedance of the second transistor to be respectively at a short circuit point or an open circuit point.
Further, step A 7 And injecting a second control signal into the active interstage matching network to enable the first second harmonic load impedance and the first third harmonic load impedance of the first transistor and the second harmonic source impedance and the second third harmonic source impedance of the second transistor to be respectively at a short circuit point or an open circuit point.
Further, step A 8 And injecting a first control signal into the active input matching network to enable the first second harmonic source impedance and the first third harmonic source impedance of the first transistor to be respectively at a short circuit point or an open circuit point.
Compared with the prior art, the invention has the following remarkable effects:
1. the impedance positions of the first transistor and the second transistor are accurately controlled in a mode of combining active matching and passive matching, the impedance positions of the transistors are initially matched through the passive matching, the matching difficulty is reduced, the impedance positions are further corrected through the active matching on the basis, the correction comprises fundamental wave impedance position correction and harmonic wave impedance position correction, the impedance position accurate control is achieved, and the overall efficiency of the power amplifier is finally improved. The invention breaks through the constraint of Foster reactance theorem on circuit design, solves the problem that the impedance of a transistor in the traditional ultra-wideband power amplifier cannot be ideally matched at all frequency points, avoids the selection of compromise among the bandwidth, the output power and the efficiency in the power amplifier, and improves the efficiency of the power amplifier;
2. the invention has a plurality of active matching networks of an active input matching network, an active interstage matching network and an active output matching network, and simultaneously, each stage of active matching network has a first control signal, a second control signal and a third control signal which are independent respectively, and the first transistor pHEMT can be controlled according to the passive input matching network, the passive interstage matching network and the passive output matching network 1 And a second transistor pHEMT 2 The control signal is flexibly adjusted under the condition of preliminary impedance matching, so that the design flexibility is enriched;
3. according to the invention, the first control signal, the second control signal and the third control signal are all the combination of the output signals of the first signal source, the second signal source, … … and the third signal source, so that the fundamental load impedance and the fundamental source impedance of the first transistor and the second transistor can be matched, and the harmonic load impedance and the harmonic source impedance can be matched, so that the second harmonic load impedance, the third harmonic load impedance, the second harmonic source impedance and the third harmonic source impedance are at an open circuit point or a short circuit point.
Drawings
FIG. 1 is a block diagram of the overall structure of the present invention;
FIG. 2 is a schematic diagram of an input matching network in an embodiment of the present invention;
FIG. 3 is a schematic diagram of an interstage matching network in an embodiment of the invention;
FIG. 4 is a schematic diagram of an output matching network in an embodiment of the present invention;
FIG. 5 is a flow chart of an implementation of the present invention;
FIG. 6 is a diagram of the effects of passive matching and active matching of the present invention;
fig. 7 is a graph comparing efficiency of the passive matching network for preliminary impedance matching with efficiency of the active matching network after further impedance modification.
Detailed Description
The invention is described in further detail below with reference to the drawings and the detailed description.
The whole structure of the invention is shown in figure 1, and comprises a passive input matching network, an active input matching network, a passive interstage matching network, an active interstage matching network, a passive output matching network, an active output matching network, and a first transistor pHEMT 1 A second transistor pHEMT 2 。
Input terminal of passive input matching network and radio frequency input RF in Connecting; the input end of the active input matching network is connected with the output end of the passive input matching network; first transistor pHEMT 1 The grid of the active input matching network is connected with the output end of the active input matching network; first transistor pHEMT 1 The source of (2) is grounded; for providing good input standing waves and power gain flatness.
Input terminal of passive interstage matching network and first transistor pHEMT 1 Is connected with the drain electrode of the transistor; the input end of the active interstage matching network is connected with the output end of the passive interstage matching network; second transistor pHEMT 2 The grid of the active interstage matching network is connected with the output end of the active interstage matching network; second transistor pHEMT 2 The source of (2) is grounded; first transistor pHEMT 1 A second transistor pHEMT 2 To the radio frequency input RF in Multiple stages of amplification are used to provide sufficient power gain.
Input end of passive output matching network and second transistor pHEMT 2 Is connected with the drain electrode of the transistor; the input end of the active output matching network is connected with the output end of the passive output matching network; radio frequency output RF out The output end of the active output matching network is connected; to provide good output power and efficiency.
The control signal of the active input matching network is a first control signal CS in1 (ii) a The control signal of the active interstage matching network is a second control signal CS in2 (ii) a The control signal of the active output matching network is a third controlSignal CS in3 。
Radio frequency input RF in The input signal is an input signal source S 0 (ii) a The first control signal CS in1 A second control signal CS in2 A third control signal CS in3 Are all the first signal source S 1 A second signal source S 2 … …, nth signal source S n A combination of the output signals; n is a positive integer and n is more than or equal to 3.
Input signal source S 0 Output signal frequency of f 0 (ii) a First signal source S 1 Output signal frequency of f 0 (ii) a Second signal source S 2 The output signal frequency is 2f 0 (ii) a … …; nth signal source S n Output signal frequency of nf 0 。
The invention relates to a matching network at each level, which comprises the following parts:
in this embodiment, a schematic diagram of an input matching network is shown in fig. 2. The passive input matching network comprises a first resistor R 1 A second resistor R 2 A third resistor R 3 A fourth resistor R 4 A first microstrip line TL 1 A second microstrip line TL 2 A third microstrip line TL 3 A fourth microstrip line TL 4 A first capacitor C 1 A second capacitor C 2 A third capacitor C 3 . A first resistor R 1 With a radio frequency input RF in Connecting; a first resistor R 1 The other end of the first resistor is respectively connected with a second resistor R 2 And a third resistor R 3 Is connected with one end of the connecting rod; third resistor R 3 And the other end of the first microstrip line TL 1 Is connected with one end of the connecting rod; first microstrip line TL 1 The other end of the first and second electrodes is grounded; a second resistor R 2 And the other end of the first capacitor C 1 Is connected with one end of the connecting rod; a first capacitor C 1 The other end of the first capacitor is respectively connected with a second capacitor C 2 And a second microstrip line TL 2 Is connected with one end of the connecting rod; second capacitor C 2 The other end of the first and second electrodes is grounded; second microstrip line TL 2 The other end of the first microstrip line and the third microstrip line TL respectively 3 And a fourth resistor R 4 Is connected with one end of the connecting rod; third microstrip line TL 3 And the other end of the first microstrip line TL with a fifth microstrip line TL in the active input matching network 5 Is connected with one end of the connecting rod; a fourth resistor R 4 And the other end of the first microstrip line TL and the fourth microstrip line TL 4 Is connected with one end of the connecting rod; fourth microstrip line TL 4 The other end of the first and second transistors is respectively connected with a gate bias voltage V G1 And a third capacitance C 3 Is connected with one end of the connecting rod; third capacitor C 3 And the other end of the same is grounded. The active input matching network comprises a fifth microstrip line TL 5 A sixth microstrip line TL 6 And a seventh microstrip line TL 7 . Fifth microstrip line TL 5 And one end of the first microstrip line TL and a third microstrip line TL in the passive input matching network 3 Is connected with one end of the connecting rod; fifth microstrip line TL 5 Is respectively connected with the sixth microstrip line TL 6 And a seventh microstrip line TL 7 Is connected with one end of the connecting rod; sixth microstrip line TL 6 And the other end of the first transistor pHEMT 1 The gate of (1) is connected; seventh microstrip line TL 7 And the other end of the first control signal CS in1 And (4) connecting.
A schematic diagram of an interstage matching network in an embodiment of the invention is shown in fig. 3. The passive interstage matching network comprises an eighth microstrip line TL 8 A ninth microstrip line TL 9 A tenth microstrip line TL 10 An eleventh microstrip line TL 11 The twelfth microstrip line TL 12 A thirteenth microstrip line TL 13 A fourth capacitor C 4 A fifth capacitor C 5 A sixth capacitor C 6 A seventh capacitor C 7 An eighth capacitor C 8 A ninth capacitor C 9 A fifth resistor R 5 And a sixth resistor R 6 . Eighth microstrip line TL 8 And a first transistor pHEMT 1 Is connected with the drain electrode of the transistor; eighth microstrip line TL 8 The other end of the first microstrip line TL and the ninth microstrip line TL respectively 9 And a tenth microstrip line TL 10 Is connected with one end of the connecting rod; ninth microstrip line TL 9 Is respectively connected with the drain electrode bias voltage V D1 And a fourth capacitance C 4 Is connected with one end of the connecting rod; fourth capacitor C 4 The other end of the first and second electrodes is grounded; tenth microstrip line TL 10 The other end of which is connected to a fifth capacitor C 5 Is connected with one end of the connecting rod; fifth capacitor C 5 Respectively with a sixth capacitor C 6 A seventh capacitor C 7 A fifth resistor R 5 Is connected with one end of the connecting rod; sixth capacitor C 6 The other end of the first and second electrodes is grounded; seventh capacitance C 7 And the other end of the first resistor and a fifth resistor R 5 Is connected with the other end of the eighth capacitor C respectively 8 And an eleventh microstrip line TL 11 Is connected with one end of the connecting rod; eighth capacitor C 8 The other end of the first and second electrodes is grounded; eleventh microstrip line TL 11 The other end of the first microstrip line and the twelfth microstrip line TL respectively 12 And a sixth resistor R 6 Is connected with one end of the connecting rod; twelfth microstrip line TL 12 And the other end of the microstrip line (TL) is connected with a fourteenth microstrip line (TL) in the active interstage matching network 14 Is connected with one end of the connecting rod; a sixth resistor R 6 And the other end of the microstrip line TL and the thirteenth microstrip line TL 13 Is connected with one end of the connecting rod; thirteenth microstrip line TL 13 Respectively connected to a gate bias voltage V G2 And a ninth capacitor C 9 Is connected with one end of the connecting rod; ninth capacitor C 9 And the other end of the same is grounded. The active interstage matching network comprises a fourteenth microstrip line TL 14 A fifteenth microstrip line TL 15 Sixteenth microstrip line TL 16 . Fourteenth microstrip line TL 14 And one end of the microstrip line TL and the twelfth microstrip line TL in the passive input matching network 12 Is connected with one end of the connecting rod; fourteenth microstrip line TL 14 The other end of the first microstrip line and the fifteenth microstrip line TL respectively 15 And a sixteenth microstrip line TL 16 Is connected with one end of the connecting rod; fifteenth microstrip line TL 15 And the other end of the second transistor pHEMT 2 The gate of (1) is connected; sixteenth microstrip line TL 16 And the other end of the first control signal CS in2 And (4) connecting.
A schematic diagram of an output matching network in an embodiment of the invention is shown in fig. 4. The passive output matching network comprises a seventeenth microstrip line TL 17 Eighteenth microstrip line TL 18 Nineteenth microstrip line TL 19 Twentieth microstrip line TL 20 Twenty-first microstrip line TL 21 A tenth capacitor C 10 An eleventh capacitor C 11 And a twelfth capacitor C 12 A thirteenth capacitor C 13 And a fourteenth capacitor C 14 . Seventeenth microstrip line TL 17 And one end of the second transistor pHEMT 2 Is connected with the drain electrode of the transistor; seventeenth microstrip line TL 17 The other end of the first microstrip line and the eighteenth microstrip line TL respectively 18 And a nineteenth microstrip line TL 19 Is connected with one end of the connecting rod; eighteenth microstrip line TL 18 Is respectively connected with the drain electrode bias voltage V D2 And a tenth capacitance C 10 Is connected with one end of the connecting rod; a tenth capacitor C 10 The other end of the first and second electrodes is grounded; nineteenth microstrip line TL 19 And the other end of the first capacitor is respectively connected with an eleventh capacitor C 11 And a twelfth capacitor C 12 Is connected with one end of the connecting rod; eleventh capacitor C 11 The other end of the first and second electrodes is grounded; a twelfth capacitor C 12 The other end of the first microstrip line and the twentieth microstrip line TL respectively 20 And twenty-first microstrip line TL 21 Is connected with one end of the connecting rod; twentieth microstrip line TL 20 The other end of the first and second electrodes is grounded; twenty-first microstrip line TL 21 The other end of the first capacitor is respectively connected with a thirteenth capacitor C 13 And a fourteenth capacitance C 14 Is connected with one end of the connecting rod; thirteenth capacitor C 13 The other end of the first and second electrodes is grounded; a fourteenth capacitance C 14 And the other end of the second microstrip line TL with a twenty-second microstrip line TL in an active output matching network 22 Is connected at one end. The active output matching network comprises a twenty-second microstrip line TL 22 Twenty-third microstrip line TL 23 And a twenty-fourth microstrip line TL 24 . Twenty-second microstrip line TL 22 And a terminal of the fourth capacitor C in the passive output matching network 14 Is connected with one end of the connecting rod; twenty-second microstrip line TL 22 The other end of the first microstrip line and the twenty-third microstrip line TL respectively 23 And a twenty-fourth microstrip line TL 24 Is connected with one end of the connecting rod; twenty third microstrip line TL 23 And the other end of (3) and a radio frequency output RF out Connecting; twenty-fourth microstrip line TL 24 And the other end of the third control signal CS in3 And (4) connecting.
The flow chart of the implementation method of the invention is shown in FIG. 5, and comprises the following steps:
step A 1 Selecting a process route according to the required working frequency range; selecting the final total gate width of the power amplifier according to the required output power and the power density of the selected process path; determining the stage number of the power amplifier according to the required gain; the interstage drive ratio is determined according to the gain compression characteristics of the selected process path device.
Step A 2 To be more convenientThe subsequent steps are described to have a first transistor pHEMT 1 And a second transistor pHEMT 2 The two-stage amplification form is illustrated as an example, and it should be noted that the described implementation method is still applicable to the multi-stage amplification form. Determination of the first transistor pHEMT by Load Pull and Source Pull tests or simulations 1 A first fundamental load impedance, a first second harmonic load impedance, a first third harmonic load impedance, a first fundamental source impedance, a first second harmonic source impedance, a first third harmonic source impedance; determining the second transistor pHEMT 2 A second fundamental load impedance, a second harmonic load impedance, a second third harmonic load impedance, a second fundamental source impedance, a second harmonic source impedance, a second third harmonic source impedance.
Step A 3 On the premise of ensuring that the insertion loss of the passive output matching network is smaller, the second transistor pHEMT is used 2 Is matched to a circular region around the output load impedance (typically 50 omega), i.e. the second pair of transistors pHEMT 2 The second fundamental load impedance of (a) is subjected to preliminary impedance matching.
Step A 4 On the premise of ensuring that the insertion loss of the passive interstage matching network is small, the first transistor pHEMT is used 1 Is impedance matched to the second transistor pHEMT 2 Is the second fundamental source impedance, i.e. for the first transistor pHEMT 1 And a second transistor pHEMT 2 The second fundamental source impedance of (a) is preliminarily impedance-matched.
Step A 5 On the premise of ensuring that the insertion loss of the passive input matching network is smaller, the transistor pHEMT is used 1 Is impedance-matched to a circular region around the input load impedance (typically 50 Ω), i.e., to the transistor pHEMT 1 Is performed for preliminary impedance matching.
Step A 6 In step A 3 On the basis of the third control signal CS in3 Injecting into active output matching network to obtain second transistor pHEMT 2 Second fundamental load impedance from a circular region near the output load impedanceThe point of output load impedance being closely matched, i.e. to the second transistor pHEMT 2 Further correcting the second fundamental load impedance to realize accurate control. On the other hand, by the third control signal CS in3 Injecting an active output matching network so that the second transistor pHEMT 2 Is at a short circuit point or an open circuit point.
Step A 7 In step A 4 On the basis, the second control signal CS in2 Injecting an active interstage matching network to couple the first transistor pHEMT 1 Is driven from the second transistor pHEMT 2 Is closely matched to the second transistor pHEMT 2 Of the second fundamental source impedance, i.e. to the first transistor pHEMT 1 And a second transistor pHEMT 2 The second fundamental source impedance is further corrected, and accurate control is realized. On the other hand, by the second control signal CS in2 Injecting an active interstage matching network so that the first transistor pHEMT 1 First second harmonic load impedance, first third harmonic load impedance, second transistor pHEMT 2 The second harmonic source impedance and the second third harmonic source impedance are at a short circuit point or an open circuit point.
Step A 8 At step A 5 On the basis, the first control signal CS in1 Injecting an active input matching network to couple the first transistor pHEMT 1 Is strictly matched to the input load impedance point from a circular region near the input load impedance, i.e. to the first transistor pHEMT 1 The first fundamental load impedance is further corrected to realize accurate control. On the other hand, by the first control signal CS in1 Injecting an active input matching network so that the second transistor pHEMT 1 The second harmonic source impedance and the second third harmonic source impedance are at a short circuit point or an open circuit point.
Step A 9 According to step A 3 Step A 8 The designed matching network completes the integration and optimization of the schematic diagram and the layout.
The passive matching and active matching effects of the present invention are shown in fig. 6. For the sake of convenience of description, the second transistor pHEMT is used 2 The fundamental load impedance of (2) to the output load impedance (typically 50 omega) is taken as an example for explanation, it is noted that the described matching effect is for the first transistor pHEMT 1 First fundamental load impedance, second transistor pHEMT 2 Second fundamental source impedance, first transistor pHEMT 1 The same applies to the first fundamental source impedance of (1). The second transistor pHEMT is referred to as the initial impedance point in the following description 2 The output load impedance (typically 50 Ω) is referred to as an optimal impedance point. The initial impedance point is close to the edge position of the Smith chart and far away from the optimal impedance point, and the initial impedance point cannot be directly matched to the optimal impedance point under the ultra-wideband condition. Therefore, the initial impedance point is firstly subjected to preliminary impedance matching through the passive output matching network, namely, the initial impedance point is matched to a circular area near the optimal impedance point, and then the impedance position is further corrected through the active output matching network, namely, the initial impedance point is strictly matched to the optimal impedance point from the circular area near the optimal impedance point.
Fig. 7 is a graph showing the comparison between the efficiency of the initial impedance matching of the passive matching network and the efficiency of the active matching network after further impedance modification in the embodiment of the present invention, where the typical value of the power added efficiency PAE is 26% when the passive matching network performs the initial impedance matching, and the typical value of the power added efficiency PAE is 32% after further impedance modification of the active matching network. According to the efficiency comparison graph, the 6-18GHz power amplifier can solve the problem of impedance matching of transistors of the ultra-wideband power amplifier, and the efficiency of the ultra-wideband power amplifier is improved.
Finally, it should be noted that: the above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the protection scope of the present invention.
Claims (9)
1. A6-18 GHz power amplifier with active matching and passive matching is characterized in that: including withoutA source input matching network, an active input matching network, a passive interstage matching network, an active interstage matching network, a passive output matching network, an active output matching network, a first transistor (pHEMT) 1 ) A second transistor (pHEMT) 2 )；
Input and Radio Frequency (RF) input of the passive input matching network in ) The input end of the active input matching network is connected with the output end of the passive input matching network; the first transistor (pHEMT) 1 ) The grid of the active input matching network is connected with the output end of the active input matching network; the first transistor (pHEMT) 1 ) The source of (2) is grounded;
the input of the passive interstage matching network is connected to a first transistor (pHEMT) 1 ) Is connected with the drain electrode of the transistor; the input end of the active interstage matching network is connected with the output end of the passive interstage matching network; the second transistor (pHEMT) 2 ) The grid of the active interstage matching network is connected with the output end of the active interstage matching network; the second transistor (pHEMT) 2 ) The source of (2) is grounded;
the input of the passive output matching network is connected to a second transistor (pHEMT) 2 ) Is connected with the drain electrode of the transistor; the input end of the active output matching network is connected with the output end of the passive output matching network; radio frequency output (RF) out ) The output end of the active output matching network is connected;
the control signal of the active input matching network is a first Control Signal (CS) in1 ) (ii) a The control signal of the active interstage matching network is a second Control Signal (CS) in2 ) (ii) a The control signal of the active output matching network is a third Control Signal (CS) in3 )；
Radio frequency input (RF) in ) Is an input signal source (S) 0 ) (ii) a Said first Control Signal (CS) in1 ) A second Control Signal (CS) in2 ) A third Control Signal (CS) in3 ) Are all the first signal source (S) 1 ) A second signal source (S) 2 ) … …, nth signal source (S) n ) A combination of the output signals; n is a positive integer and is not less than 3;
input signal source (S) 0 ) Output signal ofFrequency f 0 (ii) a A first signal source (S) 1 ) Output signal frequency of f 0 (ii) a A second signal source (S) 2 ) The output signal frequency is 2f 0 (ii) a … …; nth signal source (S) n ) Output signal frequency of nf 0 。
2. The active matching combined with passive matching 6-18GHz power amplifier of claim 1 wherein: the passive input matching network comprises a first resistor (R) 1 ) A second resistor (R) 2 ) A third resistor (R) 3 ) A fourth resistor (R) 4 ) A first microstrip line (TL) 1 ) A second microstrip line (TL) 2 ) A third microstrip line (TL) 3 ) A fourth microstrip line (TL) 4 ) A first capacitor (C) 1 ) A second capacitor (C) 2 ) A third capacitor (C) 3 ) (ii) a A first resistor (R) 1 ) And a radio frequency input terminal (RF) in ) Connecting; a first resistance (R) 1 ) Respectively with a second resistor (R) 2 ) And a third resistor (R) 3 ) Is connected with one end of the connecting rod; third resistance (R) 3 ) And the other end of the first microstrip line (TL) 1 ) Is connected with one end of the connecting rod; first microstrip line (TL) 1 ) The other end of the first and second electrodes is grounded; a second resistor (R) 2 ) And the other terminal of (C) and a first capacitor (C) 1 ) Is connected with one end of the connecting rod; a first capacitor (C) 1 ) Respectively with a second capacitor (C) 2 ) And a second microstrip line (TL) 2 ) Is connected with one end of the connecting rod; a second capacitance (C) 2 ) The other end of the first and second electrodes is grounded; second microstrip line (TL) 2 ) Respectively with a third microstrip line (TL) 3 ) And a fourth resistance (R) 4 ) Is connected with one end of the connecting rod; third microstrip line (TL) 3 ) And the other end of the first microstrip line (TL) is connected with a fifth microstrip line (TL) in the active input matching network 5 ) Is connected with one end of the connecting rod; fourth resistance (R) 4 ) The other end of (TL) and a fourth microstrip line (TL) 4 ) Is connected with one end of the connecting rod; fourth microstrip line (TL) 4 ) Respectively with a gate bias voltage (V) G1 ) And a third capacitance (C) 3 ) Is connected with one end of the connecting rod; third capacitance (C) 3 ) The other end of the first and second electrodes is grounded;
the active input matching network comprises a fifth microstrip line (TL) 5 ) The first stepSix microstrip line (TL) 6 ) And a seventh microstrip line (TL) 7 ) Fifth microstrip line (TL) 5 ) And one end of the first microstrip line (TL) is connected with a third microstrip line (TL) in the passive input matching network 3 ) Is connected with one end of the connecting rod; fifth microstrip line (TL) 5 ) Respectively with a sixth microstrip line (TL) 6 ) And a seventh microstrip line (TL) 7 ) Is connected with one end of the connecting rod; sixth microstrip line (TL) 6 ) And the other end of the first transistor (pHEMT) 1 ) The gate of (1) is connected; seventh microstrip line (TL) 7 ) And the other end of (c) and a first Control Signal (CS) in1 ) And (4) connecting.
3. The active matching combined with passive matching 6-18GHz power amplifier of claim 1 wherein: the passive interstage matching network comprises an eighth microstrip line (TL) 8 ) Ninth microstrip line (TL) 9 ) A tenth microstrip line (TL) 10 ) Eleventh microstrip line (TL) 11 ) A twelfth microstrip line (TL) 12 ) A thirteenth microstrip line (TL) 13 ) A fourth capacitor (C) 4 ) A fifth capacitor (C) 5 ) A sixth capacitor (C) 6 ) A seventh capacitor (C) 7 ) An eighth capacitor (C) 8 ) A ninth capacitor (C) 9 ) A fifth resistor (R) 5 ) And a sixth resistance (R) 6 ) (ii) a Eighth microstrip line (TL) 8 ) And a first transistor (pHEMT) 1 ) Is connected with the drain electrode of the transistor; eighth microstrip line (TL) 8 ) Respectively with a ninth microstrip line (TL) 9 ) And a tenth microstrip line (TL) 10 ) Is connected with one end of the connecting rod; ninth microstrip line (TL) 9 ) Respectively with a drain bias voltage (V) D1 ) And a fourth capacitance (C) 4 ) Is connected with one end of the connecting rod; fourth capacitance (C) 4 ) The other end of the first and second electrodes is grounded; tenth microstrip line (TL) 10 ) And the other end of the first capacitor (C) and a fifth capacitor (C) 5 ) Is connected with one end of the connecting rod; fifth capacitance (C) 5 ) Respectively with a sixth capacitance (C) 6 ) A seventh capacitor (C) 7 ) A fifth resistor (R) 5 ) Is connected with one end of the connecting rod; sixth capacitance (C) 6 ) The other end of the first and second electrodes is grounded; seventh capacitance (C) 7 ) And the other end of (C) and a fifth resistor (R) 5 ) Are connected with the other end of the eighth capacitor (C) respectively 8 ) And an eleventh microstrip line (T)L 11 ) Is connected with one end of the connecting rod; eighth capacitance (C) 8 ) The other end of the first and second electrodes is grounded; eleventh microstrip line (TL) 11 ) The other end of the first microstrip line (TL) and a twelfth microstrip line (TL) respectively 12 ) And a sixth resistance (R) 6 ) Is connected with one end of the connecting rod; twelfth microstrip line (TL) 12 ) And the other end of the first microstrip line (TL) is connected with a fourteenth microstrip line (TL) in the active interstage matching network 14 ) Is connected with one end of the connecting rod; sixth resistance (R) 6 ) And the other end of the microstrip line (TL) 13 ) Is connected with one end of the connecting rod; thirteenth microstrip line (TL) 13 ) Respectively with a gate bias voltage (V) G2 ) And a ninth capacitance (C) 9 ) Is connected with one end of the connecting rod; ninth capacitance (C) 9 ) The other end of the second switch is grounded;
the active interstage matching network comprises a fourteenth microstrip line (TL) 14 ) Fifteenth microstrip line (TL) 15 ) And a sixteenth microstrip line (TL) 16 ) Fourteenth microstrip line (TL) 14 ) And one end of the microstrip line (TL) is connected with a twelfth microstrip line (TL) in the passive input matching network 12 ) Is connected with one end of the connecting rod; fourteenth microstrip line (TL) 14 ) The other end of the first microstrip line (TL) and a fifteenth microstrip line (TL) 15 ) And a sixteenth microstrip line (TL) 16 ) Is connected with one end of the connecting rod; fifteenth microstrip line (TL) 15 ) And the other end of the second transistor (pHEMT) 2 ) The gate of (1) is connected; sixteenth microstrip line (TL) 16 ) And the other end of (c) and a second Control Signal (CS) in2 ) And (4) connecting.
4. The active matching combined with passive matching 6-18GHz power amplifier of claim 1 wherein: the passive output matching network comprises a seventeenth microstrip line (TL) 17 ) Eighteenth microstrip line (TL) 18 ) Nineteenth microstrip line (TL) 19 ) Twentieth microstrip line (TL) 20 ) Twenty-first microstrip line (TL) 21 ) A tenth capacitor (C) 10 ) An eleventh capacitor (C) 11 ) A twelfth capacitor (C) 12 ) A thirteenth capacitor (C) 13 ) And a fourteenth capacitance (C) 14 ) (ii) a Seventeenth microstrip line (TL) 17 ) And one terminal of the second transistor (pHEMT) 2 ) Is connected with the drain electrode of the transistor; seventeenth microstrip line (TL) 17 ) The other end of the first microstrip line is respectively connected with an eighteenth microstrip line(TL 18 ) And nineteenth microstrip line (TL) 19 ) Is connected with one end of the connecting rod; eighteenth microstrip line (TL) 18 ) Respectively with a drain bias voltage (V) D2 ) And a tenth capacitance (C) 10 ) Is connected with one end of the connecting rod; tenth capacitance (C) 10 ) The other end of the second switch is grounded; nineteenth microstrip line (TL) 19 ) Respectively with an eleventh capacitance (C) 11 ) And a twelfth capacitance (C) 12 ) Is connected with one end of the connecting rod; eleventh capacitance (C) 11 ) The other end of the first and second electrodes is grounded; twelfth capacitor (C) 12 ) The other end of the first microstrip line and the twentieth microstrip line (TL) respectively 20 ) And twenty-first microstrip line (TL) 21 ) Is connected with one end of the connecting rod; twentieth microstrip line (TL) 20 ) The other end of the second switch is grounded; twenty-first microstrip line (TL) 21 ) Respectively with a thirteenth capacitor (C) 13 ) And a fourteenth capacitance (C) 14 ) Is connected with one end of the connecting rod; thirteenth capacitor (C) 13 ) The other end of the second switch is grounded; a fourteenth capacitance (C) 14 ) And the other end of the first microstrip line (TL) and a twenty-second microstrip line (TL) in the active output matching network 22 ) Is connected with one end of the connecting rod;
the active output matching network comprises a twenty-second microstrip line (TL) 22 ) Twenty third microstrip line (TL) 23 ) And a twenty-fourth microstrip line (TL) 24 ) Twenty-second microstrip line (TL) 22 ) And a terminal of (C) is connected to a fourteenth capacitor (C) in the passive output matching network 14 ) Is connected with one end of the connecting rod; twenty-second microstrip line (TL) 22 ) The other end of the first microstrip line is respectively connected with a twenty-third microstrip line (TL) 23 ) And a twenty-fourth microstrip line (TL) 24 ) Is connected with one end of the connecting rod; twenty-third microstrip line (TL) 23 ) And the other end of (RF) and a radio frequency output terminal (RF) out ) Connecting; twenty-fourth microstrip line (TL) 24 ) And the other end of (c) and a third Control Signal (CS) in3 ) And (4) connecting.
5. A method for realizing a 6-18GHz power amplifier combining active matching and passive matching is characterized by comprising the following steps: using a combination of active and passive matching for the first transistor (pHEMT) 1 ) And a second transistor (pHEMT) 2 ) The impedance position of the sensor is accurately controlled: firstly, impedance positions of two transistors are matched through a passive matching circuitPreliminary matching is carried out, and matching difficulty is reduced; and further correcting the impedance position through active matching, wherein the correction comprises fundamental impedance position correction and harmonic impedance position correction.
6. The method for implementing the active matching combined with passive matching 6-18GHz power amplifier according to claim 5, characterized by comprising the following steps:
A 1 : selecting a process approach according to the required working frequency range; selecting the final total gate width of the power amplifier according to the required output power and the power density of the selected process path; determining the stage number of the power amplifier according to the required gain; determining an interstage drive ratio according to gain compression characteristics of the selected process path device;
A 2 : the first transistor (pHEMT) is determined by Load Pull and Source Pull tests or simulations 1 ) Determines the second transistor (pHEMT) based on the first fundamental load impedance, the first second harmonic load impedance, the first third harmonic load impedance, the first fundamental source impedance, the first second harmonic source impedance, and the first third harmonic source impedance 2 ) A second fundamental load impedance, a second harmonic load impedance, a second third harmonic load impedance, a second fundamental source impedance, a second harmonic source impedance, and a second third harmonic source impedance;
A 3 : under the premise of ensuring that the insertion loss of the passive output matching network is small, a second transistor (pHEMT) is arranged 2 ) Is matched to a circular region near the output load impedance;
A 4 : under the premise of ensuring that the insertion loss of the passive interstage matching network is smaller, the first transistor (pHEMT) 1 ) Is impedance matched to the second transistor (pHEMT) 2 ) A circular region near the second fundamental source impedance;
A 5 : under the premise of ensuring that the insertion loss of the passive input matching network is small, a first transistor (pHEMT) is used 1 ) Is impedance-matched to a circular region near the input load impedance;
A 6 : in step A 3 On the basis of the third Control Signal (CS) in3 ) Injecting an active output matching network to connect the second transistor (pHEMT) 2 ) Is strictly matched to the output load impedance point from the circular region around the output load impedance;
A 7 : in step A 4 On the basis, by means of a second Control Signal (CS) in2 ) Injecting an active interstage matching network into the first transistor (pHEMT) 1 ) Is driven from the second transistor (pHEMT) 2 ) Is closely matched to the second transistor (pHEMT) in a circular region around the second fundamental source impedance 2 ) A second fundamental source impedance of (a);
A 8 : in step A 5 On the basis of the first Control Signal (CS) in1 ) Injecting an active input matching network into the first transistor (pHEMT) 1 ) Is strictly matched to the input load impedance point from a circular region near the input load impedance;
A 9 : according to step A 3 Step A 8 The designed matching network completes the integration and optimization of the schematic diagram and the layout.
7. The method for implementing the active matching and passive matching 6-18GHz power amplifier according to claim 5, wherein the step A is implemented by using a plurality of stages 6 By a third Control Signal (CS) in3 ) Injecting an active output matching network to make the second transistor (pHEMT) 2 ) The second harmonic load impedance and the second third harmonic load impedance are at a short circuit point or an open circuit point, respectively.
8. The method for implementing the 6-18GHz power amplifier combining the active matching and the passive matching according to claim 5, wherein the step A is implemented 7 By means of a second Control Signal (CS) in2 ) Injecting an active interstage matching network so that the first transistor (pHEMT) 1 ) First second harmonic load impedance, first third harmonic load impedance and second transistor (pHEMT) 2 ) The second harmonic source impedance and the second third harmonic source impedance are respectively in shortWaypoints or open circuit points.
9. The method for implementing the 6-18GHz power amplifier combining the active matching and the passive matching according to claim 5, wherein the step A is implemented 8 By means of a first Control Signal (CS) in1 ) Injecting an active input matching network into the first transistor (pHEMT) 1 ) The first second harmonic source impedance and the first third harmonic source impedance are respectively at a short circuit point or an open circuit point.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116915196A (en) * | 2023-09-11 | 2023-10-20 | 合肥芯谷微电子股份有限公司 | Power amplifier |
| CN118921015A (en) * | 2024-08-02 | 2024-11-08 | 北京中电科卫星导航系统有限公司 | High-power tunable oscillator circuit |
| CN119254161A (en) * | 2024-12-05 | 2025-01-03 | 中国电子科技集团公司第五十五研究所 | Non-switching composite dual-mode large dynamic reconfigurable power amplifier and electronic equipment |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116915196A (en) * | 2023-09-11 | 2023-10-20 | 合肥芯谷微电子股份有限公司 | Power amplifier |
| CN116915196B (en) * | 2023-09-11 | 2023-12-08 | 合肥芯谷微电子股份有限公司 | Power amplifier |
| CN118921015A (en) * | 2024-08-02 | 2024-11-08 | 北京中电科卫星导航系统有限公司 | High-power tunable oscillator circuit |
| CN119254161A (en) * | 2024-12-05 | 2025-01-03 | 中国电子科技集团公司第五十五研究所 | Non-switching composite dual-mode large dynamic reconfigurable power amplifier and electronic equipment |
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