CN115763443A - Preparation method of semiconductor device and semiconductor device - Google Patents

Abstract

The invention discloses a preparation method of a semiconductor device and the semiconductor device, relates to the technical field of semiconductor device preparation, and aims to solve the problem that the performance of the semiconductor device is influenced by leakage current caused by the fact that generated hydrogen diffuses into a dielectric layer to form oxygen vacancies when a germanium-silicon layer is formed. The preparation method of the semiconductor device comprises the following steps: a substrate is provided. The substrate comprises a lower electrode layer, a dielectric layer and an upper electrode layer which are stacked from bottom to top. A first silicon seed layer is formed on the upper electrode layer. And forming an interlayer oxide layer on the first silicon seed crystal layer. And forming a germanium-silicon layer on the interlayer oxide layer. The preparation method of the semiconductor device is used for preparing the semiconductor device.

Description

A kind of preparation method of semiconductor device and semiconductor device

technical field

The invention relates to the technical field of semiconductor device preparation, in particular to a method for preparing a semiconductor device and the semiconductor device.

Background technique

In the semiconductor manufacturing process, as the integration degree of semiconductor devices increases, the thickness of the dielectric layer and the thicknesses of the upper and lower electrode layers on both sides of the dielectric layer are gradually reduced. When a germanium-silicon film is formed above a semiconductor device with an aspect ratio exceeding 40:1, a lot of hydrogen gas will be generated. At this time, due to the small thickness of the upper and lower electrode layers located on both sides of the dielectric layer, the generated hydrogen gas can penetrate The through-electrode layer diffuses into the dielectric layer, so that oxygen vacancies are formed in the dielectric layer, thereby generating leakage current and affecting the performance of the semiconductor device.

Contents of the invention

The object of the present invention is to provide a method for preparing a semiconductor device and a semiconductor device, which are used to prevent the hydrogen gas generated from diffusing into the dielectric layer when forming the silicon germanium layer, forming oxygen vacancies, thereby generating leakage current, and affecting the performance of the semiconductor device. Circumstances that have an impact occur.

In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device. The preparation method of the semiconductor device comprises:

Provide the substrate. The substrate includes a lower electrode layer, a dielectric layer and an upper electrode layer stacked from bottom to top.

A first silicon seed layer is formed on the upper electrode layer.

An interlayer oxide layer is formed on the first silicon seed layer.

A silicon germanium layer is formed on the interlayer oxide layer.

Compared with the prior art, in the preparation method of the semiconductor device provided by the present invention, in the process of forming the silicon germanium layer, firstly, the first silicon seed layer is formed on the upper electrode layer, and the first silicon seed layer is formed on the first silicon seed layer. An interlayer oxide layer is formed. At this time, when the silicon germanium layer is formed on the interlayer oxide layer, due to the existence of the interlayer oxide layer, a large amount of hydrogen gas generated will undergo redox reactions with the stable interlayer oxide layer, thereby preventing hydrogen gas from entering the dielectric layer. Therefore, the formation of oxygen vacancies in the dielectric layer is avoided, and leakage current is avoided, so that the performance of the semiconductor device is improved.

The present invention also provides a semiconductor device, which includes: a substrate stacked from bottom to top, a first silicon seed layer, an interlayer oxide layer, and a silicon germanium layer;

Wherein, the substrate includes a lower electrode layer, a dielectric layer and an upper electrode layer stacked from bottom to top.

The beneficial effect of the semiconductor device provided by the present invention is the same as that of the method for manufacturing the semiconductor device provided by the present invention, and will not be repeated here.

Description of drawings

The accompanying drawings described here are used to provide a further understanding of the present invention, and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention, and do not constitute improper limitations to the present invention. In the attached picture:

FIG. 1 is a block flow diagram of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention.

Detailed ways

In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

It should be noted that when an element is referred to as being “fixed” or “disposed on” another element, it may be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more than one, unless otherwise clearly and specifically defined.

In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right" etc. are based on those shown in the accompanying drawings. Orientation or positional relationship is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

In the description of the present invention, it should be noted that unless otherwise specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it may be mechanical connection or electrical connection; it may be direct connection or indirect connection through an intermediary, and it may be the internal communication of two elements or the interaction relationship between two elements. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention according to specific situations.

At present, when preparing a semiconductor device, firstly, a titanium nitride film needs to be formed as the lower electrode of the capacitor, and then, a dielectric layer of the capacitor is formed above the titanium nitride film. The titanium nitride film and the silicon germanium film are regenerated as the upper electrode of the capacitor. Specifically, in order to form a suitable silicon germanium film, the first deposition is performed using silane gas to obtain the first silicon seed layer. Then, use silane gas and boron trichloride gas for the second deposition to obtain the second silicon seed layer, and finally, use silane gas, germanium hydride gas, boron trichloride gas and nitrogen gas for the third deposition, A silicon germanium layer is generated. However, with the gradual improvement of the integration level of semiconductor devices, the thickness of the dielectric layer and the electrode layer is gradually reduced. At this time, when the silicon germanium layer is formed, a large amount of hydrogen gas diffuses into the dielectric layer, so that oxygen vacancies are formed in the dielectric layer, causing the semiconductor device to generate leakage current, thereby affecting the performance of the semiconductor device.

In order to overcome the above phenomenon, an embodiment of the present invention provides a method for preparing a semiconductor device. When using the method for preparing a semiconductor device to prepare a semiconductor device, the generated hydrogen will not diffuse into the dielectric layer, thereby fundamentally avoiding leakage. Possibility of current.

FIG. 1 illustrates a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.

As shown in FIG. 1, the method for preparing a semiconductor device provided by an embodiment of the present invention includes:

Step 100: providing a substrate. The substrate includes a lower electrode layer, a dielectric layer and an upper electrode layer stacked from bottom to top.

In practical applications, the above-mentioned lower electrode layer may be a titanium nitride film, or a tantalum nitride film or the like. The lower electrode layer can be formed by chemical vapor deposition, and then a dielectric layer is formed on the lower electrode layer, and an upper electrode layer is formed on the dielectric layer. The upper electrode layer here may be a titanium nitride film, or a tantalum nitride film or the like. It should be noted that the processes of sequentially forming the lower electrode layer, the dielectric layer and the upper electrode layer on the substrate are common processes, and will not be repeated here.

Step 110: forming a first silicon seed layer on the upper electrode layer. Specifically, when the upper electrode layer is a titanium nitride layer, forming the first silicon seed layer on the upper electrode layer includes: adopting a chemical vapor deposition process, under the first process condition, introducing the first process gas to form a first silicon seed layer on the titanium nitride layer by using the first process gas. The first process condition here includes: the pressure of the process chamber may be 0.3 torr-1.0 torr, for example, the pressure of the process chamber may be 0.3 torr, 0.5 torr, or 1.0 torr. The temperature of the process chamber may be 350°C-470°C, for example, the temperature of the process chamber may be 350°C, 370°C, or 470°C. The first process gas may be a silicon source gas. For example, the silicon source gas may be silane gas, and the flow rate of the silicon source gas may be 10 sccm to 1000 sccm. For example, the silicon source gas flow rate may be 150 sccm, 500 sccm, or Can be 1000 sccm.

After forming the first silicon seed layer on the upper electrode layer and before forming the interlayer oxide layer on the first silicon seed layer, the method for preparing the above-mentioned semiconductor device further includes: using a chemical vapor deposition process, under the second process condition , introducing a second process gas into the process chamber, so as to form a second silicon seed layer on the first silicon seed layer by using the second process gas. Specifically, the second process condition includes: the pressure of the process chamber is 0.3 torr˜1.0 torr, for example, the pressure of the process chamber may be 0.3 torr, 0.5 torr, or 1.0 torr. The temperature of the process chamber may be 350°C-470°C, for example, the temperature of the process chamber may be 350°C, 370°C, or 470°C. The second process gas is a silicon source gas and a boron source gas. The silicon source gas can be silane gas, and the flow rate of the silicon source gas can be 10 sccm to 1000 sccm. For example, the silicon source gas flow rate can be 150 sccm, 500 sccm, or Can be 1000 sccm. The boron source gas may be boron trichloride gas, and the flow rate of the boron source gas may be 10 sccm-1000 sccm. For example, the silicon source gas flow rate may be 150 sccm, 500 sccm, or 1000 sccm.

Step 120: forming an interlayer oxide layer on the first silicon seed layer. It should be noted here that, in order to ensure that polysilicon has the function of a conductor, the thickness of the interlayer oxide layer should not be too thick. Therefore, the thickness of the interlayer oxide layer can be 3 angstroms to 10 angstroms. For example, the thickness of the interlayer oxide layer The thickness can be 3 angstroms, 7 angstroms, or 10 angstroms. Specifically, forming the interlayer oxide layer on the first silicon seed layer includes: adopting a chemical vapor deposition process, under the third process condition, passing a third process gas into the process chamber, so as to use the third process gas to An interlayer oxide layer is formed on the silicon seed layer. The third process condition here includes: the pressure of the process chamber is 0.3 torr˜1.0 torr, for example, the pressure of the process chamber can be 0.3 torr, 0.5 torr, or 1.0 torr. The temperature of the process chamber may be 400°C-470°C, for example, the temperature of the process chamber may be 400°C, 450°C, or 470°C. The interlayer oxide layer can be a silicon dioxide thin film layer, or a silicon nitride oxide thin film layer.

For example, when the interlayer oxide layer can be a silicon dioxide thin film layer, the above-mentioned third process gas can include silicon source gas and oxygen source gas, wherein the silicon source gas is silane gas or disilane gas, and the flow rate of silicon source gas It may be 10 sccm-1000 sccm, for example, the flow rate of the silicon source gas may be 150 sccm, 500 sccm, or 1000 sccm. The oxygen source gas can be oxygen, and the flow rate of the oxygen source gas can be 10 sccm-1000 sccm, for example, the flow rate of the oxygen source gas can be 150 sccm, 500 sccm, or 1000 sccm.

For another example, when the interlayer oxide layer is a silicon oxynitride thin film layer, the third process gas includes silicon source gas, oxygen source gas and nitrogen source gas, wherein the silicon source gas is silane gas or disilane gas, and the silicon source gas The flow rate of the gas may be 10 sccm-1000 sccm, for example, the silicon source gas may be 150 sccm, 500 sccm, or 1000 sccm. The oxygen source gas can be oxygen, and the flow rate of the oxygen source gas can be 10 sccm-1000 sccm, for example, the flow rate of the oxygen source gas can be 150 sccm, 500 sccm, or 1000 sccm. The nitrogen source gas is nitrogen or ammonia, and the flow rate of the nitrogen source gas can be 10sccm-1000sccm, for example, the flow rate of the nitrogen source gas can be 150sccm, 500sccm, or 1000sccm.

Step 130: forming a SiGe layer on the interlayer oxide layer. Specifically, forming the germanium-silicon layer on the interlayer oxide layer includes: adopting a chemical vapor deposition process, under the fourth process condition, passing a fourth process gas into the process chamber, so as to use the fourth process gas to form the interlayer oxide layer. A silicon germanium layer is formed on it. The fourth process condition here includes: the pressure of the process chamber is 0.3 torr-1.0 torr, for example, the pressure of the process chamber may be 0.3 torr, 0.5 torr, or 1.0 torr. The temperature of the process chamber may be 350°C-470°C, for example, the temperature of the process chamber may be 350°C, 370°C, or 470°C. The fourth process gas includes silicon source gas, germanium source gas, boron source gas and nitrogen source gas. Wherein, the silicon source gas is silane gas or disilane gas, and the flow rate of the silicon source gas may be 10 sccm-1000 sccm, for example, the silicon source gas flow rate may be 150 sccm, 500 sccm, or 1000 sccm. The germanium source gas is germanium tetrahydrogen gas, and the flow rate of the germanium source gas may be 10 sccm-1000 sccm, for example, the germanium source gas flow rate may be 150 sccm, 500 sccm, or 1000 sccm. The boron source gas is boron gas or boron trichloride gas, and the flow rate of the boron source gas can be 10 sccm-1000 sccm, for example, the flow rate of the boron source gas can be 150 sccm, 500 sccm, or 1000 sccm. The nitrogen source gas is nitrogen. The flow rate of the nitrogen source gas may be 10 sccm˜1000 sccm, for example, the flow rate of the nitrogen source gas may be 150 sccm, 500 sccm, or 1000 sccm.

Based on the above, in the process of forming the silicon germanium layer in the method for manufacturing a semiconductor device provided by the embodiment of the present invention, firstly, a first silicon seed layer is formed on the upper electrode layer, and an interlayer silicon layer is formed on the first silicon seed layer. Oxide layer, the interlayer oxide layer has extremely stable chemical properties and electrical insulation properties. At this time, when the silicon germanium layer is formed on the interlayer oxide layer, due to the existence of the interlayer oxide layer, a large amount of hydrogen gas generated will undergo redox reactions with the stable interlayer oxide layer, thereby preventing hydrogen gas from entering the dielectric layer. Therefore, the formation of oxygen vacancies in the dielectric layer is avoided, and leakage current is avoided, so that the performance of the semiconductor device is improved. Based on this, due to the disappearance of oxygen vacancies in the dielectric layer of the semiconductor device, the breakdown voltage of the semiconductor device increases, so that the capacitance of the semiconductor device increases when the dielectric is thinner.

FIG. 2 illustrates a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention. As shown in FIG. 2, the semiconductor device provided by the embodiment of the present invention includes: a substrate stacked from bottom to top, a first silicon seed layer 4, an interlayer oxide layer 6, and a silicon germanium layer 7, wherein,

The substrate includes a lower electrode layer 1 , a dielectric layer 2 and an upper electrode layer 3 stacked from bottom to top.

As shown in FIG. 2 , the above-mentioned semiconductor device may further include a second silicon seed layer 5 . The second silicon seed layer 5 is located between the first silicon seed layer 4 and the interlayer oxide layer 6 .

The beneficial effect of the semiconductor device is the same as that of the above-mentioned method for manufacturing the semiconductor device, and will not be repeated here.

In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in an appropriate manner.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (11)

1. A method for manufacturing a semiconductor device, comprising:

providing a substrate; the substrate comprises a lower electrode layer, a dielectric layer and an upper electrode layer which are stacked from bottom to top;

forming a first silicon seed layer on the upper electrode layer;

forming an interlayer oxide layer on the first silicon seed crystal layer;

and forming a germanium-silicon layer on the interlayer oxide layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the forming of the first silicon seed layer on the upper electrode layer comprises:

and under a first process condition, introducing a first process gas into the process chamber so as to form a first silicon seed crystal layer on the upper electrode layer by utilizing the first process gas.

3. The method for manufacturing a semiconductor device according to claim 2, wherein the first process condition includes: the pressure of the process cavity is 0.3to 1.0torr, and the temperature of the process cavity is 350 to 470 ℃; and/or the presence of a gas in the atmosphere,

the first process gas is a silicon source gas.

4. The method of manufacturing a semiconductor device according to claim 1, wherein the method of manufacturing a semiconductor device further comprises, after forming the first silicon seed layer on the upper electrode layer before forming the interlayer oxide layer on the first silicon seed layer:

and under a second process condition, introducing a second process gas into the process chamber so as to form a second silicon seed crystal layer on the first silicon seed crystal layer by using the second process gas.

5. The method according to claim 4, wherein the second process condition comprises: the pressure of the process cavity is 0.3to 1.0torr, and the temperature of the process cavity is 350 to 470 ℃; and/or the presence of a gas in the atmosphere,

the second process gas is a silicon source gas and a boron source gas.

6. The method of claim 1, wherein said forming an inter-layer oxide layer on the first silicon seed layer comprises:

and under a third process condition, introducing a third process gas into the process chamber to form an interlayer oxide layer on the first silicon seed crystal layer by using the third process gas.

7. The method according to claim 6, wherein the third process condition comprises: the pressure of the process cavity is 0.3to 1.0torr, and the temperature of the process cavity is 400 to 470 ℃.

8. The method of manufacturing a semiconductor device according to claim 6, wherein the inter-layer oxide layer is a silicon dioxide thin film layer, and the third process gas comprises a silicon source gas and an oxygen source gas, wherein the silicon source gas is a silane gas or a disilane gas, and the oxygen source gas is oxygen; or the like, or, alternatively,

the oxide layer is silicon oxynitride film layer between the layer, third process gas includes that silicon source is gaseous, oxygen source gas and nitrogen source are gaseous, wherein, silicon source is gaseous for silane or disilane, oxygen source gas is oxygen, nitrogen source gas is nitrogen gas or ammonia.

9. The method of manufacturing a semiconductor device according to claim 1, wherein the forming a silicon germanium layer on the interlayer oxide layer comprises:

under a fourth process condition, introducing a fourth process gas into the process chamber so as to form a germanium-silicon layer on the interlayer oxide layer by using the fourth process gas; wherein the fourth process conditions comprise: the pressure of the process cavity is 0.3to 1.0torr, and the temperature of the process cavity is 350 to 470 ℃; and/or the presence of a gas in the gas,

the fourth process gas comprises a silicon source gas, a germanium source gas, a boron source gas and a nitrogen source gas; the silicon source gas is silane gas or disilane gas, the germanium source gas is germanium tetrahydride gas, the boron source gas is boron trichloride gas, and the nitrogen source gas is nitrogen.

10. The method for manufacturing a semiconductor device according to any one of claims 1 to 9, wherein the thickness of the interlayer oxide layer is 3to 10 angstroms.

11. A semiconductor device, characterized in that the semiconductor device comprises: the substrate, the first silicon seed crystal layer, the interlayer oxidation layer and the germanium-silicon layer are stacked from bottom to top;

the substrate comprises a lower electrode layer, a dielectric layer and an upper electrode layer which are stacked from bottom to top.

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