CN115758699B - Key pattern rapid screening method and device for full-chip light source mask optimization - Google Patents

Abstract

The invention discloses a method and device for fast screening of key figures oriented to optimization of a full-chip light source mask. The invention belongs to the field of semiconductor computational lithography. In the present invention, by flattening and slicing the full-chip graphics into equal sizes, combined with an efficient and approximate lithography imaging model and an SMO process based on lithography complexity and grading of slice defect regions, it can avoid complex screening rule design or huge graphics At the same time of spectrum analysis, the key graphics for full-chip light source mask optimization can be quickly and accurately screened or obtained. According to the lithographic imaging process, the present invention specifically simplifies each component module on the premise of ensuring the qualitative description of the characteristics of each module.

Description

Key pattern rapid screening method and device for full-chip light source mask optimization

technical field

The invention belongs to the field of semiconductor computational lithography, and more specifically relates to a method and device for fast screening of key patterns oriented to full-chip light source mask optimization.

Background technique

With the development of information science and technology, the critical dimensions of semiconductor integrated circuit (IC) devices are continuously reduced, and the optical proximity effect of lithography imaging systems is becoming more and more significant. The lithography machine is a diffraction-limited optical imaging system. Due to the phased update of its hardware, it faces the challenges of the lithography pattern transfer fidelity and the sharp reduction of the lithography process window caused by the rising IC manufacturing technology node. , various lithography resolution enhancement techniques (RET) based on computational lithography emerged as the times require.

Common photolithography resolution enhancement technologies mainly include optical proximity correction technology (OPC), light source optimization technology (SO), off-axis illumination technology (OAI), sub-resolution auxiliary pattern (SRAF) technology and phase shift mask technology (PSM). wait. Most of the above photolithography resolution enhancement technologies only optimize the light source shape, mask pattern or mask phase to complete the correction of part of the optical proximity effect. In contrast, as a combination of SO and OPC technologies, joint optimization of light source mask (SMO) can simultaneously optimize the illumination source and mask pattern, and has a higher degree of freedom in optimization. One of the most widely used lithographic resolution enhancement techniques

The optimization speed of RET technology is a key factor in determining the lithography manufacturing process and output. Although the SMO technology has a very high degree of freedom in optimization, it has disadvantages such as a huge amount of calculation and low optimization efficiency when facing full-chip optimization.

In order to improve the efficiency of optimization and reduce the difficulty of optimization, it is necessary to use graphic screening technology to screen out representative key graphics. The traditional manual-based screening method is gradually eliminated by the industry due to the high requirements for the operator's technical experience and is not suitable for the optimization of large-scale integrated circuits. The screening method based on graph clustering pre-sets the number of clusters of graph clustering, and selects graphs with specific characteristics as SMO key graphs according to the designed sorting method. Although this type of graph screening method can eliminate a large number of graphs with repeated characteristics, the graph clustering and sorting rule design process is complicated and cumbersome. With the development of signal processing technology, screening methods based on spectrum analysis are gradually emerging. Most of these methods design corresponding coverage rules based on the main frequency information of the graphics, search for representative representative frequencies according to the coverage relationship, and then screen out key graphics with representative representative frequencies. Although the key pattern screening method using spectrum analysis can effectively improve the optimized process window, with the rise of chip process manufacturing nodes, the complexity and density of layout graphics increase sharply, and the spectrum analysis workload for full-chip layout graphics is huge. , can not be applied to engineering software.

Contents of the invention

In view of the defects of the prior art, the purpose of the present invention is to provide a method and device for fast screening of key patterns oriented to full-chip light source mask optimization, aiming to solve the problem that the existing key pattern screening methods face the huge workload of spectrum analysis when facing full-chip layout patterns. question.

In order to achieve the above purpose, in the first aspect, the present invention provides a method for quickly screening key graphics for full-chip light source mask optimization, which is applied to the management nodes of distributed computing clusters, including:

S1. Receive the setting of slice size, slice ratio for graphic screening, number of SMO key graphic screening process levels, slice proportion coefficient under each process level, defect level, and sub-slice proportion coefficient of each defect level; according to the process level , to generate light source patterns of different complexity; load the full-chip mask layout, divide the full-chip mask layout according to the set slice size, and obtain the slice set C _total , randomly select slices with a set ratio from it, and obtain the mask sliceset C _Init ;

S2. Initialization process level i=1;

S3. Distribute the mask slice set C _init , the process level i, the light source graphics S _i corresponding to the process level i, and the defect level division rules to each idle computing node in the distributed computing cluster, so as to carry out the screening and distribution of SMO key graphics under level i formula calculation;

S4. Receive the defect sub-slices of each defect level under the process level i returned by each computing node in the distributed computing cluster, and classify the graphics in the defect sub-slices of the same defect level under the process level i to obtain several key graphic sets G _ij , The mask slice set C _Init is updated as the difference between the current mask slice set C _Init and all key graphics sets G _ij ;

S5. Determine whether the current mask slice is the last mask slice in the distributed computing cluster, if so, go to S6, otherwise, go to S3;

S6. Determine whether the SMO process under all process levels is completed, if not, then update the process level i=i+1, enter S3 with the updated mask slice set C _Init and process level i; if so, then follow the process level The proportion coefficient and the proportion coefficient of each defect level sub-slice are randomly selected from the key figure set G _ij of the corresponding level to form the final key figure set G _final .

Preferably, the generating of light source graphics at each process level is specifically as follows:

(1) Using a circular light source, a ring light source or a C-shaped multi-stage light source, the polarization state of the multi-stage light source is set to no polarization state, and the wavelength is set to any wavelength within the range of deep ultraviolet or extreme ultraviolet;

(2) According to the proportion coefficient of slices under each process level, the light source is sparsely sampled to different degrees by using the inverse interpolation method to obtain an approximate model of the light source;

Among them, S _i is the light source point after sparse sampling at process level i, s _ij is the original light source point, and _ni is the sparse sampling multiple at process level i, which decreases with the increase of the slice ratio coefficient α _i at each process level , namely n _i ∝1/α _i .

Preferably, the defect level is divided according to the type of defect and the size of the EPE, and the higher the defect level or the larger the EPE, the larger the defect proportion coefficient of this level.

In order to achieve the above object, in the second aspect, the present invention provides a method for simulating the internal light intensity distribution of photoresist, the method comprising:

Using the bipolar mask model, the mask slice graph is converted into a binary image, and convolved with a Gaussian convolution kernel to obtain a mask approximation model;

The ideal pupil function is used to construct the pupil, and the threshold NA must not be lower than 0.95 to obtain an approximate model of the pupil;

Combined with the light source pattern, mask approximate model and pupil approximate model, the light intensity distribution inside the photoresist is obtained by using the Abbe imaging formula.

In order to achieve the above purpose, in the third aspect, the present invention provides a method for quickly screening key graphics for full-chip light source mask optimization, which is applied to computing nodes of distributed computing clusters, including:

T1. Receive the assigned mask slice, process level i, light source pattern S _i under process level i, and defect level;

T2. Using the method described in the second aspect, construct the simulated photoresist internal light intensity distribution of the mask slice under the process level i, and substitute the photoresist internal light intensity distribution into the photoresist approximate model, through the set Threshold to extract the photoresist simulation profile of the slice;

T3. Compare the extracted photoresist simulation profile with the actual mask slice pattern, if the convergence condition of the SMO process is not satisfied, enter T4; if the convergence condition of the SMO process is satisfied, proceed to T6;

T4. Judging whether the extracted photoresist simulation profile satisfies the light source optimization convergence condition, if yes, enter T5; if not, perform light source optimization, and return to T2;

T5. Judging whether the extracted photoresist simulation profile satisfies the mask optimization convergence condition, if yes, then enter T6; if not, perform mask pattern optimization, and return to T2;

T6. Judging whether the simulated outline extracted after the SMO process satisfies the defect slice screening condition, if so, enter T7; if not, the current level of SMO process has no defect slices, end this screening, and set it to an idle state;

T7. Confirm the key level of each defect point in the mask slice, set the size according to the sub-slice, surround the defect point, cut out the defect sub-slice containing the key pattern from the mask slice, and transmit the defect sub-slice to the management node.

Preferably, the internal light intensity distribution of the photoresist is substituted into the photoresist approximate model, and the photoresist simulation profile of the slice is extracted through the set threshold, as follows:

Among them, C(x,y) is the profile of the photoresist, J(x,y) is the output pattern intensity distribution of the photoresist approximate model, I(x,y) is the internal light intensity distribution of the photoresist, and sig[] is Sigmoid function, T is the photoresist reaction threshold, and α is the empirical parameter of the photoresist model, which is set according to the actual process conditions.

To achieve the above object, in a fourth aspect, the present invention provides a computer-readable storage medium, the computer-readable storage medium stores a computer program, the computer program includes program instructions, and when the program instructions are executed by a processor When making the processor execute the method as described in the first aspect; or execute the method as described in the second aspect; or execute the method as described in the third aspect.

In order to achieve the above object, in the fifth aspect, the present invention provides a device for fast screening of key graphics, including: a processor and a memory; the memory is used to store computer execution instructions; the processor is used to execute The computer executes instructions, so that the method as described in the first aspect is executed.

In order to achieve the above object, in the sixth aspect, the present invention provides a device for fast screening of key graphics, including: a processor and a memory; the memory is used to store computer-executable instructions; the processor is used to execute The computer executes instructions, so that the method described in the third aspect is executed.

Generally speaking, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects:

(1) The present invention provides a method and device for quickly screening key graphics for full-chip light source mask optimization. The SMO process of complexity and slice defect area classification can realize fast and accurate screening or acquisition of key graphics for full-chip light source mask optimization while avoiding complex screening rule design or huge graphic spectrum analysis.

(2) The present invention proposes a method for simulating the internal light intensity distribution of the photoresist. According to the photolithographic imaging process, each component module is specifically simplified under the premise of ensuring the qualitative description of the characteristics of each module. Using the established high-efficiency approximate lithography imaging model for key pattern screening can not only ensure the accuracy of key pattern extraction in the whole chip based on the simple and fast light source mask optimization process, but also effectively improve the key pattern screening in the whole chip range efficiency.

Description of drawings

FIG. 1 is a flow chart of a method for quickly screening key patterns for full-chip light source mask optimization provided by an embodiment of the present invention.

FIG. 2 is a flow chart of constructing an efficient approximate lithographic imaging model provided by an embodiment of the present invention.

Fig. 3 is a schematic diagram of the classification of key graphics provided by the embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

The present invention provides a method for quickly screening key graphics for full-chip light source mask optimization, which is applied to management nodes of distributed computing clusters, including:

Step S1. Receive the setting of the slice size, the proportion of slices used for graphic screening, the number of SMO key graphic screening process levels, the proportion coefficient of slices under each process level, defect level, and the proportion coefficient of sub-slices of each defect level; according to the process level, generate light source graphics of different complexity; load the full-chip mask layout, and divide the full-chip mask layout according to the set slice size to obtain the slice set C _total , and randomly select slices with a set ratio from it to obtain the mask Membrane slice set C _Init .

Preferably, the generating of light source graphics at each process level is specifically as follows:

(1) Using a circular light source, a ring light source or a C-shaped multi-stage light source, the polarization state of the multi-stage light source is set to no polarization state, and the wavelength is set to any wavelength within the range of deep ultraviolet or extreme ultraviolet;

(2) According to the proportion coefficient of slices under each process level, the light source is sparsely sampled to different degrees by using the inverse interpolation method to obtain an approximate model of the light source;

Among them, S _i is the light source point after sparse sampling at process level i, s _ij is the original light source point, and _ni is the sparse sampling multiple at process level i, which decreases with the increase of the slice ratio coefficient α _i at each process level , namely n _i ∝1/α _i .

Preferably, the defect level is divided according to the type of defect and the size of the EPE, and the higher the defect level or the larger the EPE, the larger the defect proportion coefficient of this level. For example, the EPE ranges from 0 to inf. According to the size of EPE, it is: EPE is between 0 and 5, assigned defect level 1, proportional coefficient β ₁ ; EPE is between 5 and 15, assigned defect level 2, proportional coefficient β ₂ ; and so on.

Step S2. Initialize process level i=1.

Step S3. Distribute the mask slice set C _Init , the process level i, the light source graphics S _i corresponding to the process level i, and the defect level classification rules to each idle computing node in the distributed computing cluster, so as to screen the SMO key graphics under level i Distributed Computing.

Step S4. Receive the defect sub-slices of each defect level under the process level i returned by each computing node in the distributed computing cluster, classify the graphics in the defect sub-slices of the same defect level under the process level i, and obtain several key graphic sets G _ij , the mask slice set C _Init is updated as the difference set of the current mask slice set C _Init and all key graphic sets G _ij .

Step S5. Determine whether the current mask slice is the last mask slice in the distributed computing cluster, if yes, go to S6, otherwise, go to S3.

Step S6. Determine whether the SMO process under all process levels is completed, if not, update the process level i=i+1, enter S3 with the updated mask slice set C _Init and process level i; if so, follow the process The level proportion coefficient and the proportion coefficient of each defect level sub-slice are randomly selected from the key figure set G _ij of the corresponding level to form the final key figure set G _final .

The present invention provides a method for quickly screening key graphics for full-chip light source mask optimization, which is applied to computing nodes of distributed computing clusters, including:

Step T1. Receive the allocated mask slice, process level i, light source pattern S _i under process level i, and defect level.

Step T2. Construct the simulated photoresist internal light intensity distribution of the mask slice under process level i, substitute the photoresist internal light intensity distribution into the photoresist approximate model, and extract the sliced photoresist through the set threshold simulated contours.

The invention provides a method for simulating the internal light intensity distribution of a photoresist, the method comprising: using a bipolar mask model, converting a mask slice pattern into a binary image, and performing convolution with a Gaussian convolution kernel to obtain a mask Film approximation model; using the ideal pupil function to construct the pupil, the threshold NA must not be less than 0.95 to obtain the pupil approximation model; combined with the light source pattern, mask approximation model and pupil approximation model, using the Abbe imaging formula to obtain the inside of the photoresist light intensity distribution.

Preferably, the internal light intensity distribution of the photoresist is substituted into the photoresist approximate model, and the photoresist simulation profile of the slice is extracted through the set threshold, as follows:

Among them, C(x,y) is the profile of the photoresist, J(x,y) is the output pattern intensity distribution of the photoresist approximate model, I(x,y) is the internal light intensity distribution of the photoresist, and sig[] is Sigmoid function, T is the photoresist reaction threshold, and α is the empirical parameter of the photoresist model, which is set according to the actual process conditions.

Step T3. Compare the extracted photoresist simulation profile with the actual mask slice pattern, and if the convergence condition of the SMO process is not satisfied, proceed to T4; if the convergence condition of the SMO process is satisfied, proceed to T6.

Step T4. Judging whether the simulated profile of the extracted photoresist satisfies the light source optimization convergence condition, if so, proceed to T5; if not, perform light source optimization, and return to T2.

Step T5. Judging whether the extracted photoresist simulation profile satisfies the mask optimization convergence condition, if so, proceed to T6; if not, perform mask pattern optimization, and return to T2.

Step T6. Judging whether the simulated outline extracted after the SMO process satisfies the defect slice screening conditions, if so, enter T7; if not, the current level of SMO process has no defect slices, end this screening, and set it to an idle state.

Step T7. Confirm the key level of each defect point in the mask slice, set the size according to the sub-slice, surround the defect point, cut out the defect sub-slice containing the key pattern from the mask slice, and divide the defect sub-slice sent to the management node.

The present invention provides a computer-readable storage medium, the computer-readable storage medium stores a computer program, the computer program includes program instructions, and when executed by a processor, the program instructions cause the processor to perform the above method .

The present invention provides a device for fast screening of key graphics, including: a processor and a memory; the memory is used to store computer-executable instructions; the processor is used to execute the computer-executable instructions, so that as described above method is executed.

FIG. 1 is a flow chart of a method for quickly screening key patterns for full-chip light source mask optimization provided by an embodiment of the present invention. As shown in Figure 1, the working process of the entire distributed computing cluster is as follows:

Step 1. Load the full-chip mask layout on the management node of the distributed computing cluster. According to the set slice size (set by the user according to the graphic complexity and density of the mask layout), the size of the full-chip mask layout is divided into several slices, and all slice sets are recorded as C _Total ; from C _total randomly selects the slice set C _Init corresponding to the ratio c (set by the user) for SMO key graphic screening.

|C _Init |＝c|C _Total |

Use a circular light source, ring light source or C-shaped multi-stage light source to reduce the difficulty of light source realization; the polarization state is set to no polarization state, and the wavelength is set to any wavelength in the deep ultraviolet or extreme ultraviolet range (such as 193nm), according to The lithography complexity classification strategy adopts the inverse interpolation method to sparsely sample the light sources to different degrees, reducing the number of light source points and improving the key graphic screening efficiency. Under the SMO key graphics screening process level i, the light source sparse sampling method is as follows:

Among them, S _i is the light source point after sparse sampling at process level i, s _ij is the original light source point, and _ni is the sparse sampling multiple at process level i, which decreases with the increase of the slice ratio coefficient at each process level, namely n _i ∝1/α _i .

其中，m为缺陷等级总数。The key level j of the graph can be divided according to the type of defect and the size of EPE. The higher the defect level or the greater the EPE, the larger the defect proportion coefficient β _j of this level, and

Among them, m is the total number of defect levels.

Step 2. On the management node of the distributed computing cluster, filter the number of process levels k (set by the user) according to the SMO key graph, and generate light source graphs S _i (i=1,...,k) with different degrees of complexity; in the SMO In the key graphic screening process, assign the corresponding process level i according to the complexity of the light source, and set the corresponding slice proportion coefficient α _i (i=1,...,k; 0≤α _i ≤1) under this process level, and

Step 3. On the management node of the distributed computing cluster, distribute the slice set C _Init used for SMO key graph screening to each idle computing node in the distributed computing cluster, and perform distributed computing of SMO key graph screening under level i.

Step 4. In a computing node of the distributed computing cluster, use the constructed high-efficiency approximate photolithographic imaging model of process level i to simulate the internal light intensity distribution of the photoresist, and extract the simulated profile of the photoresist slice. FIG. 2 is a flow chart of constructing an efficient approximate lithographic imaging model provided by an embodiment of the present invention. As shown in Figure 2, the construction process is as follows:

Step 4.1. According to the lithography imaging process, the high-efficiency approximate lithography imaging model is divided into a light source approximation module, a mask approximation module, a pupil approximation module, and a photoresist approximation module.

Step 4.2, the light source approximation module is the light source constructed and sent by the management node.

Step 4.3, the construction process of the mask approximation module is based on the bipolar mask model, and the near field of the mask is obtained by convolution with the Gaussian convolution kernel:

Among them, M _NF (x, y) is the approximate mask model output mask near field; M _2v (x, y) is the binary image converted from the mask pattern by using the bipolar mask model; k _Gauss (x, y) is a Gaussian convolution kernel.

Step 4.4, the pupil approximation module adopts the ideal pupil function, and NA can be selected as a larger value, such as NA=0.95:

Among them, P(f _x ,f _y ) is the ideal pupil function.

Step 4.5 Combine the light source approximate model, the mask approximate model, and the pupil approximate model, and use the Abbe imaging formula to obtain the internal light intensity distribution I(x,y) of the photoresist:

Step 4.6, the photoresist approximate model is a hard threshold model based on the Sigmoid function, and the internal light intensity distribution of the photoresist is brought into the photoresist approximate model, and the photoresist profile can be completed by setting the threshold extract. The photoresist approximate model output pattern intensity distribution J(x,y) is:

Among them, sig[] is the Sigmoid function, T is the photoresist reaction threshold, and α is the empirical parameter of the photoresist model, which is set according to the actual process conditions.

The photoresist profile obtained by C(x,y) can be extracted through the following process:

Step 5. In a computing node of the distributed computing cluster, compare the extracted photoresist simulation profile with the input mask slice pattern, and if the convergence condition of the simple and fast SMO process is not met, proceed to the next step; If the simple and fast SMO process is satisfied, go to step 8.

The convergence condition of the SMO process is to meet any of the following conditions: 1) The total number of SMO optimization iterations reaches the threshold value Iter _SMO set by the user; 2) The edge placement error EPE (Edge PlacementError) between the simulation extracted contour and the design mask figure is less than the user Set the SMO process error threshold EPE _SMO .

Step 6. In a computing node of the distributed computing cluster, judge whether the extracted photoresist simulation profile meets the light source optimization convergence condition, and if so, proceed to the next step; if not, perform the corresponding light source optimization and return to the step 4.

Light source optimization methods include, but are not limited to: light source optimization based on covariance matrix adaptive evolution, and light source optimization based on partial sampling of light sources.

The light source optimization convergence condition is to meet any of the following conditions: 1) The number of light source optimization iterations reaches the SMO process optimization iteration number threshold Iter _SMO ; 2) The EPE between the simulation extracted contour and the design mask figure is less than the user-set light source optimization error Threshold EPE _Source ; 3) EPE change before and after light source optimization is less than user-set light source optimization error change threshold ΔEPE _Source .

Step 7. In a computing node of the distributed computing cluster, judge whether the extracted photoresist simulation profile meets the mask optimization convergence condition, and if so, proceed to the next step; if not, perform corresponding mask pattern optimization , return to step 4.

Mask optimization methods include, but are not limited to: mask optimization based on bilateral evolution of mask graphics, and mask optimization based on discrete cosine transform.

The mask optimization convergence condition is to satisfy any of the following conditions: 1) the number of mask optimization iterations reaches the SMO process optimization iteration number threshold Iter _SMO ; 2) the EPE between the simulation extracted contour and the design mask figure is less than the user-set 3) EPE error change before and after mask optimization is less than user-set mask optimization error change threshold _{ΔEPE Mask .}

Step 8. In a computing node of the distributed computing cluster, judge whether the simulation contour extracted after the simple and fast SMO process satisfies the defect slice screening condition, and if so, proceed to the next step; if not, proceed to step 11 .

Defective slice screening conditions can meet any of the following conditions: 1) The EPE between the simulated extracted contour and the design mask pattern is less than the user-set key pattern error threshold EPE _CP ; 2) The simulated extracted contour has defects, such as Hard-bridge , Pinch, etc.

Step 9. In a computing node of the distributed computing cluster, according to the size of the sub-slice set by the user, the corresponding graph is segmented from the current slice around the defect point.

Step 10: On the management node of the distributed computing cluster, the process level i and the key level j of the figure are screened according to the SMO key figure corresponding to the sub-slice, and the key figures in the defect sub-slices of the same level are classified into G _ij .

Fig. 3 is a schematic diagram of the classification of key graphics provided by the embodiment of the present invention. As shown in FIG. 3 , the entire full-chip mask layout is divided into four slices according to the proportions α ₁ to α ₄ , and the slice in the upper left corner is taken as an example for illustration. There are two kinds of defects in this slice, corresponding to key levels 1 and 3 respectively, and the key graphic classifications G ₁₁ and G ₁₃ are obtained under process level i.

After completing the graphic classification of defective sub-slices, remove the current slice from the initial slice set C _Init , complete the update of the slice set C _Init , and enter the next step.

Step 11. On the management node of the distributed computing cluster, judge whether the current slice is the last mask slice in the distributed computing cluster, if not, go back to step 3; if yes, go to the next step.

Step 12. On the management node of the distributed computing cluster, judge whether all the SMO processes under the lithography complexity classification are completed, if not, input the updated slice set C _Init into the distributed computing cluster, and return to Step 3: Carry out the SMO process of the next lithography complexity level; if so, select the corresponding number from the key figure set G _ij of the corresponding level at random according to the proportion of the corresponding figure w _ij in the key figure screening process level of different slices SMO The graphics are combined into the final key graphics set G _final :

w _ij =α _i β _j

Among them, k is the grading number of lithography complexity SMO process, m is the number of sub-slice defect level grading, |G _ij | and |G _final | represent the number of elements contained in the sets G _ij and G _final respectively.

It is easy for those skilled in the art to understand that the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention, All should be included within the protection scope of the present invention.

Claims (8)

1. A key graph rapid screening method oriented to full-chip light source mask optimization is characterized by being applied to management nodes of a distributed computing cluster and comprising the following steps:

s1, setting the size of a slice, the proportion of the slices used for graphic screening, the number of SMO key graphic screening process levels, the slice duty ratio coefficient under each process level, the defect level and the sub-slice duty ratio coefficient of each defect level; generating light source patterns with different complexity degrees according to the flow level; loading a full-chip mask layout, and slicing the full-chip mask layout according to the set slice size to obtain a slice set C _total Randomly selecting slices with set proportion from the above to obtain a mask slice set C _Init ；

S2, initializing a flow grade i=1;

s3, slicing the mask into a set C _Init The flow level i and the light source graph S corresponding to the flow level i _i Distributing the defect grade division rule to each idle computing node in the distributed computing cluster to carry out SMO key graph screening distributed computing under grade i;

s4, receiving defect sub-slices of all defect levels under the process level i returned by all computing nodes in the distributed computing cluster, classifying the patterns in the defect sub-slices of the same defect level under the process level i, and obtaining a plurality of key pattern sets C _ij Mask slice set C _Init Updated to the current mask slice set C _Init And all key graphics set G _ij Is the difference set of (2);

s5, judging whether the current mask slice is the last mask slice in the distributed computing cluster, if so, entering S6, otherwise, entering S3;

s6, judging whether SMO flows under all flow levels are completed, if not, updating the flow level i=i+1 to update the mask slice set C _Init And a flow class i, entering S3; if yes, according to the flow level duty ratio coefficient and the sub-slice duty ratio coefficient of each defect level, randomly selecting a key graph set G of the corresponding level _ij Selecting corresponding number of graphics to be combined into a final key graphics set G _final 。

2. The method of claim 1, wherein the generating the light source patterns with different complexity levels according to the flow level comprises:

(1) A circular light source, an annular light source or a C-shaped multi-stage light source is adopted, the polarization state of the light source is set to be a non-polarization state, and the wavelength is set to be any wavelength in the deep ultraviolet or extreme ultraviolet band range;

(2) According to the slice duty ratio coefficient of each flow level, performing sparse sampling on the light source in different degrees by adopting an inverse interpolation method to obtain a light source approximation model;

wherein S is _i The light source points s after sparse sampling under the process level i _ij N is the original light source point _i For the sparse sampling multiple under the process level i, the slice duty ratio coefficient alpha under each process level _i Rise and fall, i.e. n _i ∝1/α _i 。

3. The method of claim 1, wherein the defect levels are classified according to defect type and EPE size, and the higher the defect level or the larger the EPE, the larger the level defect duty factor.

4. A key graph rapid screening method oriented to full-chip light source mask optimization is characterized by being applied to computing nodes of a distributed computing cluster, and comprising the following steps:

t1 receiving the assigned mask slice, flow level i, and light source pattern S under flow level i _i Defect grade;

t2, constructing the simulated photoresist internal light intensity distribution of the mask slice under the process level i by using a photoresist internal light intensity distribution simulation method, substituting the photoresist internal light intensity distribution into a photoresist approximate model, and extracting the photoresist simulation contour of the slice through a set threshold value;

and T3, comparing the extracted photoresist simulation contour with an actual mask slice graph, and if the SMO flow convergence condition is not met, entering into T4; if the SMO flow convergence condition is met, entering T6;

t4, judging whether the extracted photoresist simulation contour meets the light source optimization convergence condition, and if so, entering into T5; if not, returning to T2 after light source optimization is carried out;

t5, judging whether the extracted photoresist simulation contour meets the mask optimization convergence condition, if so, entering into T6; if not, mask pattern optimization is carried out, and T2 is returned;

t6, judging whether the simulation contour extracted after the SMO process meets the defect slice screening condition, if so, entering into T7; if not, the current grade SMO flow is free of defect slices, the screening is finished, and the current grade SMO flow is set to be in an idle state;

t7, confirming the key grade of each defect point in the mask slice, cutting out a defect sub-slice containing a key pattern from the mask slice according to the set size of the sub-slice and surrounding the defect point, and transmitting the defect sub-slice to a management node;

the method for simulating the light intensity distribution in the photoresist comprises the following steps:

converting the mask slice graph into a binary graph by using a bipolar mask model, and convolving the binary graph with a Gaussian convolution kernel to obtain a mask approximation model;

constructing a pupil by adopting an ideal pupil function, wherein the threshold NA is not lower than 0.95, and obtaining a pupil approximation model;

and combining the light source pattern, the mask approximation model and the pupil approximation model, and obtaining the light intensity distribution inside the photoresist by using an Abbe imaging formula.

5. The method for rapid screening of critical patterns according to claim 4, wherein the substituting the light intensity distribution inside the photoresist into the photoresist approximation model extracts the photoresist simulation profile of the slice through a set threshold, specifically as follows:

wherein C (x, y) is the photoresist profile, J (x, y) is the photoresist approximate model output pattern intensity distribution, I (x, y) is the photoresist internal light intensity distribution, sig [ ] is a Sigmoid function, T is the photoresist reaction threshold, and alpha is the photoresist model experience parameter, and is set according to the actual process conditions.

6. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program comprising program instructions which, when executed by a processor, cause the processor to perform the method of any of claims 1-3; alternatively, the method of claim 4 or 5 is performed.

7. An apparatus for rapid screening of key graphics, comprising: a processor and a memory; the memory is used for storing computer execution instructions; the processor configured to execute the computer-executable instructions such that the method of any of claims 1-3 is performed.

8. An apparatus for rapid screening of key graphics, comprising: a processor and a memory; the memory is used for storing computer execution instructions; the processor configured to execute the computer-executable instructions such that the method of claim 4 or 5 is performed.

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