CN115756296A - Buffer management method and device, control program and controller - Google Patents

Abstract

The embodiment of the application provides a cache management method and device, a control program and a controller; the method comprises the following steps: the cache management unit MMU identifies the type of an externally connected cache controller based on the CPU configuration information; confirming an offset address in a table look-up mode based on an address management submodule and an address area corresponding to the type of the cache controller; calculating a logical address of the type of the cache controller based on the offset address; wherein, the number of the external connection channels gated by different cache controller types is different. Through the application, the problem that different controllers are compatible under the same frame is solved, and then multiple controllers can be compatible under the same frame, and the effect of improving the storage efficiency is achieved.

Description

Buffer management method and device, control program and controller

technical field

The present application relates to the technical field of communications, and in particular, to a cache management method and device, a control program, and a controller.

Background technique

In the application of Ethernet switching chips, it is often necessary to select different types of off-chip cache units, that is, cache controllers, according to application scenarios and costs. Therefore, the memory management unit (MMU) of the chip must not only meet Basic functional requirements, and must have good compatibility and portability, so that in different application scenarios, different cache controllers can be connected according to factors such as storage size, speed, power consumption, and cost, without the need for multiple development, thereby saving manpower and cost.

As the frequency and bandwidth of processors and storage controllers continue to increase, their respective performances are also improving, but the cache access efficiency often becomes the bottleneck of system performance, and the cache access efficiency is related to the implementation of the MMU. In the Ethernet switch chip, the main function of the MMU is to be responsible for the data of the packet (packet, PK), the write request of the packet descriptor (packet descriptor, PD), and the distribution of the written data, and to release them in order according to the write request; The data is read back in order according to the read request. During this process, technologies such as off-chip address management, physical address mapping, and packetization are used to maximize the use of cache bandwidth to improve the efficiency of the memory controller. The current mainstream cache controllers include DDR3/DDR4/DDR5 (Double Data Rate, DDR double rate), HBM (High Bandwidth Memory) (high bandwidth memory), etc. How to be compatible with different controllers under the same framework and ensure their Storage efficiency is the main issue to be solved.

For the above-mentioned problem of how to be compatible with different controllers under the same framework, no effective solution has been proposed so far.

Contents of the invention

Embodiments of the present application provide a cache management method and device, a control program, and a controller, so as to at least solve the problem of how to be compatible with different controllers under the same framework in the related art.

According to an embodiment of the present application, a cache management method is provided, including: the cache management unit MMU identifies the external cache controller type based on the CPU configuration information; based on the address management submodule and the address area corresponding to the above cache controller type , confirming the offset address by means of table lookup; calculating the logical address of the above-mentioned cache controller type based on the above-mentioned offset address; wherein, the number of external connection channels selected by different cache controller types is different.

According to another embodiment of the present application, a cache management device is provided, including: an identification unit for enabling the cache management unit MMU to identify the type of an external cache controller based on CPU configuration information; a confirmation unit for address-based management The address area corresponding to the submodule and the above-mentioned cache controller type confirms the offset address by means of a look-up table; the calculation unit is used to calculate the logical address of the above-mentioned cache controller type based on the above-mentioned offset address; wherein, the different above-mentioned cache The number of external connection channels gated by the controller type is different.

According to yet another embodiment of the present application, a computer-readable storage control program is also provided, wherein a computer program is stored in the above-mentioned computer-readable storage control program, wherein the above-mentioned computer program is configured to perform any one of the above-mentioned methods when running Steps in the examples.

According to another embodiment of the present application, there is also provided a controller, including a buffer and a processor, the above-mentioned controller stores a computer program, and the above-mentioned processor is configured to run the above-mentioned computer program to perform any one of the above-mentioned methods Steps in the examples.

Through this application, because the cache management unit MMU is used to identify the type of external cache controller based on the CPU configuration information; based on the address management submodule and the address area corresponding to the above cache controller type, the offset address is confirmed in a table lookup manner; The logical address of the above-mentioned cache controller type is calculated based on the above-mentioned offset address; wherein, the number of external connection channels selected by different above-mentioned cache controller types is different; therefore, the switching of different controllers under the same framework is realized, which can Solve the problem of being compatible with different controllers under the same framework, and then be compatible with multiple controllers under the same framework, and improve the effect of storage efficiency.

Description of drawings

FIG. 1 is a block diagram of a hardware structure of a mobile terminal according to a cache management method according to an embodiment of the present application;

FIG. 2 is a flowchart of a cache management method according to an embodiment of the present application;

FIG. 3 is a schematic diagram of the architecture of a cache management system according to an embodiment of the present application;

FIG. 4 is a schematic diagram of an optionE mode of HBM in a cache management method according to an embodiment of the present application;

FIG. 5 is a first schematic diagram of address correspondence in a cache management method according to an embodiment of the present application;

FIG. 6 is a second schematic diagram of address correspondence in a cache management method according to an embodiment of the present application;

FIG. 7 is a schematic diagram 3 of address correspondence in the cache management method according to an embodiment of the present application;

FIG. 8 is a schematic diagram 4 of address correspondence in the cache management method according to an embodiment of the present application;

FIG. 9 is a first schematic diagram of address mapping in a cache management method according to an embodiment of the present application;

FIG. 10 is a second schematic diagram of address mapping in a cache management method according to an embodiment of the present application;

FIG. 11 is a third schematic diagram of address mapping in a cache management method according to an embodiment of the present application;

FIG. 12 is a schematic diagram of off-chip address management according to a cache management method according to an embodiment of the present application;

FIG. 13 is a schematic structural diagram of a cache management device according to an embodiment of the present application.

Detailed ways

Embodiments of the present application will be described in detail below with reference to the drawings and in combination with the embodiments.

It should be noted that the terms "first" and "second" in the description and claims of the present application and the above drawings are used to distinguish similar objects, but not necessarily used to describe a specific sequence or sequence.

The method embodiments provided in the embodiments of the present application may be executed in mobile terminals, computer terminals or similar computing devices. Taking running on a mobile terminal as an example, FIG. 1 is a block diagram of a hardware structure of a mobile terminal according to a cache management method according to an embodiment of the present application. As shown in Figure 1, the mobile terminal may include one or more (only one is shown in Figure 1) processors 102 (processors 102 may include but not limited to processing devices such as microprocessor MCU or programmable logic device FPGA, etc.) and a memory 104 for storing data, wherein the above-mentioned mobile terminal may also include a transmission device 106 and an input and output device 108 for communication functions. Those skilled in the art can understand that the structure shown in FIG. 1 is only for illustration, and it does not limit the structure of the above mobile terminal. For example, the mobile terminal may also include more or fewer components than those shown in FIG. 1 , or have a different configuration from that shown in FIG. 1 .

The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as computer programs corresponding to the cache management method in the embodiment of the present application, and the processor 102 executes various functions by running the computer programs stored in the memory 104 A functional application and data processing, that is, to realize the above-mentioned method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory that is remotely located relative to the processor 102, and these remote memories may be connected to the mobile terminal through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 106 is used to receive or transmit data via a network. The specific example of the above network may include a wireless network provided by the communication provider of the mobile terminal. In one example, the transmission device 106 includes a network interface controller (NIC for short), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 may be a radio frequency (Radio Frequency, RF for short) module, which is used to communicate with the Internet in a wireless manner.

Fig. 2 is a flowchart of a cache management method according to an embodiment of the present application. As shown in Fig. 2, the process includes the following steps:

Step S202, the cache management unit MMU identifies the type of the external cache controller based on the CPU configuration information of the central processing unit;

Step S204, based on the address management submodule and the address area corresponding to the above cache controller type, confirm the offset address by means of table lookup;

Step S206, calculating the logical address of the above-mentioned cache controller type based on the above-mentioned offset address; wherein, the number of external connection channels selected by different cache controller types is different.

Through the embodiment of this application, since the cache management unit MMU is used to identify the type of the external cache controller based on the CPU configuration information; based on the address management submodule and the address area corresponding to the above cache controller type, the offset is confirmed in the form of a table lookup Address; the logical address of the above-mentioned cache controller type is calculated based on the above-mentioned offset address; wherein, the number of external connection channels selected by different above-mentioned cache controller types is different; therefore, the switching of different controllers under the same framework is realized , can solve the problem of being compatible with different controllers under the same framework, and then can be compatible with multiple controllers under the same framework, and can improve storage efficiency.

In one or more embodiments, the above cache management method further includes: the address mapping submodule of the above MMU reads the preset address mapping relationship; the above address mapping relationship is to convert the on-chip logical address into a value acceptable to the cache chip physical address.

In one or more embodiments, the above-mentioned cache management method further includes: the above-mentioned method also includes: the address mapping submodule of the above-mentioned MMU reads a preset address mapping relationship; the above-mentioned address mapping relationship is to convert the on-chip logical address into The physical address accepted by the cache chip; according to different application scenarios, reconfigure through the CPU to obtain the address mapping relationship corresponding to the above application scenarios after reconfiguration.

In one or more embodiments, the above-mentioned cache management method further includes: according to the requirements of the off-chip cache and the structural attributes of the cache controller, segmenting the data packet sent by the CPU to the above-mentioned MMU according to the block unit block, wherein the segmentation The divided data packet corresponds to the block address, and one data packet corresponds to multiple block addresses. The address management intervals are different when the types of the above cache controllers are different.

In one or more embodiments, the buffer management method further includes: the MMU receives off-chip data sent by the packet buffer management unit PMU, wherein the off-chip data includes a packet descriptor PD and a packet PK; extracting The data information of the above-mentioned PD; the above-mentioned data information is bundled to obtain the bundled data, and the first data in the above-mentioned PK is deleted; here, the first data may include invalid data in the bundled data.

Shifting and splicing is performed on the above grouped data to extract second data; here, the second data may include valid data in the grouped data. The data information of the above-mentioned PD in the above-mentioned grouped data and the extracted second data are grouped again to obtain the target grouped data. The above-mentioned target grouping data is sent to the off-chip cache for storage.

In one or more embodiments, the above cache management method further includes: when the data bit length of the above PD plus the extracted data bit length of the second data is less than or equal to the bus bit width, simultaneously output the above PD and the above second data;

When the data bit length of the PD plus the extracted data bit length of the second data is greater than the bus bit width, split the PD and the second data into first split data and second split data;

outputting the aforementioned PD and the aforementioned first split data;

performing a zero-padding operation on the above-mentioned second split data to obtain zero-padding processing data with a data bit length equal to the above-mentioned bus bit width, and outputting the above-mentioned zero-padding processing data.

In one or more embodiments, the above cache management method further includes: a message cache management unit PMU sends a write message;

The above-mentioned PMU stores the above-mentioned write message, and sends a write release command to the traffic buffer management unit TMMU; the above-mentioned TMMU sends a message descriptor to the queue management unit QMU;

The above-mentioned QMU issues a write command through the above-mentioned TMMU, and transparently transmits it to the above-mentioned MMU, and the above-mentioned QMU sends a write release signal to the above-mentioned TMMU after storing the above-mentioned write command;

The command queue issues a read message command, reads the read message data and returns the above read message data to the above PMU;

The above-mentioned TMMU issues a read command and reads the packet descriptor data.

Based on the above embodiments, in an application embodiment, in the cache management device provided by the present application, the MMU is located between the off-chip memory controller and the on-chip control module. FIG. 3 is a schematic diagram of the architecture of the cache management system according to the embodiment of the present application. , as shown in Figure 3, the MMU is located in the PMU (Packet Memory Unit) message storage unit, TMMU (TM Memory Management Unit memory management unit), CMD_FIFO (Command FIFO, command first-in-first-out queue) and HBM (high Bandwidth Memory, high bandwidth memory)/DDR, the buffer management method of the embodiment of the present application can mainly realize the following functions:

1) Responsible for the distribution of multi-queue message PK, message descriptor PD write request and write data, and the storage of write release;

2) Responsible for the distribution of multi-queue PK and PD read requests, and the storage of read data;

3) Support mode switching of multiple types of cache controllers;

4) The mapping from logical address to off-chip physical address can be reconfigured.

The above-mentioned PMU stores the above-mentioned write message, and sends a write release command to the traffic buffer management unit TMMU; the above-mentioned TMMU sends a message descriptor to the queue management unit QMU; the above-mentioned QMU sends a write command through the above-mentioned TMMU, and transparently transmits it to the above-mentioned MMU, After the above-mentioned QMU finishes storing the above-mentioned write command, it sends a write release signal to the above-mentioned TMMU;

The command queue issues a read message command, reads the read message data, and returns the read message data to the PMU; the above TMMU issues a read command, and reads the message descriptor data. In the whole framework, in order to solve the compatibility and improve the off-chip access bandwidth and efficiency, the main technologies used include address management, PC balance, off-chip address mapping and packetization technology. Compatibility runs through the entire cache management process, so as to take into account all Supports controller functionality and performance.

In an application embodiment, the above cache management method includes:

The first step is multi-controller switching. Through CPU configuration, the cache management module identifies the type of external cache controller, and the address management submodule confirms the offset address by looking up the table according to the address area corresponding to the controller type, thereby calculating the logical address of this type of controller; configuration Different types of cache controllers have different numbers of external connection channels to be selected. According to the requirements of the off-chip cache, this application designs off-chip cache interfaces of 16 Channels, and each Channel fully supports the five channels of write address, write data, write response, read address and read data of the AXI4 bus. In the MMU, there are HBM and DDR modes, and the mode switching is configurable. The default is HBM of 16Channel. Through CPU configuration, it can be switched to DDR mode. Users can choose to connect to different types such as DDR4 or DDR5 according to their own needs. As long as the capacity of the connection is not less than the data capacity corresponding to the maximum number of nodes managed by the address, the connected HBM/DDR Space can be used effectively;

Due to the support of different types of cache controllers, the transfer rate of each type of controller is not necessarily synchronized with the system clock of the MMU. In order to adapt to different controllers and ensure the line-speed transmission of data, some cache areas on the chip are divided. In the form of asynchronous (first-in-first-out queue) FIFO, the data is cached first, and at the same time, through the pre-reading function of the self-developed logic, the data and commands are pre-read out and enter the Ready waiting state. When the effective cache controller arrives, through the handshake mechanism The data is sent out in the same cycle, which can ensure the maximum utilization of the bandwidth of the off-chip controller and reliably process the data stream across clocks.

The second step is to configure address mapping. The address mapping sub-module reads the address mapping relationship preset by the system according to the configuration type, and the address mapping relationship can be reconfigured through the CPU according to the application scenario to adjust the best mapping method;

Since the logical address cannot be directly indexed to the address pin of the HBM/DDR, after processing by the MMU, the logical address is converted into an address that can be accepted by the cache chip, which is called a physical address. Because of the multi-level structure of caching HBM/DDR, the way of address mapping has a lot to do with the off-chip read and write bandwidth, storage rate and efficiency.

The address mapping of this application is to divide each physical channel (data bus bit width 128bit) into two virtual channels (Pseudo Channel, pseudo channel, referred to as PC, data bus bit width 64bit), and the two virtual channels share a set of addresses and control bus.

Fig. 4 is a schematic diagram of the optionE mode of HBM in the buffer management method according to the embodiment of the present application. In the optionE mode of HBM, as shown in Fig. 4, each virtual channel corresponds to a controller, and the controller operates at half the cache frequency . The virtual channel (PS) represented by Psgnt is an internal arbitration signal of the controller, and the controller determines the value of Psgnt according to the physical interface of PS. When processing logic, you only need to treat the 8 controllers of an HBMstack as 16 controllers, and one control corresponds to one physical PS.

SID is the unique address of data 8Hi, which can be regarded as a bank (storage body) address. The number of banks of 8Hi is twice that of 4Hi, which are 32 banks and 16 banks respectively. Banks with 4 consecutive IDs belong to a bank set bank_group. 8Hi and 4Hi are 8 banks and 4 banks respectively.

laddr[N:0] is an 8Byte address (a control bus has a bit width of 128 bits, which is divided into two PSs, and the bit width of each PS is 64 bits). Since the prefetch times of the HBM controller is 4, 256 bits are stored at a time. It will occupy 4 addresses, so the actual logic of laddr[1:0] will not assign an address, and the actual default is 0, and the controller does not use it.

The address sent by the MMU is the 384B address (the actual address is sent by an integer power of 2), the address of the AXI is 1 byte, and each address of the particle corresponding to the PS channel stores 128bit data, so the correspondence between the four addresses is as follows:

FIG. 5 is a schematic diagram of address correspondence in the cache management method according to an embodiment of the present application. When using Samsung HBM2 4Hi4G, the storage space of each PS is 4GB/16=2Gb, and the correspondence is as shown in FIG. 5, {A [31:A28],A[4:0]} is filled with 0:

Fig. 6 is a schematic diagram 2 of the address correspondence in the cache management method according to the embodiment of the present application. When using Samsung HBM2 8Hi8G, the storage space of each PS is 8GB/16=4Gb, and the correspondence is as shown in Fig. 6, {A [31:A29],A[4:0]} is filled with 0:

FIG. 7 is a schematic diagram of address correspondence in the cache management method according to an embodiment of the present application. Three, when using Samsung HBM2E 4Hi8G, the storage space of each PS is 8GB/16=4Gb, and the corresponding relationship is shown in FIG. 7, {A [31:A29],A[4:0]} is filled with 0:

FIG. 8 is a schematic diagram 4 of the address correspondence in the cache management method according to the embodiment of the present application. When using Samsung HBM2E 8Hi16G, the storage space of each PS is 8GB/16=4Gb, and the corresponding relationship is shown in FIG. 8, {A [31:A30],A[4:0]} is filled with 0:

Figure 9 is a schematic diagram of address mapping in the cache management method according to the embodiment of the present application. To fully utilize the bandwidth of HBM, it is necessary to use 16 PS in a balanced manner. The mapping relationship between physical addresses and physical addresses is shown in Figure 9.

FIG. 10 is a schematic diagram of address mapping in the buffer management method according to the embodiment of the present application. When DDR5 is plugged in, DDR5 connected to 3 channels can be configured, and the mapping relationship between its logical address and physical address is shown in FIG. 10 .

FIG. 11 is a schematic diagram of address mapping in the buffer management method according to the embodiment of the present application. Third, when DDR4 is plugged in, DDR5 connected to 3 channels can be configured, and the mapping relationship between its logical address and physical address is shown in FIG. 11 .

The third step is off-chip address management. According to the requirements of the off-chip cache and the structural characteristics of the cache controller, the off-chip cache address is managed in units of blocks (configurable fixed-size data units), which are called virtual addresses (also called logical addresses). A data packet sent by the device to the MMU needs to be segmented according to the block so as to correspond to the block address. After such processing, a data packet may correspond to multiple block data, that is, multiple block addresses need to be generated. Depending on the type of off-chip cache controller, the range of address management is different.

Fig. 12 is a schematic diagram of off-chip address management according to the cache management method of the embodiment of the present application. As shown in Fig. 12, the Trunk (trunk port) address is 128K, and T[16:13] is 16 large linked list IDs, and T[ 12:10] is the sub-list ID under each large linked list, T[9:0] is the linked list number in each sub-linked list, B[3:0] is the number of blks under each trunk, C[2:0 ] is the number of slices under each blk (data + 1 represents the number of slices). Linked list ID application adopts RR (Round-Robin (polling)) scheduling. When a stream comes in, RR application will first select the large linked list, then RR will select a sub-linked list in the large linked list, and then apply for a linked list from the sub-linked list. The same flow will first exhaust the blk in a turnk, and different flows will re-apply for the trunk. Address management {T[9:0], B[3:0], T[12:10], T[16:13]} can be used as a counter, and the address changes continuously. When plugging in HBM, T[16:13] correspond to 16 channels one by one; when plugging in DDR, correspondingly select 3 channels, use T[14:13] as channel_ID, that is, select 0(4, 8, 12), 1 (5, 9, 13), 2 (6, 10, 14) channels, 3, 7, 11, 15 channels can be configured not to use. Since the granularity of the lower two bits of T[16:13] is smaller, it changes faster, and the cache access efficiency after address mapping will be better. According to the set bit width, the MMU can manage 2(4+3+10+4)=2M nodes, and can manage a total of 2Mx3k (blk size can be configured, take 3k as an example)=48G data.

In order to ensure the overall performance and bandwidth, the address management module needs to ensure balanced access among the pseudo-channel PCs to avoid frequent access by individual PCs in a short period of time while the rest of the PCs are idle. If a PC returns slowly, feedback When the MMU is busy, one scheduling can be reduced based on real-time command statistics and single PC historical command statistics. From the analysis of the entire process of data flow, there is still a balanced access between PCs.

The fourth step is small packet splicing technology. Storing on-chip PDs off-chip will theoretically reduce the bandwidth and efficiency of off-chip storage due to the packet length. Packing technology is used to store it. The purpose of packing is to squeeze out the invalid bytes in the PK and PD that need to be packed outside the chip by squeezing bubbles, and then splicing the valid bytes to improve the off-chip Cache utilization.

The step of grouping is that the MMU receives the outsourced PD and PK sent by the PMU, firstly extracts and combines the PD information, and at the same time squeezes out the invalid bytes in the PK, shifts and splices the small packets, and extracts valid data , and then combine the packaged PD information and the PK from which the effective data is extracted again, and send the result to off-chip for storage.

Since the bit width of the off-chip bus is 384B, except for single packets (does not need to be combined), different types of combined packages will have different output results for each shot. There are two cases of small package splicing: PK_len≤384B); small package and small package (PD_len+PK_len>384B). When the first type of small packets are combined into small packets, the length of the PD plus the length of the extracted data is less than the bus bit width, and can be output in one shot; when the second type of small packets are combined into small packets, because the length is greater than the bus bit width, it needs to be divided into two shots. Output, the output of the first beat is 384B high, and the remaining part is output with zeros at the end of the second beat, which will affect the line speed and should be avoided as much as possible.

The solution of the present application is not only compatible with various types of cache controllers, but also can improve off-chip read and write bandwidth and access efficiency. The following uses the actual measurement data to illustrate the actual measurement data before and after the bandwidth and efficiency improvement in the case of external HBM/DDR5/DDR4 three types of controllers.

The results of testing the plug-in HBM using standard address mapping are shown in Table 1. The test results of the efficiency improvement method of the present application are shown in Table 2. Table 3 is the test data of the external DDR5, and Table 4 is the test data of the external DDR4. After comparative analysis of the actual measurement results, the total off-chip bandwidth and storage efficiency in each mode are all the same. There is an improvement.

Table 1

use case number Off-chip storage package length (Byte) Total Bandwidth (Gbps) efficiency 1 128 862 0.35 2 192 1352 0.55 3 256 1643 0.67 4 288 1607 0.65 5 352 1739 0.71 6 384 1769 0.72 7 768 1648 0.67 8 1152 1634 0.67 9 1536 1628 0.66 10 1568 1601 0.65

Table 2

Table 2 (continued)

use case number Off-chip storage package length (Byte) Total Bandwidth (Gbps) efficiency 7 768 2169 0.88 8 1152 2166 0.88 9 1536 2133 0.86 10 1568 2028 0.83

table 3

use case number Off-chip storage package length (Byte) Total Bandwidth (Gbps) efficiency 1 128 136.89 0.59 2 192 154.22 0.67 3 256 163.54 0.71 4 384 168.49 0.73 5 768 170.63 0.74 6 1152 172.45 0.75 7 1184 169.61 0.74 8 1536 173.55 0.75 9 1568 169.95 0.74 10 12288 166.54 0.72

Table 4

use case number Off-chip storage package length (Byte) Total Bandwidth (Gbps) efficiency 1 128 200.64 65.35 2 192 247.85 80.73 3 256 267.03 86.98 4 384 272.29 88.69 5 768 270.61 88.15 6 1152 243.78 79.41 7 1536 252.68 82.31 8 1568 232.25 75.65 9 6144 233.99 76.22 10 12288 220.05 71.68

Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general-purpose hardware platform, and of course also by hardware, but in many cases the former is Better implementation. Based on such an understanding, the technical solution of the present application can be embodied in the form of a software product in essence or the part that contributes to the prior art, and the computer software product is stored in a storage medium (such as ROM/RAM, disk, CD) contains several instructions to enable a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to execute the above-mentioned methods in various embodiments of the present application.

This embodiment also provides a processing device for graphics rendering, which is used to implement the above embodiments and preferred implementation modes, and what has been described will not be repeated here. As used below, the term "module" may be a combination of software and/or hardware that realizes a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementations in hardware, or a combination of software and hardware are also possible and contemplated.

FIG. 13 is a structural block diagram of a cache management device according to an embodiment of the present application. As shown in FIG. 13 , the device includes:

The identification unit 1302 is configured to enable the cache management unit MMU to identify the type of the external cache controller based on the CPU configuration information;

A confirmation unit 1304, configured to confirm the offset address in a table look-up manner based on the address management submodule and the address area corresponding to the above cache controller type;

The calculation unit 1306 is configured to calculate the logical address of the above-mentioned cache controller type based on the above-mentioned offset address; wherein, the number of external connection channels selected by different cache controller types is different.

Through this application, because the cache management unit MMU is used to identify the type of external cache controller based on the CPU configuration information; based on the address management submodule and the address area corresponding to the above cache controller type, the offset address is confirmed in a table lookup manner; The logical address of the above-mentioned cache controller type is calculated based on the above-mentioned offset address; wherein, the number of external connection channels selected by different above-mentioned cache controller types is different; therefore, the switching of different controllers under the same framework is realized, which can Solve the problem of being compatible with different controllers under the same framework, and then be compatible with multiple controllers under the same framework, and improve the effect of storage efficiency.

It should be noted that the above-mentioned modules can be realized by software or hardware. For the latter, it can be realized by the following methods, but not limited to this: the above-mentioned modules are all located in the same processor; or, the above-mentioned modules can be combined in any combination The forms of are located in different processors.

Embodiments of the present application also provide a computer-readable storage control program, where a computer program is stored in the computer-readable storage control program, wherein the computer program is configured to perform any of the above method embodiments when running. step.

In an exemplary embodiment, the above-mentioned computer-readable storage control program may include but not limited to: a driver program for a CPU and a storage controller, a control program for connecting an FPGA to an HBM/DDR3, and the like.

Embodiments of the present application also provide a controller, including a buffer (cache part of the data) and a processor, a computer program is stored in the controller, and the controller is configured to run the computer program to perform any one of the above methods Steps in the examples.

In an exemplary embodiment, the above-mentioned controller may further include a transmission device for protocol conversion, wherein the transmission device is connected to the above-mentioned controller to realize the connection with the cache controller.

For specific examples in this embodiment, reference may be made to the examples described in the foregoing embodiments and exemplary implementation manners, and details will not be repeated here in this embodiment.

Obviously, those skilled in the art should understand that each module or each step of the above-mentioned application can be realized by a general-purpose computing device, and they can be concentrated on a single computing device, or distributed in a network composed of multiple computing devices In fact, they can be implemented in program code executable by a computing device, and thus, they can be stored in a storage device to be executed by a computing device, and in some cases, can be executed in an order different from that shown here. Or described steps, or they are fabricated into individual integrated circuit modules, or multiple modules or steps among them are fabricated into a single integrated circuit module for implementation. As such, the present application is not limited to any specific combination of hardware and software.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, there may be various modifications and changes in the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of this application shall be included within the scope of protection of this application.

Claims (10)

1. A method for cache management, comprising:

the cache management unit MMU identifies the type of an externally connected cache controller based on the CPU configuration information;

confirming an offset address in a table look-up mode based on address management sub-modules and address areas corresponding to the types of the cache controllers;

calculating a logical address of the cache controller type based on the offset address; and the number of the external connection channels gated by different cache controller types is different.

2. The method of claim 1, further comprising:

the address mapping submodule of the MMU reads a preset address mapping relation; the address mapping relation is that the on-chip logic address is converted into a physical address which can be accepted by the cache chip.

3. The method of claim 1, further comprising:

the address mapping submodule of the MMU reads a preset address mapping relation; the address mapping relation is that the on-chip logic address is converted into a physical address which can be accepted by the cache chip;

and according to different application scenes, reconfiguring through the CPU to obtain an address mapping relation corresponding to the application scenes after reconfiguration.

4. The method of claim 1, further comprising:

and segmenting data packets sent to the MMU by the CPU according to the demand of the off-chip cache and the structural attribute of a cache controller, wherein the segmented data packets correspond to block addresses, one data packet corresponds to a plurality of block addresses, and the cache controller has different types and different address management intervals.

5. The method of claim 1, further comprising:

the MMU receives off-chip data sent by a message cache management unit PMU, wherein the off-chip data comprises a message descriptor PD and a message PK;

extracting data information of the PD;

the data information is spliced to obtain spliced data, and the first data in the PK is deleted;

shifting and splicing the spliced data to extract second data;

splicing and packaging the data information of the PD in the spliced and packaged data and the extracted second data again to obtain target spliced and packaged data

And sending the target packet data to an off-chip cache for storage.

6. The method of claim 5, further comprising:

when the data bit length of the PD plus the data bit length of the extracted second data is less than or equal to the bus bit width, outputting the PD and the second data simultaneously;

when the data bit length of the PD plus the extracted data bit length of the second data is larger than the bus bit width, splitting the PD and the second data into first split data and second split data;

outputting the PD and the first split data;

and carrying out zero padding operation on the second split data to obtain zero padding processing data with the data bit length equal to the bus bit width, and outputting the zero padding processing data.

7. The method according to any one of claims 1 to 6, further comprising:

a message cache management unit (PMU) issues a write message;

the PMU stores the write message and sends a write release command to a traffic cache management unit (TMMU); the TMMU transmits a message descriptor to a queue management unit QMU;

the QMU sends a write command through the TMMU and transmits the write command to the MMU, and the QMU sends a write release signal to the TMMU after finishing storing the write command;

the command queue issues a message reading command, reads message reading data and returns the message reading data to the PMU;

and the TMMU issues a read command and reads the message descriptor data.

8. A cache management apparatus, comprising:

the identification unit is used for enabling the cache management unit MMU to identify the type of the externally connected cache controller based on the CPU configuration information of the central processing unit;

the confirming unit is used for confirming the offset address in a table look-up mode based on the address management submodule and the address area corresponding to the type of the cache controller;

a calculating unit, configured to calculate a logical address of the cache controller type based on the offset address; and the number of the external connection channels gated by different cache controller types is different.

9. A computer-readable storage control program, characterized in that a computer program is stored in the computer-readable storage program, wherein the computer program is arranged to perform the method of any of claims 1 to 7 when executed.

10. A controller comprising a buffer and a processor, wherein a computer program is stored in the controller, and wherein the processor is configured to execute the computer program to perform the method according to any of claims 1 to 7.

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