CN115754388A - Probe card, chip testing method, testing machine and storage medium - Google Patents
Probe card, chip testing method, testing machine and storage medium Download PDFInfo
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Abstract
The invention is suitable for the technical field of chip testing, and provides a probe card, a chip testing method, a testing machine and a storage medium, wherein the probe card comprises a first probe unit and a second probe unit, the first probe unit comprises a first probe area and a second probe area, and the second probe unit comprises a third probe area and a fourth probe area; the second probe area and the third probe area are connected by adopting an insulating material in a bridging manner, and the probe card is rectangular; a first pin card hole opening position capable of accommodating two rows of chips to be tested is arranged between the first probe area and the second probe area, and a second pin card hole opening position capable of accommodating two rows of chips to be tested is arranged between the third probe area and the fourth probe area; the first probe area, the second probe area, the third probe area and the fourth probe area are respectively provided with a row of probes, and each probe is used for contacting with a chip to be tested which is arranged on a probe station. The invention can improve the chip testing efficiency by improving the simultaneous testing number of the probe card.
Description
Technical Field
The invention belongs to the technical field of chip testing, and particularly relates to a probe card, a chip testing method, a testing machine and a storage medium.
Background
Wafer (CP) testing is performed between wafer manufacturing and packaging in the whole Chip manufacturing process, each Chip on the whole wafer is tested, and among many factors affecting the CP testing efficiency of the chips, the most important factor is the number of simultaneous tests, and under the existing tester resources, a Chip with a large number of pins can only test 8 chips, 16 chips or 32 chips at a time in the CP testing, because the number of simultaneous tests is too small, the Chip testing efficiency is very low.
Disclosure of Invention
In view of this, embodiments of the present invention provide a probe card, a chip testing method, a testing machine and a storage medium, which solve the problem of low chip testing efficiency by manufacturing a probe card with a larger number of simultaneous tests and using the probe card to perform testing.
A first aspect of embodiments of the present invention provides a probe card including a first probe unit including a first probe region and a second probe region, and a second probe unit including a third probe region and a fourth probe region;
the second probe area and the third probe area are connected by adopting an insulating material in a bridging manner;
a first pin card hole opening position capable of accommodating two rows of chips to be tested is arranged between the first probe area and the second probe area, and a second pin card hole opening position capable of accommodating two rows of chips to be tested is arranged between the third probe area and the fourth probe area;
the first probe area, the second probe area, the third probe area and the fourth probe area are respectively provided with a row of probes, and each probe is used for contacting with a chip to be tested which is placed on a probe table.
A second aspect of the embodiments of the present invention provides a chip testing method applied to a testing machine, which is implemented based on the probe card, and includes:
setting a test program matched with the probe card;
setting a probe station to be in a jump test mode;
if receiving a starting signal sent by the probe station, executing the test program to test a chip to be tested;
after the test is finished, sending a finished signal to a probe station, returning to the step of testing the chip to be tested by executing the test program if a test trigger signal sent by the probe station is received, until all the chips to be tested are tested;
the probe station is used for sending a start signal to the tester when a chip to be tested is moved to a position contacted with the probe, and moving the next chip to be tested to a position contacted with the probe and sending the next start signal to the tester when an end signal sent by the tester is received until all chips to be tested are tested;
the jump test mode is to continuously test m times of chips to be tested, jump n rows of chips to be tested after testing k rows of chips each time, and then test, wherein m, k and n are positive integers.
A third aspect of the embodiments of the present invention provides a testing machine, which includes a memory, a processor, and a computer program stored in the memory and operable on the processor, wherein the processor implements the steps of the chip testing method according to the second aspect of the embodiments of the present invention when executing the computer program.
A fourth aspect of embodiments of the present invention provides a computer-readable storage medium, which stores a computer program that, when executed by a processor, implements the steps of the chip testing method according to the second aspect of embodiments of the present invention.
According to the first aspect of the embodiment of the invention, the simultaneous measurement number is determined according to the pin number and the channel number of the testing machine required by the item to be tested of the chip to be tested, and the probe card comprising the first probe unit and the second probe unit is designed and manufactured, so that the simultaneous measurement number of the probe card can be effectively improved, and the chip testing efficiency can be improved when the probe card is used for testing.
In the second aspect of the embodiments of the present invention, a probe station is set to a skip test mode by setting a test program matched with the probe card provided in the first aspect, and if a start signal sent by the probe station is received, the test program is executed to test a chip to be tested, after the test is finished, an end signal is sent to the probe station, and if a test trigger signal sent by the probe station is received, the step of executing the test program to test the chip to be tested is returned, until all the chips to be tested are tested, so that the chip test efficiency can be effectively improved.
It is understood that, the beneficial effects of the third aspect and the fourth aspect can be referred to the related description of the second aspect, and are not described herein again.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a probe card provided in an embodiment of the present application;
FIG. 2 is a first flowchart of a chip testing method according to an embodiment of the present disclosure;
FIG. 3 is a second flowchart of a chip testing method according to an embodiment of the present disclosure;
FIG. 4 is a third schematic flowchart of a chip testing method according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a first skip test mode provided in an embodiment of the present application;
fig. 6 is a schematic diagram of a second skip test mode provided in the embodiment of the present application;
fig. 7 is a schematic diagram of a third skip mode provided in the embodiment of the present application;
fig. 8 is a schematic diagram of a chip testing process provided in an embodiment of the present application;
FIG. 9 is a schematic structural diagram of a chip testing apparatus provided in an embodiment of the present application;
fig. 10 is a schematic structural diagram of a testing machine according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.
Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless otherwise specifically stated.
The probe card provided by the embodiment of the application is used for contacting with a chip to be tested to test the chip, determining the number of simultaneous measurement according to the number of pins and the number of channels of a testing machine required by a project to be tested of the chip to be tested, and designing and manufacturing the probe card comprising a first probe unit (the first probe unit comprises a first probe area and a second probe area) and a second probe unit (the second probe unit comprises a third probe area and a fourth probe area). The second probe area of the probe card is connected with the third probe area through a bridging mode, the number of simultaneous measurement is increased, and the problems that the needle inserting force is influenced to influence the test result due to the fact that the needles of the probes in the first probe area are too long when the needles of the probes in the first probe area are discharged towards the right side of the opening position of the first needle card and the needles of the probes in the fourth probe area are discharged towards the left side of the opening position of the second needle card are solved.
As shown in fig. 1, a probe card 100 according to an embodiment of the present invention includes a first probe unit 1 and a second probe unit 2, where the first probe unit 1 includes a first probe region 11 and a second probe region 12, and the second probe unit 2 includes a third probe region 21 and a fourth probe region 22;
the second probe region 12 and the third probe region 21 are connected by using an insulating material in a bridging manner;
a first needle card hole opening position 13 capable of accommodating two rows of chips to be tested is arranged between the first probe area 11 and the second probe area 12, and a second needle card hole opening position 23 capable of accommodating two rows of chips to be tested is arranged between the third probe area 21 and the fourth probe area 22; the first probe area 11, the second probe area 12, the third probe area 21 and the fourth probe area 22 are respectively provided with a row of probes 3, and each probe is used for contacting with a chip to be tested which is arranged on a probe station.
In application, the probe card may further include more probe units, such as a first probe unit, a second probe unit, a third probe unit of 8230, a k-th probe unit, each of which includes two probe regions; the probe card can also comprise more bridging arrangements, such as bridging the second probe area and the third probe area, bridging the fourth probe area and the fifth probe area, and bridging the fourth probe area and the fifth probe area, wherein the fourth probe area and the fifth probe area are 8230, and bridging the 2k-2 probe area and the 2k-1 probe area; the probe card also comprises more pin card hole opening positions, such as a first pin card hole opening position, a second pin card hole opening position, a third pin card hole opening position \8230 \ 8230and a k-th pin card hole opening position; the probes of the first probe area and the second probe area are discharged from the first probe card opening position, the probes of the third probe area and the fourth probe area are discharged from the second probe card opening position, the probes of the fifth probe area and the sixth probe area are discharged from the third probe card opening position \8230 \ 8230, and the probes of the 2k-1 probe area and the 2k probe area are discharged from the k-th probe card opening position.
In one embodiment, the first probe unit further comprises a first circuit board, and the second probe unit further comprises a second circuit board;
the two rows of probes of the first probe unit are respectively connected with the first circuit board through conducting wires, and the two rows of probes of the second probe unit are respectively connected with the second circuit board through conducting wires.
In application, in a cantilever type probe card structure, the first probe unit further comprises a first circuit board, the second probe unit further comprises a second circuit board, and the third probe unit further comprises a third circuit board, \8230 \ 8230;, the kth probe unit further comprises a kth circuit board; the two rows of probes of the first probe unit are respectively connected with the first circuit board through a lead, the two rows of probes of the second probe unit are respectively connected with the second circuit board through a lead, the two rows of probes of the third probe unit are respectively connected with the third circuit board through leads, \ 8230 \ the two rows of probes of the kth probe unit are respectively connected with the kth circuit board through leads.
In one embodiment, the first and second probe units are cantilever probe cards, and the probes are cantilever probes.
In one embodiment, the bridge pitch between the second probe region and the third probe region is the width of N chips, where N is an even number that is not zero.
In an application, in a cantilever probe card structure, a bridging distance between the second probe region and the third probe region may be a width of four chips to be tested, a width of six chips to be tested, or a bridging distance between the second probe region and the third probe region is a width of N chips to be tested according to a size of the chips to be tested.
In an application, in a cantilever probe card structure, a bridging distance between probe regions may be a width of four chips to be tested, a width of six chips to be tested, or a width of N chips to be tested according to a size of the chips to be tested.
In one embodiment, when a probe card with a measurement count of 64 is manufactured, since too many measurements will affect the probe outlet, the probe card may be designed into 4 rows, as shown in fig. 6, and widths of four chips to be tested are reserved between the second probe area and the third probe area of the probe card for bridging.
As shown in fig. 2, an exemplary chip testing method applied to a testing machine includes the following steps S201 to S204:
step S201, a test program matching the probe card is set, and the process proceeds to step S202.
In application, the types of chips to be tested are different, the items to be tested of the chips are different, and the used probe cards are also different, so that a test program matched with the probe cards needs to be set when the chips are tested.
Step S202, the probe station is set to the skip mode, and the process proceeds to step S203.
In application, if a common probe card is used for testing, the jump test mode only plays a role in sampling detection and cannot detect all chips; if the probe card with the bridging structure provided by the application is used, all chips to be tested can be tested in the jump test mode.
In application, when a probe station matched with a probe card is used for testing, the probe station is set to be in a jump test mode.
In application, a wafer is placed on a probe station, after a chip is contacted with a probe in a probe card, a signal for starting testing is sent to a testing machine, and after the testing machine receives the starting signal sent by the probe station, a testing program is started to test the chip to be tested.
And step S204, after the test is finished, sending a finishing signal to the probe station, and returning to the step S203 until the test of all the chips to be tested is finished.
In application, after the chip test is finished, the tester sends a finished signal to the probe station, receives the test trigger signal sent by the probe station again, and executes the test program to test the chip to be tested until all the chips to be tested are tested.
The probe station is used for sending a start signal to the tester when the chip to be tested is moved to the position contacted with the probe, and moving the next chip to be tested to the position contacted with the probe and sending the next start signal to the tester when the end signal sent by the tester is received until the test of all the chips to be tested is completed.
As shown in fig. 3, in an embodiment, before step S203, the method further includes:
s2031, mounting a probe card on a probe station;
s2032, placing the chip to be tested on a probe station.
In application, a probe card and a chip to be tested are arranged on a probe station through mechanical motion equipment such as a mechanical arm and a transmission belt of a testing machine.
As shown in fig. 4, step S204 further includes:
s2040, after one-time test is finished, sending a finished signal to a probe station;
s2041, storing the test result in a storage module;
s2042, the probe station receives the end signal sent by the tester, moves the next chip to be tested to the position contacted with the probe and sends a next start signal to the tester.
The jump test mode is to continuously test m times of chips to be tested, jump n rows of chips to be tested after testing k rows of chips each time, and then test, wherein m, k and n are positive integers.
In one embodiment, if 4 rows of chips are tested simultaneously each time, the skip test mode is to continuously test m chips to be tested, and after 4 rows of chips are tested each time, skip N rows of chips to be tested and then test m = (N + 2)/2, N = N +2.
In application, the test skipping mode can be to continuously test the chip to be tested for 3 times, and after 4 columns of chips are tested each time, skip 6 columns of chips to be tested and then test.
The bridging distance between the second probe area and the third probe area is the width of 4 chips, 4 columns of chips are tested at the same time each time, the 1 st, 2 nd, 7 th and 8 th columns of chips are tested for the first time, the 3 rd, 4 th, 9 th and 10 th columns of chips are tested for the second time, the 5 th, 6 th, 11 th and 12 th columns of chips are tested for the third time, the 6 th to 12 th columns of chips to be tested are skipped for the fourth time, the 13 th, 14 th, 19 th and 20 th columns of chips are tested, and the like.
In one embodiment, if 3 rows of chips are tested simultaneously each time, the first probe region, the second probe region, and the third probe region, or the first probe region, the second probe region, and the fourth probe region are used for testing, in the skip test mode, m chips to be tested are tested continuously, after 3 rows of chips are tested each time, N rows of chips to be tested are skipped for testing, and m = (N + 2)/2, N = (N + 2)/2.
In application, the test skipping mode can be to continuously test the chip to be tested for 3 times, and after 3 columns of chips are tested each time, skip 3 columns of chips to be tested and then test.
The bridging distance between the second probe area and the third probe area is the width of 4 chips, 3 columns of chips are tested at the same time each time, the 1 st, 2 nd and 7 th columns of chips are tested for the first time, the 3 rd, 4 th and 8 th columns of chips are tested for the second time, the 5 th, 6 th and 9 th columns of chips are tested for the third time, the 3 columns of chips of the 7 th to 9 th columns are skipped for the fourth time, the 10 th, 11 th and 16 th columns of chips are tested, and the like.
If 3 rows of chips are tested simultaneously each time, the second probe area, the third probe area, the fourth probe area or the first probe area, the third probe area and the fourth probe area are used for testing, the skip test mode is that m times of chips to be tested are tested continuously, N rows of chips to be tested are skipped after 3 rows of chips are tested each time, and then the testing is carried out, wherein m = N +1, N =2 (N + 1).
In application, the skip test mode may be to continuously test 5 times of chips to be tested, and after testing 3 columns of chips each time, skip 10 columns of chips to be tested and then test.
The bridging distance between the second probe area and the third probe area is the width of 4 chips, 3 columns of chips are tested at the same time each time, the 1 st, 6 th and 7 th columns of chips are tested for the first time, the 2 nd, 8 th and 9 th columns of chips are tested for the second time, the 3 rd, 10 th and 11 th columns of chips are tested for the third time, the 4 th, 12 th and 13 th columns of chips are tested for the fourth time, the 5 th, 14 th and 15 th columns of chips are tested for the fifth time, the 10 th to-15 th columns of chips to be tested are skipped for the sixth time, the 16 th, 21 th and 22 th columns of chips are tested, and the like.
In application, the skip test mode may be to continuously test 3 chips (1, 2, 3), skip 4 chips (4, 5,6, 7), then continuously test 3 chips (8, 9, 10), skip 4 chips, and so on. . As shown in fig. 5, a schematic diagram of a skip mode is exemplarily shown; and the bridging distance between the second probe area and the third probe area is continuously tested and is the width of 4 chips, and 3 rows of chips are simultaneously tested each time.
In one embodiment, if 2 rows of chips to be tested are tested simultaneously each time, the first probe region and the third probe region, or the first probe region and the fourth probe region, or the second probe region and the third probe region, or the second probe region and the fourth probe region are used for testing, the skip test mode is to continuously test m times of chips to be tested, and after 2 rows of chips are tested each time, N rows of chips to be tested are skipped for testing, and m = N +1, N = m.
In application, the test skipping mode may be to continuously test 5 times of chips to be tested, and after 2 columns of chips are tested each time, skip 5 columns of chips to be tested and then test.
The bridging distance between the second probe area and the third probe area is the width of 4 chips, 2 columns of chips are tested at the same time each time, the 1 st and 6 th columns of chips are tested for the first time, the 2 nd and 7 th columns of chips are tested for the second time, the 3 rd and 8 th columns of chips are tested for the third time, the 4 th and 9 th columns of chips are tested for the fourth time, the 5 th and 10 th columns of chips are tested for the fifth time, the 5 th to-10 th columns of chips to be tested are skipped for the sixth time, the 11 th and 16 th columns of chips are tested, and the like.
In one embodiment, when the probe card shown in fig. 6 is used for testing, when the probe card is mounted on a probe station and tested by a testing machine, a test program matched with the probe card is firstly set, then the probe station is set to a skip test mode, the testing machine executes the test program to test a chip to be tested when receiving a start signal sent by the probe station, after the test is finished, an end signal is sent to the probe station, and the probe station moves a next chip to be tested to a position contacting with a probe and sends a next start signal to the testing machine when receiving the end signal sent by the probe station until all chips to be tested are tested.
The skip test mode of the probe station is set to continuously test 3 times of chips to be tested, and after 4 columns of chips are tested each time, 6 columns of chips to be tested are skipped, and then the test is performed, as shown in fig. 7, the skip test process includes testing 1 st, 2 nd, 7 th and 8 columns of chips for the first time, testing 3 rd, 4 th, 9 th and 10 th columns of chips for the second time, testing 5 th, 6 th, 11 th and 12 th columns of chips for the third time, skipping 6 th columns of chips to be tested (7 th to 12 th columns) for the fourth time, testing 13 th, 14 th, 19 th and 20 th columns of chips, testing 15 th, 16 th, 21 th and 22 th columns of chips for the sixth time, and testing 17 th, 18 th, 23 th and 24 th columns of chips for the seventh time.
Fig. 8 is a schematic diagram of a chip testing process provided in an embodiment of the present application.
In the actual test requirements of the chip, not all items to be tested can be directly tested, some items can be tested after being baked, and some items can be tested after being erased by Ultraviolet (UV).
Among the items to be tested, the test item which can be tested for the first time without baking or erasing can be tested by using a first probe card; items requiring baking, after which a second test can be performed using a second probe card; items needing to be erased, and a third test can be performed after the erasing by using the first probe card; different kinds of chips select proper test flow according to the requirements of different test items, and not all chips are tested according to the test flow shown in fig. 8.
In the chip testing process, a certain probe card is determined to be used for testing according to the time length and the pin number required by the item to be tested.
In one embodiment, all the items to be tested of a certain chip can be directly tested, but the testing time of a certain item is long, in this case, the item with long testing time can be tested by the first probe card, and other items to be tested can be tested by the second probe card. According to the test items, different probe cards are used for testing different items to be tested, so that the test time can be saved, the test cost is reduced, and the test efficiency is improved.
In application, a testing machine with 512 channels is used for testing a Micro Controller Unit (MCU) chip, a large-capacity MCU chip has 32 pins, and when a memory Unit is tested, burning tests are required, but the large-capacity burning tests usually require more than 10 seconds, and some tests even require more than twenty seconds to be completed, and only four pins including a power supply, a ground, a data port and a clock port are required in the burning tests, so that a first probe card is used for making 128 simultaneous testing numbers for burning tests, a second probe card is used for making 16 simultaneous testing numbers for testing other items to be tested, when a first probe card is used for testing, a probe stage is required to be set to a skip test mode, and after all items to be tested which can be tested by using the first probe card are tested, the first probe card is changed into the second probe card for testing other items to be tested. By using two probe cards with different structures to test different items to be tested, the time consumed by chip testing can be effectively reduced, and the chip testing efficiency is greatly improved on the premise of increasing the cost of manufacturing one probe card.
In one embodiment, the test time for a wafer is calculated as:
the machine action time is 0.5 second, and the test coefficient is 1.4.
The testing time of a single chip is 10s, the total testing amount is 50000, the cost of one pin card is 20000 yuan, the time price of the testing machine is 100 yuan/hour, the time of one testing item is 5s, two pin cards are made, the first probe card is made into 128 simultaneous testing numbers, the second probe card is made into 16 simultaneous testing numbers, and the cost of the current testing is calculated as follows:
when two probe cards are used for testing, the testing time can be saved, and the testing efficiency is improved.
The cost of making one more probe card can be earned back by testing only 39 wafers.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
The embodiment of the application also provides a chip testing device which is used for executing the steps in the chip testing method. The chip test device may be a virtual application (virtual application) in the tester, run by a processor of the tester, or may be the tester itself.
As shown in fig. 9, the chip testing apparatus 200 according to the embodiment of the present application includes:
a program setting unit 201 for setting a test program matched with the probe card, and entering a mode setting unit 202;
a mode setting unit 202, configured to set the probe station to a skip test mode, and enter a test unit 203;
the test unit 203 is used for executing a test program to test a chip to be tested if a start signal sent by the probe station is received, and entering the return unit 204;
a returning unit 204, configured to send an end signal to the probe station after the test is finished, and return to the testing unit 203 until all chips to be tested are tested;
the probe station is used for sending a start signal to the tester when the chip to be tested is moved to the position contacted with the probe, and moving the next chip to be tested to the position contacted with the probe and sending the next start signal to the tester when an end signal sent by the tester is received until the test of all the chips to be tested is finished;
the jump test mode is to continuously test m times of chips to be tested, after k rows of chips are tested each time, n rows of chips to be tested are skipped and then tested, and m, k and n are positive integers.
In application, each unit in the chip testing apparatus may be a software program module, may also be implemented by different logic circuits integrated in a processor, and may also be implemented by a plurality of distributed processors.
As shown in fig. 10, an embodiment of the present application further provides a testing machine 300, including: at least one processor 301 (only one processor is shown in fig. 10), a memory 302, and a computer program 303 stored in the memory 302 and executable on the at least one processor 301, the steps in the various chip test method embodiments described above being implemented when the computer program 303 is executed by the processor 301.
In an application, a tester may include, but is not limited to, a memory, a processor. Those skilled in the art will appreciate that fig. 10 is merely an example of a testing machine and is not intended to be limiting, and may include more or fewer components than those shown, or some components may be combined, or different components may be included, such as input output devices, network access devices, mechanical motion devices, etc. The input and output devices may include cameras, audio capture/playback devices, display devices, keyboards, keys, etc. The network access device may include a communication module for communicating with other devices. The mechanical motion device may include a robot arm, a conveyor belt, etc. for mounting and transporting a probe card, a chip to be tested, etc.
In Application, the Processor may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, etc. A general purpose processor may be a microprocessor or any conventional processor or the like.
In an application, the memory may be an internal storage unit of the tester in some embodiments, such as a hard disk or a memory of the tester. The memory may also be an external storage device of the tester in other embodiments, such as a plug-in hard disk provided on the tester, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like. Further, the memory may also include both internal storage units and external storage devices of the tester. The memory is used for storing an operating system, an application program, a Boot Loader (Boot Loader), data, and other programs, such as program codes of computer programs. The memory may also be used to temporarily store data that has been output or is to be output.
In application, the Communication module may be configured as any device capable of performing wired or Wireless Communication directly or indirectly with other devices according to actual needs, for example, the Communication module may provide a solution applied to a network device, including a Communication interface (e.g., universal Serial Bus (USB), a wired Local Area Network (LAN), a Wireless Local Area Network (WLAN) (e.g., wi-Fi network), bluetooth, zigbee, mobile Communication network, global Navigation Satellite System (GNSS), frequency Modulation (FM), wireless Communication technology (NFC), infrared technology (Infrared, IR), and the like.
It should be noted that, for the information interaction, execution process, and other contents between the above-mentioned devices/units, the specific functions and technical effects thereof are based on the same concept as those of the embodiment of the method of the present application, and specific reference may be made to the part of the embodiment of the method, which is not described herein again.
It will be clear to those skilled in the art that, for convenience and simplicity of description, the above division of the functional units is only used as an example, and in practical applications, the above function distribution may be performed by different functional units according to needs, that is, the internal structure of the device is divided into different functional units to perform all or part of the above described functions. Each functional unit in the embodiments may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units are only used for distinguishing one functional unit from another, and are not used for limiting the protection scope of the present application. The specific working process of the units in the system may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.
The embodiment of the present application provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the chip testing method of any one of the above embodiments is implemented.
The embodiments of the present application provide a computer program product, which, when running on a testing machine, enables the testing machine to execute the chip testing method of any of the above embodiments.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the methods of the embodiments described above may be implemented by a computer program instructing related hardware to execute the computer program, and the computer program may be stored in a computer readable storage medium, and when executed by a processor, may implement the steps of the embodiments of the methods described above. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include at least: any entity or device capable of carrying computer program code to a test machine, recording medium, computer Memory, read-Only Memory (ROM), random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, and software distribution media. Such as a usb-disk, a removable hard disk, a magnetic or optical disk, etc.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus, tester, and method may be implemented in other ways. For example, the above-described apparatus and tester embodiments are merely illustrative, and for example, a division of a unit is merely a logical functional division, and an actual implementation may have another division method, for example, two or more units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the embodiments of the present application, and they should be construed as being included in the present application.
Claims (10)
1. A probe card comprising a first probe unit including a first probe region and a second probe region, and a second probe unit including a third probe region and a fourth probe region;
the second probe area and the third probe area are connected by adopting an insulating material in a bridging mode;
a first pin card hole opening position capable of accommodating two rows of chips to be tested is arranged between the first probe area and the second probe area, and a second pin card hole opening position capable of accommodating two rows of chips to be tested is arranged between the third probe area and the fourth probe area;
the first probe area, the second probe area, the third probe area and the fourth probe area are respectively provided with a row of probes, and each probe is used for contacting with a chip to be tested which is placed on a probe station.
2. The probe card of claim 1, wherein the first probe unit further comprises a first circuit board, and the second probe unit further comprises a second circuit board;
the two rows of probes of the first probe unit are respectively connected with the first circuit board through leads, and the two rows of probes of the second probe unit are respectively connected with the second circuit board through leads.
3. The probe card of claim 1, wherein the first and second probe units are cantilever probe cards, and the probes are cantilever probes.
4. The probe card of claim 1, wherein a bridge pitch between the second probe region and the third probe region is a width of N chips, wherein N is an even number different from zero.
5. A chip testing method realized based on the probe card of any one of claims 1 to 4, which is applied to a testing machine, and comprises the following steps:
setting a test program matched with the probe card;
setting a probe station to be in a jump test mode;
if receiving a starting signal sent by the probe station, executing the test program to test a chip to be tested;
after the test is finished, sending a finished signal to a probe station, returning to the step of testing the chip to be tested by executing the test program if a test trigger signal sent by the probe station is received, until all the chips to be tested are tested;
the probe station is used for sending a start signal to the tester when a chip to be tested is moved to a position contacted with the probe, and moving the next chip to be tested to a position contacted with the probe and sending the next start signal to the tester when an end signal sent by the tester is received until the test of all chips to be tested is finished;
the jump test mode is to continuously test m times of chips to be tested, jump n rows of chips to be tested after testing k rows of chips each time, and then test, wherein m, k and n are positive integers.
6. The chip testing method of claim 5, comprising:
if 4 rows of chips are tested simultaneously each time, the skip test mode is to continuously test m times of chips to be tested, and after 4 rows of chips are tested each time, N rows of chips to be tested are skipped and then m = (N + 2)/2, N = N +2 is tested;
the bridging distance between the second probe area and the third probe area is the width of 4 chips, 4 columns of chips are tested at the same time each time, the 1 st, 2 nd, 7 th and 8 th columns of chips are tested for the first time, the 3 rd, 4 th, 9 th and 10 th columns of chips are tested for the second time, the 5 th, 6 th, 11 th and 12 th columns of chips are tested for the third time, the 6 th to 12 th columns of chips to be tested are skipped for the fourth time, the 13 th, 14 th, 19 th and 20 th columns of chips are tested, and the like.
7. The chip testing method of claim 5, comprising:
if 3 rows of chips are tested at the same time, the first probe area, the second probe area and the third probe area are utilized, or the first probe area, the second probe area and the fourth probe area are utilized for testing, the jump testing mode is to continuously test m times of chips to be tested, after 3 rows of chips are tested each time, N rows of chips to be tested are skipped, and then the testing is carried out, wherein m = (N + 2)/2, N = (N + 2)/2;
the bridging distance between the second probe area and the third probe area is the width of 4 chips, 3 rows of chips are tested at the same time each time, the 1 st, 2 nd and 7 th rows of chips are tested for the first time, the 3 rd, 4 th and 8 th rows of chips are tested for the second time, the 5 th, 6 th and 9 th rows of chips are tested for the third time, the 3 rows of chips of the 7 th to 9 th rows are skipped for the fourth time, the 10 th, 11 th and 16 th rows of chips are tested, and the like;
if 3 rows of chips are tested at the same time, testing by using the second probe area, the third probe area, the fourth probe area or the first probe area, the third probe area and the fourth probe area, wherein the jump testing mode is to continuously test m times of chips to be tested, skip N rows of chips to be tested after 3 rows of chips are tested each time, and then test m = N +1, N =2 (N + 1);
the bridging distance between the second probe area and the third probe area is the width of 4 chips, 3 columns of chips are tested at the same time each time, the 1 st, 6 th and 7 th columns of chips are tested for the first time, the 2 nd, 8 th and 9 th columns of chips are tested for the second time, the 3 rd, 10 th and 11 th columns of chips are tested for the third time, the 4 th, 12 th and 13 th columns of chips are tested for the fourth time, the 5 th, 14 th and 15 th columns of chips are tested for the fifth time, the 10 th to-15 th columns of chips to be tested are skipped for the sixth time, the 16 th, 21 th and 22 th columns of chips are tested, and the like.
8. The chip testing method of claim 5, comprising:
if 2 rows of chips to be tested are tested simultaneously each time, the first probe area, the third probe area, or the first probe area, the fourth probe area, or the second probe area, the third probe area, or the second probe area and the fourth probe area are used for testing, the jump testing mode is that m times of chips to be tested are tested continuously, N rows of chips to be tested are skipped after 2 rows of chips are tested each time, and then the test is carried out, wherein m = N +1, N = m;
the bridging distance between the second probe area and the third probe area is the width of 4 chips, 2 rows of chips are tested at the same time each time, the 1 st and 6 th rows of chips are tested for the first time, the 2 nd and 7 th rows of chips are tested for the second time, the 3 rd and 8 th rows of chips are tested for the third time, the 4 th and 9 th rows of chips are tested for the fourth time, the 5 th and 10 th rows of chips are tested for the fifth time, the 5 th rows of chips to be tested, namely the 6 th to 10 th rows, are tested for the sixth time, the 11 th and 16 th rows of chips are tested, and the like.
9. A testing machine comprising a memory, a processor and a computer program stored in said memory and executable on said processor, characterized in that said processor implements the steps of the chip testing method according to any one of claims 5 to 8 when executing said computer program.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the chip testing method according to one of claims 5 to 8.
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| CN118131017A (en) * | 2024-03-28 | 2024-06-04 | 芯测通(深圳)半导体有限公司 | Wafer testing method and wafer needle testing equipment |
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