CN115733123A - Overcurrent protection circuit of power tube - Google Patents

Abstract

The invention relates to the field of electronic circuits, in particular to an overcurrent protection circuit of a power tube. The overcurrent protection circuit of the power tube comprises a control circuit, a power drive circuit and an overcurrent judgment circuit; the power driving circuit comprises a plurality of power tubes to be subjected to overcurrent protection, and converts current signals flowing through the plurality of power tubes to be subjected to overcurrent protection into voltage signals; the overcurrent judgment circuit comprises a plurality of logic devices, and the plurality of logic devices judge whether the current signals corresponding to the voltage signals are overcurrent or not and generate overcurrent judgment signals after carrying out logic processing on the voltage signals; the control circuit generates a power tube on-off signal through the overcurrent judgment signal to control the on-off of a plurality of power tubes to be subjected to overcurrent protection in the power driving circuit. The invention adopts the logic device to realize overcurrent protection, and solves the problems that the current flowing through the power tube is greater than the SOA current for a long time to cause the damage of the power tube and the large static current is needed to cause the large static power consumption of the circuit.

Description

Overcurrent protection circuit of power tube

Technical Field

The invention relates to the field of electronic circuits, in particular to an overcurrent protection circuit of a power tube.

Background

In the field of current electronic circuits, metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or Insulated Gate Bipolar Transistors (IGBTs) are often used to serve as power tube driven loads. For example, if the MOSFET is operated in a non-safety operation area, the MOSFET may be burned out, so that the load may not operate normally. Therefore, the normal operation of the power tube is the key of the normal driving of the load. The Safe working area of the power tube is called SOA (Safe operating area), and the SOA curve defines the current, voltage and time of the power tube capable of safely working for a long time; if the power tube works above the SOA, phenomena such as overheating and burnout can occur, so that overcurrent protection is generally performed on the power tube to avoid overheating and burnout caused by overcurrent.

The overcurrent protection of the power tube is to control the power tube to be disconnected after detecting the overcurrent of the power tube so as to prevent the power tube from exceeding the SOA working area. The traditional overcurrent protection scheme is that a current signal flowing through a power tube is sampled by a resistor and then converted into a voltage signal, and then the voltage signal is compared with a reference voltage to output an overcurrent protection signal. The conventional method of comparing the voltage signal with a reference voltage is implemented based on the judgment of a comparator, but the circuit structure of the judgment of the comparator is relatively complex and high in cost; meanwhile, because the comparator has power consumption limitation and parasitic capacitance, the judgment delay of the comparator is large, so that the power tube cannot be closed in time under an overcurrent state, and damage is caused. In order to make the decision delay of the comparator as small as possible, the comparator is often designed to be complex, or needs a very large quiescent current, which causes the quiescent power consumption of the power transistor to become large.

Disclosure of Invention

The invention aims to provide an overcurrent protection circuit of a power tube, which can quickly turn off the power tube when the power tube is in overcurrent, and has the advantages of simple circuit and lower cost.

The technical scheme for solving the technical problems is as follows: an overcurrent protection circuit of a power tube comprises a control circuit, a power drive circuit and an overcurrent judgment circuit;

the power driving circuit is used for driving a load, comprises a plurality of power tubes to be subjected to overcurrent protection, and is used for converting current signals flowing through the plurality of power tubes to be subjected to overcurrent protection into voltage signals;

the overcurrent judgment circuit is electrically connected with the power drive circuit and comprises a plurality of logic devices, and the plurality of logic devices judge whether the current signal corresponding to the voltage signal is overcurrent or not after performing logic processing on the voltage signal and generate an overcurrent judgment signal;

the control circuit is respectively electrically connected with the overcurrent judgment circuit and the power drive circuit, and the control circuit generates a power tube on-off signal through the overcurrent judgment signal so as to control the on-off of the power tubes to be subjected to overcurrent protection in the power drive circuit.

On the basis of the technical scheme, the invention can be further improved as follows.

Further, the power transistor is specifically a metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor.

Further, the circuit also comprises a clamping protection circuit; the overcurrent judgment circuit is electrically connected with the power driving circuit through the clamping protection circuit;

the clamping protection circuit is used for clamping the voltage signal to generate a clamping processing voltage signal;

after the plurality of logic devices in the overcurrent judgment circuit perform logic processing on the clamp processing voltage signal, judging whether the current signal corresponding to the clamp processing voltage signal is overcurrent or not, and generating an overcurrent judgment signal.

Further, the power tubes to be subjected to overcurrent protection comprise a first P-type power tube, a second P-type power tube, a first N-type power tube and a second N-type power tube; the grid electrode of the first P-type power tube, the grid electrode of the second P-type power tube, the grid electrode of the first N-type power tube and the grid electrode of the second N-type power tube are all used for accessing the power tube on-off signals output by the control circuit; the source electrode of the first P-type power tube and the source electrode of the second P-type power tube are both used for accessing a first level, and the source electrode of the first N-type power tube and the source electrode of the second N-type power tube are both grounded; the drain electrode of the first P-type power tube is connected with the drain electrode of the first N-type power tube, and the drain electrode of the second P-type power tube is connected with the drain electrode of the second N-type power tube; a node between the drain electrode of the first P-type power tube and the drain electrode of the first N-type power tube and a node between the drain electrode of the second P-type power tube and the drain electrode of the second N-type power tube are both outputs of the power driving circuit and are respectively connected to two ends of a load; and the node between the drain electrode of the first P-type power tube and the drain electrode of the first N-type power tube and the node between the drain electrode of the second P-type power tube and the drain electrode of the second N-type power tube are also used for outputting the voltage signal to the clamping protection circuit.

Further, the clamp protection circuit comprises a first P-type clamp protection tube, a second P-type clamp protection tube, a first N-type clamp protection tube and a second N-type clamp protection tube; a grid electrode of the first P-type clamp protection tube and a grid electrode of the second P-type clamp protection tube are used for being connected to a second level, the grid electrode of the first N-type clamp protection tube is connected to the grid electrode of the first N-type power tube, the grid electrode of the second N-type clamp protection tube is connected to the grid electrode of the second N-type power tube, a source electrode of the first P-type clamp protection tube and a drain electrode of the first N-type clamp protection tube are connected to a node between a drain electrode of the first P-type power tube and a drain electrode of the first N-type power tube, and a source electrode of the second P-type clamp protection tube and a drain electrode of the second N-type clamp protection tube are connected to a node between a drain electrode of the second P-type power tube and a drain electrode of the second N-type power tube; and the drain electrode of the first P-type clamp protection tube, the drain electrode of the second P-type clamp protection tube, the source electrode of the first N-type clamp protection tube and the source electrode of the second N-type clamp protection tube are all outputs of the clamp protection circuit and are used for outputting the clamp processing voltage signal to the overcurrent judgment circuit.

Further, the plurality of logic devices includes a first inverter, a second inverter, a first buffer, and a second buffer; the input end of the first phase inverter is connected to the drain electrode of the first P-type clamp protection tube, the input end of the second phase inverter is connected to the drain electrode of the second P-type clamp protection tube, the input end of the first buffer is connected to the source electrode of the first N-type clamp protection tube, and the input end of the second buffer is connected to the source electrode of the second N-type clamp protection tube; the output end of the first phase inverter, the output end of the second phase inverter, the output end of the first buffer and the output end of the second buffer are all outputs of the overcurrent judgment circuit and are used for outputting the overcurrent judgment signal to the control circuit.

Further, the control circuit comprises a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a first nor gate, a second nor gate, a third nor gate and a fourth nor gate; the input end of the first NOR gate is connected to the output end of the first phase inverter, the output end of the first NOR gate is connected to the input end of the third phase inverter, and the output end of the third phase inverter is connected to the grid electrode of the first P-type power tube; the input end of the third nor gate is connected to the output end of the second inverter, the output end of the third nor gate is connected to the input end of the fifth inverter, and the output end of the fifth inverter is connected to the grid electrode of the second P-type power tube; the input end of the second nor gate is connected to the output end of the first buffer, the output end of the second nor gate is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the grid electrode of the first N-type power tube; the input end of the fourth nor gate is connected to the output end of the second buffer, the output end of the fourth nor gate is connected to the input end of the sixth inverter, and the output end of the sixth inverter is connected to the gate of the second N-type power tube; and the output end of the third phase inverter, the output end of the fourth phase inverter, the output end of the fifth phase inverter and the output end of the sixth phase inverter are all output of the control circuit and are used for outputting the on-off signal of the power tube to the power driving circuit.

Further, an input end of the first nor gate is further configured to input a first external signal, where the first external signal is specifically a switch control signal of the first P-type power transistor; the input end of the second nor gate is further used for inputting a second external signal, and the second external signal is specifically a switch control signal of the first N-type power tube; the input end of the third nor gate is further configured to input a third external signal, where the third external signal is specifically a switch control signal of a second P-type power transistor; the input end of the fourth nor gate is further configured to input a fourth external signal, where the fourth external signal is specifically a switch control signal of the second N-type power transistor.

Further, power terminals of the first inverter, the second inverter, the third inverter and the fifth inverter are all connected to the first level, and ground terminals of the first inverter, the second inverter, the third inverter and the fifth inverter are all connected to the second level; the power supply terminals of the first buffer, the second buffer, the fourth inverter and the sixth inverter are all connected to a third level, and the ground terminals of the first buffer, the second buffer, the fourth inverter and the sixth inverter are all grounded.

Further, the first level is a high voltage power supply level, the second level is a high voltage power supply level and is lower than the first level by 5V, and the third level is a 5V level.

The invention has the beneficial effects that: the overcurrent protection circuit of the power tube provided by the invention is a circuit which does not realize overcurrent protection through a comparator, and adopts a logic device to realize overcurrent protection; the response speed of the comparator is in the order of hundred nanoseconds, and the response speed of the logic device is generally in the order of nanoseconds, so that the response speed of realizing overcurrent protection through the logic circuit is far faster than that of the comparator in the related technology, and the problem that the power tube is damaged because the current flowing through the power tube is longer than the SOA current for a long time is solved; in addition, the overcurrent protection circuit based on the logic device has simple structure, does not consume static current, ensures the low-power-consumption design of the circuit, and solves the problem that the complex comparator circuit needs larger static current to cause larger static power consumption of the circuit.

Drawings

Fig. 1 is a block diagram of an overcurrent protection circuit of a power transistor according to the present invention;

fig. 2 is another structural block diagram of an overcurrent protection circuit of a power tube according to the present invention;

FIG. 3 is a schematic circuit diagram of an overcurrent protection circuit of a power transistor according to the present invention;

FIG. 4 is a timing diagram of signals when the power driving circuit is not over-current protected;

fig. 5 is a timing diagram of signals when overcurrent protection occurs in the power driving circuit.

Detailed Description

The principles and features of this invention are described below in conjunction with the following drawings, which are set forth to illustrate, but are not to be construed to limit the scope of the invention.

As shown in fig. 1, an overcurrent protection circuit of a power tube includes a control circuit 101, a power driving circuit 102, and an overcurrent decision circuit 104;

the power driving circuit 102 is used for driving a load RL, comprises a plurality of power tubes to be subjected to overcurrent protection, and is used for converting current signals flowing through the plurality of power tubes to be subjected to overcurrent protection into voltage signals;

the overcurrent judgment circuit 104 is electrically connected to the power driving circuit 102, and includes a plurality of logic devices, and the plurality of logic devices perform logic processing on the voltage signal, and then judge whether the current signal corresponding to the voltage signal is overcurrent, and generate an overcurrent judgment signal;

the control circuit 101 is electrically connected to the over-current decision circuit 104 and the power driving circuit 102, respectively, and the control circuit 101 generates a power tube on-off signal through the over-current decision signal to control on-off of the power tubes to be over-current protected in the power driving circuit 102.

In the invention, when the power driving circuit 102 adopts the power tube to drive the load RL to operate, the power tube has current flowing through, and because the on-resistance of the power tube exists, the current signal flowing through the power tube can be converted into a voltage signal; the overcurrent decision circuit 104 performs logic processing on the voltage signal generated by the power driving circuit 102 by using a logic device, so as to generate an overcurrent decision signal for indicating whether the current signal corresponding to the voltage signal is overcurrent; when the current signal flowing through the power transistor is overcurrent, the control circuit 101 controls the power transistor in the power driving circuit 102 to be rapidly turned off according to the overcurrent determination signal, thereby stopping the driving of the load RL by the power driving circuit 102. Because the overcurrent protection circuit of the power tube does not adopt the comparator to carry out overcurrent judgment, but adopts the logic device to directly output the overcurrent judgment signal to control the on-off of the power tube, and the response speed of the logic device is far higher than that of the comparator, the overcurrent protection circuit of the power tube can avoid the problem of damage caused by that the current flowing through the power tube is longer than the SOA current and is not turned off in time. In addition, the invention adopts a logic device to realize overcurrent protection, has simple circuit structure, does not consume quiescent current, and ensures the low-power-consumption design of the circuit.

In this particular embodiment: the power tube is a metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor. Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or Insulated Gate Bipolar Transistors (IGBTs) are often used to act as power tube drive loads.

In this particular embodiment: the overcurrent protection circuit of the power tube of the invention further comprises a clamping protection circuit 103. Specifically, as shown in fig. 2, the over-current decision circuit 104 is electrically connected to the power driving circuit 102 through the clamp protection circuit 103; the clamp protection circuit 103 is configured to clamp the voltage signal to generate a clamp processing voltage signal; the plurality of logic devices in the overcurrent judgment circuit 104 specifically perform logic processing on the clamp processing voltage signal, and then judge whether the current signal corresponding to the clamp processing voltage signal is overcurrent, and generate an overcurrent judgment signal.

With reference to fig. 2, the overcurrent protection circuit of the power transistor of the present invention has the following working processes:

the power driving circuit 102 drives a load through the power tubes to be subjected to overcurrent protection, converts current signals flowing through the power tubes to be subjected to overcurrent protection into voltage signals, and outputs the voltage signals to the clamping protection circuit 103;

the clamp protection circuit 103 clamps the voltage signal output by the power driving circuit 102, generates a clamp processing voltage signal for protecting the over-current decision circuit 104, and outputs the clamp processing voltage signal to the over-current decision circuit 104;

the overcurrent decision circuit 104 performs logic processing on the clamp processing voltage signal output by the clamp protection circuit 103 through the plurality of logic devices to generate an overcurrent decision signal and outputs the overcurrent decision signal to the control circuit 101;

the control circuit 101 generates a power tube on-off signal through the overcurrent decision signal to control the on-off of the plurality of power tubes to be subjected to overcurrent protection in the power driving circuit 102.

In the invention, the clamping processing circuit 103 is used for protecting the overcurrent judging circuit 104, and protecting the logic devices in the overcurrent judging circuit 104 from being burnt out, thereby improving the working stability of the circuit of the invention.

In this particular embodiment: as shown in fig. 3, the power transistors to be subjected to overcurrent protection in the power driving circuit 102 include a first P-type power transistor H1, a second P-type power transistor H2, a first N-type power transistor L1, and a second N-type power transistor L2; the grid electrode of the first P-type power tube H1, the grid electrode of the second P-type power tube H2, the grid electrode of the first N-type power tube L1 and the grid electrode of the second N-type power tube L2 are all used for accessing the power tube on-off signal output by the control circuit 101; the source electrode of the first P-type power tube H1 and the source electrode of the second P-type power tube H2 are both used for being connected to a first level VM, and the source electrode of the first N-type power tube L1 and the source electrode of the second N-type power tube L2 are both grounded; the drain electrode of the first P-type power tube H1 is connected with the drain electrode of the first N-type power tube L1, and the drain electrode of the second P-type power tube H2 is connected with the drain electrode of the second N-type power tube L2; a node between the drain of the first P-type power tube H1 and the drain of the first N-type power tube L1 and a node between the drain of the second P-type power tube H2 and the drain of the second N-type power tube L2 are both outputs of the power driving circuit 102 and are respectively connected to two ends of a load RL; the node between the drain of the first P-type power transistor H1 and the drain of the first N-type power transistor L1 and the node between the drain of the second P-type power transistor H2 and the drain of the second N-type power transistor L2 are further configured to output the voltage signal to the clamp protection circuit 103.

In particular, the load RL is in particular an inductive load, such as an electric motor.

Specifically, in the power driving circuit 102, when the gate of the first P-type power transistor H1 receives the power transistor on-off signal GH1 from the control circuit 101 and is at a high level, the first P-type power transistor H1 is turned off, and no current flows through the first P-type power transistor H1; when the first P-type power tube H1 is turned on and if the current flowing through the first P-type power tube H1 is greater than the preset current value, because the on-resistance of the first P-type power tube H1 exists and the voltage drop of the on-resistance is large, the voltage of the drain of the first P-type power tube H1 is at a low level, that is, a node OUT1 between the drain of the first P-type power tube H1 and the drain of the first N-type power tube L1 generates a low-level signal, and the low-level signal generated by the node OUT1 is output to the clamp protection circuit 103.

The working process of the second P-type power tube H2 is the same as that of the first P-type power tube H1.

The working process of the first N-type power tube L1 is the same as that of the second N-type power tube L2, and is similar to that of the first P-type power tube H1, except that the turn-off levels of the first N-type power tube L1 and the second N-type power tube L2 are opposite to that of the first P-type power tube H1.

The first P-type power tube H1 is conducted under the condition that the grid voltage is lower than the source voltage by V _thp Or V _thp The above; v _thp The on-voltage threshold of the first P-type power transistor H1 is also usually about 1 to 2V. When the GH1 is at a high level, the first P-type power tube H1 is turned off; when the GH1 is at a low level, the first P-type power transistor H1 can be fully turned on.

The first N-type power tube L1 is conducted under the condition that the grid voltage is higher than the source voltage by V _thn Or V _thn The above; v _thn The on-voltage threshold of the first N-type power transistor L1 is usually about 1 to 2V. When the GL1 is at a high level, the first N-type power transistor L1 may be completely turned on; when GL1 is low, the first N-type power transistor L1 is turned off.

When the power driving circuit 102 has no overcurrent, the first P-type power tube H1 and the second N-type power tube L2 are turned on at the same time or the second P-type power tube H2 and the first N-type power tube L1 are turned on at the same time; the first P-type power transistor H1 and the first N-type power transistor L1 are not allowed to be turned on simultaneously or the second P-type power transistor H2 and the second N-type power transistor L2 are not allowed to be turned on simultaneously.

In the invention, a first P-type power tube H1, a second P-type power tube H2, a first N-type power tube L1 and a second N-type power tube L2 form an H-type full-bridge driving circuit. The intermediate load RL is the load to be driven, and is typically an inductive motor. The function of such a circuit is to drive the motor in rotation. In one state, the first P-type power tube H1 and the second N-type power tube L2 are turned on simultaneously, the second P-type power tube H2 and the first N-type power tube L1 are turned off simultaneously, and the current flows from the first level VM to GND through the first P-type power tube H1, the load RL and the second N-type power tube L2 in sequence. In the next state, the first P-type power tube H1 and the second N-type power tube L2 are turned off at the same time, the second P-type power tube H2 and the first N-type power tube L1 are turned on at the same time, and the current flows from the first level VM to GND through the second P-type power tube H2, the load RL and the first N-type power tube L1 in sequence. The power driving circuit 102 is usually used to alternately drive the motor in the above two states. The time for the first P-type power tube H1 and the second N-type power tube L2 to be conducted simultaneously is longer, or the time for the second P-type power tube H2 and the first N-type power tube L1 to be conducted simultaneously is longer, so that the direction of the current in the load RL and the magnitude of the average current are determined; the frequency of the alternation determines the magnitude of the current ripple.

In this particular embodiment: as shown in fig. 3, the clamp protection circuit 103 includes a first P-type clamp protection tube PM1, a second P-type clamp protection tube PM2, a first N-type clamp protection tube NM1, and a second N-type clamp protection tube NM2; a grid electrode of the first P-type clamp protection tube PM1 and a grid electrode of the second P-type clamp protection tube PM2 are both used for being connected to a second level VM-5, a grid electrode of the first N-type clamp protection tube NM1 is connected to a grid electrode of the first N-type power tube L1, a grid electrode of the second N-type clamp protection tube NM2 is connected to a grid electrode of the second N-type power tube L2, a source electrode of the first P-type clamp protection tube PM1 and a drain electrode of the first N-type clamp protection tube NM1 are both connected to a node between a drain electrode of the first P-type power tube H1 and a drain electrode of the first N-type power tube L1, and a source electrode of the second P-type clamp protection tube PM2 and a drain electrode of the second N-type clamp protection tube NM2 are both connected to a node between a drain electrode of the second P-type power tube H2 and a drain electrode of the second N-type power tube L2; the drain of the first P-type clamp protection tube PM1, the drain of the second P-type clamp protection tube PM2, the source of the first N-type clamp protection tube NM1, and the source of the second N-type clamp protection tube NM2 are all outputs of the clamp protection circuit 103, and are configured to output the clamp processing voltage signal to the overcurrent decision circuit 104.

Specifically, in the clamp protection circuit 103, the four clamp protection tubes (the first P-type clamp protection tube PM1, the second P-type clamp protection tube PM2, the first N-type clamp protection tube NM1, and the second N-type clamp protection tube NM 2) have the same operation procedure, and the operation procedure of the first P-type clamp protection tube PM1 will be described below by taking the first P-type clamp protection tube PM1 as an example:

when the source electrode of the first P-type clamp protection tube PM1 receives a high level output from the power driving circuit 102, the first P-type clamp protection tube PM1 outputs a high level to the overcurrent judging circuit 104 at the same time at the drain electrode, and meanwhile, the first P-type clamp protection tube PM1 protects the overcurrent judging circuit 104 from working in a safe area; when the source of the first P-type clamp protection tube PM1 receives the low level output from the power driving circuit 102, the first P-type clamp protection tube PM1 outputs a low level to the overcurrent decision circuit 104 at the same time at the drain, and the first P-type clamp protection tube PM1 protects the overcurrent decision circuit 104 from working in a safe area.

In this particular embodiment: as shown in fig. 3, the plurality of logic devices in the over-current decision circuit 104 include a first inverter INV1, a second inverter INV2, a first buffer BUF1, and a second buffer BUF2; the input end of the first inverter INV1 is connected to the drain electrode of the first P-type clamp protection tube PM1, the input end of the second inverter INV2 is connected to the drain electrode of the second P-type clamp protection tube PM2, the input end of the first buffer BUF1 is connected to the source electrode of the first N-type clamp protection tube NM1, and the input end of the second buffer BUF2 is connected to the source electrode of the second N-type clamp protection tube NM2; the output end of the first inverter INV1, the output end of the second inverter INV2, the output end of the first buffer BUF1, and the output end of the second buffer BUF2 are all outputs of the over-current decision circuit 104, and are used for outputting the over-current decision signal to the control circuit 101.

Specifically, in the over-current decision circuit 104, the working process of the first inverter INV1 is the same as that of the second inverter INV2, and the working process of the first inverter INV1 is described below by taking the first inverter INV1 as an example: when the input end of the first inverter INV1 receives the low level output from the clamp protection circuit 103, the inverter INV1 outputs a high level, and the over-current decision circuit 104 outputs the high level to the control circuit 101; when the input end of the first inverter INV1 receives the high level output from the clamp protection circuit 103, the inverter INV1 outputs a low level, and the over-current decision circuit 104 outputs the low level to the control circuit 101.

Specifically, in the over-current determining circuit 104, the working process of the first buffer BUF1 is the same as the working process of the second buffer BUF2, and the working process of the first buffer BUF1 is described below by taking the first buffer BUF1 as an example: when the input end of the first buffer BUF1 receives the low level output from the clamp protection circuit 103, the first buffer BUF1 outputs the low level, and the overcurrent judgment circuit 104 outputs the low level to the control circuit 101; when the input terminal of the first buffer BUF1 receives the high level output from the clamp protection circuit 103, the first buffer BUF1 outputs the high level, and the over-current decision circuit 104 outputs the high level to the control circuit 101.

In this particular embodiment: as shown in fig. 3, the control circuit 101 includes a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a first NOR gate NOR1, a second NOR gate NOR2, a third NOR gate NOR3, and a fourth NOR gate NOR4; the input end of the first NOR gate NOR1 is connected to the output end of the first inverter INV1, the output end of the first NOR gate NOR1 is connected to the input end of the third inverter INV3, and the output end of the third inverter INV3 is connected to the gate of the first P-type power tube H1; the input end of the third NOR gate NOR3 is connected to the output end of the second inverter INV2, the output end of the third NOR gate NOR3 is connected to the input end of the fifth inverter INV5, and the output end of the fifth inverter INV5 is connected to the gate of the second P-type power tube H2; the input end of the second NOR gate NOR2 is connected to the output end of the first buffer BUF1, the output end of the second NOR gate NOR2 is connected to the input end of the fourth inverter INV4, and the output end of the fourth inverter INV4 is connected to the gate of the first N-type power tube L1; an input end of the fourth NOR gate NOR4 is connected to an output end of the second buffer BUF2, an output end of the fourth NOR gate NOR2 is connected to an input end of the sixth inverter INV6, and an output end of the sixth inverter INV6 is connected to a gate of the second N-type power transistor L2; the output end of the third inverter INV3, the output end of the fourth inverter INV4, the output end of the fifth inverter INV5, and the output end of the sixth inverter INV6 are all outputs of the control circuit 101, and are configured to output the power transistor on-off signal to the power driving circuit 102. The input end of the first NOR gate NOR1 is further configured to input a first external signal INH1, where the first external signal INH1 is a switch control signal of the first P-type power transistor H1; the input end of the second NOR gate NOR2 is further configured to input a second external signal INL1, where the second external signal INL1 is specifically a switch control signal of the first N-type power transistor L1; the input end of the third NOR gate NOR3 is further configured to input a third external signal INH2, where the third external signal INH2 is a switch control signal of the second P-type power transistor H2; the input end of the fourth NOR gate NOR4 is further configured to input a fourth external signal INL2, where the fourth external signal INL2 is specifically a switch control signal of the second N-type power transistor L2.

Specifically, in the control circuit 101, the first NOR gate NOR1 and the third inverter INV3 form a path of control circuit, the second NOR gate NOR2 and the fourth inverter INV4 form a path of control circuit, the third NOR gate NOR3 and the fifth inverter INV5 form a path of control circuit, and the fourth NOR gate NOR4 and the sixth inverter INV6 form a path of control circuit; the first NOR gate NOR1 and the third inverter INV3 are exemplified as follows: when the input terminal OCP _ H1 of the first NOR gate NOR1 is at a high level, the first NOR gate NOR1 outputs a low level to the third inverter INV3; at this time, the third inverter INV3 outputs a shutdown signal of high level to the power driving circuit 102.

Specifically, the first P-type power tube H1, the second P-type power tube H2, the first N-type power tube L1, and the second N-type power tube L2 form an H-type full bridge driving circuit. The intermediate load RL is the load to be driven, typically an inductive motor. The function of such a circuit is to drive the motor in rotation. In one state, the first P-type power tube H1 and the second N-type power tube L2 are turned on simultaneously, the second P-type power tube H2 and the first N-type power tube L1 are turned off simultaneously, and the current flows from the first level VM to GND through the first P-type power tube H1, the load RL and the second N-type power tube L2 in sequence. In the next state, the first P-type power tube H1 and the second N-type power tube L2 are turned off at the same time, the second P-type power tube H2 and the first N-type power tube L1 are turned on at the same time, and the current flows from the first level VM to GND through the second P-type power tube H2, the load RL and the first N-type power tube L1 in sequence. The power driver circuit 102 typically alternates between these two states to drive the motor. Under the condition that the power tubes of the power driving circuit 102 do not have overcurrent, if the motor needs to be normally driven to operate, two pairs of power tubes need to be controlled to be alternately switched on and off; then, the first external signal INH1, the second external signal INL1, the third external signal INH2 and the fourth external signal INL2 are respectivelyIs the switching control signal for these four power transistors, which is typically a square wave signal. For example: the second NOR gate NOR2 and the fourth inverter INV4 are driving and controlling circuits of the first N-type power transistor L1; the first external signal INL1 is an input control signal, when the input level of the first external signal INL1 is high VDD, the voltage at the GL1 node is also high, and the difference between the gate-source voltages of the first N-type power transistor L1 is larger than V _thn Much higher, for example 5V, the first N-type power transistor L1 can be fully turned on.

In this particular embodiment: the power supply ends of the first inverter INV1, the second inverter INV2, the third inverter INV3 and the fifth inverter INV5 are all connected to the first level VM, and the ground ends of the first inverter INV1, the second inverter INV2, the third inverter INV3 and the fifth inverter INV5 are all connected to the second level VM-5; the power supply ends of the first buffer BUF1, the second buffer BUF2, the fourth inverter INV4 and the sixth inverter INV6 are all connected with a third level VDD, and the grounding ends of the first buffer BUF1, the second buffer BUF2, the fourth inverter INV4 and the sixth inverter INV6 are all grounded. Preferably, the first level VM is a high voltage power supply level, the second level VM-5 is a high voltage power supply level and is lower than the first level VM by 5V, and the third level VDD is a 5V level.

Specifically, VDD generally refers to a 5V level, and GND is ground. VM is a high voltage power supply, and VM-5 is generated by another voltage conversion module, and is 5V lower than VM. VM-5 is exactly ground with respect to the VM. If the grounding ends of the first inverter INV1, the second inverter INV2, the third inverter INV3 and the fifth inverter INV5 are directly grounded instead of VM-5, devices capable of bearing the voltage of VM are required between the gate and the source of the first P-type power tube H1, the second P-type power tube H2, the first P-type clamp protection tube PM1 and the second P-type clamp protection tube PM2, and the process requirement is high, and even the implementation is difficult. However, if only 5V needs to be borne (the difference between the first level VM and the second level VM-5 is 5V), the process requirement is much lower, and the applicability is greatly improved.

Fig. 4 is a timing diagram of signals when the power driving circuit 102 is not overcurrent protected. Referring to fig. 4, the process protection process will be described by taking the first P-type power transistor H1, the first P-type clamp protection tube PM1, the first inverter INV1, the first NOR gate NOR1, and the third inverter INV3 as an example: when the current I _ H1 flowing through the first P-type power tube H1 does not exceed the preset current Vth _ OCP _ H1, the node OUT1 is always at a high level, after receiving a high level signal output by the node OUT1, the first P-type clamp protection tube PM1 outputs a high level to the first inverter INV1, the output OCP _ H1 of the first inverter INV1 is set to a low level, at this time, the first NOR gate NOR1 and the third inverter INV3 work normally, and the power tube H1 is turned on or off normally.

Fig. 5 is a timing diagram of signals of the power driving circuit 102 when overcurrent protection occurs. Referring to fig. 5, a process of protecting the process is described by taking the first P-type power transistor H1, the first P-type clamp protection tube PM1, the first inverter INV1, the first NOR gate NOR1, and the third inverter INV3 as an example: when the current I _ H1 flowing through the first P-type power tube H1 exceeds the preset current Vth _ OCP _ H1, the node OUT1 is always at a low level, the first P-type clamp protection tube PM1 outputs the low level to the first inverter INV1 after receiving the low level signal output by the node OUT1, the output OCP _ H1 of the first inverter INV1 is set to a high level, at this time, the first NOR gate NOR1 outputs the low level, and then the third inverter INV3 outputs the power tube on-off signal at the high level, so that the first P-type power tube H1 is turned off.

The overcurrent protection circuit of the power tube provided by the invention is an overcurrent protection circuit which does not realize overcurrent protection through a comparator, and adopts a logic device to realize overcurrent protection; the response speed of the comparator is in the order of hundred nanoseconds, and the response speed of the logic device is generally in the order of nanoseconds, so that the response speed of realizing overcurrent protection by using the logic circuit is far faster than that of the comparator, and the problem that the power tube is damaged because the current flowing through the power tube is larger than the SOA current for a long time is solved; in addition, the overcurrent protection circuit based on the logic device has simple structure, does not consume static current, ensures the low-power-consumption design of the circuit, and solves the problem that the complex comparator circuit needs larger static current to cause larger static power consumption of the circuit.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the scope of the present invention, which is intended to cover any modifications, equivalents, improvements, etc. within the spirit and scope of the present invention.

Claims (10)

1. The utility model provides an overcurrent protection circuit of power tube which characterized in that: the power supply comprises a control circuit (101), a power driving circuit (102) and an over-current judgment circuit (104);

the power driving circuit (102) is used for driving a load (RL), comprises a plurality of power tubes to be subjected to overcurrent protection, and is used for converting current signals flowing through the plurality of power tubes to be subjected to overcurrent protection into voltage signals;

the overcurrent judgment circuit (104) is electrically connected with the power drive circuit (102) and comprises a plurality of logic devices, and the logic devices judge whether the current signal corresponding to the voltage signal is overcurrent or not after performing logic processing on the voltage signal and generate an overcurrent judgment signal;

the control circuit (101) is electrically connected with the overcurrent judgment circuit (104) and the power driving circuit (102) respectively, and the control circuit (101) generates a power tube on-off signal through the overcurrent judgment signal so as to control the on-off of the power tubes to be subjected to overcurrent protection in the power driving circuit (102).

2. The overcurrent protection circuit of the power tube according to claim 1, wherein: the power tube is a metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor.

3. The overcurrent protection circuit of the power tube according to claim 1 or2, further comprising a clamp protection circuit (103); the overcurrent judgment circuit (104) is electrically connected with the power drive circuit (102) through the clamping protection circuit (103);

the clamping protection circuit (103) is used for clamping the voltage signal to generate a clamping processing voltage signal;

after the plurality of logic devices in the overcurrent judgment circuit (104) perform logic processing on the clamp processing voltage signal, whether the current signal corresponding to the clamp processing voltage signal is overcurrent or not is judged, and the overcurrent judgment signal is generated.

4. The overcurrent protection circuit of a power tube according to claim 3, wherein: the power tubes to be subjected to overcurrent protection comprise a first P-type power tube (H1), a second P-type power tube (H2), a first N-type power tube (L1) and a second N-type power tube (L2); the grid electrode of the first P-type power tube (H1), the grid electrode of the second P-type power tube (H2), the grid electrode of the first N-type power tube (L1) and the grid electrode of the second N-type power tube (L2) are all used for being connected to the power tube on-off signal output by the control circuit (101); the source electrode of the first P-type power tube (H1) and the source electrode of the second P-type power tube (H2) are used for being connected to a first level (VM), and the source electrode of the first N-type power tube (L1) and the source electrode of the second N-type power tube (L2) are grounded; the drain electrode of the first P-type power tube (H1) is connected with the drain electrode of the first N-type power tube (L1), and the drain electrode of the second P-type power tube (H2) is connected with the drain electrode of the second N-type power tube (L2); a node between the drain electrode of the first P-type power tube (H1) and the drain electrode of the first N-type power tube (L1) and a node between the drain electrode of the second P-type power tube (H2) and the drain electrode of the second N-type power tube (L2) are both outputs of the power driving circuit (102) and are respectively connected to two ends of a load (RL); the node between the drain of the first P-type power tube (H1) and the drain of the first N-type power tube (L1) and the node between the drain of the second P-type power tube (H2) and the drain of the second N-type power tube (L2) are further configured to output the voltage signal to the clamp protection circuit (103).

5. The overcurrent protection circuit of the power transistor according to claim 4, wherein: the clamp protection circuit (103) comprises a first P-type clamp protection tube (PM 1), a second P-type clamp protection tube (PM 2), a first N-type clamp protection tube (NM 1) and a second N-type clamp protection tube (NM 2); a grid electrode of the first P-type clamp protection tube (PM 1) and a grid electrode of the second P-type clamp protection tube (PM 2) are used for being connected to a second level (VM-5), a grid electrode of the first N-type clamp protection tube (NM 1) is connected to a grid electrode of the first N-type power tube (L1), a grid electrode of the second N-type clamp protection tube (NM 2) is connected to a grid electrode of the second N-type power tube (L2), a source electrode of the first P-type clamp protection tube (PM 1) and a drain electrode of the first N-type clamp protection tube (NM 1) are connected to a node between a drain electrode of the first P-type power tube (H1) and a drain electrode of the first N-type power tube (L1), and a source electrode of the second P-type clamp protection tube (PM 2) and a drain electrode of the second N-type clamp protection tube (NM 2) are connected to a node between a drain electrode of the second P-type power tube (H2) and a drain electrode of the second N-type power tube (L2); the drain electrode of the first P-type clamp protection tube (PM 1), the drain electrode of the second P-type clamp protection tube (PM 2), the source electrode of the first N-type clamp protection tube (NM 1) and the source electrode of the second N-type clamp protection tube (NM 2) are all outputs of the clamp protection circuit (103) and are used for outputting the clamp processing voltage signal to the overcurrent judgment circuit (104).

6. The overcurrent protection circuit of a power tube according to claim 5, wherein: the plurality of logic devices include a first inverter (INV 1), a second inverter (INV 2), a first buffer (BUF 1), and a second buffer (BUF 2); the input end of the first inverter (INV 1) is connected to the drain electrode of the first P-type clamp protection tube (PM 1), the input end of the second inverter (INV 2) is connected to the drain electrode of the second P-type clamp protection tube (PM 2), the input end of the first buffer (BUF 1) is connected to the source electrode of the first N-type clamp protection tube (NM 1), and the input end of the second buffer (BUF 2) is connected to the source electrode of the second N-type clamp protection tube (NM 2); the output end of the first inverter (INV 1), the output end of the second inverter (INV 2), the output end of the first buffer (BUF 1) and the output end of the second buffer (BUF 2) are all outputs of the over-current judgment circuit (104), and are used for outputting the over-current judgment signal to the control circuit (101).

7. The overcurrent protection circuit of a power tube according to claim 6, wherein: the control circuit (101) comprises a third inverter (INV 3), a fourth inverter (INV 4), a fifth inverter (INV 5), a sixth inverter (INV 6), a first NOR gate (NOR 1), a second NOR gate (NOR 2), a third NOR gate (NOR 3) and a fourth NOR gate (NOR 4); the input end of the first NOR gate (NOR 1) is connected to the output end of the first inverter (INV 1), the output end of the first NOR gate (NOR 1) is connected to the input end of the third inverter (INV 3), and the output end of the third inverter (INV 3) is connected to the grid electrode of the first P-type power tube (H1); the input end of the third NOR gate (NOR 3) is connected to the output end of the second inverter (INV 2), the output end of the third NOR gate (NOR 3) is connected to the input end of the fifth inverter (INV 5), and the output end of the fifth inverter (INV 5) is connected to the grid electrode of the second P-type power tube (H2); an input end of the second NOR gate (NOR 2) is connected to an output end of the first buffer (BUF 1), an output end of the second NOR gate (NOR 2) is connected to an input end of the fourth inverter (INV 4), and an output end of the fourth inverter (INV 4) is connected to a grid electrode of the first N-type power tube (L1); an input end of the fourth NOR gate (NOR 4) is connected to an output end of the second buffer (BUF 2), an output end of the fourth NOR gate (NOR 2) is connected to an input end of the sixth inverter (INV 6), and an output end of the sixth inverter (INV 6) is connected to a gate of the second N-type power tube (L2); the output end of the third inverter (INV 3), the output end of the fourth inverter (INV 4), the output end of the fifth inverter (INV 5) and the output end of the sixth inverter (INV 6) are all outputs of the control circuit (101), and are used for outputting the power tube on-off signal to the power driving circuit (102).

8. The overcurrent protection circuit of a power transistor according to claim 7, wherein: the input end of the first NOR gate (NOR 1) is further used for inputting a first external signal (INH 1), wherein the first external signal (INH 1) is a switch control signal of a first P-type power tube (H1); the input end of the second NOR gate (NOR 2) is further used for inputting a second external signal (INL 1), and the second external signal (INL 1) is specifically a switch control signal of the first N-type power tube (L1); the input end of the third NOR gate (NOR 3) is further used for inputting a third external signal (INH 2), wherein the third external signal (INH 2) is a switch control signal of a second P-type power tube (H2); the input end of the fourth NOR gate (NOR 4) is further configured to input a fourth external signal (INL 2), where the fourth external signal (INL 2) is specifically a switch control signal of the second N-type power transistor (L2).

9. The overcurrent protection circuit of the power tube of claim 7, wherein: the power supply ends of the first inverter (INV 1), the second inverter (INV 2), the third inverter (INV 3) and the fifth inverter (INV 5) are all connected with the first level (VM), and the grounding ends of the first inverter (INV 1), the second inverter (INV 2), the third inverter (INV 3) and the fifth inverter (INV 5) are all connected with the second level (VM-5); the power ends of the first buffer (BUF 1), the second buffer (BUF 2), the fourth inverter (INV 4) and the sixth inverter (INV 6) are all connected with a third level (VDD), and the grounding ends of the first buffer (BUF 1), the second buffer (BUF 2), the fourth inverter (INV 4) and the sixth inverter (INV 6) are all grounded.

10. The overcurrent protection circuit of the power tube of claim 9, wherein: the first level (VM) is a high voltage power supply level, the second level (VM-5) is a high voltage power supply level and is lower than the first level (VM) by 5V, and the third level (VDD) is a 5V level.

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