CN115732411A - Method for forming semiconductor structure - Google Patents

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a barrier region and a pattern region, the substrate comprises a target layer for forming a target pattern, a core layer is formed on the target layer of the pattern region, and a groove penetrating through the core layer is formed in the core layer; forming a side wall layer on the side wall of the groove; after forming the side wall layer, forming a barrier layer in the groove of the barrier region, wherein the barrier layer covers opposite side walls of the side wall layer, and the barrier layer divides the corresponding groove in the extending direction of the groove; after the barrier layer is formed, removing the core layer in the pattern area to expose the area to be etched of the target layer; and after removing the core layer, etching the target layer by taking the side wall layer and the barrier layer as masks, and forming a target pattern in the target layer. The probability that the barrier layer is removed in multiple etching processes is reduced, and correspondingly, the pattern precision of a target pattern formed in the target layer is improved, so that the performance of the semiconductor structure is improved.

Description

Method for forming semiconductor structure

Technical Field

The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.

Background

With the rapid growth of the semiconductor Integrated Circuit (IC) industry, semiconductor technology is driven by moore's law to move towards smaller process nodes, so that the integrated circuit is developed towards smaller size, higher circuit precision and higher circuit complexity.

In the course of integrated circuit development, the functional density (i.e., the number of interconnect structures per chip) is generally increasing, while the geometric size (i.e., the minimum component size that can be produced using the process steps) is decreasing, which correspondingly increases the difficulty and complexity of integrated circuit fabrication.

Disclosure of Invention

The embodiment of the invention provides a method for forming a semiconductor structure, which is beneficial to further improving the performance of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a barrier region and a pattern region, the substrate comprises a target layer for forming a target pattern, a core layer is formed on the target layer of the pattern region, and a groove penetrating through the core layer is formed in the core layer; forming a side wall layer on the side wall of the groove; after the side wall layer is formed, forming a barrier layer in the groove of the barrier region, wherein the barrier layer covers opposite side walls of the side wall layer, and the barrier layer divides the corresponding groove in the extending direction of the groove; after the barrier layer is formed, removing the core layer in the pattern area to expose the area to be etched of the target layer; and after removing the core layer, etching the target layer by taking the side wall layer and the barrier layer as masks, and forming a target pattern in the target layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

the embodiment of the invention provides a method for forming a semiconductor structure, wherein a barrier layer is formed in a groove of a barrier region, the barrier layer covers opposite side walls of a side wall layer, the barrier layer divides the corresponding groove in the extending direction of the groove, a core layer of a pattern region is subsequently removed, the side wall layer and the barrier layer are used as etching masks, and in the process of forming a target pattern on a target layer, because the size of the barrier layer along the normal direction of the surface of a substrate is larger, the influence of an etching process on the barrier layer is smaller, the probability of removing the barrier layer in multiple etching processes is reduced, correspondingly, the pattern precision of forming the target pattern in the target layer is improved, and the performance of the semiconductor structure is improved.

Drawings

Fig. 1 to 4 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;

fig. 5 to fig. 14 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

Detailed Description

The performance of semiconductor structures currently needs to be improved. The reason why the performance of a semiconductor structure needs to be improved is analyzed in combination with a method for forming a semiconductor structure.

Fig. 1 to 4 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.

Referring to fig. 1 to 2, fig. 1 is a top view, fig. 2 is a cross-sectional view of fig. 1 taken along direction ab, and a substrate including a barrier region 10A and a pattern region 10B is provided, the substrate including a target layer 10 for forming a target pattern, a dielectric layer 11 formed on the top of the target layer 10, a core layer 12 formed on the dielectric layer 11 of the pattern region 10B, and a sidewall layer 16 formed on the sidewall of the core layer 12.

Referring to fig. 3, in the barrier region 10A, the dielectric layer 11 exposed by the core layer 12 and the sidewall layer 16 is removed, and a trench 13 penetrating the dielectric layer 11 is formed.

Referring to fig. 4, a barrier layer 17 is formed in the trench 13, and the barrier layer 17 exposes the sidewall of the sidewall layer 16.

The subsequent process also comprises the following steps: and removing the core layer 12, and patterning the target layer 10 by using the side wall layer 16 and the barrier layer 17 as masks to form a target pattern in the target layer 10.

According to research, in the process of patterning the target layer 10 by using the sidewall layer 16 and the barrier layer 17 as masks, each film layer located between the target layer 10 and the dielectric layer 11 may pass through multiple pattern transfers to be transferred into the target layer 10 to form a target pattern, however, in the process of passing through multiple pattern transfers, since the dimension of the barrier layer 17 in the direction of the normal of the substrate surface is too small, the probability that the barrier layer 17 is removed in the process of multiple pattern transfers is increased, and accordingly, the target pattern formed in the barrier region 10A has poor precision, thereby affecting the performance of the semiconductor structure.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a barrier region and a pattern region, the substrate comprises a target layer for forming a target pattern, a core layer is formed on the target layer of the pattern region, and a groove penetrating through the core layer is formed in the core layer; forming a side wall layer on the side wall of the groove; after the side wall layer is formed, forming a barrier layer in the groove of the barrier region, wherein the barrier layer covers opposite side walls of the side wall layer, and the barrier layer divides the corresponding groove in the extending direction of the groove; after the barrier layer is formed, removing the core layer in the pattern area to expose the area to be etched of the target layer; and after removing the core layer, etching the target layer by taking the side wall layer and the barrier layer as masks, and forming a target pattern in the target layer.

In the forming method provided by the embodiment of the invention, the barrier layer is formed in the groove of the barrier region, the barrier layer covers opposite side walls of the side wall layer, the barrier layer divides the corresponding groove in the extending direction of the groove, the core layer of the pattern region is removed in the subsequent process, and the side wall layer and the barrier layer are used as etching masks, so that in the process of forming the target pattern on the target layer, because the size of the barrier layer along the normal direction of the substrate surface is larger, the influence of an etching process on the barrier layer is smaller, the probability that the barrier layer is removed in multiple etching processes is reduced, correspondingly, the pattern precision of forming the target pattern in the target layer is improved, and the performance of the semiconductor structure is improved.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Fig. 5 to 14 are schematic structural diagrams corresponding to steps in an embodiment of a method for fabricating a semiconductor structure according to the present invention.

Referring to fig. 5, fig. 5 (a) is a plan view, and fig. 5 (b) is a sectional view of fig. 5 (a) along the direction AB. Providing a substrate including a barrier region 100A and a pattern region 100B, the substrate including a target layer 100 for forming a target pattern, the target layer 100 of the pattern region 100B having a core layer 102 formed thereon, the core layer 102 having a trench 103 formed therein through the core layer 102.

The substrate is used for providing a process platform for subsequent process procedures.

In this embodiment, semiconductor devices such as transistors and capacitors may be formed in the substrate, and functional structures such as a resistor structure and a conductive structure may be formed in the substrate.

The target layer 100 is used as a material layer to be patterned subsequently to form a target pattern.

The target pattern may be a gate structure, an interconnection trench in a Back end of line (BEOL) process, a fin in a fin field effect transistor (FinFET), a channel stack in a Gate All Around (GAA) transistor or a fork gate transistor (forkheet), a Hard Mask (HM) layer, or the like.

In this embodiment, the target layer 100 is a dielectric layer, the target layer 100 is patterned subsequently, a plurality of interconnection trenches are formed in the target layer 100, metal interconnection lines are formed in the interconnection trenches, and the target layer 100 is used for realizing electrical isolation between the metal interconnection lines in a back-end process.

Therefore, the target layer 100 is made of a low-k dielectric material (low-k dielectric material refers to a dielectric material having a relative dielectric constant of 2.6 or more and 3.9 or less), an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant of less than 2.6), silicon oxide, silicon nitride, silicon oxynitride, or the like.

In this embodiment, the target layer 100 is made of an ultra-low k dielectric material, so that parasitic capacitance between the interconnection lines at the back section is reduced, and further, the RC delay at the back section is reduced. Specifically, the material of the target layer 100 may be SiOCH.

In this embodiment, the pattern region 100B is a region where a target pattern is to be formed later, and the blocking region 100A is a region where a blocking layer is to be formed later (as shown in a dashed line frame in fig. 5), so that the target patterns on both sides of the blocking region 100A are isolated from each other in the extending direction of the core layer 102.

Specifically, the pattern region 100B surrounds the blocking region 100A.

In this embodiment, in the step of providing the substrate, the substrate further includes an etching stop layer 101, and the etching stop layer 101 is located on the target layer 100.

The etching stop layer 101 is used in an etching process of a subsequent pattern definition process to define an etching stop position, so that the loss of the target layer 100 is reduced, the depth consistency of the etching process is improved, and the effect of the subsequent patterning process is improved.

And then, the pattern is transferred to the etching stop layer 101, and the patterned etching stop layer 101 is used for transferring the pattern to the target layer 100, so that the pattern transfer precision is improved.

In this embodiment, the material of the etch stop layer 101 is titanium nitride. In other embodiments, the material of the etch stop layer may also be silicon nitride, aluminum oxide, silicon oxide, tungsten nitride, aluminum nitride, or the like.

In this embodiment, the core layer 102 provides a process foundation for the subsequent formation of a sidewall layer covering the sidewalls of the core layer 102.

It should be noted that, before the step of subsequently etching the target layer 100 to form the target pattern, the core layer 102 needs to be removed first, and in order to facilitate removing the core layer 102, a material that is easy to remove is selected. To this end, the material of the core layer 102 includes one or more of amorphous carbon (a-C), spin-on carbon (SOC), and spin-on mask (SOH). As an example, the material of the core layer 102 is amorphous carbon.

It should be noted that, when the selective deposition process is subsequently adopted to form the barrier layer covering the sidewall of the sidewall layer in the trench in the barrier region, H is first used ₂ The plasma passivates the exposed material layer, and if the core layer 102 is exposed, the surface of the core layer 102 is modified into dangling bonds (C-H) by selecting the materials, so that the core layer 102 is difficult to react with a precursor adopted by a selective deposition process in the process of forming the barrier layer, that is, the deposition difficulty of the barrier layer on the top of the passivated core layer 102 is increased.

The trench 103 provides a spatial location for the subsequent formation of sidewall layers and barrier layers.

In this embodiment, the extending direction of the groove 103 is the same as the extending direction of the core layer 102.

In this embodiment, the step of forming the core layer 102 and the trench 103 includes: forming a core material layer (not shown) on top of the target layer 100; and patterning the core material layer, wherein the remaining core material layer on the top of the target layer 100 is used as the core layer 102, and a groove 103 is formed in the adjacent core layer 102.

In this embodiment, the process of patterning the core material layer includes a dry etching process.

Specifically, the dry etching process includes an anisotropic dry etching process having anisotropic etching characteristics. Namely, the longitudinal etching rate is greater than the transverse etching rate, so that the method has high pattern conversion precision, and can ensure the appearance quality of the side wall of the groove 103 while removing part of the core material layer.

In this embodiment, the core layer 102 is a bar shape, and the core layer 102 is separated from the substrate of the graphic region 100B.

Specifically, the core layer 102 has opposite ends in the extending direction of the core layer 102, and the core layer 102 has opposite sidewalls in a direction perpendicular to the extending direction of the core layer 102.

Referring to fig. 6, fig. 6 (a) is a plan view, and fig. 6 (b) is a sectional view of fig. 6 (a) in the AB direction. A sidewall layer 106 is formed on the sidewall of the trench 103.

The sidewall layer 106 serves as an etching mask for subsequently forming a target pattern in the target layer 100.

In this embodiment, the step of forming the sidewall layer 106 on the sidewall of the trench 103 includes: forming a side wall material layer (not shown) on the bottom and the side wall of the trench 103 and the top of the core layer 102; removing the side wall material layers on the top of the core layer 102 and the bottom of the trench 103, and remaining the side wall material layers on the side wall of the trench 103 as the side wall layers 106.

Specifically, in the step of forming the side wall material layer, the side wall material layer is located on the side wall, the end portion, and the top of the core layer 102, and is also located on the top of the target layer.

In this embodiment, after removing the side wall material layers on the top of the core layer 102 and the bottom of the trench 103 (i.e., the top of the target layer 100), a side wall group 181 surrounding the core layer 102 is formed, where the side wall group 181 includes a side wall layer 106 located on the side wall of the trench 103 and having the same extending direction as the core layer 102, and a side wall connection portion 180 covering the end of the core layer 102 and connected to the side wall layer 106.

Specifically, the process of removing the sidewall material layer on the top of the core layer 102 and the bottom of the trench 103 includes a dry etching process.

In this embodiment, in the step of forming the side wall layer 106 on the side wall of the trench 103, the side wall layer 106 further covers the side wall of the trench 103 extending in the transverse direction, with the direction perpendicular to the extending direction of the core layer 102 as the transverse direction.

In this embodiment, the process of forming the sidewall layer 106 includes an atomic layer deposition process. Specifically, the process for forming the side wall material layer comprises an atomic layer deposition process.

The ald process includes multiple ald cycles, which provides good step coverage, facilitates improving the thickness uniformity of the sidewall layer 106, and enables the sidewall layer 106 to cover the sidewall of the core layer 102. In other embodiments, the sidewall material layer may also be formed by a Chemical Vapor Deposition (CVD) process.

Specifically, in order to facilitate the subsequent removal of the core layer 102, a material having a high etching selectivity with respect to the material of the core layer 102 needs to be selected as the material of the sidewall layer 106. For this reason, in the present embodiment, the material of the sidewall layer 106 includes one or more of SiN and SiON.

It should be noted that a selective deposition process is subsequently adopted to form a barrier layer on the sidewall of the sidewall layer 106, and by selecting the above materials, the material of the sidewall layer 106 is easy to react with the precursor adopted by the selective deposition process, thereby facilitating the subsequent formation of the barrier layer on the sidewall of the sidewall layer 106.

Referring to fig. 7 to 8, fig. 7 (a) is a plan view, and fig. 7 (b) is a sectional view of fig. 7 (a) in the AB direction; fig. 8 (a) is a top view, fig. 8 (b) is a cross-sectional view along the direction AB of fig. 8 (a), after the sidewall layer 106 is formed, a barrier layer 109 is formed in the trench 103 of the barrier region 100A, the barrier layer 109 covers opposite sidewalls of the sidewall layer 106, and the barrier layer 106 divides the corresponding trench 103 in the extending direction of the trench 103.

In this embodiment, after the core layer 102 in the pattern region 100B is subsequently removed, the sidewall layer 106 and the barrier layer 109 are used as an etching mask, and in the process of forming the target pattern on the target layer 100, since the size of the barrier layer 109 along the normal direction of the substrate surface is large, the influence of the etching process on the barrier layer 109 is small, the probability that the barrier layer 109 is removed in multiple etching processes is reduced, and accordingly, the pattern accuracy of forming the target pattern in the target layer 100 is improved, so that the performance of the semiconductor structure is improved.

With reference to fig. 7 to 8, a detailed description will be made of a step of forming a barrier layer 109 in the trench 103 of the barrier region 100A.

Referring to fig. 7, a filling layer 107 is formed on top of the substrate, and the filling layer 107 covers the top of the core layer 102 and the sidewall layer 106 and fills in the trench 103.

The filling layer 107 plays a role of blocking in the subsequent process of forming the barrier layer, so that the probability of forming the barrier layer in the pattern area 100B is reduced, the barrier layer is formed at a target position, the pattern precision of forming a target pattern in the target layer 100 is improved, and the performance of the semiconductor structure is improved.

It should be noted that after the barrier layer is formed subsequently, the filling layer 107 remaining on the top of the substrate needs to be removed, and in order to remove the filling layer 107, a material that is easy to remove needs to be selected as a material of the filling layer. To this end, the material of the filling layer 107 includes one or more of amorphous carbon (a-C), spin-on carbon (SOC), and spin-on mask (SOH). As an example, the material of the core layer 102 is amorphous carbon.

It should be noted that when a selective deposition process is subsequently used to form a barrier layer, H is used before the material of the barrier layer is deposited in the trench 103 in the barrier region 100A ₂ The plasma passivates the exposed surface of the filling layer 107, and the surface of the filling layer 107 is modified into a dangling bond (C-H) by selecting the materials, so that the filling layer 107 is difficult to react with a precursor adopted by a selective deposition process in the process of depositing the material of the barrier layer, the difficulty of depositing the barrier layer on the side wall and the top of the filling layer 107 subjected to passivation is increased, the step of removing the barrier layer formed on the top and the side wall of the filling layer 107 is omitted, the process cost is saved, and the process efficiency is improved.

With continued reference to fig. 7, after forming the filling layer 107, the filling layer 107 of the barrier region 100A is removed, an opening 108 is formed in the filling layer 107, the opening 108 exposes the bottom of the trench 103 of the barrier region 100A along the extending direction of the core layer 102, and the opening 108 exposes opposite sidewalls of the sidewall layer 106 in a direction perpendicular to the extending direction of the core layer 102.

The openings 108 provide spatial locations for subsequent barrier layer formation.

In this embodiment, in the step of forming the opening 108 in the filling layer 107 by using the direction perpendicular to the extending direction of the core layer 102 as the transverse direction, the opening 108 further extends to both sides along the transverse direction, and exposes a part of the top of the core layer 102 adjacent to the barrier region 100A.

Specifically, the opening 108 extends along the lateral direction to two sides and exposes a portion of the top of the core layer 102 adjacent to the barrier region 100A, increasing the process window for removing the filling layer 107 of the barrier region 100A. Specifically, when the filling layer 107 of the blocking region 100A is removed, a photolithography process is required to define the position of the opening 108, so that the size of the opening 108 is increased, and accordingly, the requirement on the overlay (overlay) precision in the photolithography process is reduced; meanwhile, the process window for forming the barrier layer in the groove 103 in the following process is increased, and the process difficulty for depositing the barrier layer in the groove 103 is reduced.

It should be noted that, in the step of removing the filling layer 107 in the blocking region 100A, since the opening 108 extends along the lateral direction to two sides, a process window for removing the filling layer 107 in the blocking region 100A is correspondingly increased, and a process difficulty for removing the filling layer 107 in the blocking region 100A is reduced.

It should be noted that a selective deposition process that is subsequently adopted is not easy to deposit on the top of the core layer 102, and therefore, the opening 108 exposes a portion of the top of the core layer 102 adjacent to the blocking region 100A, which increases a process window and reduces the probability of forming a blocking layer on the top of the core layer 102 subsequently.

Specifically, the step of removing the filling layer 107 of the barrier region 100A includes: forming a first mask layer (not shown) having a first mask opening (not shown) on top of the filling layer 107, the first mask opening being located above the blocking region 100A; and etching and removing the filling layer 107 of the blocking region 100A by using the first mask layer mask.

The first mask layer is used as an etching mask for removing the filling layer 107 in the blocking region 100A.

In this embodiment, the first mask layer includes an organic material layer, an anti-reflective coating layer on the organic material layer, and a photoresist layer on the anti-reflective coating layer.

The organic material layer provides a flat surface for the formation of the photoresist layer, thereby improving the exposure effect in the process of forming the photoresist layer. The material of the organic material layer includes an organic material. In this embodiment, the material of the organic material layer is Spin-on carbon (SOC). In other embodiments, the material of the organic material layer may also be other organic materials, such as: one or more of an Organic Dielectric Layer (ODL) material, a Deep ultraviolet Absorbing Oxide (DUO) material, and an Advanced Patterning Film (APF) material.

The material of the anti-reflective coating includes a BARC (bottom anti-reflective coating) material. As an example, the BARC material is a Si-ARC (silicon-containing anti-reflective coating) material.

In this embodiment, before removing the filling layer 107 of the blocking region 100A, the method further includes: and sequentially etching the anti-reflection coating and the material layer by taking the photoresist layer as a mask.

It should be noted that, in other embodiments, the photoresist layer may be consumed during the etching of the anti-reflective coating layer and the organic material layer, and the first mask layer may only include the organic material layer and the anti-reflective coating layer on the organic material layer.

Referring to fig. 8, a barrier layer 109 is formed in the trench 103 exposed by the opening 108.

The opening 108 exposes the bottom of the trench 103 of the blocking region 100A along the extending direction of the core layer 102, and the opening 108 exposes opposite sidewalls of the sidewall layer 106 in a direction perpendicular to the extending direction of the core layer 102, so that the blocking layer 109 is formed over a target layer of the blocking region 100A after the blocking layer 109 is formed in the trench 103 exposed by the opening 108.

The barrier layer 109 serves as an etch mask for a subsequent etch target layer.

Specifically, the step of forming the barrier layer 109 in the trench 103 exposed by the opening 108 includes: a barrier layer 109 is formed on the sidewall of the sidewall layer 106 exposed by the opening 108 by an area-selective-deposition (ASD) process, and the barrier layers 109 on the opposite sidewalls of the sidewall layer 106 are in contact with each other.

In this embodiment, in the selective deposition process, the deposition difficulty of the barrier layer 109 on the surface of the core layer 102 is greater than that on the surface of the side wall 106, so that the barrier layer 109 can be selectively formed on the side wall of the side wall 106.

Specifically, the step of the selective deposition process comprises: passivating the surface of the core layer 102; after the passivation, a barrier layer 109 is selectively deposited on the sidewall of the sidewall spacer 106 exposed by the recess 103.

The passivation treatment of the surface of the filling layer 107 increases the difficulty of depositing the barrier layer 109 on the surface of the filling layer 107, thereby reducing the probability of forming the barrier layer 109 on the surface of the filling layer 107.

In this example, NH was used ₃ Or H ₂ The plasma passivates the surface of the core layer 102.

In the selective deposition process, NH is used before the material is deposited ₃ Or H ₂ The plasma passivates the surface of the core layer 102 to modify the surface of the core layer 102 into dangling bonds (C-H), so that the dangling bonds can inhibit reaction with a precursor used in a deposition process during the formation of the barrier layer 109, that is, the barrier layer 109 is difficult to react with the precursor used in the deposition process, thereby increasing the surface of the barrier layer 109 on the passivated core layer 102Difficulty of face deposition.

The selective deposition process has the characteristics of deposition flexibility and the like, the deposition rates of the selective deposition process on different materials are different, so that the required process requirements are met, in the process of forming the barrier layer 109 on the side wall of the side wall layer 106 exposed out of the trench 103 by adopting the selective deposition process, the deposition rate of the barrier layer 109 on the side wall of the side wall layer 106 exposed out of the trench 103 is far greater than the deposition rates on the surfaces of the core layer 102 and the filling layer 107, so that a small amount of the barrier layer 109 is deposited on the surfaces of the core layer 102 and the filling layer 107, and meanwhile, in the subsequent cleaning process, the small amount of the barrier layer 109 formed on the surfaces of the core layer 102 and the filling layer 107 can be removed completely.

Accordingly, by selecting the selective deposition process, the barrier layer 109 can be directly formed at the target position without performing patterning (e.g., etching), thereby reducing the number of process steps and the process cost.

It should be noted that, in order to fill the recess 103 in the blocking region 100A to reduce the probability of gaps occurring in the blocking layer 109 formed in the recess 103, the blocking layers 109 formed on the opposite sidewalls of the sidewall layer 106 are in contact during the process of forming the blocking layer 109 by using a selective deposition process.

It should be noted that, in the process of forming the opening 108, the opening 108 is also exposed on the top of the sidewall layer 106, and therefore, in the process of the selective deposition process, the barrier layer 109 is also formed on the top of the sidewall layer 106 exposed by the opening 108.

In this embodiment, the material of the barrier layer 109 includes TiN, tiO, and HfO ₂ One or more of (a).

By selecting TiN, tiO and HfO ₂ Can be formed using a selective deposition process such that the material of the barrier layer 109 is compatible with the selective deposition process. Meanwhile, the TiN, tiO and HfO ₂ Is harder, and the core layer 102 and the filler layer 107 are subsequently removedIn the process, the removal rate of the barrier layer 109 is lower than that of the core layer 102 and the filling layer 107, so that the topography of the barrier layer 109 along the normal direction of the substrate surface is not easy to change, thereby providing a good process foundation for the subsequent patterning of the target layer 100.

In this embodiment, after forming the barrier layer 109, the method further includes: and removing the first mask layer.

Specifically, the process for removing the first mask layer includes an ashing process.

Referring to fig. 9, fig. 9 (a) is a plan view, fig. 9 (b) is a cross-sectional view of fig. 9 (a) in an AB direction, and fig. 9 (c) is a cross-sectional view of fig. 9 (a) in a CD direction, and the remaining filling layer 107 is removed.

The filler layer 107 is removed to provide a process foundation for subsequent removal of the core layer 102.

It should be noted that, in the step of removing the remaining filling layer 107, the etching selectivity ratio between the filling layer 107 and the barrier layer 109 is not too small. If the etching selection ratio of the filling layer 107 to the barrier layer 109 is too small, the barrier layer 109 formed in the barrier region 100A is also easily removed completely in the process of removing the filling layer 107, which affects the precision of a target pattern formed in the target layer 100, thereby reducing the performance of the semiconductor structure. For this reason, in this embodiment, in the step of removing the remaining filling layer 107, the etching selection ratio of the filling layer 107 to the barrier layer 109 is greater than 10:1.

in this embodiment, the process of removing the remaining filling layer 107 includes a wet etching process.

The wet etching process has the characteristics of an isotropic etching process, has the characteristics of high etching target, high etching efficiency and the like, and can reduce the damage to the etching stop layer 101 at the bottom of the trench 103 and the side wall layer 106 on the side wall of the trench 103 while removing the filling layer 107 completely.

In other embodiments, an ashing process may also be used to remove the fill layer.

Referring to fig. 10, fig. 10 (a) is a top view, fig. 10 (B) is a cross-sectional view of fig. 10 (a) taken along the direction AB, and fig. 10 (c) is a cross-sectional view of fig. 10 (a) taken along the direction CD, after the barrier layer 109 is formed, the core layer 102 of the pattern region 100B is removed to expose the region to be etched of the target layer 100.

The core layer 102 is removed to expose the region to be etched in the target layer 100, thereby preparing for the subsequent formation of the target pattern in the target layer 100.

In this embodiment, the process of removing the core layer 102 in the pattern region 100B includes a wet etching process.

The wet etching process has the characteristics of an isotropic etching process, has the characteristics of strong etching target, high etching efficiency and the like, and can reduce damage to the etching stop layer 101 at the bottom of the core layer 102, the side wall layer 106 on the side wall of the core layer 102 and the barrier layer 109 while removing the core layer 102 cleanly.

Referring to fig. 11, fig. 11 (a) is a plan view, fig. 11 (b) is a sectional view of fig. 11 (a) taken along the direction AB, and fig. 11 (c) is a sectional view of fig. 11 (a) taken along the direction CD, with the sidewall connection part 180 removed.

Specifically, the sidewall connecting portion 180 needs to be removed according to different patterns of the metal interconnection line, and in other embodiments, the sidewall connecting portion may not be removed.

In this embodiment, the process of removing the sidewall connecting portion 180 includes a dry etching process.

Referring to fig. 12 to 13, fig. 12 (a) is a top view, fig. 12 (b) is a cross-sectional view of fig. 12 (a) along the AB direction, fig. 12 (c) is a cross-sectional view of fig. 12 (a) along the CD direction, fig. 13 (a) is a top view, fig. 13 (b) is a cross-sectional view of fig. 13 (a) along the AB direction, and fig. 13 (c) is a cross-sectional view of fig. 13 (a) along the CD direction, after removing the core layer 102, the target layer 100 is etched using the sidewall layer 106 and the barrier layer 109 as a mask, and a target pattern 120 is formed in the target layer 100.

By forming the barrier layer 109, a part of the target pattern 120 is isolated in the extending direction of the target pattern 120.

As can be seen from the foregoing description, the size of the barrier layer 109 along the normal direction of the substrate surface is relatively large, and the influence of the related etching process on the barrier layer 109 is relatively small, so that the probability that the barrier layer 109 is removed in the multiple etching processes is reduced, and accordingly, the pattern precision and the pattern quality of the target pattern 120 formed in the target layer 100 are improved.

It should be noted that the target layer 100 is a dielectric layer, and therefore, after the target layer 100 is etched by using the sidewall layer 106 and the barrier layer 109 as masks, the target pattern 120 is an interconnection trench.

The interconnection groove provides a spatial position for the subsequent formation of the metal interconnection line.

In this embodiment, the step of etching the target layer 100 by using the sidewall layer 106 and the blocking layer 109 as masks and forming the target pattern 120 in the target layer 100 includes: etching the etching stop layer 101 by using the sidewall layer 106 and the barrier layer 109 as masks, forming a second mask opening 110 in the etching stop layer 101, wherein the second mask opening 110 exposes a region to be etched of the target layer 100, and the remaining etching stop layer 101 is used as a second mask layer 130; and etching the exposed target layer 100 by using the second mask layer 130 as a mask to form an interconnection groove in the target layer 100.

The second mask layer 130 is formed by etching the etching stop layer 101 with the sidewall layer 106 and the barrier layer 109, which is beneficial to improving the process stability and the process effect of etching the target layer 100 and improving the precision of pattern transfer.

It should be noted that, in the present embodiment, other film layers or structures in the substrate below the target layer 100 are not illustrated, and therefore, in an actual process, the bottom of the interconnection trench exposes a corresponding conductive structure (e.g., a contact hole plug, etc.).

Referring to fig. 13 in combination, in this embodiment, after the target pattern 120 is formed, the method further includes: the second mask layer 130 is removed.

Referring to fig. 14, fig. 14 (a) is a plan view, fig. 14 (b) is a sectional view of fig. 14 (a) in an AB direction, and fig. 14 (c) is a sectional view of fig. 14 (a) in a CD direction, and after the target pattern 120 is formed, the forming method further includes: metal interconnect lines 126 are formed in the interconnect trenches.

The metal interconnect lines 126 are used to electrically connect the semiconductor structure to external circuitry or other interconnect structures.

In this embodiment, the metal interconnection line 126 is made of copper. In other embodiments, the metal interconnection line may also be made of a conductive material such as aluminum.

In this embodiment, the metal interconnection line 126 is formed in the interconnection groove by an electrolytic copper plating method.

Accordingly, the process for forming the metal interconnect line 126 includes a filling step of the conductive material and a planarization step of the conductive material to remove the conductive material above the top of the dielectric layer.

In this embodiment, a chemical mechanical polishing process is used to planarize the conductive material.

The chemical mechanical polishing process makes the metal interconnection line 126 formed in the interconnection groove have a flat surface, which improves the electrical connection effect of the metal interconnection line 126.

The detailed description of the metal interconnection line 160 is omitted here.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (15)

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a barrier region and a pattern region, the substrate comprises a target layer for forming a target pattern, a core layer is formed on the target layer of the pattern region, and a groove penetrating through the core layer is formed in the core layer;

forming a side wall layer on the side wall of the groove;

after the side wall layer is formed, forming a barrier layer in the groove of the barrier region, wherein the barrier layer covers opposite side walls of the side wall layer, and the barrier layer divides the corresponding groove in the extending direction of the groove;

after the barrier layer is formed, removing the core layer in the pattern area to expose the area to be etched of the target layer;

and after removing the core layer, etching the target layer by taking the side wall layer and the barrier layer as masks, and forming a target pattern in the target layer.

2. The method of forming a semiconductor structure of claim 1, wherein forming a barrier layer in the trench of the barrier region comprises: forming a filling layer on the top of the substrate, wherein the filling layer covers the tops of the core layer and the side wall layer and is filled in the groove; removing the filling layer of the barrier region, forming an opening in the filling layer, wherein the opening exposes the bottom of the trench of the barrier region along the extending direction of the core layer, and the opening exposes opposite sidewalls of the sidewall layer in a direction perpendicular to the extending direction of the core layer; forming a barrier layer in the trench exposed by the opening;

after forming the barrier layer, before removing the core layer of the pattern region, further comprising: and removing the residual filling layer.

3. The method of forming a semiconductor structure according to claim 2, wherein the step of forming a barrier layer in the trench exposed by the opening comprises: and forming a barrier layer on the side wall layer sidewall exposed from the opening by adopting a selective deposition process, wherein the barrier layers of the opposite side walls of the side wall layer are in contact with each other.

4. The method according to claim 3, wherein in the step of forming the opening in the filler layer, the opening further extends to both sides in the lateral direction with a direction perpendicular to the direction in which the core layer extends as a lateral direction, and exposes a portion of the top of the core layer adjacent to the barrier region;

the barrier layer is also formed on the top of the side wall layer exposed from the opening.

5. The method of forming a semiconductor structure of claim 2, wherein removing the fill layer of the barrier region comprises: forming a first mask layer with a first mask opening on the top of the filling layer, wherein the first mask opening is positioned above the blocking region; etching and removing the filling layer of the blocking area by using the first mask layer mask; and removing the first mask layer.

6. The method of forming a semiconductor structure of claim 1, wherein the step of forming a sidewall layer on sidewalls of the trench comprises: forming a side wall material layer on the bottom and the side wall of the groove and the top of the core layer; and removing the side wall material layers at the top of the core layer and the bottom of the groove, and reserving the rest side wall material layers positioned on the side wall of the groove as the side wall layers.

7. The method of forming a semiconductor structure of claim 1, wherein the step of forming a sidewall layer on sidewalls of the trench comprises: forming a side wall group surrounding the core layer, wherein the side wall group comprises side wall layers which are positioned on the side walls of the grooves and have the same extending direction as the core layer, and side wall connecting parts connected with the side wall layers;

after removing the core layer and before forming a target pattern in the target layer, the method further includes: and removing the side wall connecting part.

8. The method of forming a semiconductor structure of claim 1, wherein the process of removing the core layer of the pattern region comprises a wet etching process.

9. The method for forming a semiconductor structure according to claim 2, wherein in the step of removing the remaining filling layer, an etching selection ratio of the filling layer to the barrier layer is greater than 10:1.

10. the method of forming a semiconductor structure of claim 1, wherein the material of the core layer comprises one or more of a-C, SOC, and SOH.

11. The method of forming a semiconductor structure according to claim 1, wherein the material of the sidewall layer comprises one or more of SiN and SiON.

12. The method of forming a semiconductor structure of claim 2, wherein the material of the fill layer comprises one or more of a-C, SOC, and SOH.

13. The method of forming a semiconductor structure of claim 1, wherein the material of the barrier layer comprises TiN, tiO, and HfO ₂ One or more of (a).

14. The method of forming a semiconductor structure of claim 1, wherein the process of forming the sidewall layer comprises an atomic layer deposition process.

15. The method of forming a semiconductor structure of claim 1, wherein the target layer is a dielectric layer, and the target pattern is an interconnect trench;

in the step of providing the substrate, the substrate further comprises an etching stop layer, and the etching stop layer is positioned on the target layer;

and etching the target layer by taking the side wall layer and the barrier layer as masks, wherein the step of forming a target pattern in the target layer comprises the following steps: etching the etching stop layer, forming a second mask opening in the etching stop layer, exposing the area to be etched of the target layer through the second mask opening, and taking the remaining etching stop layer as a second mask layer; etching the exposed target layer by taking the second mask layer as a mask, and forming an interconnection groove in the target layer;

after forming the target pattern, the forming method further includes: and forming a metal interconnection line in the interconnection groove.

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