CN115720297A - Pixel integration time adjusting method, circuit and electronic equipment - Google Patents

Abstract

The invention provides a pixel integration time adjusting method, a device and electronic equipment, and the scheme is that a clock signal is obtained; judging the rising edge and the falling edge of the clock signal; when the first conversion edge of the clock signal is detected to arrive, controlling the integration time to control the target pixel to be switched into an integration state; and when the second conversion edge of the clock signal arrives, triggering a system signal to control the reading circuit to collect and read the signal of the target pixel. The control of the integration time and the control of acquiring and reading signals are respectively carried out by adopting different conversion edges, so that external triggering can be used for adjusting the integration time.

Description

A pixel integration time adjustment method, circuit and electronic equipment

technical field

The invention relates to the technical field of electronic circuits, in particular to a pixel integration time adjustment method, circuit and electronic equipment for realizing integration time adjustment through external triggering.

Background technique

For traditional sensors, the interval between adjacent trigger pulses and the integration time adjustment adjusted by the internal counter and register usually have the following limitations: 1. Timeliness, because it usually takes two frames to get results when configuring registers and valid configuration values. 2. Time limit, the control circuit is generally in a standby state between trigger pulses, and the integration time cannot be controlled. Or there is a limit on the maximum or minimum integration time. 3. You can also add a certain integration time after the trigger, and then sample and read. The maximum line frequency achieved. Traditional external triggers can only trigger the acquisition and readout of system signals, and cannot be used to adjust the integration time.

Contents of the invention

In view of this, an embodiment of the present invention provides a pixel integration time adjustment method, circuit and electronic equipment to realize.

In order to achieve the above purpose, embodiments of the present invention provide the following technical solutions:

A method for adjusting pixel integration time, comprising:

Get the clock signal;

judging the rising edge and falling edge of the clock signal;

When detecting that the first transition edge of the clock signal arrives, control the integration time to control the target pixel to enter the integration state;

When it is determined that the second transition edge of the clock signal arrives, the system signal is triggered to control the readout circuit to collect and read the signal of the target pixel.

Optionally, in the above pixel integration time adjustment method,

The first conversion edge is a rising edge, and the second conversion edge is a falling edge.

Optionally, in the above pixel integration time adjustment method,

The number of the clock signals is N, and the N is a positive integer not less than 2, and the target pixel corresponding to each clock signal is different.

Optionally, in the above pixel integration time adjustment method,

The pixel is a 5T pixel, and the control of the integration time includes: controlling the TG2 switch tube of the 5T pixel to be disconnected;

When it is determined that the falling edge of the clock signal arrives, the method further includes: controlling the TG2 switch to be turned on;

The 5T pixel includes:

TG1 switch tube, TG2 switch tube, RST switch tube, SF drive tube, SEL switch tube and PPD diode;

Wherein, the first ends of the TG2 switch tube, the RST switch tube and the SF drive tube are connected to the VDD power supply;

The second end of the TG2 switch tube is connected to the first end of the TG1 switch tube; and connected to the cathode of the PPD diode, and the anode of the PPD diode is grounded;

The second end of the TG1 switch tube is connected to the second end of the RST switch tube and the control terminal of the SF drive tube;

The second end of the SF drive transistor is connected to the first end of the SEL switch transistor, and the second end of the SEL switch transistor is used as the output end of the 5T pixel.

Optionally, in the above pixel integration time adjustment method,

When the number of the clock signals is not less than 2, the level switching periods of at least some of the clock signals may be different.

Optionally, in the above pixel integration time adjustment method,

When it is judged that the falling edge of the clock signal arrives, the system signal is triggered to control the readout circuit to collect and read the signal of the target pixel, including:

Determine whether the falling edge of any one of the clock signals has arrived, and when the falling edge of any one of the clock signals is detected, detect whether the other clock signals are in the low-level area, and if they are in the low-level area, then Indicates the arrival of the falling edge of the clock signal, and triggers the system signal to control the readout circuit to collect and read the signal of the target pixel.

A pixel integration time adjustment device, comprising:

A clock signal acquisition unit, configured to acquire a clock signal;

A rising and falling edge judging unit, configured to judge the rising and falling edges of the clock signal;

The integration control unit is used to control the integration time when the first conversion edge of the clock signal is detected, so as to control the target pixel to enter the integration state;

The collection control unit is configured to trigger the system signal to control the readout circuit to collect and read the signal of the target pixel when it is judged that the second transition edge of the clock signal is coming.

Optionally, in the above-mentioned pixel integration time adjusting device,

The first conversion edge is a rising edge, and the second conversion edge is a falling edge.

Optionally, in the above-mentioned pixel integration time adjusting device,

The number of the clock signals is N, and the N is a positive integer not less than 2, and the target pixel corresponding to each clock signal is different.

An electronic device comprising:

memory and a processor, the memory storing a program suitable for execution by the processor, the program for:

Get the clock signal;

judging the rising edge and falling edge of the clock signal;

When detecting that the first transition edge of the clock signal arrives, control the integration time to control the target pixel to enter the integration state;

When it is determined that the second transition edge of the clock signal arrives, the system signal is triggered to control the readout circuit to collect and read the signal of the target pixel.

Based on the above technical solutions, in the above solutions provided by the embodiments of the present invention, in the above solutions disclosed in the embodiments of the present application, by identifying the transition edges of the clock signal, different transition edges are used to control and control the integration time and The control of acquisition and readout signals enables external triggers to be used to adjust the integration time as well.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work.

FIG. 1 is a schematic flow diagram of a pixel integration time adjustment method disclosed in an embodiment of the present application;

FIG. 2 is a schematic diagram of a trigger effect of a pixel integration time adjustment method disclosed in an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a 5T pixel disclosed in an embodiment of the present application;

FIG. 4 is a schematic diagram of a trigger effect of a pixel integration time adjustment method disclosed in another embodiment of the present application;

FIG. 5 is a schematic structural diagram of a pixel integration time adjustment device disclosed in an embodiment of the present application;

FIG. 6 is a schematic structural diagram of an electronic device disclosed in an embodiment of the present application.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The invention uses the rising edge of the external trigger signal (the external trigger signal is a clock signal) to trigger the acquisition and readout of the system signal, and triggers the adjustment of the integration time through the falling edge.

Referring to FIG. 1 , the pixel integration time adjustment method disclosed in the embodiment of the present application includes: steps S101-S104.

Step S101: Obtain a clock signal.

In this solution, the external trigger signals are all clock signals, and the clock signal is composed of a high-level signal and a low-level signal. set up.

Step S102: judging the rising edge and falling edge of the clock signal.

After the clock signal is acquired, the clock signal is analyzed to determine whether a rising edge or a falling edge of the clock signal arrives. Specifically, the rising edge and falling edge of the clock signal can be judged by the result of the level change of the clock signal. For example, the clock signal changes from a high level 1 to a low level 0, indicating that the clock signal When a falling edge occurs, the clock signal changes from low level 0 to high level 1, indicating that the clock signal has a rising edge.

Step S103: When it is detected that the first transition edge of the clock signal arrives, control the integration time, so as to control the target pixel to enter the integration state.

In this scheme, the first conversion edge and the second conversion edge refer to the rising edge and the falling edge of the clock signal, specifically, the rising edge is used as the first conversion edge signal, and the falling edge is used as the second conversion edge. edge signal, or use the falling edge as the first conversion signal, and use the second conversion edge as the second conversion signal, which can be set according to user needs. In this scheme, for the convenience of explaining the scheme, the The solution is introduced by taking the first transformation edge as a rising edge and the second transformation edge as a falling edge as an example.

Referring to FIG. 2 , when the rising edge of the clock signal is detected, the integration time is controlled to control the target pixel to enter the integration state. When the falling edge of the clock signal is detected, the system signal is triggered to control the readout circuit to collect and read the signal of the target pixel.

Step S104: when it is determined that the second transition edge of the clock signal is coming, trigger the system signal to control the readout circuit to collect and read the signal of the target pixel.

In this step, when the arrival of the second transition edge of the clock signal is detected, the collection and reading of the system signal is triggered, so as to collect and read the signal of the target pixel through the system signal control readout circuit.

In the above solution disclosed in the embodiment of the present application, by identifying the transition edge of the clock signal, different transition edges are used to control the integration time and the control of the acquisition and readout signal, so that the external trigger can also be used to perform Adjust the integration time.

In the technical solution disclosed in another embodiment of the present application, different picture elements can use the same clock signal to control the integration time, data acquisition and reading, or use different clock signals to control the integration time, data acquisition and reading. The control taken, that is, in this solution, the number of the clock signal is N, and the N is a positive integer not less than 2, for example, the number of the clock signal can be 2, 3, 4, etc., and The target pixels corresponding to each clock signal are different, and different target pixels use different clock signals to control the integration time and data acquisition and reading.

In the technical solution disclosed in the embodiment of the present application, the structure of the pixel can be selected according to user needs. For example, in the technical solution disclosed in the embodiment of the present application, the pixel is a 5T pixel, see FIG. 3, the 5T pixels, including:

TG1 switch tube, TG2 switch tube, RST switch tube, SF drive tube, SEL switch tube and PPD diode, the node corresponding to the control end of the SF drive tube is called the FD node;

Wherein, the first ends of the TG2 switch tube, the RST switch tube and the SF drive tube are connected to the VDD power supply;

The second end of the TG2 switch tube is connected to the first end of the TG1 switch tube; and connected to the cathode of the PPD diode, and the anode of the PPD diode is grounded;

The second end of the TG1 switch tube is connected to the second end of the RST switch tube and the control terminal of the SF drive tube;

The second end of the SF drive transistor is connected to the first end of the SEL switch transistor, and the second end of the SEL switch transistor is used as the output end of the 5T pixel. Corresponding to the 5T pixel of the above structure, the control of the integration time is specifically: controlling the TG2 switch tube of the 5T pixel to be turned off, the TG2 switch tube is turned off, and the photoelectrons are stored in the PPD diode at this time. Reset the FD node in the 5T pixel, sample the reset signal of the FD node, complete the integration of the 5T pixel and transmit the electrons stored on the PPD to the FD node, sample the section signal of the FD node, and read the sampling signal of the FD node. When it is determined that the falling edge of the clock signal arrives, it also includes: controlling the TG2 switch to be turned on. After the falling edge of the clock signal arrives and before the rising edge arrives, the clock signal is in a low level state, and the 5T pixel is in In the continuous reset state, the PPD diode is in a fully depleted state (fully depleted state) through the conduction of the TG2 switch tube.

In the technical solution disclosed in another embodiment of the present application, by identifying the rising and falling edges of each clock signal, it can be realized by sub-area (different external trigger signals (clock signals) are given to different areas (which can be 5T pixel)) Realize the control of different integration times for the same readout, that is, collect and read each 5T image signal at the same time, at this time, when it is judged that the falling edge of the clock signal arrives, trigger the system signal to control the readout circuit Collect and read the signal of the target pixel, including:

Determine whether the falling edge of any one of the clock signals has arrived, and when the falling edge of any one of the clock signals is detected, detect whether the other clock signals are in the low-level area, and if they are in the low-level area, then Indicates the arrival of the falling edge of the clock signal, and triggers the system signal to control the readout circuit to collect and read the signal of the target pixel.

For example, referring to FIG. 4, when the number of the clock signals is 2, one of the clock signals is recorded as clock signal 1, and the other is recorded as clock signal 2. When the falling edge of the clock signal 1 arrives, the clock signal is judged Whether the falling edge of 2 arrives or the clock signal 2 is at a low level, if the judgment result is yes, it indicates that the falling edge of the clock signal arrives, triggering the system signal to control the readout circuit to signal to all target pixels Collect and read. If the judgment result is no, continue to wait until the falling edge of the clock signal 2 arrives or when it is at a low level, trigger the system signal to control the readout circuit to collect and read the signals of all target picture elements, if The falling edge of the clock signal 2 comes first, and the judgment based on the above principle is also required.

Corresponding to the above method, the present application also discloses a pixel integration time adjustment device, as shown in Fig. 5, the device may include: a clock signal acquisition unit A, a rising and falling edge judging unit B, an integration control unit C and an acquisition control unit D .

A clock signal acquisition unit A, corresponding to step S101 in the above method, for acquiring a clock signal;

Rising and falling edge judging unit B, corresponding to step S102 in the above method, for judging the rising and falling edges of the clock signal;

The integration control unit C, corresponding to step S103 in the above method, is used to control the integration time when it is detected that the first transition edge of the clock signal arrives, so as to control the target pixel to enter the integration state;

The collection control unit D, corresponding to step S104 in the above method, is used to trigger the system signal to control the readout circuit to collect and read the signal of the target pixel when it is judged that the second transition edge of the clock signal arrives .

Wherein, the first conversion edge is a rising edge, and the second conversion edge is a falling edge. The number of the clock signals is N, and the N is a positive integer not less than 2, and the target pixel corresponding to each clock signal is different.

Corresponding to the above method, the pixel is a 5T pixel, and when the integral control unit controls the integration time, it specifically: controls the TG2 switch tube of the 5T pixel to be disconnected;

When the acquisition control unit determines that the falling edge of the clock signal arrives, the acquisition control unit is further configured to: control the TG2 switch to be turned on.

Corresponding to the above method, when the acquisition control unit determines that the falling edge of the clock signal arrives and triggers the system signal to control the readout circuit to acquire and read the signal of the target pixel, it is specifically used for:

Determine whether the falling edge of any one of the clock signals has arrived, and when the falling edge of any one of the clock signals is detected, detect whether the other clock signals are in the low-level area, and if they are in the low-level area, then Indicates the arrival of the falling edge of the clock signal, and triggers the system signal to control the readout circuit to collect and read the signal of the target pixel.

Corresponding to the above method, the present application also discloses an electronic device. FIG. 6 is a hardware structure diagram of the electronic device provided by the embodiment of the present invention. Referring to FIG. 6, it may include: at least one processor 100, at least one communication interface 200, at least one memory 300 and at least one communication bus 400;

In the embodiment of the present invention, the number of the processor 100, the communication interface 200, the memory 300, and the communication bus 400 is at least one, and the processor 100, the communication interface 200, and the memory 300 complete the mutual communication through the communication bus 400; obviously, The communication connections shown in the processor 100, communication interface 200, memory 300 and communication bus 400 shown in FIG. 6 are only optional;

Optionally, the communication interface 200 can be an interface of a communication module, such as an interface of a GSM module;

The processor 100 may be a central processing unit CPU, or an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention.

The memory 300 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one magnetic disk memory.

Wherein, the processor 100 is specifically used for:

Get the clock signal;

judging the rising edge and falling edge of the clock signal;

When detecting that the first transition edge of the clock signal arrives, control the integration time to control the target pixel to enter the integration state;

When it is determined that the second transition edge of the clock signal arrives, the system signal is triggered to control the readout circuit to collect and read the signal of the target pixel.

The processor is further configured to execute the steps disclosed in any one of the above method embodiments of the present application, which will not be described here.

In the technical solutions disclosed in the embodiments of the present application, the electronic device may be a mobile phone, a computer or other smart terminal devices.

For the convenience of description, when describing the above system, the functions are divided into various modules and described separately. Of course, when implementing the present application, the functions of each module can be realized in one or more pieces of software and/or hardware.

Each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for relevant parts, please refer to the part of the description of the method embodiment. The systems and system embodiments described above are only illustrative, and the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is It can be located in one place, or it can be distributed to multiple network elements. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. It can be understood and implemented by those skilled in the art without creative effort.

Professionals can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software or a combination of the two. In order to clearly illustrate the possible For interchangeability, in the above description, the composition and steps of each example have been generally described according to their functions. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present invention.

The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be directly implemented by hardware, software modules executed by a processor, or a combination of both. Software modules can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other Any other known storage medium.

It should also be noted that in this article, relational terms such as first and second etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations Any such actual relationship or order exists between. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A pixel integration time adjustment method, characterized in that, comprising: Get the clock signal; judging the rising edge and falling edge of the clock signal; When detecting that the first transition edge of the clock signal arrives, control the integration time to control the target pixel to enter the integration state; When it is determined that the second transition edge of the clock signal arrives, the system signal is triggered to control the readout circuit to collect and read the signal of the target pixel. 2. pixel integration time adjustment method according to claim 1, is characterized in that, The first conversion edge is a rising edge, and the second conversion edge is a falling edge. 3. pixel integration time adjustment method according to claim 2, is characterized in that, The number of the clock signals is N, and the N is a positive integer not less than 2, and the target pixel corresponding to each clock signal is different. 4. The pixel integration time adjustment method according to claim 3, wherein the pixel is a 5T pixel, and the control of the integration time includes: controlling the TG2 switching tube of the 5T pixel to be disconnected; When it is determined that the falling edge of the clock signal arrives, the method further includes: controlling the TG2 switch to be turned on; The 5T pixel includes: TG1 switch tube, TG2 switch tube, RST switch tube, SF drive tube, SEL switch tube and PPD diode; Wherein, the first ends of the TG2 switch tube, the RST switch tube and the SF drive tube are connected to the VDD power supply; The second end of the TG2 switch tube is connected to the first end of the TG1 switch tube and simultaneously connected to the cathode of the PPD diode, and the anode of the PPD diode is grounded; The second end of the TG1 switch tube is connected to the second end of the RST switch tube and the control terminal of the SF drive tube; The second end of the SF drive transistor is connected to the first end of the SEL switch transistor, and the second end of the SEL switch transistor is used as the output end of the 5T pixel. 5. pixel integration time adjustment method according to claim 3, is characterized in that, When the number of the clock signals is not less than 2, the level switching periods of at least some of the clock signals are different. 6. pixel integration time adjustment method according to claim 5, is characterized in that, when it is judged that the falling edge of said clock signal arrives, trigger system signal to control the readout circuit to collect the signal of target pixel and read, including: Determine whether the falling edge of any one of the clock signals has arrived, and when the falling edge of any one of the clock signals is detected, detect whether the other clock signals are in the low-level area, and if they are in the low-level area, then Indicates the arrival of the falling edge of the clock signal, and triggers the system signal to control the readout circuit to collect and read the signal of the target pixel. 7. A pixel integration time adjustment device, characterized in that it comprises: A clock signal acquisition unit, configured to acquire a clock signal; A rising and falling edge judging unit, configured to judge the rising and falling edges of the clock signal; The integration control unit is used to control the integration time when the first conversion edge of the clock signal is detected, so as to control the target pixel to enter the integration state; The collection control unit is configured to trigger the system signal to control the readout circuit to collect and read the signal of the target pixel when it is judged that the second transition edge of the clock signal is coming. 8. The pixel integration time adjusting device according to claim 7, characterized in that, The first conversion edge is a rising edge, and the second conversion edge is a falling edge. 9. The pixel integration time adjusting device according to claim 8, characterized in that, The number of the clock signals is N, and the N is a positive integer not less than 2, and the target pixel corresponding to each clock signal is different. 10. An electronic device, characterized in that it comprises: memory and a processor, the memory storing a program suitable for execution by the processor, the program for: get clock signal; Judging the rising edge and falling edge of the clock signal; When detecting that the first transition edge of the clock signal arrives, control the integration time to control the target pixel to enter the integration state; When it is determined that the second transition edge of the clock signal arrives, the system signal is triggered to control the readout circuit to collect and read the signal of the target pixel.

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