CN115718685A - CPU test method, device, electronic equipment and storage medium - Google Patents

Abstract

Embodiments of the present invention provide a CPU testing method, device, electronic equipment and storage medium, and relate to the technical field of testing. Including: building basic test cases according to verification scenarios; configuring external random stimulus for basic test cases to obtain random test cases; controlling the CPU to execute random test cases to generate test results; reading the state value of the status register, and judging the running test according to the state value Whether it is completed; if the running test is completed, judge whether the random test case is successfully executed according to the test result, and end the running test when it is determined that the random test case is successfully executed. The test scenarios are enriched by accessing external random excitations; the simulation environment is only used in C language, and the complexity is not high; at the same time, a real CPU is used to ensure the completeness of the test scenarios and the reliability of the test results.

Description

CPU testing method, device, electronic equipment and storage medium

technical field

The present invention relates to the technical field of testing, in particular to a CPU testing method, device, electronic equipment and storage medium.

Background technique

With the development of the semiconductor industry, the functions of SOC (System On Chip, System-on-Chip) are becoming more and more complex. Improving the verification efficiency and reliability of the CPU (Central Processing Unit, central processing unit) subsystem is of great significance to the development of SOC.

Existing CPU subsystems are generally tested through a simulation environment, and virtual components can be used to replace the real CPU, but the reliability of this test method is not high. If the simulation verification is carried out under the real CPU, the relatively simple C language/C++ is used to generate the driver and stimulus, but the CPU itself does not have an effective mechanism for generating random stimulus, so the test scenarios in this simulation environment are single.

Therefore, there is an urgent need for a CPU testing method with high reliability and more test scenarios.

Contents of the invention

In order to solve the above technical problems, the embodiments of the present application provide a CPU testing method, device, electronic equipment, and storage medium.

In the first aspect, the embodiment of the present application provides a CPU testing method, the method comprising:

Build basic test cases based on verification scenarios;

Configuring an external source random stimulus for the basic test case to obtain a random test case;

Control CPU to carry out described random test case, generate test result;

Read the status value of the status register, and judge whether the running test is completed according to the status value;

If the running test is completed, judge whether the random test case is executed successfully according to the test result, and end the running test when it is determined that the random test case is executed successfully.

In one embodiment, the configuration of external random stimulus for the basic test case to obtain a random test case includes:

Configuring a preset seed number for the basic test case to obtain a verification test case;

Verifying the verification test case;

If the verification is passed, an external local(time) function is used to generate a random seed number, and the random seed number is configured for the basic test case to obtain the random test case.

In one embodiment, the use of an external local (time) function to generate a random seed number includes:

Obtain the first system time corresponding to the current moment;

Using the local(time) function to convert the first system time into the random seed number.

In one embodiment, the method also includes:

update the random seed number;

Generate new test cases, and execute running tests with the new test cases.

In one embodiment, the updating of the random seed number includes:

Obtain the second system time corresponding to the current moment;

Using the local(time) function to convert the second system time into an update seed number;

The random seed number is replaced with the updated seed number.

In one embodiment, the execution of the random test case by the control CPU includes:

Obtaining an operation code from a static memory outside the CPU, so that the CPU executes the random test case according to the operation code.

In one embodiment, the steps before the control CPU executes the random test case also include:

Compiling the random test case, obtaining a compilation result and generating a compilation log;

storing the compilation result in the static memory;

If the execution of the random test case fails, error checking is performed according to the compilation log and the test result.

In a second aspect, the embodiment of the present application provides a CPU testing device, the CPU testing device comprising:

Building blocks for building basic test cases based on verification scenarios;

A configuration module, configured to configure an external source random stimulus for the basic test case to obtain a random test case;

Execution module, is used for controlling CPU to carry out described random test case, generates test result;

Judging module, for reading the status value of the status register, and judging whether the running test is completed according to the status value;

The determining module is configured to judge whether the random test case is executed successfully according to the test result if the running test is completed, and end the running test when it is determined that the random test case is executed successfully.

In a third aspect, an embodiment of the present application provides an electronic device, including a memory and a processor, the memory is used to store a computer program, and the computer program executes the CPU testing method provided in the first aspect when the processor is running .

In a fourth aspect, the embodiment of the present application provides a computer-readable storage medium, which stores a computer program, and the computer program executes the CPU testing method provided in the first aspect when running on a processor.

The CPU test method provided by the above-mentioned application constructs a basic test case according to the verification scenario; configures an external source random stimulus for the basic test case to obtain a random test case; controls the CPU to execute a random test case to generate test results; reads the state value of the status register , judge whether the running test is completed according to the state value; if the running test is completed, judge whether the random test case is successfully executed according to the test result, and end the running test when it is determined that the random test case is successfully executed. The test scenarios are enriched by accessing external random excitations; the simulation environment is only used in C language, and the complexity is not high; at the same time, a real CPU is used to ensure the completeness of the test scenarios and the reliability of the test results.

Description of drawings

In order to illustrate the technical solution of the present application more clearly, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the application, and therefore should not be regarded It is regarded as a limitation on the scope of protection of the present application. In the respective drawings, similar components are given similar reference numerals.

Fig. 1 shows a schematic flow chart of the CPU testing method provided by the embodiment of the present application;

Fig. 2 shows a schematic structural diagram of the simulation environment provided by the embodiment of the present application;

FIG. 3 shows a schematic structural diagram of a CPU testing device provided by an embodiment of the present application.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all of them.

The components of the embodiments of the application generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations. Accordingly, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application.

Hereinafter, the terms "comprising", "having" and their cognates that may be used in various embodiments of the present application are only intended to represent specific features, numbers, steps, operations, elements, components or combinations of the foregoing, And it should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing or adding one or more features, numbers, steps, operations, elements, components or a combination of the foregoing possibilities.

In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions, and should not be construed as indicating or implying relative importance.

Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the application belong. The terms (such as those defined in commonly used dictionaries) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning, Unless clearly defined in the various embodiments of the present application.

Example 1

With the development of the semiconductor industry, the functions of SOC (System On Chip, system-on-chip) are becoming more and more complex. Improving the verification efficiency and reliability of the CPU subsystem is of great significance to the development of SOC. Based on this, an embodiment of the present disclosure provides a CPU testing method.

Specifically, referring to Figure 1, the CPU testing method includes:

The CPU testing method provided in the embodiment of the present application is mainly applied in a simulation environment of CPU testing, and is mainly used for testing a subsystem of the CPU. Wherein, as shown in FIG. 2 , the simulation environment includes five components: DUT, driver program storage SRAM, driver program and monitoring information.

Wherein, the DUT (Design under Test, design under test) is the part that needs to be tested in the embodiment of the present application, including the RTL (Register Transfer Level, register transfer level circuit) of the CPU, IP core and peripherals. A SRAM (Static Random Access Memory, static random access memory) in the peripheral device will divide a fixed area and use it as a boot ROM (Read-Only Memory, read-only memory) of the CPU.

SRAM is used to cache testcase (test cases). After the driver program is written into the SRAM, the simulation environment will read the driver program in the SRAM and put it into the boot ROM of the CPU. The CPU will analyze the driver program and complete the command execution with the corresponding peripherals.

The driver program includes the CPU startup program and testcase (test case). Among them, the CPU startup program is realized by assembly language. testcase is an executable C file, which is used to realize the test scenario that needs to be simulated. It generates random stimulus by calling an external random program. At the same time, the checker (judgment) function is also implemented in the testcase.

The role of the checker is to monitor whether the simulation meets expectations. During the execution of the testcase, the checker judges whether there is an error or abnormality in the execution of the testcase by reading the status register; after the command is executed, the checker compares the data to judge whether the execution of the testcase is successful. Finally, the judgment result is output as the monitoring information of the simulation.

The monitoring information of the simulation environment is divided into two parts. The first part is the compilation log file of the CPU startup program and testcase, which is used to record the compilation information of the testcase. During the debugging process, the corresponding instruction information can be obtained through the PC address of the CPU. The second part is the log information generated by the testcase simulation, including random incentive information and checker results.

Based on the above components and their functions, start the simulation. Step S110, building a basic test case according to the verification scenario; wherein, the basic test case is an executable file.

Step S120, configuring an external random stimulus for the basic test case to obtain a random test case; the external random stimulus is used to improve the coverage of the scenario and can be generated by calling an external task_rand program. At this time, a section of area can be divided from the CPU peripheral SRAM to be used as the boot ROM of the CPU.

The instruction set of the CPU itself based on the RISCV architecture does not have a random function, so this embodiment reproduces the rand random function of the C language, as shown in Algorithm 1:

Algorithm one:

The rand random function of the C language converts the system time into a seed number through the srand function, as shown in Algorithm 2:

Algorithm 2:

void srand(unsigned int seed){

next=seed;

}

However, the embedded CPU does not have an effective random seed generation mechanism, so the embodiment of this application uses an external program to generate random incentives, please refer to Algorithm 3:

Algorithm three:

It should be noted that, firstly, it is necessary to perform preliminary simulation verification on each basic test case to confirm that each test case has realized the corresponding verification scenario (feature), and the next step can only be carried out after each test case process is confirmed to be correct and the simulation results meet expectations verify.

Based on this, in one embodiment, a preset seed number is configured for the basic test case to obtain a verification test case; the verification test case is verified; wherein, the preset seed number may be 0.

If the verification is passed, an external local(time) function is used to generate a random seed number, and the random seed number is configured for the basic test case to obtain the random test case.

The process of generating random seed numbers is called regression verification. In each regression verification process, different seed numbers are used as basic test cases to configure random incentives to ensure the improvement of verification coverage.

In one running test, in one embodiment, the first system time corresponding to the current moment is acquired; the first system time is converted into the random seed number by using the local(time) function.

When entering the next running test, in one embodiment, update the random seed number; generate a new test case, and use the new test case to execute the running test.

In one embodiment, the simulation environment uses a perl script to perform regression verification on all test cases, and the script executes each line of command in the file sequentially. When testing whether all testcase processes are correct, each line of command in the perl script is each testcase simulation command, and the number of regressions is 1. After the process is confirmed to be correct and the simulation is passed, multiple regression verifications are performed. At this point, add a command to modify the seed number (command 1) before each testcase simulation command to ensure that each regression produces a different random stimulus.

Command 1: perl-pi-e's|0x00000000|localtime(time)|g'testcase path

Between simulation executions, use this command to use the system time as the seed number to replace the default seed number 0x00000000 in testcase. Among them, local(time) is a built-in function of perl, which will convert the system time into second output; among them, testcase path' is the path of the testcase to be verified.

The seed number in each testcase in the simulation environment is set to 0x00000000, and other zero values in the testcase are represented by 0x0, so as to ensure that the modification of the seed number will not affect the functions of other functions in the testcase.

Next, execute the simulation command of the testcase. Under different simulation times, the same testcase gets different seed numbers to generate different incentives. After multiple regressions, the scene can be completely covered.

After the testcase is executed, use the perl command (command 2) to modify the random seed number to the default value 0x00000000, so that the same testcase can get other random seed numbers next time, so as to realize the multiplexing of the peripheral random function.

Command 2: perl --pi --e 's|randseed=(.*)|randseed=0x00000000|g' testcasepathway

Step S130, controlling the CPU to execute the random test cases to generate test results;

In one embodiment, the operation code is obtained from a static memory outside the CPU, so that the CPU executes the random test case according to the operation code.

When the simulation starts, the simulation environment will obtain the operation code (opcode) from the SRAM and put it into the boot ROM of the CPU. The CPU reads commands from the boot ROM, decodes opcodes and executes random test cases.

Step S140, read the status value of the status register, and judge whether the running test is completed according to the status value;

During the process of CPU executing a random use case, the checker works synchronously, and outputs the necessary address and data information to the log file for the reproduction of the test scenario until the end of the simulation. At the same time, the status value of the status register is monitored to determine whether the simulation is successful or abnormal, and the simulation results are stored in the log information. If an exception occurs, the simulation ends prematurely.

In one embodiment, the random test case is compiled, a compilation result is obtained and a compilation log is generated; the compilation result is stored in the static memory;

You can use the makefile script to compile random test cases, and convert the compiled results into hexadecimal and store them in SRAM. At the same time, a compilation log will be generated for use in the subsequent error checking (Debug) stage.

If the execution of the random test case fails, error checking is performed according to the compilation log and the test result.

Step S150, if the running test is completed, judge whether the random test case is successfully executed according to the test result, and end the running test when it is determined that the random test case is successfully executed. After the simulation is over, judge whether the testcase is successfully executed according to the log information. If the simulation is successful, execute the next testcase to be verified; if it fails, debug according to the compilation log and log information.

Compared with the existing technology, first, the real CPU is replaced by System Verilog and UVM components. Although a standard verification language is used, the reliability of the CPU simulated by the components is not high. In view of this shortcoming, the simulation environment of the embodiment of the present application uses a real CPU, and the reliability of the verification result is guaranteed.

Second, use C language/C++ to generate the driver program, System Verilog to generate random excitation, and perform simulation verification under the real CPU, but this method increases the complexity of the simulation environment. To solve this problem, the drivers and random functions of this verification environment are implemented in C language.

Third, use C language/C++ to generate drivers and incentives, but because the embedded CPU does not have an effective seed mechanism, random incentives cannot be obtained. To solve this problem, this verification environment automatically generates different random excitations in each simulation process through an external random function.

To sum up, the CPU test method provided in this embodiment enriches the test scenarios by accessing external source random excitation; the simulation environment is only used in C language, and the complexity is not high; at the same time, a real CPU is used to ensure the completeness of the test scenario and the test reliability of the results.

Example 2

In addition, an embodiment of the present disclosure provides a CPU testing device.

Specifically, as shown in Figure 3, the CPU testing device 300 includes:

A construction module 310, configured to construct a basic test case according to a verification scenario;

The configuration module 320 is configured to configure an external source random stimulus for the basic test case to obtain a random test case;

Execution module 330, is used for controlling CPU to carry out described random test case, generates test result;

Judging module 340, for reading the status value of the status register, and judging whether the running test is completed according to the status value;

The determining module 350 is configured to judge whether the random test case is successfully executed according to the test result if the running test is completed, and end the running test when it is determined that the random test case is successfully executed.

The CPU testing device 300 provided in this embodiment can implement the CPU testing method provided in Embodiment 1, and to avoid repetition, details are not repeated here.

The CPU test device provided in this embodiment enriches the test scenarios by accessing external source random excitation; only uses C language to simulate the environment, and the complexity is not high; at the same time, a real CPU is used to ensure the completeness of the test scenarios and the reliability of the test results sex.

Example 3

In addition, an embodiment of the present disclosure provides an electronic device, including a memory and a processor, the memory stores a computer program, and the computer program executes the CPU testing method provided in Embodiment 1 when running on the processor.

The electronic device provided in the embodiment of the present invention can implement the CPU testing method provided in Embodiment 1, and details are not repeated here to avoid repetition.

The electronic equipment provided in this embodiment enriches the test scenarios by accessing external source random excitation; the simulation environment is only used in C language, and the complexity is not high; at the same time, a real CPU is used to ensure the completeness of the test scenarios and the reliability of the test results .

Example 4

The present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the CPU testing method provided in Embodiment 1 is realized.

In this embodiment, the computer-readable storage medium may be a read-only memory (Read-Only Memory, ROM for short), a random access memory (Random Access Memory, RAM for short), a magnetic disk, or an optical disk.

The computer-readable storage medium provided in this embodiment can implement the CPU testing method provided in Embodiment 1, and details are not repeated here to avoid repetition.

It should be noted that, in this document, the term "comprising", "comprising" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or terminal comprising a set of elements includes not only those elements, It also includes other elements not expressly listed, or elements inherent in the process, method, article, or terminal. Without further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article or terminal comprising the element.

Through the description of the above embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus a necessary general-purpose hardware platform, and of course also by hardware, but in many cases the former is better implementation. Based on such an understanding, the technical solution of the present application can be embodied in the form of a software product in essence or the part that contributes to the prior art, and the computer software product is stored in a storage medium (such as ROM/RAM, disk, CD) contains several instructions to enable a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in various embodiments of the present application.

The embodiments of the present application have been described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementations. The above-mentioned specific implementations are only illustrative and not restrictive. Those of ordinary skill in the art will Under the inspiration of this application, without departing from the purpose of this application and the scope of protection of the claims, many forms can also be made, all of which belong to the protection of this application.

Claims (10)

1. a CPU testing method, is characterized in that, described method comprises: Build basic test cases based on verification scenarios; Configuring an external source random stimulus for the basic test case to obtain a random test case; Control CPU to carry out described random test case, generate test result; Read the status value of the status register, and judge whether the running test is completed according to the status value; If the running test is completed, judge whether the random test case is executed successfully according to the test result, and end the running test when it is determined that the random test case is executed successfully. 2. CPU test method according to claim 1, is characterized in that, described basic test case configuration exogenous random excitation, obtains random test case, comprises: Configuring a preset seed number for the basic test case to obtain a verification test case; Verifying the verification test case; If the verification is passed, an external local(time) function is used to generate a random seed number, and the random seed number is configured for the basic test case to obtain the random test case. 3. CPU test method according to claim 2, is characterized in that, said use external local (time) function to generate random seed number, comprising: Obtain the first system time corresponding to the current moment; Using the local(time) function to convert the first system time into the random seed number. 4. CPU testing method according to claim 3, is characterized in that, described method also comprises: update the random seed number; Generate new test cases, and execute running tests with the new test cases. 5. CPU testing method according to claim 4, is characterized in that, described updating described random seed number, comprises: Obtain the second system time corresponding to the current moment; Using the local(time) function to convert the second system time into an update seed number; The random seed number is replaced with the updated seed number. 6. CPU testing method according to claim 1, is characterized in that, described control CPU carries out described random test case, comprises: Obtaining an operation code from a static memory outside the CPU, so that the CPU executes the random test case according to the operation code. 7. CPU testing method according to claim 6, is characterized in that, described control CPU carries out the step before described random test case, also comprises: Compiling the random test case, obtaining a compilation result and generating a compilation log; storing the compilation result in the static memory; If the execution of the random test case fails, error checking is performed according to the compilation log and the test result. 8. A CPU testing device, characterized in that the device comprises: Building blocks for building basic test cases based on verification scenarios; A configuration module, configured to configure an external source random stimulus for the basic test case to obtain a random test case; Execution module, is used for controlling CPU to carry out described random test case, generates test result; Judging module, for reading the status value of the status register, and judging whether the running test is completed according to the status value; The determining module is configured to judge whether the random test case is executed successfully according to the test result if the running test is completed, and end the running test when it is determined that the random test case is executed successfully. 9. An electronic device, characterized in that it comprises a memory and a processor, the memory stores a computer program, and the computer program executes the CPU according to any one of claims 1 to 7 when the processor runs Test Methods. 10. A computer-readable storage medium, characterized in that it stores a computer program, and the computer program executes the CPU testing method according to any one of claims 1 to 7 when running on a processor.

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