CN115713953A - Semiconductor device, memory chip, integrated circuit product and operation method - Google Patents

Abstract

The invention provides a semiconductor device, a memory chip, an integrated circuit product and an operation method, and belongs to the technical field of semiconductor devices. The semiconductor device includes: n MTJ cells, any MTJ cell includes at least two MTJs; a control unit for performing a write operation and a read operation on the N MTJ cells; the control unit is used for controlling the current of the write operation in a gating mode, writing the operated bit sequence into the MTJ (magnetic tunnel junction) in M MTJ units, wherein M is the bit number of the operated bit sequence; the control unit is used for gating control current of operation, injecting the MTJ in the M MTJ units and controlling the current flowing out of the M MTJ units based on the operation bit sequence, wherein the control duration of the injection or outflow current is the product value of a locking value and unit time; the control unit is used for determining an operation result based on the read-out values of the outflow currents of the M MTJ units. The invention can be used to provide magnetic memories and chips with operational capabilities.

Description

Semiconductor device, storage and calculation chip, integrated circuit product and operation method

technical field

The present invention relates to the technical field of semiconductor devices, in particular to a semiconductor device, an operation method of the semiconductor device, a memory chip and an integrated circuit product.

Background technique

With the vigorous development of chip applications and chip technologies in fields such as big data centers, the Internet of Things, new energy vehicles, and artificial intelligence, massive amounts of unstructured data have been generated, accompanied by a sharp increase in the demand for high-efficiency processing of these data. In the current traditional von Neumann computing architecture, the calculator and the memory are separated, and the data is transmitted through the data bus. However, in chip applications such as the Internet of Things, big data centers, and artificial intelligence, massive data Transmission and processing make the traditional von Neumann computing architecture face the dual challenges of bandwidth and power consumption, which are called "storage wall" and "power consumption wall" respectively.

The technical goal of "storage-computing integration" is to complete the calculation inside the storage array, break the "storage wall" and "power consumption wall", effectively reduce the power consumption of data transfer, and achieve an order of magnitude improvement in computing energy efficiency indicators. Therefore, the technology of realizing chips with integrated storage and computing characteristics (integrated storage and computing chips or storage and computing chips) is considered by the industry to be one of the disruptive technologies in the post-Moore era that solves the bottleneck of von Neumann computing architecture and relieves the pressure of device size reduction. However, limited by the complexity of chip design and manufacturing costs, as well as the lack of application drivers, the early storage-computing integration technology only stayed in the research stage and has not been practically applied. The current integrated storage and calculation technology integrates Static Random Access Memory (SRAM) and logical computing unit into one unit. However, SRAM is actually used as a cache memory, and the logical computing unit completes the actual operation. At the same time, the data storage of SRAM is volatile, and the storage-computing integration technology of this method still faces the problem of static power consumption.

Contents of the invention

The purpose of the present invention is to provide a semiconductor device, a memory chip, an integrated circuit product and an operation method, which avoids the need to complete the calculation operation in the logic calculation unit to perform read and write operations on the semiconductor device for the data in the semiconductor device as a storage element , and then break through the power consumption and chip area bottlenecks of semiconductor devices and storage chips, and realize storage chips with substantial computing capabilities.

In order to achieve the above object, an embodiment of the present invention provides a semiconductor device, which includes:

N MTJ units, any MTJ unit includes at least two MTJs, and N is a positive integer;

a control unit, configured to perform write operations and read operations on the N MTJ units;

The control unit is used to gate-control the current of the write operation, and write the operated bit sequence to the MTJs in the M MTJ units, where M is the number of bits of the operated bit sequence;

The control unit is configured to gatedly control the current for an arithmetic operation to inject into the MTJs in the M MTJ units, and to control the current flowing out of the M MTJ units, either injected or outflowed, based on the operational bit sequence The control duration of the current is the product value of the locking value and the specified unit time;

The control unit is configured to determine an operation result based on the read values of the outgoing currents of the M MTJ units.

Specifically, among the M MTJ units, the control duration of the injection current of the MTJ in each MTJ unit is locked to increase or decrease according to an exponential multiple of 2;

The control duration of the outflow current of the M MTJ units is locked to increase or decrease according to an exponential multiple of 2.

Specifically, the calculation result is expressed as the sum of the read values of the flowing currents of the M MTJ units after the control duration of the currents flowing out of the M MTJ units is all over.

Specifically, the operation result is composed of the sum of the first type of product value, and the first type of product value is the product value of the unit operation value of each MTJ unit and the corresponding lock value in the M MTJ units ;

The unit operation value is composed of the sum of the second type of product value, and the second type of product value is the readout value of the outgoing current of each MTJ in one of the M MTJ units and the corresponding locking The product of values.

Specifically, all MTJs in any MTJ unit share the same bottom electrode, and each MTJ has an independent top electrode.

Specifically, the control unit includes a first control transistor array and a second control transistor array;

The specified transistor in the first control transistor array is used to gatedly control the current flowing out of the bottom electrodes of the M MTJ units, wherein the specified transistor is locked according to the index of 2 between the gated times Doubling up or down;

The specified transistor in the second control transistor array is used to gate-control the current injected into the top electrode of the specified MTJ in the M MTJ units for the operation operation, wherein the specified transistor is selected between the gate time The time is locked to increase or decrease according to the exponential multiple of 2.

Specifically, there are P groups of transistors in the designated transistors in the second control transistor array, and whether each group of transistors is gated is controlled by the operation bit sequence, and P is the number of bits in the operation bit sequence;

The same group of transistors is specifically used to gate-control the current injected into the operation operation to the top electrodes of the MTJs in the M MTJ units recorded with the same bit value, the same bit value being the same bit in the bit sequence to be operated The bit value on the bit.

Specifically, among the M MTJ units, the gating time of the current flowing out of the j-th MTJ unit is 2 ^j-1 T ₁ , where j is 1 to the number of bits in the operation bit sequence, and T ₁ is the specified unit time;

The locking value corresponding to the j th MTJ unit is 2 ^j-1 .

Specifically, in any MTJ unit of the M MTJ units, the gating time of the current injected into the MTJ corresponding to the i-th bit is 2 ^i-1 T ₂ , and i takes 1 to the operated bit The number of bits in the sequence, T ₂ is the specified unit time,

The lock value corresponding to this MTJ is 2 ^i-1 .

Specifically, the rth transistor in the first control transistor array is connected to the bottom electrode of any one of the MTJ units and is also connected to the pth source line, and is used to selectively control the flow out of any one of the MTJs. Unit current, r and p are positive integers.

Specifically, the c-th transistor in the second control transistor array is connected to the top electrode of the corresponding MTJ in any MTJ unit, and is also connected to the n-th bit line and the m-th word line respectively, for The current injected into the corresponding MTJ is gated, and c, n, m are positive integers.

Specifically, the semiconductor device is a spin magnetic memory unit;

The value of the current for the operation operation is smaller than the value of the current for the write operation, and the direction of the current for the operation operation is the same as the direction of the current for the read operation.

Specifically, the control unit includes a CMOS logic unit;

The control unit is used to apply the first VCMA voltage to the top electrode of the MTJ corresponding to the selected bit to be written in the specified MTJ unit in the first cycle of the writing operation, and through the CMOS logic The SOT current of the unit and configuration, the first type of bit value in the bit sequence to be written, and the bit is correspondingly written into the specified MTJ unit;

The control unit is configured to apply a second VCMA voltage to the top electrode of the MTJ corresponding to the selected bit to be written in the designated MTJ unit in the second period of the writing operation, and pass the The CMOS logic unit and the configured SOT current write the second-type bit value in the bit sequence to be written into the specified MTJ unit correspondingly.

Specifically, the CMOS logic unit includes an NOR gate and an AND gate.

Specifically, the control unit is used to apply a VCMA voltage to the top electrode of the MTJ corresponding to the bit to be read during the read operation, control the configured SOT current to inject into the MTJ, and determine where the MTJ flows out. The readout value of the current of the MTJ cell.

Specifically, the control unit is configured to apply a VCMA voltage to the top electrode of the MTJ corresponding to at least two bits to be read in the specified MTJ unit during the read operation, and control the configured SOT current to inject the MTJ, and determine the readout value of the current flowing out of the designated MTJ cell,

The control duration of the injection current increases or decreases exponentially of 2 between the at least two bits.

An embodiment of the present invention provides a semiconductor device, which includes:

a control unit comprising at least 3 transistors, and the at least 3 transistors are all formed on the substrate;

MTJ unit, including at least 2 MTJs, the structures of the at least 2 MTJs are nano-column structures, and the nano-column structures are respectively grown in the regions of at least 2 transistors among the at least 3 transistors;

The at least 2 MTJs have the same bottom electrode, and each MTJ has an independent top electrode;

The top electrodes of the at least two MTJs are respectively connected to the at least two transistors, and the bottom electrodes of the at least two MTJs are connected to one of the at least three transistors.

An embodiment of the present invention provides a method for operating a semiconductor device, wherein the semiconductor device includes N MTJ units and a control unit, any MTJ unit includes at least two MTJs, and N is a positive integer; the control unit is used to control all The N MTJ units perform a write operation and a read operation; the operation method is performed by the control unit, and the operation method includes:

Gating to control the current of the write operation, writing the operated bit sequence to the MTJs in M MTJ units, where M is the number of bits in the operated bit sequence;

Based on the operation bit sequence, strobingly controls the current of the operation operation, injects the MTJ in the M MTJ units, and controls the current flowing out of the M MTJ units, and the control duration of the injection or outflow current is a locking value The product value with the specified unit time;

An operation result is determined based on the read values of the flowing currents of the M MTJ cells.

In another aspect, an embodiment of the present invention provides a storage and calculation chip, which includes the aforementioned semiconductor device.

In yet another aspect, an embodiment of the present invention provides an integrated circuit product, which includes: at least one processor and the aforementioned semiconductor device, where the semiconductor device is connected to the at least one processor; or, the integrated circuit product includes : the aforementioned storage and calculation chip.

The semiconductor device including the MTJ unit of the magnetic tunnel junction (Magnetic Tunnel Junctions, MTJ) in the present invention is a non-volatile memory, and the memory is a magnetic random access memory or a magnetic memory (Magnetoresistive Random Access Memory, MRAM). When the present invention needs to carry out logical calculation on the bit sequence to be operated, first, the control unit performs a write operation on the MTJ unit according to the characteristics of the bit sequence to be operated and the bit sequence to be operated, and then uses the current of the operation operation to flow out through the MTJ unit The readout value of the current obtains the result of the bit operation, and there is no need to read the operated bit sequence and the operated bit sequence into the logic calculation unit (such as the arithmetic logic operation unit and the register file) / do not need to realize the calculation through the calculation unit, the The calculation is specifically a multiplication calculation, which breaks through the bottleneck of power consumption and chip area of semiconductor devices and products under the same data storage capacity.

Other features and advantages of the embodiments of the present invention will be described in detail in the following detailed description.

Description of drawings

The accompanying drawings are used to provide a further understanding of the embodiments of the present invention, and constitute a part of the specification, and are used together with the following specific embodiments to explain the embodiments of the present invention, but do not constitute limitations to the embodiments of the present invention. In the attached picture:

FIG. 1 is a schematic diagram of a stacked structure of an MTJ used in an embodiment of the present invention;

FIG. 2 is a schematic diagram of an exemplary MTJ unit according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an exemplary MTJ unit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of an exemplary array semiconductor device according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an exemplary CMOS logic unit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of an exemplary MTJ unit with 8 MTJs according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of an exemplary MTJ unit performing a write operation in the first cycle according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of an exemplary MTJ unit performing a second cycle write operation according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of an exemplary MTJ unit performing a single-bit read operation according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of an exemplary MTJ unit performing a two-bit read operation according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of an exemplary MTJ unit performing a four-bit read operation according to an embodiment of the present invention;

FIG. 12 is a schematic diagram of an exemplary MTJ unit performing an eight-bit read operation according to an embodiment of the present invention;

FIG. 13 is a schematic diagram of an exemplary MTJ unit performing 2×2 bit-scale operation operations according to an embodiment of the present invention;

FIG. 14 is a schematic diagram of an exemplary MTJ unit performing 4×3 bit-scale operation operations according to an embodiment of the present invention;

FIG. 15 is a schematic diagram of an exemplary integrated circuit product according to an embodiment of the present invention;

FIG. 16 is a schematic diagram of an exemplary integrated circuit product according to an embodiment of the present invention.

Detailed ways

The specific implementation manners of the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation manners described here are only used to illustrate and explain the embodiments of the present invention, and are not intended to limit the embodiments of the present invention.

The applicant found that based on new non-volatile memory technologies (such as resistive change memory, phase change memory, spin magnetic memory, etc.), it is expected to find a solution for a storage-computing integrated chip that truly integrates storage and computing. Among them, spin-transfer torque magnetic random access memory (Spin-Transfer Torque Magnetoresistive Random Access Memory, STT-MRAM) and spin-orbit torque magnetic random access memory (Spin-Orbit Torque Magnetoresistive Random Access Memory, SOT-MRAM) and other spin magnetic The emergence of memory devices and experimental research have brought new hope for the faster development of memory-computing integration technology. The resistive storage principle of the MRAM in the embodiment of the present invention can not only be used to store data, but also can realize computing power.

The structure of an MTJ in an MRAM can consist of two (ferromagnetic) layers (of) ferromagnetic material, and a very thin (of) non-ferromagnetic insulating material (of insulating oxide) layer between the two layers of ferromagnetic material (Oxide Barrier, OB, also remember: oxide barrier layer); the magnetization vector of the two layers of ferromagnetic material layer is basically fixed, called pinned layer (PinnedLayer, PL, also remember: pinned layer), and the other Or the magnetization vector forms a stable direction parallel or antiparallel to the direction of the pinned layer under the action of a magnetic field, which is called the free layer (Free Layer, FL).

As an example of an embodiment of the present invention, as shown in Figure 1, the structure of the MTJ is an MTJ nanopillar (MTJnanopillar, MTJ_np), the ferromagnetic material layer is a cobalt-iron-boron (CoFeB) layer, and the non-ferromagnetic insulating material layer is an oxide Magnesium (MgO) layer, three material layers form a magnetic tunnel junction; the magnetization vector of the pinning layer PL is not easy to reverse and the direction of the magnetization vector is relative to the oxide barrier layer OB, from the far side of the pinning layer PL to the near side Direction, that is, upward in Figure 1. For example, the MTJ nanocolumn is applicable to the STT current switching state mechanism, and when the value of the STT current I _STT injected into the MTJ nanocolumn is greater than the value of the switching threshold current I _C0 , the magnetization vector of the free layer FL is easily flipped. If the direction of the current I _STT is from the free layer FL to the direction of the pinned layer PL, so that the direction of the magnetization vector of the free layer FL is opposite to the direction of the magnetization vector of the pinned layer PL, the MTJ nanocolumn is in antiparallel ( Anti-Parallel, denoted as: AP) state, if the direction of the current _ISTT is the same as the direction of the magnetization vector of the pinning layer PL, so that the direction of the magnetization vector of the free layer FL is also the direction of the magnetization vector of the pinning layer PL Similarly, at this time, the MTJ nanocolumn is in a parallel (Parallel, denoted as: P) state, therefore, the magnetization vector of the entire MTJ has two states: parallel and antiparallel. Correspondingly, MTJ exhibits two types of resistance, high resistance (corresponding to the AP state) and low resistance (corresponding to the P state), and the storage of single-bit data can be realized by using the resistance change between these two states, such as The bit value (ie logical value) of the data corresponding to the P state is "0", and the bit value (ie logical value) of the data corresponding to the AP state is "1", as shown in Table 1 below.

Table 1 Relationship table between MTJ state and logic value

MTJ status logical value AP status 1 P state 0

It can be understood that this is a configurable example rather than a limited implementation. If a transistor for controlling data reading and writing is added (as a logic control circuit), an MRAM storage unit is formed. In the embodiment of the present invention, for the purpose of brevity, "MTJ" may refer to a stacked body having a magnetic tunnel junction function, and the stacked body may have an electrode layer; the above-mentioned STT current will be used as a component current of the SOT current in the following content.

MRAM has the advantages of non-volatility, high integration, low power consumption, and high durability. Compared with the reading and writing speed of SRAM/Dynamic Random Access Memory (DRAM), the MRAM storage unit is a resistive device, which is more suitable for reading and writing data under current drive. MRAM also has the characteristics of fast reading and writing, and at the same time , Consistent with Flash flash memory, the data of MRAM is not easy to lose when power is off. The silicon chip area occupied by the unit storage capacity of MRAM has advantages over SRAM, NOR Flash/embedded NOR Flash. The read and write latency of MRAM is close to that of top-level SRAM, and MRAM has better power consumption performance among various memory and memory technologies. The most prominent thing is that the manufacturing process of MRAM is compatible with the standard CMOS semiconductor process, while the manufacturing process of DRAM/Flash is incompatible with the standard CMOS semiconductor process. MRAM can be integrated into the same chip with the logic control circuit. Application prospect and value. In view of this, the embodiment of the present invention will provide an integrated solution for MRAM storage and computing.

Example 1

An embodiment of the present invention provides a semiconductor device, which may include:

N MTJ units, any MTJ unit includes at least two MTJs, and N is a positive integer;

a control unit, configured to perform write operations and read operations on the N MTJ units;

The control unit is used to selectively control the current of the write operation, and write the operated bit sequence to the MTJs in M MTJ units, where M is the number of bits of the operated bit sequence and M≤N;

The control unit is configured to gatedly control the current for an arithmetic operation to inject into the MTJs in the M MTJ units, and to control the current flowing out of the M MTJ units, either injected or outflowed, based on the operational bit sequence The current control duration is the product value of the (configured) locking value and the specified unit time; the control unit is used to determine the operation result based on the readout values of the outgoing currents of the M MTJ units.

In an embodiment of the present invention, the semiconductor device is a non-volatile memory unit, and the semiconductor device is also a spin magnetic memory unit/spin-electron device. The MTJ unit is a physical, spin magnetic storage medium; there are at least two MTJs in any MTJ unit, for example, 2 MTJs, 4 MTJs, 8 MTJs, 16 MTJs, etc., the structure of each MTJ in the MTJ unit It can be a stacked structure, such as nanopillars; in some application scenarios, the number of MTJs in any MTJ unit can meet 2 ^a or can be an even number, a=1, 2, 3..., and in some customized application scenarios , the number of MTJs in any MTJ unit can be a customized number, such as an odd number or a specified number. The control unit may include a plurality of transistors, the manufacturing process of the transistors is compatible with the manufacturing process of the MTJ in the MTJ unit, and the transistors can connect each MTJ to a word line (Wordline, which can be marked as WL) and a bit line (Bitline, which can be marked as WL). Note BL), used to perform instruction operations on each MTJ unit, instruction operations may include write (instruction) operations and/or read (instruction) operations, so that any MTJ unit and transistor can form a memory unit, the A memory cell is a unit (bit-cell) that records a binary value/bit value, and any MTJ in the memory cell can correspond to a specified bit (associated with a word line and a bit line), so that any two of the memory cells The bits corresponding to MTJ have high and low characteristics.

All MTJs in any (any) MTJ unit share the same bottom electrode, each MTJ has an independent top electrode, the bottom electrode is the bottom electrode layer, and the top electrode is the top electrode layer. Both the bottom electrode and the top electrode can be metal layers, and the material of the metal layer can be metal materials such as gold or copper, or conductive materials containing metal elements, and the materials of the two electrode layers can be the same or selected independently. The bottom electrode is in contact with the free layer of any MTJ in the MTJ unit, or the distance between the bottom electrode and the free layer of any MTJ is smaller than the distance between the bottom electrode and the pinning layer of any MTJ, that is, the bottom electrode There may be a bottom functional layer structure between the free layer of any one MTJ, such as a layer structure for buffering (facilitating manufacture)/regulating magnetization vector/adjusting the exchange bias field, etc. (the exchange bias field may also be at the bottom electrode generated); the top electrode is in contact with the pinning layer of any one of the MTJs in the MTJ unit, or the distance between the top electrode and the pinning layer of any one of the MTJs in the MTJ unit is smaller than that of the top electrode and any one of the MTJ units The distance between the free layer of the MTJ, that is, the distance between the top electrode and any one of the pinned layers of the MTJ may have a top functional layer structure, such as a layer structure for buffering. The bottom electrode may also be in contact with designated substrate regions. It can be understood that there is no difference between the top electrode and the bottom electrode. In the embodiment of the present invention, relative to the layer structure of the MTJ, the direction from the free layer to the pinned layer can be the direction of the top, and the direction from the pinned layer to The orientation of the free layer may be the orientation of the bottom, which is only used as a shorthand for the convenience of explanation.

表示MTJ状态为AP状态和P状态中任意一者，采用单向箭头“↑”表示钉轧层的状态不易变化特点，自由层和钉轧层之间是无箭头的阻挡层，并采用沿垂直于自由层指向钉轧层的方向较短的灰度区域表示顶电极(层)，采用沿垂直于该方向较长的灰度区域表示底电极(层)。MTJ_L的钉轧层PL_L与顶电极TE_L独立接触，MTJ_R的钉轧层PL_R与顶电极TE_R独立接触，MTJ_L的自由层FL_L和MTJ_R的自由层FL_L均与底电极BE接触，共享底电极BE，1个MTJ单元可以包括1个底电极BE，在沿底电极BE的延展方向(也是沿垂直于自由层指向钉轧层的方向)，2个MTJ在底电极BE上的接触区域之间具有指定的间隔距离。此时，控制单元可以包括3个晶体管，顶电极TE_L和顶电极TE_R分别与晶体管M_L、晶体管M_R连接，底电极BE分别与晶体管M₀、接地端连接。其中，MTJ_L的顶电极TE_L与MTJ_R的顶电极TE_R，MTJ_L的钉轧层PL_L与MTJ_R的钉轧层PL_R，MTJ_L的阻挡层OB_L与MTJ_R的阻挡层OB_R，MTJ_L的自由层FL_L与MTJ_R的自由层FL_R，均是不接触的、没有连接的。On the basis of the above content, as the first exemplary MTJ unit structure example disclosed in the present invention, referring to FIG. pinned layer, and also includes the top and bottom electrodes, in Figure 2, with double arrows

Indicates that the MTJ state is either AP state or P state, and the one-way arrow "↑" indicates that the state of the pinned layer is not easy to change. There is a barrier layer without arrows between the free layer and the pinned layer, and the The shorter gray-scale area in the direction from the free layer to the pinned layer represents the top electrode (layer), and the longer gray-scale area in the direction perpendicular to this direction represents the bottom electrode (layer). The pinned layer PL _L of MTJ _L is in independent contact with the top electrode TE _L , the pinned layer PL _R of MTJ _R is in independent contact with the top electrode TE _R , the free layer FL _L of MTJ _L and the free layer FL _L of MTJ _R are both in contact with the bottom electrode The electrodes BE are in contact with each other and share the bottom electrode BE. One MTJ unit can include one bottom electrode BE. Along the extension direction of the bottom electrode BE (also along the direction perpendicular to the free layer and pointing to the pinning layer), two MTJs are in the direction of the bottom electrode BE. The contact areas on the BE have a specified separation distance between them. At this time, the control unit may include three transistors, the top electrode TE _L and the top electrode _TER are respectively connected to the transistor _ML and the transistor _MR , and the bottom electrode BE is respectively connected to the transistor M ₀ and the ground terminal. Among them, the top electrode TE _L of MTJ _L and the top electrode TE _R of MTJ _R , the pinning layer PL _L of MTJ _L and the pinning layer PL _R of MTJ _R , the barrier layer OB _L of MTJ _L and the barrier layer OB of MTJ _{R R} , the free layer F _L of MTJ _L and the free layer F _R of MTJ _R are not in contact and connected.

On the basis of Fig. 2, as the second exemplary MTJ unit structure example disclosed in the present invention, see Fig. 3, one MTJ unit may include 4 MTJs, MTJ ₀₀ ~ MTJ ₀₃ , top electrodes TE ₀₀ ~ TE ₀₃ They are respectively connected to the transistors M ₀₀ ~ M ₀₃ , and the four contact areas of the free layers FL ₀₀ ~ FL ₀₃ on the bottom electrode BE are arranged at equal intervals along the extension direction of the bottom electrode BE, which is conducive to the implementation of multi-bit read and write operations . In the embodiment of the present invention, for the purpose of brevity, the distinguishing text numbers "first", "second", etc. are not added. For example, MTJ ₀₀ to MTJ ₀₃ can respectively represent: first (having a magnetic tunnel junction function) The stacked body MTJ ₀₀ , the second stacked body MTJ ₀₁ , the third stacked body MTJ ₀₂ and the fourth stacked body MTJ ₀₃ ; the top electrodes TE ₀₀ to TE ₀₃ can respectively represent: the first top electrode TE ₀₀ , the second top electrode TE ₀₁ , the third top electrode TE ₀₂ and the fourth top electrode TE ₀₃ , etc., can be understood according to this in the embodiments of the present invention.

In an exemplary example disclosed by the present invention, a semiconductor device has a plurality of MTJ units arranged, and the number and arrangement of MTJs in each MTJ unit are the same, and the MTJ unit may include 8 MTJs, and the 8 MTJs The MTJs may share a bottom electrode, the bottom electrode may be in the shape of strips, and the eight MTJs are arranged at equal intervals along the extending direction of the bottom electrode. There is at least one transistor in the first control transistor array in the control unit, and the at least one transistor connects the bottom electrode of the MTJ unit to the source line (Source Line, SL); the second control transistor array in the control unit has 8 transistors, the The 8 transistors can be the first control transistor group, and the 8 transistors can correspond to the aforementioned 8 MTJs respectively, and any one of the 8 transistors connects the top electrode of the MTJ corresponding to the arbitrary transistor to the word lines and bit lines.

In this example, the aforementioned at least one transistor may be the rth transistor, one end of the strip-shaped bottom electrode may be connected to the pth source line through the rth transistor, and the rth transistor is controlled by a specified control signal , the control signal can be generated by a signal generator, the rth transistor can be used to selectively control the current flowing out of each MTJ unit, and the pulse width of the control signal can be used to lock the control duration of the rth transistor; in the aforementioned semiconductor device In the MTJ unit adjacent to the aforementioned MTJ unit arrangement position, the bottom electrode of the adjacent MTJ unit can be connected to the p-1th source line through the r-1th transistor, or can be connected to the p-1th source line through the r+1th transistor Connect to the p+1th source line. The aforementioned eight MTJs can be regarded as being arranged in relative order in the extension direction of the bottom electrode, for example, the first MTJ, the second MTJ, ..., the c-th MTJ, ..., the eighth MTJ, the aforementioned eight Among the MTJs, the c-th MTJ corresponds to the c-th transistor, and the top electrode of the c-th MTJ is connected to the n-th bit line through the c-th transistor, and is also connected to the m-th word line. The c-th transistor is controlled by The mth word line and the c-1th transistor are controlled by the m-1th word line or the c+1th transistor is controlled by the m+1th word line, the c-1th transistor, the cth The transistor and the c+1th transistor etc. can be used to selectively control the current injected into each MTJ, and the pulse width of the control signal on the word line can be used to lock the control duration of the transistor connected to the corresponding word line; the second in the control unit There are another 8 transistors in the control transistor array, and the other 8 transistors can be the second control transistor group, and the top electrode of the cth MTJ in the adjacent MTJ unit is connected with the cth transistor in the second control transistor group. The n+1th bit line or the n-1th bit line is connected to the mth word line, and the cth transistor in the second control transistor group is controlled by the mth word line. Among them, r, p, c, n, m are positive integers. The corresponding relationship between components and bits in the semiconductor device is shown in Table 2 below.

Table 2 Correspondence between components and bits in semiconductor devices

Two MTJ units in a semiconductor device are shown in Table 2, BL _n represents the nth bit line (in some cases, the subscript starts from 0, then BL ₀ represents the first bit line, BL _n represents the n+th 1 bit line), WL _m represents the m-th word line, SL _p represents the p-th source line, MTJU _M represents the M-th MTJ unit, MTJ _Mc represents the c-th MTJ in the M-th MTJ unit (each MTJ The number of MTJs in the unit is at least 2), Q _r represents the transistor in the first control transistor array corresponding to the Mth MTJ unit (that is, the rth transistor), and Q _Mc represents the transistor corresponding to the Mth MTJ unit The transistor in the second control transistor array (that is, the c-th transistor), CMc represents the bit corresponding to the c-th MTJ in the M-th MTJ unit; and BL _n-1 represents the n-1th bit line and is the same as BL _n is adjacent (subscript ±1), MTJU _M-1 indicates the M-1th MTJ unit and is adjacent to MTJU _M , and so on, the correspondence between more components in the semiconductor device can be obtained (/corresponding) relationship and the corresponding (/corresponding) relationship with bits. It can be understood that the subscript of the MTJ indicates the positioning position area of the MTJ in the semiconductor device, and the positioning position area can be jointly determined by the corresponding bit line and the word line, for example, the word line can represent the column address information of the corresponding MTJ, And let the bit line represent the row address information of the corresponding MTJ, or, in more cases, let the word line represent the row address information of the corresponding MTJ, and let the bit line represent the column address information of the corresponding MTJ.

As an example of an exemplary array semiconductor device disclosed in the present invention, as shown in Fig. 4 (the transistor identifier is rewritten as Q), the semiconductor device may include M MTJ units, and each MTJ unit may include 8 MTJs, the MTJs Arranged at equal intervals between them, combined with Table 2, the corresponding relationship between each MTJ and bits, transistors, word lines, bit lines, and source lines can be observed. For MTJU ₀ to MTJU _M , MTJ ₀₀ to MTJ ₀₇ in MTJU ₀ , MTJ ₁₀ to MTJ ₁₇ in MTJU ₁ ... MTJ _M0 to MTJ _M7 in MTJU _M. The M MTJ units are respectively connected to source lines (SL ₀ -SL _p ) through r transistors in the first control transistor array, Q ₀ -Q _r . The MTJ is connected to the corresponding bit line and word line through the corresponding transistors (Q ₀₀ ~ Q _M7 ) in the second control transistor array to form a memory unit. The bits are C00 ~ CM7. Consistently, for example, the MTJ ₁₁ is connected to the second bit line _BL1 through the transistor _Q11 and the gate of the transistor _Q11 is also connected to the second word line _WL1 , and the bit corresponding to the MTJ ₁₁ is C11. Wherein, the transistors in the first control transistor array and the second control transistor array are strobed and controlled by a specified signal source, and the gate time of the transistor is controlled by the pulse width. Each signal source can be realized by a signal generator, or the transistor can be The gate is connected to the port that generates the voltage signal.

The magnetic anisotropy of the semiconductor device of the embodiment of the present invention is regulated by voltage, and the MTJs in the semiconductor device are voltage-regulated magnetic anisotropy (Voltage Control Magnetic Anisotropy, VCMA) MTJs, denoted as VCMA-MTJ, that is, relative The pinning layer PL of the MTJ passes through the transistor in the second control transistor array corresponding to the MTJ and the bit line connected to the transistor. The MTJ can be connected to an external voltage V _b (applied on the bit line corresponding to the MTJ), and the specific external voltage V _b makes the magnetization direction of the free layer FL of the MTJ easier/uneasy to reverse after passing a current . In the embodiment of the present invention, the following configurations are possible:

Set the AP state: when the applied voltage V _b is higher than the critical flip voltage V _c and the applied voltage V _b is a forward voltage, the configured SOT current (component current) passes through the MTJ to switch the state of the MTJ to the AP state;

Set P state: when the applied voltage V _b is higher than the critical flip voltage V _c and the applied voltage V _b is a negative voltage, the configured SOT current (component current) passes through the MTJ to switch the state of the MTJ to the P state;

Read MTJ state: When the applied voltage V _b is lower than the critical flipping voltage V _c and the applied voltage V _b is a negative voltage, or when the applied voltage V _b is 0, the configured SOT current (component current) passes through the MTJ , the state of the MTJ is not easy to flip, that is, it remains unchanged from the state before the applied voltage V _b is applied.

Positive and negative are relative. For example, the positive voltage is connected to the pinning layer PL of the MTJ with a voltage value greater than 0, and the negative voltage is connected to the pinned layer PL of the MTJ with a voltage value of less than 0. The magnetization vector direction of the pinned layer PL is the direction from the free layer FL to the pinned layer PL.

In the writing operation of the embodiment of the present invention, in some application scenarios, the aforementioned SOT current may be injected into the MTJ unit through the bottom electrode of the MTJ unit and its component current flows out from the top electrode of the MTJ, the state of the MTJ is switched to the AP state, Or its component current is injected by the top electrode of the MTJ and flows out from the bottom electrode of the MTJ cell, the state of the MTJ is switched to the P state; the value of the SOT current in the read operation of the embodiment of the present invention can be smaller than the write The value of the SOT current for the operation, and the SOT current for the read operation is a spin-directional current whose component current is injected by the top electrode of the MTJ and flows out from the bottom electrode of the MTJ unit, and the SOT current for the write operation can change the state of the MTJ, The SOT current for a read operation cannot change the MTJ state.

The aforementioned control unit may also include a CMOS logic unit. The manufacturing process of the CMOS logic unit is also compatible with the manufacturing process of the MTJ unit. The CMOS logic unit can function as a gate control for writing operations, and can be placed in the aforementioned control unit of the semiconductor device. The CMOS logic unit may include an NOR gate and an AND gate, and both the NOR gate and the AND gate may have dual input terminals. The XOR gate and the AND gate may correspond to a specified bit, and the specified bit may be a bit corresponding to the same word line, and the XOR gate and the AND gate may constitute a pair of elements. In some application scenarios, bit C(M-1)c and bit CMc etc. corresponding to the mth word line WL _m ; the quantity of MTJ in the storage unit or the second control transistor array is used to control each storage The number of transistors in a cell is the same as the number of pairs of elements consisting of NOR gates and AND gates.

For a pair of NOR gates and AND gates, the input terminals of the NOR gate can respectively receive the control (command/) signal of the first cycle or the second cycle of the write operation (mark W1/0 signal, or write signal) and Receive the bit value on the specified sequence bit of the bit sequence to be written; the input terminal of the AND gate can receive the control (command/) signal of the VCMA of the write operation respectively, record the VCMA voltage, the size and the positive and negative directions of the VCMA voltage respectively Depending on the magnitude and positive and negative direction of the applied voltage V _b applied on the bit line, the control duration of the VCMA voltage depends on the voltage signal of the configured pulse width, which is recorded as the WPD1 signal, and the AND gate The input terminal of the NOR gate also receives the output value/signal of the NOR gate, is connected with the output terminal of the NOR gate, and the output terminal of the AND gate is connected to a specified word line (the output value/signal of the NOR gate is connected to A designated word line) is used for gating and controlling the column where the MTJ corresponding to the word line is located. It will be appreciated that the WPD1 signal provides control over the duration of the applied voltage _Vb applied to the MTJ. The WPD1 signal may include low-level (logic value 0) and high-level (logic value 1) voltage signals, and the W1/0 signal may also include low-level and high-level voltage signals.

The writing operation in the embodiment of the present invention may be referred to as a "double cycle 1/0" writing operation for short.

In the first write operation example, in the first cycle (time) of the write operation, when the W1/0 signal is set to low level (logic value 0) and the WPD1 signal corresponding to the specified bit line is set to High level (logic value 1), the magnitude of the negative applied voltage V _b is higher than the critical flipping voltage V _c , at this time the applied WPD1 signal and the applied voltage V _b are the first VCMA voltage applied, through the CMOS logic unit and The configured SOT current (the component current is injected from the top electrode of each MTJ) can write the first type of bit value in the bit sequence/data to be written, the first type of bit value can be a logic value 0, and the bit is correspondingly written into the memory cell In the MTJ of the MTJ unit specified in ; in the second cycle of the write operation, when the W1/0 signal is set to high level (logic value 1) and the WPD1 signal corresponding to the specified bit line is set to high level ( Logical value 1), the magnitude of the forward applied voltage V _b is higher than the critical flip voltage V _c , at this time the applied WPD1 signal and the applied voltage V _b are the second VCMA voltage applied, passing through the CMOS logic unit and the configured SOT current (The component current flows out from the top electrodes of each MTJ), and the second type of bit value to be written in the bit sequence/data can be written into the MTJ of the memory cell correspondingly. The CMOS logic unit plays a role in selecting the MTJ corresponding to the bit to be written in different periods of the write operation and matching the currently written bit value in the bit sequence to be written. The first period and the second period can be configured based on a reference clock or pulse width.

In the second write operation example, in the first cycle of the write operation, when the W1/0 signal is set to high level (logic value 1) and the WPD1 signal corresponding to the specified bit line is set to high level (logic value 1), the magnitude of the positive applied voltage V _b is higher than the critical flip voltage V _c , the WPD1 signal applied at this time and the applied voltage V _b is the first VCMA voltage applied, through the CMOS logic unit and the configured SOT The current (the component current flows out from the top electrodes of each MTJ) can write the first type of bit value in the bit sequence/data to be written, the first type of bit value can be a logic value 1, and the bit is correspondingly written into the specified bit in the storage unit In the MTJ of the MTJ cell; in the second cycle of the write operation, when the W1/0 signal is set low (logic value 0) and the WPD1 signal corresponding to the specified bit line is set high (logic value 1 ), the magnitude of the negative applied voltage V _b is higher than the critical flipping voltage V _c , the WPD1 signal applied at this time and the applied voltage V _b is the second VCMA voltage applied, through the CMOS logic unit and the configured SOT current (component current Injected from the top electrodes of each MTJ), the second type of bit value to be written in the bit sequence/data can be written, the second type of bit value can be logic value 0, and the bit is correspondingly written into the MTJ of the memory cell.

As an exemplary array structure of a CMOS logic unit matching the aforementioned example of an array-type semiconductor device, referring to FIG. 5 , the CMOS logic unit may include 8 pairs of paired elements consisting of an NOR gate and an AND gate. For example, in the first pair of elements, the input terminal of the NOR gate XNOR0 receives the W1/0 signal and the bit value corresponding to the specified bit D0 in the data bit; the AND gate AND0 receives the output value of the output terminal of the NOR gate XNOR0 and the WPD1 signal, and the AND gate The output value C:0 of the AND0 output terminal will be used to gate the first word line WL ₀ , and the gates of the other pairs of elements in the CMOS logic unit can be obtained similarly, and will not be repeated here.

In the above-mentioned write operation, the voltage drop directions of both the first VCMA voltage and the second VCMA voltage can change the energy barrier of the MTJ. The VCMA voltage is added to the top electrode of the MTJ. In this configuration, by configuring the magnitude of the SOT current, adjust the magnitude of the VCMA voltage applied to the target MTJ (ie, the MTJ corresponding to the bit to be written or read), then A write operation or the subsequently mentioned read operation can be selectively performed on the target MTJ. The selection of the target MTJ is realized by switching transistors in the aforementioned first control transistor array and the second control transistor array. In the read operation, the MTJ energy barrier is high when the reverse and small VCMA voltage is applied (that is, the applied voltage V _b is negative and lower than the voltage V _c ), and the SOT current is not enough to drive It flips, and the corresponding MTJ state will not change; in the write operation, the MTJ energy of positive/negative and larger VCMA voltage (that is, the applied voltage V _b is positive or negative and higher than) is applied The potential barrier is low, the SOT current can drive it to flip to a specified state, and the corresponding MTJ state will change. In the embodiment of the present invention, the bit correspondence refers to the high and low characteristics of the specified bit in the bit sequence to be written in the bit sequence to be written, and the bit corresponding to the specified MTJ of the storage unit is in the corresponding position of the storage unit The high and low characteristics of the bits in the bits corresponding to all MTJs are consistent/uniquely corresponding, that is, the specified bit and the specified MTJ are bit-corresponding/bit-corresponding, and the specified MTJ can be written to the specified bit. The bit value of is achieved through the selective switching of each transistor. It is worth noting that the writing operation of the semiconductor device in the embodiment of the present invention may not require an erasing operation, may not require a separately configured erasing operation, and the writing operation does not need to pay attention to the state of the MTJ before the writing operation.

As an exemplary writing operation scenario of the foregoing array-type semiconductor device example, the bit sequence D[7:0] to be written is 10110100, and the bits are sequentially marked as D0 to D7. If the bit sequence to be written is written into the second MTJ unit MTJU ₁ , as shown in Figure 6, the MTJ state in MTJU ₁ is either AP state or P state, and the extension along the bottom electrode BE ₁ of MTJU ₁ In the direction, the MTJ ₁₇ farthest from the second transistor _Q1 in the first control transistor array is the lowest bit, and according to the aforementioned second write operation example, it is configured to write a logic value of 1 in the first cycle (the first type of bit value at this time), write logic value 0 (the second type of bit value at this time) in the second cycle, then first to (corresponding to the existence of "1" in the bit sequence to be written) MTJ ₁₀ , MTJ ₁₂ , MTJ ₁₃ , and MTJ ₁₅ perform a write operation, and then perform a write operation on MTJ ₁₁ , MTJ ₁₄ , MTJ ₁₆ , and MTJ ₁₇ (corresponding to the "0" existing bit in the bit sequence to be written). Performing the write operation of the foregoing semiconductor device may include:

W1) Providing the first VCMA voltage VCMA1 to MTJU ₁ :

Based on the specified row and column address signals, select MTJU ₁ (to latch the address information in the row and column address signals) through the row and column decoder, connect the second bit line BL ₁ to the positive applied voltage V _b , and set the WPD1 signal to is high level;

W2) Configure the signal size, and select the word line based on the bit sequence to be written and the configured signal:

As shown in Figure 7, set the W1/0 signal to high level (logic value 1), and simultaneously input D0 to D7 in the bit sequence D[7:0] to be written into 8 pairs of the same Each NOR gate in the OR gate and the AND gate connects the output signals C: 0 ~ C: 7 of the 8 AND gates of the CMOS logic unit to the word lines WL ₀ ~ WL ₇ . The paired NOR gate receives the bit value of bit D0) output signal C:0 is connected to the first word line WL ₀ , and the AND gate (the paired NOR gate receives the bit value of bit D1) outputs signal C : 1 is connected to the 2nd word line WL ₁ ... the output signal C: 7 of the AND gate (the paired NOR gate receives the bit value of the bit position D7) is connected to the 8th word line WL ₇ ;

W3) Pass the selected word line, gate the transistor, and perform the first cycle of the write operation to write:

The first word line WL 0 , the third word line WL ₂ , the fourth word line WL ₃ , and the sixth word line selected by the output signals C:0, C:2, C: ₃ , and C:5 at this time The line WL ₅ gates the first transistor Q ₁₀ , the third transistor Q ₁₂ , the fourth transistor Q ₁₃ , and the sixth transistor Q _{15 in the second control transistor array, and at the same time turns on the second transistor Q 15} in the first control transistor array. The gate of a transistor Q ₁ is connected to the WPD2 signal, and the WPD2 signal is set as an open signal of a specified pulse width (logic value 0 or 1, depending on the type of the transistor Q ₁ ), the specified pulse width is the first period, and In one cycle, there is an SOT current in the first direction at the bottom electrode BE ₁ of MTJU ₁ , and the first direction is from the MTJ ₁₇ of the lowest bit (the contact area on the bottom electrode BE ₁ ) to the MTJ ₁₀ of the highest bit (in the bottom electrode BE 1). The direction of the contact area on the _electrode BE ₁ ), or the direction of flowing out of the MTJU 1 from the bottom electrode BE ₁ of the MTJU ₁ through the second transistor Q ₁ , the component currents of the SOT current pass through the MTJ ₁₀ , MTJ ₁₂ , MTJ ₁₃ , and MTJ ₁₅ respectively , and the direction of the component currents is from the free layer to the direction of _the pinning layer ₍ indicated by the dotted arrow in Figure 7, which _is also the direction of flowing _out of the top electrode). The state of is set as the AP state, thereby completing the recording of the first type of bit value in the bit sequence to be written;

W4) Provide the second VCMA voltage VCMA2 to the MTJU ₁ , that is, apply a negative external voltage V _b , and set the WPD1 signal to a high level. Configure the signal size, and select the word line based on the bit sequence to be written and the configured signal:

Set the W1/0 signal to low level (logic value 0), and keep D0 to D7 in the aforementioned bit sequence D[7:0] to be written and simultaneously input them to 8 pairs of NOR gates and ANDs in the CMOS logic unit Each of the NOR gates in the gate connects the output signals C: 0 to C: 7 of the 8 AND gates of the CMOS logic unit to the word lines WL ₀ to WL ₇ ;

W5) Through the selected word line, gate the transistor, and perform the second cycle of the write operation to write:

As shown in Figure 8, the second word line WL ₁ , the fifth word line WL ₄ , the seventh word line WL ₆ , The eighth word line WL ₇ gates the second transistor Q ₁₁ , the fifth transistor Q ₁₄ , the seventh transistor Q ₁₆ , and the eighth transistor Q ₁₇ in the second control transistor array, and at the same time switches the first control The gate of the second transistor Q ₁ in the transistors is connected to the WPD2 signal, and the WPD2 signal is set as an on (voltage) signal with a specified pulse width. The specified pulse width is the second period. In the second period, the bottom electrode of MTJU ₁ BE ₁ has SOT current in the second direction, the second direction is from the MTJ ₁₀ of the highest bit (the contact area on the bottom electrode BE ₁ ) to the MTJ ₁₇ of the lowest bit (the contact area on the bottom electrode BE ₁ ) direction, or the direction in which the second transistor Q ₁ is injected into the bottom electrode BE ₁ of MTJU ₁ , the component currents of the SOT current pass through MTJ ₁₁ , MTJ ₁₄ , MTJ ₁₆ , and MTJ ₁₇ respectively, and the directions of the component currents are all determined by the pinning The layer points to the direction of the free layer (indicated by the dotted arrow in Figure 8, which is also the direction of the injection top electrode), and after the end of the second period, the states of MTJ ₁₁ , MTJ ₁₄ , MTJ ₁₆ , and MTJ ₁₇ are set to P state, thereby completing the pending The record of the second type of bit value written in the bit sequence can be obtained in the following Table 3.

Table 3 The relationship table between MTJ state and logic value in MTJU ₁ after write operation

MTJU₁ MTJ₁₀ MTJ_n MTJ₁₂ MTJ₁₃ MTJ₁₄ MTJ₁₅ MTJ₁₆ MTJ₁₇ MTJ status AP P AP AP P AP P P logical value 1 0 1 1 0 1 0 0

It should be noted that the current of the aforementioned writing operation is the SOT current and its component currents in the writing operation. The steps W1) to W5) of the write operation performed on MTJU1 are used in the above content, and the same applies to the rest of the MTJ units. In the semiconductor device, one or more MTJ units can perform the write operation step W1 synchronously or asynchronously. ) to step W5). The aforementioned SOT current in the first direction and the SOT current in the second direction can be driven and generated by the second source line SL ₁ . The transistor Q1 is connected to the bottom electrode _BE1 and also connected to the source, the source can be connected to a current source or a voltage source, and the gate is controlled by the WPD2 signal. The transistors in the first transistor array can be configured according to this. In some application scenarios, The sources of the array devices are arranged in one or more specified location areas. The aforementioned first period and the second period may be equal in duration, or each may have an independent duration configuration. It can be understood that, alternatively, after configuring according to the aforementioned first write operation example, in the first cycle, the W1/0 signal can be configured to be set to a low level, so as to realize the "0" in the bit sequence to be written Write into the MTJ unit, and then in the second cycle, you can configure the W1/0 signal to be set to a high level, so as to write "1" in the bit sequence to be written into the MTJ unit. The relationship between the bit sequence to be written, the signal configuration and the output signal can be seen in Table 4 below.

Table 4 Relationship table between bit sequences and signals

In this table 4, Dx represents any bit in the bit sequence to be written, and x is 0, 1, 2, 3, etc.; C: x represents the output signal of the CMOS logic unit corresponding to Dx, 1 represents the enable signal, and 0 Indicates a shutdown signal.

On the basis of the aforementioned semiconductor device comprising 8 MTJ units of the MTJ unit, as an exemplary single-bit read operation scenario of this example, performing the read operation of the aforementioned semiconductor device may include:

R1) Select MTJU ₁ through the row and column decoder based on the designated row and column address signals. As shown in FIG. 9 , the bottom electrode _BE1 is connected to the source through the transistor Q1 in the first control transistor array, and the bottom electrode _BE1 is also connected to the ground terminal. Connect the second bit line BL ₁ to the pre-charge sense amplifier (Pre-Charge Sense Amplifier, PCSA or SA for short), and the second bit line BL ₁ is pre-charged to the specified potential V _DD by PCSA , and then stop charging. It can be understood that multiple MTJ units can share the same PCSA, and the PCSA also includes multiple transistors. Multiple transistors can form a differential circuit, and the differential circuit is connected to the potential V _DD . In some transistor connection configuration scenarios, the differential circuit can also be connected to the source The line SL ₁ is connected and can also be connected with the ground terminal, the differential circuit can convert the current pulse into a voltage pulse, and the PCSA can also include a counter connected with the output terminal of the differential circuit for counting the voltage pulse, which is not shown in Figure 9 out.

R2) Provide a small, reversed VCMA voltage or no VCMA voltage to MTJU _1. Based on the specified row and column address signals, the word line is selected by the row and column decoder (applied open signal) and simultaneously (applied open signal) Through the transistor in the second control transistor array corresponding to the MTJ in MTJU ₁ , the MTJ is the MTJ corresponding to the bit to be read, for example, the MTJ corresponding to the bit to be read is MTJ ₁₂ , select the third a word line WL ₂ and select the corresponding transistor Q ₁₂ and transistor Q ₁ at the same time;

R3) After _the transistor _Q1 is turned on by the WPD2 signal, and the transistor _Q12 is selected by the third word line WL2, the generated current passes through PCSA to the second bit line _BL1 , and is injected into the MTJ ₁₂ through the transistor _Q12 , forming a component current injected into the MTJ ₁₂ , the SOT current flowing out of the MTJ ₁₂ passes through the bottom electrode BE ₁ , passes through the transistor Q ₁ , and flows out from the source before the second source line SL ₁ is grounded. The PCSA obtains the readout value by comparing the value of the component current with the value of the reference current to determine the state of the MTJ ₁₂ , and the current direction on the bottom electrode BE ₁ is that the contact area of the MTJ ₁₂ on the bottom electrode BE ₁ points to the MTJ ₁₀ on the bottom electrode BE ₁ on the orientation of the contact area. Since the high and low resistance states of MTJ ₁₂ produce different voltage drops on the second bit line BL ₁ , the magnitudes of the currents injected into or out of MTJ ₁₂ are also different, and the pair (injected or) a readout of the current flowing out of the MTJ ₁₂ . Among them, the judgment of the final output logic value 0 and 1 is determined by the PCSA according to the comparison between the value of the injected or outgoing current and a configured reference current value. The value of the reference current is configured to take the current value of the AP state and the P state. The current value between the current value of the AP state and the current value of the P state is relative to the same voltage value. If the read operation is performed after the aforementioned write operation, the state of the MTJ ₁₂ read at this time is the AP state, that is, the bit C12 stores a logic value of 1. In some application scenarios, the MTJ unit or MTJ used for reference can be configured, and the outflow or injection current of the MTJ unit or MTJ has the value characteristics of the reference current, thereby obtaining the reference current; applying the VCMA voltage in the read operation is optional, That is, the read operation can be performed without applying the VCMA voltage.

The semiconductor device of the embodiment of the present invention also supports a read operation of multiple (at least two) bits. In the MTJ unit, reading multiple bits is to simultaneously drive current injection into each MTJ corresponding to the bit to be read, and the control duration of the injection current increases exponentially by 2 between the bits to be read or drop. For example, there are 4 MTJs in the MTJ unit, and 4 MTJs store binary data. The 4 bits are from the lowest bit to the highest bit, and the bit values D0, D1, D2, and D3 are stored in sequence. Before reading the binary data, Lock the gate time of the transistors corresponding to the lowest bit to the highest bit as 1 unit time, 2 unit times, 4 unit times and 8 unit times, and the unit time can be 1 or more clock cycle times , that is, the four locked values are 1, 2, 4, and 8 respectively. At this time, the control duration of the four MTJ injection currents is the gate time of the transistor, and the pulse width of the transistor’s turn-on signal can be determined according to the gate time of each transistor configuration. When starting to read the binary data, first precharge the bit line connected to the MTJ unit, and after the voltage of the bit line reaches the potential V _DD , simultaneously apply 4 turn-on signals of the configured pulse width to the 4 transistors in parallel, And the control current is continuously injected into the MTJ of storage D0 with 1 unit time, read D0, the control current is continuously injected into the MTJ of storage D1 with 2 unit times, and D1 is read, and the current is continuously injected into the MTJ of storage D2 with 4 unit times , read D2, control the current to continuously inject the MTJ of storage D3 with 8 unit time, and read D3.

Since the current passing through the MTJ unit will reduce the voltage on the bit line, the binary data is proportional to the voltage drop ΔV on the bit line, then the PCSA can be configured according to the proportional relationship, and the PCSA can pass the value of the current flowing out of the MTJ unit and the reference current. Value determines the binary data read (read value). It should be noted that, in principle, the above-mentioned binary data Bin=D3D2D1D0 can continue to be used, and based on the conversion relationship between binary numbers and decimal numbers (the selection of the locking value is also determined based on this relationship), the binary data Bin represents Decimal number Dec:

Dec＝8×D3+4×D2+2×D1+D0

The decimal number Dec ranges from 0 to 15. On the basis of the aforementioned MTJ units of the four MTJs, the current passing through each MTJ is constant during the time when the transistor is selected, and the voltage drop ΔV is:

ΔV＝8×R ₃ I+4×R ₂ I+2×R ₁ I+R ₀ I=I×(8R ₃ +4R ₂ +2R ₁ +R ₀ )

R ₃ , R ₂ , R ₁ , and R ₀ are the resistances of the MTJ from the highest bit to the lowest bit respectively. The resistance of the MTJ in the AP state can be denoted as R _AP , and the resistance in the P state can be denoted as R _P , R _AP >R _P . If the binary data Bin=1111, then the voltage drop at this time is the maximum voltage drop ΔVmax:

ΔVmax=I×(8R _AP +4R _AP +2R _AP +R _AP )=15×IR _AP

If the binary data Bin=0000, the voltage drop at this time is the minimum voltage drop ΔVmin:

ΔVmin=I×(8R _P +4R _P +2R _P +R _P )=15×IR _P

At the same time, it can be noticed that the difference between binary number 1111 and binary number 0000 is binary number 1111 (decimal number 15), and ΔVmax-ΔVmin=15×I(R _AP -R _P ), therefore, each binary number can be passed through I(R _AP -R _P ) to distinguish and identify, where (R _AP -R _P ) is a fixed value, it can be seen that only need to pay attention to the current (the value of the value and/or the value change when the transistor is turned off) can determine the multi-bit Read out the value, the size of this I can be used as the value of the reference current configured by the PCSA or as the configuration basis of its value. In the embodiments of the present invention, the specific disclosures such as the numbers and subscripts recorded for illustration are not the only limited embodiments of the present invention, and may be changed according to actual conditions such as product characteristics and application scenarios. Each disclosure in the embodiments of the present invention Quantities can be understood in this way.

On the basis of the aforementioned semiconductor device comprising 8 MTJ units of the MTJ unit, as an exemplary multi-bit read operation scenario of this example, performing the two-bit read operation of the aforementioned semiconductor device may also include:

RT1) Select MTJU ₁ through the row and column decoder based on the designated row and column address signals. As shown in Figure 10 (2T, T, etc. indicate that the transistor is controlled by the word line for the duration of current injection, and the current direction is indicated by a dotted arrow), the bottom electrode _BE1 is connected to the source through the transistor Q1 in the first control transistor array, and the bottom electrode _BE1 is also connected to the source. Connect to ground. Connect the second bit line BL ₁ to PCSA, the second bit line BL ₁ is precharged to the potential V _DD by PCSA, and then stop charging;

RT2) Based on the specified row and column address signals, the seventh word line WL ₆ and the eighth word line WL ₇ are selected through the row and column decoder, and at the same time, an open signal is applied in parallel to select the MTJ corresponding to the specified bit in MTJU ₁ A second control transistor in the transistor array.

In step RT2), the designated bits are bits C16-C17, and after the writing operation, the states of MTJ ₁₆ -MTJ ₁₇ are AP state, AP state. Select the seventh word line WL ₆ and the eighth word line WL ₇ and select the corresponding transistors Q ₁₆ ~ Q ₁₇ and transistor Q ₁ at the same time. The switching time of transistors Q ₁₆ ~ Q ₁₇ is the respective locking value and unit The product value of time (T), lock value is 2, 1, the gating time is 2 unit time and 1 unit time respectively, transistor _Q1 can be turned off after 2 unit time. Among them, in the first unit time, two component currents are continuously injected into MTJ ₁₆ to MTJ 17 through transistors Q ₁₆ to Q _{17 at} the same time, and the direction of the SOT current on the bottom electrode BE ₁ is the contact of MTJ ₁₇ on the bottom electrode BE ₁ The area points to the contact area of MTJ ₁₆ on the bottom electrode BE ₁ (or points to the source from the contact area of MTJ ₁₇ on the bottom electrode BE ₁ ), and the current corresponding to "1" will be obtained after the first unit time (pulse ). In the second unit time, one component current is still continuously injected into MTJ ₁₆ through transistor Q ₁₆ , and transistor Q ₁₇ is turned off, so there will be no component current passing through MTJ ₁₇ , and the SOT current direction on the bottom electrode BE ₁ is from MTJ ₁₆ The contact area on the bottom electrode BE ₁ points to the source, after this 2nd unit time a current (pulse) corresponding to "1" will be obtained, the current corresponding to "1" in 1T and the current corresponding to "1" in 2T The current of MTJU 1 is regarded as a current pulse of a readout value, and after 2 unit times, the readout value of the current flowing out of MTJU ₁ at this time is 11.

On the basis of the two-bit read operation, the four-bit read operation of the aforementioned semiconductor device can be performed, see FIG. 11, and can also include:

RF1) Based on the specified row and column address signals, the row and column decoder selects MTJU ₁ , the second bit line BL ₁ is precharged to the potential V _DD by PCSA, and then stops charging.

RF2) Based on the designated row and column address signals, the fourth word line WL ₄ to the eighth word line WL ₇ are selected through the row and column decoder, and at the same time, an open signal is applied in parallel to select the MTJ corresponding to the designated bit in MTJU ₁ The second controls the transistors in the transistor array. At this time, the gate times of the transistors are 8T, 4T, 2T, and 1T respectively, and the locking values are respectively 8, 4, 2, and _1. The transistor Q1 can be turned off after 8T.

Wherein, in step RT2), the specified bits are bits C14-C17, and after the writing operation, the states of MTJ ₁₄ -MTJ ₁₇ are P state, AP state, P state, and P state.

In the first unit time, 4 component currents are continuously injected into MTJ ₁₄ ～ MTJ ₁₇ through transistors Q ₁₄ ～ Q ₁₇ at the same time, and the direction of the SOT current on the bottom electrode BE ₁ is from the contact area of MTJ ₁₇ on the bottom electrode BE ₁ Pointing to the source, the current (pulse) corresponding to "0" will be obtained after the first unit time.

In the second unit time, the three component currents are still continuously injected into MTJ ₁₄ ~ MTJ ₁₆ through transistors Q ₁₄ ~ Q ₁₆ , and transistor Q ₁₇ is turned off, MTJ ₁₇ will have no component current passing through, and the SOT on the bottom electrode BE ₁ The direction of the current is from the contact area of the MTJ ₁₆ on the bottom electrode BE ₁ to the source, and a current (pulse) corresponding to "0" will be obtained after the second unit time.

In the 4th unit time, the two component currents are still continuously injected into MTJ ₁₄ ～ MTJ ₁₅ through transistors Q ₁₄ ～ Q ₁₅ , and after the 2nd unit time, transistor Q ₁₆ has been turned off, and there will be no component current passing through MTJ ₁₆ , the direction of the SOT current on the bottom electrode _BE1 is from the contact area of the MTJ ₁₅ on the bottom electrode _BE1 to the source, and a current (pulse) corresponding to "1" will be obtained after the fourth unit time.

In the 8th unit time, a component current is still continuously injected into MTJ ₁₄ through the transistor Q ₁₄ , and after the 4th unit time, the transistor Q ₁₅ has been closed, and there will be no component current passing through the MTJ ₁₅ , and the bottom electrode BE ₁ The SOT current direction of the MTJ ₁₄ is from the contact area of the MTJ 14 on the bottom electrode BE ₁ to the source, and a current (pulse) corresponding to "0" will be obtained after the 8th unit time.

Within the above-mentioned 8 unit times, from the start time of the first unit time to the end time of the eighth unit time, the PCSA obtains the readout value "0100" through the above-mentioned current pulse.

On the basis of the four-bit read operation, as shown in Figure 12, the eight-bit read operation of the aforementioned semiconductor device can be performed, and can also include:

RE1) In the first 8T, read the lower four bits of the semiconductor device according to step RF1) to step RF2);

RE2) In the second 8T, read the upper four bits of the semiconductor device according to step RF1) to step RF2), and obtain the read value "10110100".

Among them, in some application scenarios, the first 8T and the second 8T can have the same start time, while in other application scenarios, the start time of the second 8T can be after the end time of the first 8T . It can be understood that, based on the configuration of the number of MTJs in the semiconductor device, more bit read operations can also be performed according to the above read operations. It should be added that in the aforementioned single-bit read operation, the read value can be complemented by the processor or can be configured in a multi-bit manner, so that the read value of the lower bit of the read bit is 0. The current of the read operation is the SOT current in the read operation and its component current.

In the embodiment of the present invention, the foregoing semiconductor device may also perform an operation on the operated bit sequence and the operated bit sequence, and the operation may be a multiplication operation. When the calculation operation is performed, it is necessary to perform a write operation of the calculated bit sequence on the M MTJ units first. In the first application scenario, the bit sequence to be operated may have been recorded in a specified MTJ unit, and M MTJ units other than the specified MTJ unit may be selected to perform the aforementioned write operation; in the second In the application scenario, the bit sequence to be operated may have been recorded in the specified MTJ unit, and an idle (writable) or adjacent MTJ unit may be selected to form M units with the specified MTJ unit, and further The aforementioned write operation is performed on M-1 units; in the third application scenario, the bit sequence to be operated is not recorded, and M idle units are selected, and the aforementioned write operation is performed on the M units. Wherein, M is the number of bits in the operation bit sequence.

In the embodiment of the present invention, the calculation operation is based on the selective on/off of the transistor in the control unit (whether it is gated) and the gate time locking, and the value of the current flowing out of the MTJ unit is compared with the value of the reference current to determine the calculation result. In the aforementioned M MTJ units, the control duration of the injection current of the MTJ in each MTJ unit can be locked to increase or decrease according to the exponential multiple of 2, that is, the locking value corresponding to the MTJ is configured to be based on 2 The exponential multiplication of MTJ unit increases or decreases; the control duration of the outflow current of M MTJ units can be locked to increase or decrease according to the exponential multiplication of 2, that is, the locking value corresponding to the MTJ unit is configured to follow the exponential of 2 Double increase or decrease, the increase or decrease of the lock value corresponding to MTJ can be configured relative to the bit sequence of the operated bit sequence stored in MTJ in each MTJ unit, and the increase or decrease of lock value corresponding to MTJ unit can be relative to MTJ The high and low order of the operation bit sequence for determining whether the transistors connected to the same word line are selected between the cells is arranged in high and low order. It should be noted that the value of the current for the operation operation is smaller than the value of the current for the aforementioned write operation, and the direction of the current for the operation operation may be the same as the direction of the current for the aforementioned read operation.

For the expression or determination of the operation result, the operation result is expressed as the sum of the readout values of the flowing current of the M MTJ units after the control duration of the current flowing out of the M MTJ units is all over; In some application scenarios, the configured reference current value can be used to compare the current flowing out of the M MTJ units and collected by the current branch where the MTJ unit is located with the configured reference current value, and the read value is the calculation result. The operation result is composed of the sum of the product values of the first type, and the product value of the first type is the product value of the unit operation value of each MTJ unit and the corresponding locking value in the M MTJ units; The unit operation value is formed by the sum of the product values of the second type, and the product value of the second type is the ratio of the read value of the outgoing current of each MTJ in one of the M MTJ units and the corresponding locking value product value.

On the basis of the above-mentioned write operation and read operation, the above-mentioned write operation and calculation operation of the operated bit sequence can be performed by the transistors in the first control transistor array and the transistors in the second control transistor array of the control unit.

The specified transistor in the first control transistor array is used to gate-control the current of the operation operation flowing out of the bottom electrodes of the M MTJ units, wherein the specified transistor is locked between the gate times is to increase or decrease according to an exponential multiple of 2; the specified transistor in the second control transistor array is used to gate-control the current injected into the top electrode of the MTJ specified in the M MTJ units for the operation operation, wherein , between the gate times of the specified transistors, is locked to grow or fall according to a power of 2. There are P groups of transistors in the transistors specified in the second control transistor array, and whether each group of transistors is strobed is controlled by the operation bit sequence, and P is the bit number of the operation bit sequence; the same group of transistors is specifically used for gating and controlling the current injected into the top electrodes of the MTJs in the M MTJ units with the same bit value recorded on the same bit in the bit sequence to be operated.

On the basis of the above content, as an example of an exemplary operation operation disclosed in the present invention, performing an operation operation of a semiconductor device may include:

A1) Perform the write operation of the operated bit sequence to M MTJ units, wherein bit alignment is formed in each MTJ unit, and M is the number of bits of the operated bit sequence;

A2) Lock the gate time of the transistors in the first control transistor array corresponding to the M MTJ units (specified, that is, currently used), and the gate time increases or decreases exponentially by 2;

A3) Lock the gating time of the transistors in the second control transistor array corresponding to the MTJ in each MTJ unit, the gating time increases or decreases exponentially by 2, and there are P groups of transistors in the transistors in the second control transistor array , whether each group of transistors is gated is controlled by the operation bit sequence to be transmitted on the word line, and the same group of transistors is specifically used for gating to control the injection of the operation into the top electrodes of MTJs with the same bit value recorded in M MTJ units The operating current, the same bit value is the bit value on the same bit in the bit sequence to be operated (also because the bits are aligned);

A4) Simultaneously turn on the transistors in the first control transistor array and the transistors in the second control transistor array, and after the longest gating time ends, obtain the readout value of the current flowing out of the M MTJ units through PCSA, the readout value That is, the operation result.

The gating time locked in the above steps A2) and A4), that is, the control of the injection or outflow current is continued, and the locking method conforms to the relationship between the locking values.

As an example of an exemplary 2×2 bit-scale operation operation disclosed in the present invention, as shown in Figure 13, the bit sequence to be operated is 01, and the bit sequence to be operated is 10 (at this time, M is taken as 2), and the bit to be operated is The sequence is recorded to two MTJ units through a write operation, such as MTJU ₀ and MTJU ₁ . The bits corresponding to MTJ ₀₂ and MTJ ₀₃ used in MTJU ₀ are C02 and C03 from high to low, and the state of MTJ corresponds to The bit values are 0 and 1 respectively, the bits corresponding to MTJ ₁₂ and MTJ ₁₃ in MTJU ₁ are respectively C12 and C13 from high to low, and the bit values corresponding to the state of MTJ are 0 and 1 respectively. The transistor gating time of the first control transistor array and the second control transistor array takes a clock period T as a unit time. By configuring the WPD2 signal corresponding to the source lines SL ₀ and SL ₁ , the gate timing of the first control transistor array transistors Q ₀ and Q ₁ can be locked to 2T ₁ and T ₁ ; a group corresponding to the word line WL ₂ The gate time of transistors Q ₀₂ and Q ₁₂ is locked to 2T ₂ , and the gate time of a group of transistors Q ₀₃ and Q ₁₃ corresponding to word line WL ₃ is locked to T ₂ (at this time, P is 2). Since the operation bit sequence is 10, a group of transistors Q ₀₃ and Q ₁₃ corresponding to the word line WL ₃ will be selected as strobing and non-selecting respectively, and a group of transistors Q ₀₂ and Q ₁₂ corresponding to the word line WL ₂ will be are selected as gated and ungated, respectively. The bit lines BL ₀ ˜BL ₁ are precharged to the potential V _DD .

When the transistor gating (control) starts, the transistors Q ₀ , Q ₁ and the transistors Q ₀₂ , Q ₀₃ are turned on at the same time, and the read operation for each MTJ unit starts. After the first T ₁ , read the current flowing out of MTJU ₁ to obtain the read value 01, read the current flowing out of MTJU ₀ to obtain the read value 00, 01 is superimposed on 00 to be 01, and at the end of the first T, the transistor Q ₁ is off; after the second T ₁ , read the current flowing out of MTJU ₁ to get the read value 01, the read value 01 obtained after the first T is superimposed on the 01 after the second T, which is 10, and in the second T Transistor Q ₀ is closed at the end of each T ₁ , and the gating (control) ends, then the final readout value is 10, and the 10=01×10 simultaneously, therefore, the multiplication operation of the magnetic storage semiconductor device is realized. The realization of the superposition is the result of the counter in the aforementioned PCSA continuously counting up/down within 2T time, which can be determined based on the readout values of the outgoing currents of the M MTJ units.

As an example of an exemplary 4×3-bit operation operation disclosed in the present invention, as shown in Figure 14, the bit sequence to be operated is 1011 (decimal number 11), and the operation bit sequence is 110 (decimal number 6), at this time M is taken as 3, and the bit sequence to be operated is written into 3 MTJ units, such as MTJU ₀ , MTJU ₁ , and MTJU ₂ . Each MTJ unit can have or be used with 4 MTJs. MTJ ₀₀ , _{MTJ 01 ,} and MTJ in MTJU 0 _02. The bits corresponding to MTJ ₀₃ are C00, C01, C02, and C03 from high to low, and the bit values corresponding to the MTJ status are 1, 0, 1, and 1 respectively. In this way, the three MTJ units are completed The write operation of the operated bit sequence obtains Table 5 of logical value records corresponding to the MTJ state in each MTJ unit of the operated bit sequence.

Table 5 Write the logic value record table corresponding to the 3 MTJ units after the bit sequence to be operated

bit C00 C01 C02 C03 MTJU₀ MTJ₀₀ MTJ₀₁ MTJ₀₂ MTJ₀₃ logical value 1 0 1 1 bit C10 C11 C12 C13 MTJU₁ MTJ₁₀ MTJ₁₁ MTJ₁₂ MTJ₁₃ logical value 1 0 1 1 bit C20 C21 C22 C23 MTJU₂ MTJ₂₀ MTJ₂₁ MTJ₂₂ MTJ₂₃ logical value 1 0 1 1

In Table 5, the bit sequence to be operated can be regarded as forming a bit alignment in each MTJ unit. At this time, three transistors are used in the first control transistor array, and the transistors _{Q 0} , Q ₁ , and Q ₂ are respectively gated to control the current flow out of the bottom electrodes BE ₀ , BE ₁ , and _{BE 2 of} MTJU 0 , MTJU ₁ , and MTJU 2 , and The bottom electrodes BE ₀ , BE ₁ , BE ₂ of MTJU ₀ , MTJU ₁ , MTJU ₂ are connected to the source through transistors Q ₀ , Q ₁ , Q ₂ , and the readout value of the current of each MTJ unit is obtained through SA. Wherein, the gate times of transistors Q ₀ , Q ₁ , and Q ₂ are locked to 4T ₁ , 2T ₁ , and T _{1 ,} respectively. The bit lines BL ₀ -BL ₂ are precharged to the potential V _DD .

At this time, 12 transistors are used in the second control transistor array, and the transistors Q ₀₀ , Q ₁₁ , Q ₁₂ , and Q ₁₃ respectively gate and control the current injection of the top electrodes of MTJ ₀₀ , MTJ ₀₁ , MTJ ₀₂ , and MTJ ₀₃ , and the transistor Q ₀₀ , Q ₁₁ , Q ₁₂ , and Q ₁₃ are locked to 8T ₂ , 4T ₂ , 2T ₂ , and T ₂ respectively, and the transistors Q ₀₀ , Q ₁₁ , Q ₁₂ , and Q ₁₃ are also controlled by word lines WL ₀ , Controlled by WL ₁ , WL ₂ , and WL ₃ , and can be divided into 4 groups of transistors (at this time, P is taken as 4). After the operation bit sequence is copied in 4 copies, it is transmitted through word lines WL ₀ , WL ₁ , WL ₂ , and WL ₃ The gates of the transistors (in the second control transistor array) corresponding to the specified bits are configured in this way to complete the configuration of the second control transistor arrays corresponding to the remaining MTJ units. Among them, the first group of transistors connected to the word line WL ₀ are transistors Q ₀₀ , Q ₁₀ , and Q ₂₀ , which are selected as strobe, strobe, and non-selection; the second group of transistors connected to the word line WL ₁ are transistors Q ₀₁ , Q ₁₁ , Q ₂₁ are selected as strobe, strobe, and non-select; the third group of transistors connected to the word line WL ₂ are transistors Q ₀₂ , Q ₁₂ , Q ₂₂ , which are selected as strobe, strobe, not strobe; the fourth group of transistors connected to the word line WL ₃ are transistors Q ₀₃ , Q ₁₃ , Q ₂₃ , which are selected as strobe, strobe, or not strobe; the operation bit sequence and the second control transistor The relationship between whether the array is gated or not is shown in Table 6.

Table 6 Relation table between operation bit sequence and transistor gating in the second control transistor array

At the beginning of transistor gating, transistors Q ₀ , Q ₁ , Q ₂ , transistors Q ₀₀ ˜Q ₀₃ , and transistors Q ₁₀ ˜Q ₁₃ are turned on at the same time, and each MTJ unit is read. After the first T ₁ , read the current flowing out of MTJU ₂ to get a read value of 0000, read the current flowing out of MTJU ₁ to get a read value of 1011, read the current flowing out of MTJU ₀ to get a read value of 1011, superimposed to 10110 , transistor _Q2 is turned off. After the second T ₁ , read the current flowing out of MTJU ₁ to obtain a read value of 1011, read the current flowing out of MTJU ₀ to obtain a read value of 1011, the two are superimposed to 10110, and obtained after the first T ₁ 10110 is superimposed with the 10110 obtained after the second _T1 to be 101100, and the transistor _Q1 is turned off. After the 3rd _T1 , read the current flowing out of MTJU ₀ to obtain a read value of 1011, and the 101100 obtained after the 2nd _T1 is superimposed on the 1011 obtained after the 3rd _T1 , which is 110111. After the 4th T ₁ , read the current flowing out of MTJU ₀ to get the read value 1011, and the 110111 obtained after the 3rd T ₁ is superimposed on the 1011 obtained after the 3rd T ₁ , and the final result is 1000010, that is Decimal number 66, as shown in Table 7 below.

Table 7 Recording table of gate time, readout value and result of the first control transistor array

It should be noted that the current of the operation operation includes the current of the read operation of each MTJ unit gated in the operation operation and the outflow current of the MTJ unit that is not gated, and the magnitude of the outflow current can be 0 or a specified value, The direction of the outgoing current having a specified value may coincide with the direction of the current for the read operation. The number of components such as PCSA or counters and the configuration of specific line connections can be adjusted according to product characteristics, and the specific superposition time and superposition method can also be adjusted. For example, the readout values of each MTJ unit can be superimposed at one time after 4 T ₁ , or consider the outflow current of each MTJ unit as a current pulse wave lasting for 4 T ₁ within 4 T ₁ , and obtain the readout value of the current pulse wave. The unit time T ₁ is greater than or equal to 2 ^(P-1) T ₂ , the unit time T ₂ can be a clock cycle time, that is, T ₂ can be equal to one unit time T in the aforementioned read operation, and P is the bit of the bit sequence to be operated Numbers, for example, in an example of a 4×3 bit-scale arithmetic operation, T ₁ is greater than or equal to 8T ₂ . It can be noticed that in the arithmetic operation, the configuration of the second control transistor array transistor gating time in the read operation of each MTJ unit is consistent with the corresponding configuration in the aforementioned independent read operation of the MTJ unit, Whether or not to strobe depends on the operation bit sequence. Operations, write operations, and read operations can be configured with enable signals corresponding to each operation, so as to select the operations that the MTJ unit needs to perform.

In the aforementioned semiconductor device in the embodiment of the present invention, the control unit first performs a write operation on the operated bit sequence according to the bit number of the operated bit sequence, locks the transistor of the outflow current of the MTJ unit and locks the injection current of the MTJ in each MTJ unit The gate time or control duration of the transistor, and then read the MTJ unit after the write operation, and the read value is the operation result of the operation, thus completing the multiplication operation in the aforementioned semiconductor device. It is worth noting that the multiplication operation is realized through the above-mentioned write operation, read operation and gate time configuration of the transistor (reflected by the current of the operation operation), and there is no need to introduce additional multiplication logic in the aforementioned semiconductor devices The device for computing does not need to adjust the layout and/or size of the transistors in the control unit due to the realization of the multiplication operation, that is, the implementation of the multiplication operation in the embodiment of the present invention does not occupy additional chip area, nor does it use the embodiment of the present invention The transistors of the external logic components of the semiconductor device realize the operation, and then break through the power consumption and chip area bottleneck of the semiconductor device under the same data storage capacity.

Example 2

The embodiment of the present invention and the embodiment 1 belong to the same inventive concept, and the embodiment of the present invention provides a semiconductor device, and the semiconductor device may include: the control unit and the MTJ unit in the embodiment 1.

The control unit may include at least 3 transistors, and the at least 3 transistors are all formed on the substrate;

The MTJ unit may include at least 2 MTJs, the structures of the at least 2 MTJs are all nanocolumn structures, and the nanocolumn structures are respectively grown in the regions of at least 2 transistors among the at least 3 transistors, that is, any MTJ may be The growth is formed in the area of 1 transistor, and does not occupy additional unused areas;

The at least 2 MTJs have the same bottom electrode, and each MTJ has an independent top electrode;

The top electrodes of the at least 2 MTJs are respectively connected to the at least 2 transistors (one-to-one correspondence), and the bottom electrodes of the at least 2 MTJs are connected to the at least 3 transistors (except the at least 2 transistors). other than) 1 transistor connection.

In the embodiment of the present invention, the nanocolumn structure can be grown and formed in the substrate area occupied by the transistor of the control unit by epitaxial growth technology, and the transistor can be the transistor in the second control transistor array in Embodiment 1, The nanocolumn structure of the MTJ will not consume additional substrate area, nor will it occupy additional area of the fabricated chip alone. At the same time, the embodiment of the present invention realizes the structure of "(q+1)T(q)MTJ", and q is a positive integer. For example, the 8 MTJs in the embodiment of the present invention only need 9 control transistors to realize the read operation, write It only takes 2 units of time to complete the write operation, while the existing storage device requires 16 control transistors for 8 storage elements (such as transistors in SRAM) to realize read and write operations, and requires 9 units It takes time to complete the write operation, and the number of transistors has a great influence on the chip area. The embodiment of the present invention improves the chip area required to achieve the same storage capacity, and improves the integration scale of the storage units in the same chip area.

Example 3

The embodiment of the present invention and embodiments 1 and 2 all belong to the same inventive concept, and the embodiment of the present invention provides a method for operating a semiconductor device, wherein the semiconductor device may be the semiconductor device in embodiment 1, and the semiconductor device may include N MTJs unit and a control unit, any MTJ unit includes at least two MTJs, and N is a positive integer; the control unit is used to perform write operations and read operations on the N MTJ units; the operation method is determined by the control unit Execution, the method of operation may include:

AE1) Gating to control the current of the write operation, writing the operated bit sequence to the MTJs in M MTJ units, where M is the number of bits of the operated bit sequence;

AE2) Based on the operation bit sequence, gatingly controls the current for the operation operation, injects the MTJ in the M MTJ units, and is used to control the current flowing out of the M MTJ units, and the control of the injection or outflow current continues The time is the product value of the locked value and the specified unit time;

The control unit is configured to determine an operation result based on the read values of the outgoing currents of the M MTJ units.

In the embodiment of the present invention, step AE1) may perform a write operation on each MTJ unit in the manner of the "double cycle 1/0" write operation in Embodiment 1. Step AE2) can control the current and obtain the readout value in the manner of the arithmetic operation in Embodiment 1.

Specifically, the operation method may include: performing a write operation and a read operation of the semiconductor device.

Specifically, the control unit includes a CMOS logic unit; performing the writing operation of the semiconductor device may include:

In the first period, the first VCMA voltage is applied to the top electrode of the MTJ corresponding to the selected bit to be written in the designated MTJ unit, and the bit to be written is The first type of bit value in the sequence, the bit is correspondingly written in the specified MTJ unit;

In the second period, apply a second VCMA voltage to the top electrode of the MTJ corresponding to the selected bit to be written in the specified MTJ unit, and pass the CMOS logic unit and the configured SOT current to the For the second type of bit value in the bit sequence to be written, the bit is correspondingly written into the specified MTJ unit.

Specifically, performing the read operation of the semiconductor device may include:

Apply the VCMA voltage to the top electrode of the MTJ corresponding to the bit to be read, control the configured SOT current to inject into the MTJ, and determine the readout value of the current flowing out of the MTJ unit where the MTJ is located.

Specifically, performing the read operation of the semiconductor device may also include:

Applying a VCMA voltage to the top electrode of the MTJ corresponding to at least two bits to be read in the specified MTJ unit, controlling the injection of the configured SOT current into the MTJ, and determining the readout value of the current flowing out of the specified MTJ unit ,

The control duration of the injection current increases or decreases exponentially of 2 between the at least two bits.

Example 4

The embodiment of the present invention and embodiments 1 to 3 all belong to the same inventive concept. The embodiment of the present invention provides a storage and calculation chip, or called a spin storage and calculation integrated chip. The storage and calculation chip can include the said semiconductor device. In some application scenarios, the aforementioned control unit may only include the first control transistor array, the second control transistor array, and the CMOS logic unit, and the storage and calculation chip may also include peripheral circuits that respond to instructions from the read-write controller (which can be used to generate Enable signal, clock signal and pulse width controlled current/voltage signal, etc.), row and column decoder, precharge amplifier, word line, bit line, source line, and bus interface and other memory chip components. The storage and computing chip can have a chip particle package, and each chip particle can have a specified storage capacity.

The embodiment of the invention also provides integrated circuit products. In the first example, referring to FIG. 15, the integrated circuit product may include a plurality of aforementioned storage and calculation chips 403, and the integrated circuit product may also include a chip bus 402 and a chip 401 of a read-write controller. The chip 401 is connected to the storage and calculation chip 403 through the chip bus 402 . The chip 401 of the read-write controller and any storage chip are different chip particles with independent packaging. The chip bus 402 is implemented on the circuit board 400. The circuit board 400 is provided with the chip 401 of the read-write controller and the storage chip. 403 bus interface, the circuit board 400 can also be provided with other interfaces, and other interfaces can be used for power supply and for connecting or communicating with equipment using this integrated circuit product, such as servers, industrial computers, etc. , Embedded equipment, detection terminal equipment, metering terminal equipment, etc.

In the second example, referring to FIG. 16 , the integrated circuit product may include: at least one processor 411 and the semiconductor device 412 described in Embodiments 1 and 2, the semiconductor device 412 communicates with the at least one processor 412 via an on-chip bus 414 The processor 411 is connected, and at least one processor 411 and the semiconductor device 412 may be disposed in the same chip package 410 . The integrated circuit product may be a system on chip (System on Chip, SoC) or a microcontroller chip (Micro-Controller Unit, MCU), and the integrated circuit product may also include a commonly integrated memory 413, and the memory 413 is connected via the bus 414. The memory 413 integrated with at least one processor 411 may include a read-only memory (ROM, Read-Only Memory), a static random-access memory (Static Random Access Memory, SRAM), a flash memory (Flashmemory), and the like. Figure 15 and Figure 16 are for the purpose of showing exemplary product modules, and the size and layout of actual chips or products can be adjusted according to the required product feature design.

The integrated circuit product of the embodiment of the present invention uses the aforementioned semiconductor device, which effectively solves the problem of storage wall and power consumption wall in the transmission and processing of massive data, and improves the stability, reliability, and processing efficiency of the data storage and processing system.

The optional implementations of the embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above-mentioned embodiments. Within the scope of the technical concept of the embodiments of the present invention, the embodiments of the present invention can be Various simple modifications are made to the technical solution, and these simple modifications all belong to the protection scope of the embodiments of the present invention.

In addition, it should be noted that the various specific technical features described in the above specific implementation manners may be combined in any suitable manner if there is no contradiction. In order to avoid unnecessary repetition, the embodiments of the present invention will not further describe various possible combinations.

Those skilled in the art can understand that all or part of the steps in the method of the above-mentioned embodiments can be completed by instructing the relevant hardware through a program. (processor) executes all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium may be non-transitory, and the storage medium may include various media capable of storing program codes such as read-only memory and flash memory. The aforementioned CMOS is the abbreviation of Complementary Metal Oxide Semiconductor, that is, Complementary Metal Oxide Semiconductor.

In addition, various implementations of the embodiments of the present invention can also be combined arbitrarily, as long as they do not violate the idea of the embodiments of the present invention, they should also be regarded as the content disclosed in the embodiments of the present invention.

Claims (20)

1. A semiconductor device, characterized in that the semiconductor device comprises: N MTJ units, any MTJ unit includes at least two MTJs, and N is a positive integer; a control unit, configured to perform write operations and read operations on the N MTJ units; The control unit is used to gate-control the current of the write operation, and write the operated bit sequence to the MTJs in the M MTJ units, where M is the number of bits of the operated bit sequence; The control unit is configured to gatedly control the current for an arithmetic operation to inject into the MTJs in the M MTJ units, and to control the current flowing out of the M MTJ units, either injected or outflowed, based on the operational bit sequence The control duration of the current is the product value of the locking value and the specified unit time; The control unit is configured to determine an operation result based on the read values of the outgoing currents of the M MTJ units. 2. The semiconductor device according to claim 1, wherein Among the M MTJ units, the MTJ injection current control duration in each MTJ unit is locked to increase or decrease according to an exponential multiple of 2; The control duration of the outflow current of the M MTJ units is locked to increase or decrease according to an exponential multiple of 2. 3. The semiconductor device according to claim 2, wherein The operation result is expressed as the sum of the read values of the flowing currents of the M MTJ units after the control duration of the current flowing out of the M MTJ units is all over. 4. The semiconductor device according to claim 2 or 3, characterized in that, The operation result is composed of the sum of the product values of the first type, and the product value of the first type is the product value of the unit operation value of each MTJ unit and the corresponding locking value among the M MTJ units; The unit operation value is composed of the sum of the second type of product value, and the second type of product value is the readout value of the outgoing current of each MTJ in one of the M MTJ units and the corresponding locking The product of values. 5. The semiconductor device according to claim 2, wherein, All MTJs in any MTJ unit share the same bottom electrode, and each MTJ has an independent top electrode. 6. The semiconductor device according to claim 5, wherein The control unit includes a first control transistor array and a second control transistor array; The specified transistor in the first control transistor array is used to gatedly control the current flowing out of the bottom electrodes of the M MTJ units, wherein the specified transistor is locked according to the index of 2 between the gated times Doubling up or down; The specified transistor in the second control transistor array is used to gate-control the current injected into the top electrode of the specified MTJ in the M MTJ units for the operation operation, wherein the specified transistor is selected between the gate time The time is locked to increase or decrease according to the exponential multiple of 2. 7. The semiconductor device according to claim 6, wherein There are P groups of transistors among the transistors specified in the second control transistor array, and whether each group of transistors is gated is controlled by the operation bit sequence, and P is the number of bits of the operation bit sequence; The same group of transistors is specifically used to gate-control the current injected into the operation operation to the top electrodes of the MTJs in the M MTJ units recorded with the same bit value, the same bit value being the same bit in the bit sequence to be operated The bit value on the bit. 8. The semiconductor device according to claim 6, wherein Among the M MTJ units, the gating time of the current flowing out of the j-th MTJ unit is 2 ^j-1 T ₁ , where j is 1 to the number of bits in the operation bit sequence, and T ₁ is the specified unit time; The locking value corresponding to the j th MTJ unit is 2 ^j-1 . 9. The semiconductor device according to claim 8, wherein In any MTJ unit of the M MTJ units, the gating time of the current injected into the MTJ corresponding to the i-th bit is 2 ^i-1 T ₂ , i takes 1 to the bit of the operated bit sequence number, _T2 is the specified unit time, The lock value corresponding to this MTJ is 2 ^i-1 . 10. The semiconductor device according to claim 6, wherein The rth transistor in the first control transistor array is connected to the bottom electrode in any one of the MTJ units and is also connected to the pth source line, and is used to selectively control the current flowing out of any one of the MTJ units , r and p are positive integers. 11. The semiconductor device according to claim 10, wherein The c-th transistor in the second control transistor array is connected to the top electrode of the corresponding MTJ in any of the MTJ units, and is also connected to the n-th bit line and the m-th word line respectively, for gate ground Controlling the current injected into the corresponding MTJ, c, n, m are positive integers. 12. The semiconductor device according to claim 1, wherein The semiconductor device is a spin magnetic memory cell; The value of the current for the operation operation is smaller than the value of the current for the write operation, and the direction of the current for the operation operation is the same as the direction of the current for the read operation. 13. The semiconductor device according to claim 5, wherein, The control unit includes a CMOS logic unit; The control unit is used to apply the first VCMA voltage to the top electrode of the MTJ corresponding to the selected bit to be written in the specified MTJ unit in the first cycle of the writing operation, and through the CMOS logic The SOT current of the unit and configuration, the first type of bit value in the bit sequence to be written, and the bit is correspondingly written into the specified MTJ unit; The control unit is configured to apply a second VCMA voltage to the top electrode of the MTJ corresponding to the selected bit to be written in the designated MTJ unit in the second period of the writing operation, and pass the The CMOS logic unit and the configured SOT current write the second-type bit value in the bit sequence to be written into the specified MTJ unit correspondingly. 14. The semiconductor device according to claim 13, wherein, The CMOS logic unit includes an NOR gate and an AND gate. 15. The semiconductor device according to claim 5, wherein, The control unit is used to apply a VCMA voltage to the top electrode of the MTJ corresponding to the bit to be read during the read operation, control the injection of the configured SOT current into the MTJ, and determine the flow rate of the MTJ unit where the MTJ is located. The readout value of the current. 16. The semiconductor device according to claim 5, wherein The control unit is configured to apply a VCMA voltage to the top electrode of the MTJ corresponding to at least two bits to be read in the specified MTJ unit during the read operation, control the configured SOT current to inject into the MTJ, and determine the readout value of the current flowing out of the specified MTJ cell, The control duration of the injection current increases or decreases exponentially of 2 between the at least two bits. 17. A semiconductor device, characterized in that the semiconductor device comprises: a control unit comprising at least 3 transistors, and the at least 3 transistors are all formed on the substrate; MTJ unit, including at least 2 MTJs, the structures of the at least 2 MTJs are nano-column structures, and the nano-column structures are respectively grown in the regions of at least 2 transistors among the at least 3 transistors; The at least 2 MTJs have the same bottom electrode, and each MTJ has an independent top electrode; The top electrodes of the at least two MTJs are respectively connected to the at least two transistors, and the bottom electrodes of the at least two MTJs are connected to one of the at least three transistors. 18. A method for operating a semiconductor device, wherein the semiconductor device includes N MTJ units and a control unit, any MTJ unit includes at least two MTJs, and N is a positive integer; the control unit is used to control The N MTJ units perform a write operation and a read operation; the operation method is performed by the control unit, and the operation method includes: Gating to control the current of the write operation, writing the operated bit sequence to the MTJs in M MTJ units, where M is the number of bits in the operated bit sequence; Based on the operation bit sequence, strobingly controls the current of the operation operation, injects the MTJ in the M MTJ units, and controls the current flowing out of the M MTJ units, and the control duration of the injection or outflow current is a locking value The product value with the specified unit time; An operation result is determined based on the read values of the flowing currents of the M MTJ cells. 19. A storage and calculation chip, characterized in that the storage and calculation chip comprises the semiconductor device according to any one of claims 1 to 17. 20. An integrated circuit product comprising: at least one processor and the semiconductor device according to any one of claims 1 to 17, the semiconductor device being connected to the at least one processor; or, The integrated circuit product comprises: the storage and calculation chip described in claim 19.

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