CN115706517A - Resonant half-bridge flyback converter with omitted period and control method thereof - Google Patents

Abstract

A resonant half-bridge flyback converter with a skip cycle and a control method thereof. The resonant half-bridge flyback converter includes: a first transistor and a second transistor for forming a half-bridge circuit; the transformer and the resonance capacitor are connected in series and coupled to the half-bridge circuit; and the switching control circuit is used for generating a first driving signal and a second driving signal to respectively control the first transistor and the second transistor so as to switch the transformer to generate the output voltage. The first driving signal is used for exciting the transformer. Between two consecutive pulses of the first drive signal, the second drive signal comprises at most one pulse. The switching control circuit is used for generating a omitting period when the output power is lower than a preset threshold value. The resonant pulse of the second driving signal is omitted in an omission period, wherein the omission period correspondingly increases with decreasing output power.

Description

Resonant half-bridge flyback converter with omitted period and its control method

technical field

The invention relates to a flyback converter, in particular to a resonant half-bridge flyback converter with an omitted period. The invention also relates to a control method for controlling a resonant half-bridge flyback converter.

Background technique

Please refer to FIG. 1. FIG. 1 shows an asymmetrical duty cycle flyback converter (Asymmetrical Duty Cycle Flyback Converter) of the prior art U.S. Patent No. 5,959,850. This prior art discloses a zero voltage switching (zero voltage switching, ZVS ) half-bridge flyback converter, thereby achieving high power efficiency. ZVS can be defined as switching a transistor on when the voltage across the transistor (eg, drain-to-source voltage) is zero or close to zero. However, the disadvantage of the prior art is that the power conversion efficiency of the power converter is low in the light load state.

Another disadvantage of the above-mentioned prior art is that the output voltage of the power converter is not variable, specifically, the above-mentioned prior art to be changed to a ZVS flyback converter with a variable output voltage must The switching of the transformer is controlled by detecting the demagnetization period of the transformer.

Another prior art US Patent No. 7,151,681 is a multiple-sampling circuit for measuring reflected voltage and discharge time of a transformer (Multiple-sampling circuit for measuring reflected voltage and discharge time of a transformer). This prior art discloses a detection transformer output The method of voltage and demagnetization period, however, the present prior art cannot realize ZVS of the power converter, which is used for discontinuous conduction mode (DCM) operation.

FIG. 2 shows a waveform diagram of a prior art half-bridge flyback converter operating in discontinuous conduction mode in a light load state. The driving signal SH is used to drive the upper switch of the half-bridge flyback converter to excite the transformer, and the driving signal SL is used to drive the lower switch of the half-bridge flyback converter. The signal waveform of the excitation current IM shows that the transformer operates at discontinuous conduction mode. When the output power of the half-bridge flyback converter decreases, the pulse width PW of the drive signal SH decreases due to the feedback control of the half-bridge flyback converter, and the pulse width of the drive signal SL also decreases correspondingly. Therefore, the half-bridge flyback As the switching frequency of the Chi-mode converter increases, the switching losses also increase. After the driving signal SH turns to a low level (off), the first pulse of the driving signal SL is enabled during the demagnetization period of the transformer. The second pulse of the driving signal SL is enabled to generate a circulating current, thereby realizing zero-voltage switching of the high-side switch.

The disadvantage of the above-mentioned prior art is that when operating in the discontinuous conduction mode, the driving signal SL needs to be switched on/off twice in one switching cycle, so the average switching frequency of the driving signal SL is greatly increased, resulting in a large number of switching loss and results in energy loss in the lower side switch.

Compared with the prior art US Pat. No. 7,151,681, the present invention provides a resonant half-bridge flyback converter with omitted periods to improve power efficiency in medium load and light load operating states.

Compared with the prior art US patent US 5,959,850, the present invention provides a method for generating a demagnetization signal and a switching control circuit, wherein the period of the demagnetization signal is equal to the demagnetization period of the transformer, and the present invention can be used to have a programmable output voltage ZVS flyback converters, such as USB PD power converters.

Compared with the prior art shown in FIG. 2, the present invention provides a control circuit of an asymmetrical half-bridge (asymmetrical half-bridge, AHB) flyback converter, which uses three transistors to improve the operation status of medium load and light load. power conversion efficiency.

Contents of the invention

In terms of one of the viewpoints, the present invention provides a resonant half-bridge flyback converter, comprising: a first transistor and a second transistor for forming a half-bridge circuit; a transformer and a resonant capacitor connected in series and parallel to each other coupled to the half-bridge circuit; and a switching control circuit for generating a first driving signal and a second driving signal to respectively control the first transistor and the second transistor, and then switch the transformer to generate an output voltage ; wherein the first drive signal is used to excite the transformer; wherein between two consecutive pulses of the first drive signal, the second drive signal includes at most one pulse, wherein the at most one pulse of the second drive signal includes a resonant pulse or a zero voltage switching (zero voltage switching, ZVS) pulse, the resonant pulse is used to operate a resonant period after the transformer is excited, the zero voltage switching pulse is used to realize the zero voltage switching of the first transistor; Wherein the switching control circuit includes a timer, and the timer is used to generate an omission period when an output power is lower than a preset threshold value, wherein the output power corresponds to the output voltage; wherein, a of the second driving signal The resonant pulse is omitted during the omitted period; wherein the omitted period increases as the output power decreases.

In a preferred embodiment, the second drive signal does not include a second pulse between two consecutive pulses of the first drive signal, so that the second pulse is not used to achieve zero-voltage switching of the first transistor .

In a preferred embodiment, in the omitted period, both the first driving signal and the second driving signal include zero pulses.

In a preferred embodiment, the duration of the resonance pulse of the second driving signal is equal to or longer than a demagnetization period of the transformer.

In a preferred embodiment, after the first transistor is turned off during the skipping period, a part of a demagnetization current of the transformer flows through a body diode of the second transistor.

In a preferred embodiment, the first drive signal comprises at most one pulse between two consecutive pulses of the second drive signal.

In a preferred embodiment, after each pulse of the second driving signal, a pulse of the first driving signal is subsequently generated.

In a preferred embodiment, after the omitted period, the second transistor is turned on by a zero-voltage switching pulse to realize zero-voltage switching of the first transistor.

In a preferred embodiment, when the output power is lower than the preset threshold, the omission period starts at a non-conduction time point when the first driving signal becomes non-conductive.

In a preferred embodiment, the omission period starts at a non-conduction point when the first drive signal turns non-conduction, and when the omission period ends, the second drive signal produces a zero-voltage switching pulse.

In a preferred embodiment, the resonant period further includes an extended zero-voltage switching period, and the extended zero-voltage switching period is used to realize zero-voltage switching of the first transistor.

From another point of view, the present invention also provides a control method for controlling a resonant half-bridge flyback converter, wherein the resonant half-bridge flyback converter includes a first transistor and a second transistor, used to form a half-bridge circuit; and a transformer and a resonant capacitor, which are connected in series with each other and coupled to the half-bridge circuit, the control method includes: switching the transformer in a periodic switching manner by switching the half-bridge circuit to generate a output voltage; when an output power is lower than a preset threshold value, an omission period is generated, wherein the output power corresponds to the output voltage; wherein the conduction of the first transistor is used to excite the transformer; the conduction of the second transistor is used for To realize a resonance period or realize zero voltage switching (zero voltage switching, ZVS) of the first transistor; wherein a resonance pulse used to control the second transistor to realize the resonance period is omitted in the omitted period; wherein the omission The period increases as the output power decreases.

The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, characteristics and effects of the present invention.

Description of drawings

Figure 1 shows a prior art flyback converter with asymmetric duty cycle.

FIG. 2 shows a waveform diagram of a prior art half-bridge flyback converter operating in discontinuous conduction mode in a light load state.

FIG. 3 shows a schematic diagram of an embodiment of the resonant half-bridge flyback converter of the present invention.

FIG. 4 shows an operation waveform corresponding to the embodiment of FIG. 3 .

FIG. 5 shows an operation waveform diagram for reducing the switching frequency of the driving signal SH and the driving signal SL.

FIG. 6 shows an operating waveform diagram of an embodiment of the resonant half-bridge flyback converter with omitted periods of the present invention.

FIG. 7 shows a block diagram of an embodiment of the primary-side controller in the resonant half-bridge flyback converter of the present invention.

FIG. 8 shows a block diagram of an embodiment of the primary-side controller in the resonant half-bridge flyback converter of the present invention.

FIG. 9 shows the operation waveform diagram of the demagnetization simulator of the present invention to generate the demagnetization signal.

FIG. 10 shows a schematic diagram of a specific embodiment of the demagnetization simulator generating the demagnetization signal Sdmg of the present invention.

FIG. 11 shows a schematic diagram of a preferred embodiment of the resonant half-bridge flyback converter of the present invention.

FIG. 12 shows an operation waveform diagram of a preferred embodiment of the primary-side controller 201 operating in the discontinuous conduction mode of the present invention.

FIG. 13 shows a block diagram of a preferred embodiment of the primary side controller of the present invention.

Explanation of symbols in the figure

10: transformer

100: Secondary side controller

20: Resonant capacitor

200: primary side controller

201: primary side controller

205: Clock generator

208: primary side controller

22: Timer

230: capacitance

231: switch

240: Control elements

243: Control elements

248: Control elements

25: Timer

250: Demagnetization Simulator

255: Resistance

260: Cycle counter

271, 272: Transistors

280: Comparator

285: Logic Circuits

30: first transistor

300: Resonant Half-Bridge Flyback Converter

35: Body Diode

40: second transistor

45: Body diode

51, 52, 55, 60: resistance

70: Secondary side synchronous rectifier

75: Body Diode

90: Optocoupler

900: Resonant Half-Bridge Flyback Converter

C: capacitance value

CPO: Comparator output

DCM: Discontinuous Conduction Mode

ID: discharge current

IM: excitation current

IP: primary side switching current

IS: Secondary side switching current

kn: knee point

Lr: leakage inductance

LX: switch node

M1: first transistor

M2: second transistor

M3: third transistor

n, m: turns ratio

NA: auxiliary winding

NC: positive integer

NNP: Coupling Node

NP: primary side winding

NS: Secondary side winding

PW: pulse width

PZV: Zero Voltage Switching Pulse

Rs: resistance value

Rt: resistance value

S1: the first driving signal

S2: Second driving signal

S3: The third drive signal

Sdmg: demagnetization signal

SG: driving signal

SH: drive signal

SL: drive signal

SMP: Sampled signal

t1-t9: point in time

t3': time point

ta-te: time point

TA: first period

ta', tc': point in time

TB: second period

TC: third period

Tcyc1: switching cycle

Tcyc2: switching cycle

Td1: the first non-conduction period

Td2: the second non-conduction period

TDS: Demagnetization period

TDSX: Turn-on period

TDSX': conduction period

TRH: time period

TRL: time period

TSL: Turn-on period

TW: Excitation period

Tx: omit cycle

TZ: the third non-conduction period

VAUX: auxiliary signal

VC: cross voltage

Vcr: cross voltage

VCS: current sense signal

VCSp: voltage level

VDP: voltage drop

VFB: feedback signal

Vg: voltage level

VHB: switching node voltage

VIN: input voltage

Vinx: voltage level

VNA: auxiliary winding signal

VO: output voltage

VPK: voltage surge

Vref: reference voltage

Vth: voltage threshold

VX: reflected voltage

Detailed ways

The drawings in the present invention are all schematic diagrams, mainly intended to show the coupling relationship between various circuits and the relationship between various signal waveforms. As for the circuits, signal waveforms and frequencies, they are not drawn to scale.

FIG. 3 shows a schematic diagram of an embodiment of the resonant half-bridge flyback converter of the present invention. The resonant half-bridge flyback converter 300 includes: a first transistor 30 and a second transistor 40 for forming a half-bridge circuit. The transformer 10 and the resonant capacitor 20 are connected in series with each other and coupled to the switching node LX of the half-bridge circuit. The transformer 10 includes a primary winding NP, a secondary winding NS and an auxiliary winding NA, wherein the primary winding NP and the secondary winding NS have Turn ratio n, the secondary side winding NS and the auxiliary winding NA have a turn ratio m. The primary-side controller 200 generates the driving signal SH and the driving signal SL, and the driving signal SH and the driving signal SL switch the transformer 10 through the half-bridge circuit to generate the output voltage VO on the secondary side of the transformer 10 . The driving signal SH drives the first transistor 30 to excite the transformer 10 . The driving signal SL turns on the second transistor 40 during the demagnetization and resonant period of the transformer 10, and the driving signal SL is also used to turn on the second transistor 40 to generate a circulating current flowing through the transformer 10, so as to realize the zero of the first transistor 30. voltage switching. The resistor 60 generates the current sensing signal VCS by detecting the primary side switch current IP of the transformer 10 .

The driving signal SH and the driving signal SL are generated according to the feedback signal VFB, wherein the feedback signal VFB is generated according to the output power of the resonant half-bridge flyback converter 300 . The secondary-side controller 100 is coupled to the output voltage VO to generate a feedback signal VFB, and the feedback signal VFB is coupled to the primary-side controller 200 via the optocoupler 90 . The secondary-side controller 100 is also used to generate the driving signal SG to drive the secondary-side synchronous rectifier 70 during the demagnetization period TDS of the transformer 10 . The auxiliary winding NA generates an auxiliary winding signal VNA when the transformer 10 is switched. The resistors 51 and 52 are used to attenuate the auxiliary winding signal VNA to generate an auxiliary signal VAUX. The auxiliary signal VAUX is coupled to the primary side controller 200 . In one embodiment, the resistor 55 is coupled to the primary side controller 200 , and the demagnetization signal Sdmg is generated by setting parameters through the resistor 55 .

FIG. 4 shows an operation waveform corresponding to the embodiment of FIG. 3 . When the driving signal SH is turned on, the transformer 10 is excited and generates an excitation current IM, and when the driving signal SH is not turned on, the transformer 10 is demagnetized. During the demagnetization period TDS, the transformer 10 generates a secondary side switching current IS, and the driving signal SL is related to the demagnetization period TDS of the transformer 10 . In one embodiment, the conduction period TSL (ie, the pulse width) of the driving signal SL is equal to or longer than the demagnetization period TDS of the transformer 10 , thereby preventing the transformer 10 from operating in a continuous conduction mode (CCM). During the demagnetization period TDS of the transformer 10 , a reflected voltage VX is generated on the resonant capacitor 20 , wherein the relationship between the reflected voltage VX and the output voltage VO is: VX=n*VO.

When the driving signal SH is off, the driving signal SL can be turned on, and when the driving signal SL is off, the driving signal SH can be turned on. A dead time (eg period TRH, period TRL) may be included between the driving signal SH and the driving signal SL (ie, when the driving signal SH and the driving signal SL are both non-conductive).

Details of the operations in different time periods of FIG. 4 are detailed in the following description.

The time period from time point t1 to time point t2 is the exciter transformer cycle. During this time period, the first transistor 30 is turned on and the second transistor 40 is turned off. The primary side switch current IP flowing through the transformer 10 increases and the voltage of the resonant capacitor 20 also increases. At this time, the transformer 10 is excited and the resonant capacitor 20 is charged. The secondary side synchronous rectifier 70 is turned off and its body diode 75 is reverse biased. Therefore, no energy is converted to the secondary side at this time.

The time period from time point t2 to time point t3 is the first circulating current period. In this period, both the first transistor 30 and the second transistor 40 are turned off, and the circulating current of the transformer 10 forces the switching node voltage VHB of the half-bridge circuit to drop until the second until the body diode 45 of the second transistor 40 is turned on. The period from time point t2 to time point t3 is related to the quasi-resonant period to realize zero-voltage switching of the second transistor 40. At this time, the voltage on the primary side of the transformer 10 is the same as the voltage of the resonant capacitor 20 at time point t3. .

The period from time point t3 to time point t4 is the resonant cycle (positive current). In this period, in the state of zero voltage switching, the first transistor 30 is turned off and the second transistor 40 is turned on. At this time, the output voltage VO is equal to the resonance The voltage Vcr across the capacitor 20 is divided by the turns ratio n, the current starts to flow through the secondary side synchronous rectifier 70, and the energy stored in the transformer 10 is converted to the output terminal to generate the output voltage VO. Since the leakage inductance Lr of the transformer 10 and the resonant capacitor 20 (Cr) form an LC tank, the secondary side current is in the form of a sine wave in a period determined by the resonant frequency Lr and Cr. The primary side current of the transformer 10 is the sum of the excitation current IM and the secondary side switching current IS. The current flowing through the resonant tank (Lr, Cr) is still a positive current, which is mainly driven by the magnetizing inductance of the transformer 10 and flows through the resonant capacitor 20 .

The time period from time point t4 to time point t5 is the resonant cycle (negative current). During this time period, the first transistor 30 continues to be turned off and the second transistor 40 continues to be turned on. The energy is continuously converted to the secondary side, but the resonant tank current is resonated The voltage of the capacitor 20 is reverse driven, and the energy of the resonant capacitor 20 is not only converted to the secondary side, but also used to reduce the excitation current of the transformer 10 when the second transistor 40 is continuously turned on (for example, from time point t4 to time point t5). level is pulled to a negative value.

The period from time point t5 to time point t6 is the reverse excitation transformer cycle (negative current). In this period, from the end of the demagnetization period TDS of the transformer 10 to when the second transistor 40 is turned off, the resonant capacitor 20 reversely excites the transformer 10, and generate a negative current.

The period from the time point t6 to the time point t7 is the second circulating current period. In this period, both the first transistor 30 and the second transistor 40 are turned off, and the negative current of the transformer 10 is induced from the time point t5 to the time point t6. To force the switching node voltage VHB on the switching node LX in the half-bridge circuit to increase until it turns on the body diode 35 of the first transistor 30 .

After time point t7, another period similar to the period from time point t1 to time point t2 begins, the first transistor 30 is turned on in the zero voltage switching state and the second transistor 40 is turned off, if the circulating current in the transformer resonant tank Still a negative current, the excess energy in the resonant tank will be sent back to the input (the node that supplies the input voltage VIN).

In the light load state, when the output power decreases, the pulse width of the drive signal SH and the drive signal SL will decrease correspondingly, so the switching frequency of the drive signal SH and the drive signal SL increases under the light load state, due to the core loss ( core loss), switching loss (switching loss) and other power losses increase, resulting in poor power conversion efficiency of the power converter.

FIG. 5 shows an operation waveform diagram for reducing the switching frequency of the driving signal SH and the driving signal SL. One way to improve power efficiency is to reduce the switching frequency by prolonging the time between when the driving signal SL is turned off (such as time point t3) and when the driving signal SH is turned on (such as time point t5). However, the driving signal SL Turning off will generate a circulating current, which will cause a voltage surge VPK of the switching node voltage VHB and a voltage drop VDP of the auxiliary signal VAUX. The voltage surge VPK and the voltage drop VDP will cause power loss and noise.

It should be noted that the turning on or off of the driving signal SH and the driving signal SL respectively correspond to turning on or off of the first transistor 30 and the second transistor 40 .

FIG. 6 shows an operating waveform diagram of an embodiment of the resonant half-bridge flyback converter with omitted periods of the present invention.

Please refer to FIG. 6 , in one embodiment, the driving signal SH is turned on during the excitation cycle of the excitation transformer 10 (for example, from time point t1 to time point t2 ), so as to excite the transformer 10 . After the drive signal SH is turned off, the drive signal SL is turned on during the resonance period (for example, from time point t2 to time point t3), and has a resonance pulse (for example, from time point t2 to time point t3), and an excitation period and a resonance period form A switching cycle (eg time point t1 to time point t3).

As shown in FIG. 6, in one embodiment, the omission period Tx starts at the non-conduction time point when the drive signal SH turns non-conduction (such as time point t4), and when the omission period Tx ends (such as time point t6), the driving signal SL turns on. In one embodiment, when the output power is reduced due to power saving, the skipping period Tx will correspondingly increase (ie, the switching frequency will decrease).

Please continue to refer to FIG. 6 , compared to a period without an omitted period, such as time point t1 to time point t3, the driving signal SL is not conducted during the omitted period (such as Tx) and there is no resonant pulse. For example, in the existing In the technology, a pulse of the driving signal SL from the time point t4 to the time point t5, that is, the resonant pulse of the driving signal SL, has been omitted in this embodiment, as shown in FIG. 6 , therefore, in the omitted period ( From time point t4 to time point t6), there is no negative circulation current. In the prior art, the voltage surge VPK generated by switching the node voltage VHB and the voltage drop VDP generated by the auxiliary signal VAUX are also avoided in this embodiment. In one embodiment, as shown in FIG. 6 , the driving signal SH is also in a non-conducting state during the omitted period (for example, Tx).

In one embodiment, after the driving signal SH is turned off, during a part of the omitted period (for example, a part of the time between time point t4 and time point t5), a part of the demagnetization current of the transformer 10 flows through the second Body diode 45 of transistor 40 . In other words, in one embodiment, there is no double pulses in the driving signal SL. In one embodiment, there is no double pulse in the driving signal SH. From one point of view, after a single pulse of the driving signal SH, a single pulse of the driving signal SL is generated, and after a single pulse of the driving signal SL, a single pulse of the driving signal SH is generated, even if the resonant half-bridge flyback conversion The same is true for the device operating in a state with omitted cycles. From another point of view, between two consecutive pulses of the driving signal SH, the driving signal SL includes at most one pulse, and between two consecutive pulses of the driving signal SL, the driving signal SH includes at most one pulse.

In one embodiment, when the output power is lower than a predetermined threshold, an omission period Tx is generated. In one embodiment, the omission period Tx increases correspondingly as the output power decreases. In one embodiment, even if the driving signal SL cannot achieve zero-voltage switching of the first transistor 30, the second driving signal does not include a second pulse between two consecutive pulses of the first driving signal, and thus does not Zero-voltage switching of the first transistor 30 is achieved with the second pulse.

Please continue to refer to FIG. 6 , in one embodiment, the zero-voltage switching pulse (for example, PZV) of the driving signal SL turns on the second transistor 40 after the omission period passes, so as to realize the zero-voltage switching period (for example, from time point t6 to time point t7).

As shown in FIG. 6 , in one embodiment, at least one switching period (for example, time point t7 to time point t9 ) is generated after the zero-voltage switching pulse PZV after the cycle is omitted.

Please continue to refer to FIG. 6 , in one embodiment, the resonant period may include a continuation of the zero-voltage switching period (for example, time point t3' to time point t3), and the continuation of the zero-voltage switching period is used to realize the zero-voltage switching of the first transistor 30. In other words, in this embodiment, the first part of the resonance pulse (such as time point t2 to time point t3') is used to realize the resonance between the transformer 10 and the resonant capacitor 20, and the second part of the resonance pulse (such as time point t3' to time point Point t3) is used to generate circulating current to realize zero-voltage switching of the first transistor 30 .

FIG. 7 shows a block diagram of an embodiment of the primary-side controller in the resonant half-bridge flyback converter of the present invention. In one embodiment, the primary controller 200 includes a timer 25 and a control element 240 . In one embodiment, the control element 240 is used to generate the driving signal SH and the driving signal SL according to the input voltage VIN (via the auxiliary signal VAUX) and the feedback signal VFB, and the timer 25 is used to generate the aforementioned skip period Tx.

As shown in Figure 7, in one embodiment, the timer 25 judges whether the output power is lower than the preset threshold according to the information related to the output power, and when the output power is judged to be lower than the preset threshold, the timer 25 starts Calculate the omission period Tx, and control the control element 240 to omit the pulses of the driving signal SH and the driving signal SL in the omission period Tx.

Please refer to Figure 4 again. When the resonant half-bridge flyback converter is in the state of medium load and light load, the resonant period from time point t4 to time point t5 is short and cannot generate enough negative current (energy) to achieve zero The voltage switches, therefore, the main part of the negative current comes from the current generated from the time point t5 to the time point t6.

However, a higher negative current will lead to higher power loss. In order to control the negative current for zero-voltage switching at an appropriate level, the control of the demagnetization period must be accurate, so it is necessary to generate a demagnetization signal Sdmg corresponding to the transformer 10 Demagnetization period TDS.

FIG. 8 shows a block diagram of an embodiment of the primary-side controller in the resonant half-bridge flyback converter of the present invention. In one embodiment, the primary controller 208 includes a demagnetization simulator 250 and a control element 248 . In one embodiment, the control element 248 is used to generate the driving signal SH and the driving signal SL according to the input voltage VIN (via the auxiliary signal VAUX) and the feedback signal VFB, and the demagnetization simulator 250 is used to generate the demagnetization related signal. The demagnetization signal Sdmg is used to simulate the demagnetization period TDS, wherein the demagnetization related signal is eg the reflected voltage of the transformer 10 (via the auxiliary signal VAUX).

Please refer to FIG. 9 at the same time. FIG. 9 shows the operation waveform diagram of the demagnetization simulator generating the demagnetization signal of the present invention.

In the switching period, the resonant half-bridge flyback converter operates periodically in the discontinuous conduction mode (for example, from time point ta to time point tc'), and the driving signal SH first turns on the first transistor 30 to excite the transformer 10 and then generate the primary side switching current IP (for example, from the time point ta' to the time point tb), and after the first transistor 30 is turned off, the driving signal SL is used to conduct ( For example, from the time point tb to the time point tc′) the second transistor 40 is used to generate a circulating current (for example, from the time point tc to the time point tc′) to realize the zero-voltage switching of the first transistor 30 . In the switching period of the non-discontinuous conduction mode, the conduction period TSL (such as time point tb to time point tc') of the driving signal SL is determined by the pulse width of the demagnetization signal Sdmg (such as TDSX'), wherein the demagnetization signal Sdmg is generated by the demagnetization simulator 250 based on corrections in the previously forced inserted discontinuous conduction mode. In one embodiment, the conduction period TDSX' of the demagnetization signal Sdmg is corrected during the previous actively forced discontinuous conduction mode period, and used to enable the control element 248 to control the minimum conduction time of the second transistor 40 , thereby During the discontinuous conduction mode after the first transistor 30 is turned off, the transformer 10 is demagnetized. In one embodiment, as shown in FIG. 9 , the conduction period TSL of the driving signal SL (such as time point tb to time point tc') can be the conduction period TDSX' of the demagnetization signal Sdmg plus a delay time (for example, From the time point tc to the time point tc′), after the demagnetization period, a negative circulating current is established on the primary side switch current IP, so as to realize the zero-voltage switching of the first transistor 30 .

It should be noted that the non-discontinuous conduction mode refers to the operation mode that is not discontinuous conduction mode, such as: continuous conduction mode (continuous conduction mode, CCM), or quasi-resonant mode (quasi-resonant mode, QRM) operation, the quasi-resonant mode is also called boundary conduction mode (boundary conduction mode, BCM).

In one embodiment, when the primary-side switch current IP has a preset number (such as a positive integer NC) of switching cycles (such as time point ta to time point t1), it operates in a non-discontinuous conduction mode (such as a quasi-resonant mode ), at least one switching cycle is actively forced to operate in the discontinuous conduction mode (for example, time point t1 to time point t3). Therefore, the demagnetization simulator 250 is used to correct the conduction period TDSX of the demagnetization signal Sdmg according to the demagnetization period TDS of the transformer 10 in the forced-insert discontinuous conduction mode.

As shown in FIG. 9 , in the forced-inserted discontinuous conduction mode, the demagnetization period TDS of the transformer 10 starts from the rising edge (rising edge) of the auxiliary signal VAUX, and starts between the auxiliary signal VAUX (such as time point t2 to time point The falling edge (falling edge, ie knee point kn) of t3) ends. Specifically, in this embodiment, the reflected voltage can be detected by sensing the auxiliary signal VAUX, which comes from the auxiliary winding NA of the transformer 10 during the off period of the first transistor 30 . The duration of the reflected voltage, that is, the pulse width of the auxiliary signal VAUX from the rising edge to the knee point kn, is related to the demagnetization period TDS of the transformer 10 .

In one embodiment, the primary-side controller 208 further includes a cycle counter 260, which is used to calculate the number of switching cycles operating in the discontinuous conduction mode according to the primary-side switch current IP, and when the primary-side switch current IP When it is determined that there have been a predetermined number of switching cycles without operating in the discontinuous conduction mode, the cycle counter 260 is used to control the control element 248 to actively force the operation in the discontinuous conduction mode. In one embodiment, the period counter 260 can sense the primary side switch current IP through the current sensing signal VCS, so as to determine the operation in the non-discontinuous conduction mode.

In one embodiment, as shown in FIG. 9, during the forced discontinuous conduction mode switching period, the driving signal SL continuously controls the second transistor 40 to be non-conductive, so that the half-bridge circuit not only operates in the discontinuous conduction mode, but also Also operates in an asynchronous switching mode, wherein a portion of the demagnetization current of the transformer 10 (eg, IP from time t2 to time t2') flows through the body diode 45 of the second transistor 40 during the forced discontinuous conduction mode switching period .

Please continue to refer to FIG. 9 , after the discontinuous conduction mode DCM (for example, from time point t4 to time point t5), the first pulse of the driving signal SL turns on the second transistor 40 to excite the transformer 10 from the resonant capacitor 20 to the transformer 10 , and then generate a negative circulating current (IP from time point t4 to time point t5 ) to realize zero-voltage switching of the first transistor 30 .

FIG. 10 shows a schematic diagram of a specific embodiment of a demagnetization simulator for generating a demagnetization signal Sdmg according to the present invention. In one embodiment, the demagnetization simulator 250 includes a timing generator 205 , a comparator 280 and a logic circuit 285 .

In one embodiment, the timing generator 205 includes an integrator. The integrator is composed of a switch 231 and a capacitor 230. The switch 231 is controlled by the sampling signal SMP. The sampling signal SMP is related to the driving signal SH to sample the current sensing signal VCS. The discharge current ID is related to n*VO, and is used to discharge the voltage VC across the capacitor 230 . The cross voltage VC is compared with the reference voltage Vref by the comparator 280 . The logic circuit 285 generates the demagnetization signal Sdmg according to the comparator output CPO and the sampling signal SMP related to the driving signal SH. In one embodiment, the reference voltage Vref is 0 volts, and when the primary side switch current IP is 0, the current sensing voltage VCS is 0.

In one embodiment, the duration of the demagnetization signal Sdmg is related to the voltage level (Vinx) of the input voltage of the transformer 10, that is, as shown in FIG. 3, the coupling node NNP between the primary winding NP and the resonant capacitor 20 The voltage of the demagnetization signal Sdmg is also related to the voltage level (eg n*VO) of the output voltage of the transformer 10 and the excitation period (TW) of the transformer 10 when the first transistor 30 is turned on. It should be noted that the voltage level Vinx of the input voltage of the transformer 10 is equal to the input voltage VIN minus the voltage Vcr across the resonant capacitor 20 .

According to the demagnetized magnetic flux of the transformer 10 is equal to the excited magnetic flux of the transformer 10, the following formula 1 can be listed:

Vinx*TW＝n*VO*TDS (Formula 1)

Where TW is the occurrence time of the voltage level Vinx of the input voltage of the transformer 10 during the excitation period of the transformer 10 ; n*VO is the voltage of the transformer 10 during the demagnetization period TDS of the transformer 10 . n is the turns ratio of the primary winding NP and the secondary winding NS, and VO is the voltage of the secondary winding NS (that is, the output voltage).

After the transformer 10 is energized, the level VCSp of the current sensing signal VCS is related to the peak value of the primary side switch current IP at the end of the energization process, and is generated on the resistor 60 shown in FIG. 3 , which can be represented by the following formula 2:

VCSp＝(Vinx/L)*TW*Rs (Formula 2)

Where L is the inductance of the primary winding NP of the transformer 10 , Rs is the resistance of the resistor 60 , and VCSp is the voltage level of the transformer 10 at the end of the excitation process.

Let ID=n*VO/Rt, where Rt is the resistance value of the resistor 55 .

The pulse width TDSX of the demagnetization signal Sdmg can be expressed as:

TDSX=(C*VCSp)/ID, where C is the capacitance of the capacitor 230 .

TDSX＝(Rt*C*VCSp)/(n*VO)

TDSX＝(Rt*C/(n*VO))*(Rs/L)*Vinx*TW

Let Rt=L/(Rs*C) (Equation 3)

TDSX＝(Vinx*TW)/(n*VO) (Formula 4)

When the condition of Equation 3 is satisfied, the conduction period TDSX of the demagnetization signal Sdmg shown in Equation 4 is equal to the demagnetization period TDS of the transformer 10 .

Please continue to refer to FIG. 10, the switch 231 is turned on to sample the current sensing signal VCS to the capacitor 230, and when the switch 231 is turned off (ie, when the excitation ends), the level VCSp of the current sensing signal VCS is kept at the capacitor 230 , the switch 231 is controlled by the sampling signal SMP. When the switch 231 is turned off, the demagnetization signal Sdmg is enabled (eg, through the logic circuit 285 ), in other words, when the demagnetization signal Sdmg is enabled, the voltage VC across the capacitor 230 is the peak value of the current sensing signal VCS. After the switch 231 is turned off, the discharge current ID starts to discharge the capacitor 230. When the capacitor 230 is fully discharged (VC=0V) through the discharge current ID (ID=n*VO/Rt), the demagnetization signal Sdmg is disabled. The resistor 55 shown in FIG. 10 and FIG. 3 is used to set the preset pulse width of the demagnetization signal Sdmg.

In one embodiment, in the forcedly inserted discontinuous conduction mode switching period, the pulse width TDSX of the demagnetization signal Sdmg can be compared with the demagnetization period TDS indicated by the pulse width of the auxiliary signal VAUX through the demagnetization simulator 250 Therefore, the pulse width TDSX of the demagnetization signal Sdmg can be corrected for the next DCM switching period. In one embodiment, the demagnetization simulator 250 is also used to adjust the resistance value of the resistor 255 according to the detected demagnetization period TDS in the discontinuous conduction mode, so as to correct the pulse period TDSX of the demagnetization signal Sdmg.

In other embodiments, in addition to adjusting the resistance value of the resistor 255, the demagnetization simulator 250 can also correct the pulse period TDSX of the demagnetization signal Sdmg by adjusting the voltage threshold Vth to determine the end of the demagnetization signal Sdmg, or Adjust the capacitance of the capacitor 230 , or adjust, for example, the ratio of the current mirror formed by the transistor 271 and the transistor 272 in FIG. 10 .

FIG. 11 shows a schematic diagram of a preferred embodiment of the resonant half-bridge flyback converter of the present invention. The resonant half-bridge flyback converter 900 is similar to the resonant half-bridge flyback converter 300 of FIG. 3 . In this embodiment, the resonant half-bridge flyback converter 900 includes a first transistor M1, a second transistor M2, and a third transistor M3, and the first transistor M1, the second transistor M2, and the third transistor M3 are used to form a half-bridge circuit. From one point of view, the first transistor M1 and the third transistor M3 are configured as the lower-side transistors of the resonant half-bridge flyback converter 900 , and the second transistor M2 is configured as the upper-side transistor of the resonant half-bridge flyback converter 900 transistor.

According to the feedback signal VFB and the input voltage VIN, the primary side controller 201 is used to generate the first drive signal S1, the second drive signal S2 and the third drive signal S3, the first drive signal S1, the second drive signal S2 and the third drive signal The signal S3 is coupled to switch the transformer 10 through the half-bridge circuit, thereby generating the output voltage VO on the secondary side of the transformer 10 . The second driving signal S2 drives the second transistor M2 to excite the transformer 10. The third driving signal S3 turns on the third transistor M3 during the demagnetization and resonance period of the transformer 10. The third driving signal S3 is also used to turn on the third transistor. M3 is used to generate a circulating current flowing through the transformer 10 and realize zero-voltage switching of the second transistor M2 in a heavy load state. In other words, the second transistor M2 is the upper bridge switch on the primary side of the resonant half-bridge flyback converter 900 and may correspond to the first transistor 30 in FIG. The side lower bridge switch may correspond to the second transistor 40 of FIG. 3 . From a point of view, the first transistor M1 is used for parallel connection with the third transistor M3 and serves as an auxiliary primary-side low-bridge switch, and has an independent control signal S1.

In one embodiment, after the transformer 10 is excited by turning on the second transistor M2 when operating in the discontinuous conduction mode under a light load state, the third transistor M3 is controlled to be in the demagnetization and resonance period of the transformer 10. conduction. After the demagnetization, when the third transistor M3 is continuously turned off, the first driving signal S1 is used to turn on the first transistor M1 to generate a circulating current flowing through the transformer 10 to realize zero-voltage switching of the second transistor M2. Therefore, the third transistor M3 can avoid switching twice in one switching cycle of the discontinuous conduction mode.

Since the first transistor M1 is only used to generate circulating current to realize zero-voltage switching, in one embodiment, the actual size (eg aspect ratio) of the first transistor M1 can be configured to be much smaller than the actual size of the third transistor M3 . Therefore, the driving capability and parasitic capacitance (eg, gate capacitance) of the first transistor M1 are lower than those of the third transistor M3 , and the switching loss of the first transistor M1 is therefore lower than that of the third transistor M3 .

For example, the gate switching loss Pg of a transistor can be expressed as:

Pg＝0.5*Ciss*Vg*Vg*Freq

Where Ciss is the input capacitance of the transistor, Vg is the voltage level of the gate driving signal, and Freq is the switching frequency of the gate driving signal.

According to the switching power loss equation above, the first transistor M1 with a smaller actual size is dedicated to realize the zero-voltage switching of the second transistor M2 in the discontinuous conduction mode, so the gate switching loss of the first transistor M1 is lower than the actual size Larger third transistor M3.

In addition, in one embodiment, the amplitude of the voltage level (ie, Vg) of the first driving signal S1 is lower than the amplitude of the voltage level of the third driving signal S3, so the switching loss of the first transistor M1 can also be reduced, and In an embodiment, the maximum rating of the gate of the first transistor M1 (eg, the gate-to-source voltage) may also be lower than the maximum rating of the gate of the third transistor M3 .

The resistor 60 generates the current sensing signal VCS by detecting the primary side switching current IP of the transformer 10, and the primary side controller 201 is used to generate the first driving signal S1 according to the input voltage VIN, and according to the input voltage VIN and/or the output voltage VO to generate a third driving signal S3. The primary side controller 201 is also used for generating the second driving signal S2 according to the feedback signal VFB.

FIG. 12 shows an operation waveform diagram of a preferred embodiment of the primary-side controller 201 operating in the discontinuous conduction mode of the present invention. In the operation of the discontinuous conduction mode, the primary-side controller 201 operates in the first switching cycle Tcyc1 and controls the first driving signal S1 to turn on the first transistor M1 in the first period TA, thereby generating a circulating current to realize the first Zero-voltage switching when the second transistor M2 is turned on. After the first period TA, the first driving signal S1, the second driving signal S2 and the third driving signal S3 are used to turn off the first transistor M1 and the second transistor M1 in the first non-conduction period Td1 (ie, the dead period). The second transistor M2 and the third transistor M3. In one embodiment, the first non-conduction period Td1 is related to a quasi-resonant period for realizing zero-voltage switching of the second transistor M2. After the first non-conduction period Td1 , the second driving signal S2 turns on the second transistor M2 in the second period TB, and the conduction of the second transistor M2 is used to excite the transformer 10 . After the second time period TB, the first driving signal S1, the second driving signal S2 and the third driving signal S3 are used to turn off the first transistor M1, the second transistor M2 and the third transistor in (ie, the dead time period). M3. In one embodiment, the second non-conduction period Td2 is related to another quasi-resonant period for realizing zero-voltage switching of the third transistor M3. After the second non-conduction period Td2 , the third driving signal S3 turns on the third transistor M3 in the third period TC, and the third transistor M3 turns on in the demagnetization period of the transformer 10 . After the third period TC, the first driving signal S1, the second driving signal S2 and the third driving signal S3 are used to turn off the first transistor M1, the second transistor M2 and the third transistor M1 in the third non-conduction period TZ. The transistor M3, wherein the excitation current IM is maintained at zero during the third non-conduction period TZ (ie, the discontinuous conduction mode). After the third non-conduction period TZ, another switching period Tcyc2 starts.

FIG. 13 shows a block diagram of a preferred embodiment of the primary side controller of the present invention. In one embodiment, the primary side controller 213 includes a timer 22 and a control element 243 . The control element 243 is used for generating the first driving signal S1 , the second driving signal S2 and the third driving signal S3 according to the input voltage VIN (via VAUX ) and the feedback signal VFB.

The timer 22 is used for timing to generate the third non-conduction period TZ, and the third non-conduction period TZ starts at the end of the pulse of the third driving signal S3 (for example, the falling edge). In one embodiment, when the output power of the resonant half-bridge flyback converter decreases, the third non-conduction period TZ increases correspondingly. Therefore, the switching frequency of the resonant half-bridge flyback converter can also be adjusted by the resonant half-bridge The output power of the flyback converter is reduced correspondingly, thereby improving performance in light load operating conditions.

The present invention has been described above with reference to preferred embodiments, but the above description is only for those skilled in the art to easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. The various embodiments described are not limited to single application, and can also be used in combination. For example, two or more embodiments can be used in combination, and some components in one embodiment can also be used to replace another embodiment. corresponding components. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. It is limited to the signal itself, and also includes performing voltage-to-current conversion, current-to-voltage conversion, and/or ratio conversion on the signal when necessary, and then processing or computing the converted signal to generate a certain output result. It can be seen that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which will not be listed here. Accordingly, the scope of the invention should encompass the above and all other equivalent variations.

Claims (16)

1. A resonant half-bridge flyback converter, comprising: A first transistor and a second transistor are used to form a half-bridge circuit; A transformer and a resonant capacitor are connected in series with each other and coupled to the half-bridge circuit; and a switching control circuit, used to generate a first driving signal and a second driving signal to respectively control the first transistor and the second transistor, and then switch the transformer to generate an output voltage; wherein the first driving signal is used to excite the transformer; Wherein between two consecutive pulses of the first drive signal, the second drive signal includes at most one pulse, wherein the at most one pulse of the second drive signal includes a resonant pulse or a zero voltage switching pulse, the resonant pulse Used to operate a resonant period after the transformer is excited, the zero voltage switching pulse is used to realize the zero voltage switching of the first transistor; Wherein the switching control circuit includes a timer, and the timer is used to generate an omission period when an output power is lower than a preset threshold value, wherein the output power corresponds to the output voltage; wherein, a of the second driving signal The resonant pulse is omitted during the omitted period; wherein the omitted period increases as the output power decreases. 2. The resonant half-bridge flyback converter of claim 1, wherein the second drive signal does not include a second pulse between two consecutive pulses of the first drive signal, and thus does not start with the first Two pulses achieve zero voltage switching of the first transistor. 3. The resonant half-bridge flyback converter as claimed in claim 1, wherein in the omitted period, both the first driving signal and the second driving signal comprise zero pulses. 4. The resonant half-bridge flyback converter as claimed in claim 1, wherein the duration of the resonant pulse of the second driving signal is equal to or longer than a demagnetization period of the transformer. 5. The resonant half-bridge flyback converter as claimed in claim 1 , wherein a part of a demagnetization current of the transformer flows through a part of the second transistor after the first transistor is turned off during the omission period. body diode. 6. The resonant half-bridge flyback converter of claim 1, wherein the first driving signal comprises at most one pulse between two consecutive pulses of the second driving signal. 7. The resonant half-bridge flyback converter of claim 1, wherein a pulse of the first driving signal is generated after each pulse of the second driving signal. 8. The resonant half-bridge flyback converter as claimed in claim 1, wherein after the omitted period, the second transistor is turned on by a zero-voltage switching pulse to realize zero-voltage of the first transistor switch. 9. The resonant half-bridge flyback converter as claimed in claim 1, wherein when the output power is lower than the preset threshold, the skipping period starts at a time when the first driving signal turns non-conductive Point of non-conduction. 10. The resonant half-bridge flyback converter as claimed in claim 1 , wherein the skipping period starts at a non-conduction point when the first drive signal turns non-conducting, and ends when the skipping period , the second driving signal generates a zero-voltage switching pulse. 11. The resonant half-bridge flyback converter as claimed in claim 1, wherein the resonant period further includes a continuous zero voltage switching period, and the continuous zero voltage switching period is used to realize zero voltage switching of the first transistor. 12. A control method for controlling a resonant half-bridge flyback converter, wherein the resonant half-bridge flyback converter includes a first transistor and a second transistor to form a half-bridge circuit; and a A transformer and a resonant capacitor are connected in series with each other and coupled to the half-bridge circuit, and the control method includes: switching the transformer in a periodic switching manner to generate an output voltage by switching the half-bridge circuit; generating an omitted period when an output power is lower than a preset threshold, wherein the output power corresponds to the output voltage; Wherein the conduction of the first transistor is used to excite the transformer; the conduction of the second transistor is used to realize a resonant cycle or zero-voltage switching of the first transistor; A resonant pulse used to control the second transistor to realize the resonant period is omitted in the omitted period; wherein the omitted period increases as the output power decreases. 13. The control method as claimed in claim 12, wherein the duration of the resonance pulse of the second transistor is equal to or longer than a demagnetization period of the transformer. 14. The control method of claim 12, wherein a part of a demagnetization current of the transformer flows through a body diode of the second transistor after the skip period turns off the first transistor. 15. The control method as claimed in claim 12, wherein the first transistor is turned on after the second transistor is turned off. 16. The control method as claimed in claim 12, wherein after the skipping period, the second transistor is turned on according to a zero-voltage switching pulse to realize zero-voltage switching of the first transistor.

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