CN115694774A - Universal clock management system and method for multiple Ethernet interface modes - Google Patents

Abstract

The invention discloses a general clock management system and method for multiple Ethernet interface modes, including a PLL module, a Devider module, a MUX_1 module, a MUX_2 module, a MAC module, a MUX_3 module, a MUX_4 module, a MUX_6 module, and a MUX_7 module; Multiplexing the clock signals in various interface modes and setting bidirectional pins, thereby reducing the number of signals; separating the receiving and transmitting channels to make the interface clearer; users only need to select the port mode and operating frequency according to their own needs , the structure will automatically switch to the clock frequency that matches it; the general clock management method effectively solves the problems of complex clock structure, many interface signals, and difficult use by users; at the same time, the clock path and data path in the two working modes of the RGMII interface The separation ensures the convergence of the physical implementation timing.

Description

A general clock management system and method for multiple Ethernet interface modes

technical field

The invention belongs to the field of computer communication and network, in particular to a general clock management system and method for multiple Ethernet interface modes.

Background technique

At present, in the mainstream Ethernet switch chip, in order to facilitate the use of users, its management port will support multiple interface modes, such as GMII/MII/RGMII/RevMII, etc., in order to achieve better adaptation with the peer end, the RGMII interface supports both There are two modes: nominal and delay; since each interface mode has its own operating rate and clock frequency, the clock structure is complicated, the interface signals are many, and users are not easy to use; and the two operating modes of the RGMII interface have different requirements for timing , causing the physical implementation timing to be difficult to converge.

Contents of the invention

In order to solve the problems in the prior art, the present invention provides a general clock management system and method for multiple Ethernet interface modes to solve the above problems.

To achieve the above object, the present invention provides the following technical solutions:

A general clock management system for multiple Ethernet interface modes, including a PLL module, a Devider module, a MUX_1 module, a MUX_2 module, a MAC module, a MUX_3 module, a MUX_4 module, a MUX_6 module, and a MUX_7 module;

The output end of the PLL module is connected to the input end of the Devider module, the output end of the Devider module is connected to the input end of the MUX_1 module, and the output end of the MUX_1 module is connected to the input end of the MUX_2 module; the input end of the MUX_2 module is connected to a bidirectional PAD circuit;

The MUX_2 module is used to switch the four interface modes of GMII/MII/RGMII/RevMII according to the control signal; the output end of the MUX_2 module is connected to the input end of the MAC module; the MAC module is used for interface mode and rate selection sampling;

For the receiving channel, the RvMII interface mode in the MUX_2 module selects the clock frequency output by the MUX_1 module. In the GMII/MII/RGMII three interface modes, select the external input IMP_RXCLK. If it is the RGMII interface mode, select the clock frequency after nominal and delay switching; MUX_3 The module is used to select IMP_RXCLK and imp_rxclk_d according to the delay mode control signal received by the IMP interface; the MUX_7 module is used to select the received data and control signals in the RGMII interface mode;

For the transmission channel, the GMII/RGMII/RvMII three interface modes in the MUX_2 module select the clock frequency output by the MUX_1 module. In the MII interface mode, select the external input IMP_TXCLK. If it is the RGMII interface mode, select the clock frequency after nominal and delay switching;

The MUX_4 module is used for selecting the clock according to the delay mode control signal; the MUX_6 module is used for the delay mode control signal to select the sending data and the control signal.

Preferably, the PLL module is used to multiply the input 25MHz clock by 10 to generate a 250MHz clock and transmit it to the Devider module.

Preferably, the Devider module is used to divide the frequency of the clock output by the PLL module to generate three kinds of clocks of 125MHz/25MHz/2.5MHz.

Preferably, the MUX_1 module is used to select three clock frequencies of 125MHz/25MHz/2.5MHz after frequency division of the Devider module according to the control signal.

Preferably, a Delay module is also included, and the Delay module is used to delay the control signal.

Preferably, the MUX_3 module selects the clock imp_rxclk_d when the IMP_RXC_DELAY signal is 1, otherwise selects the clock IMP_RXCLK.

Preferably, the MUX_4 module is used to select the clock according to the delay mode control signal IMP_TXC_DELAY sent by the IMP interface to generate the clock IMP_GTX_CLK; when the IMP_TXC_DELAY signal is 1, select the clock after the delay module, otherwise select the clock generated by the MUX_1 module.

Preferably, the MUX_6 module is used to send the delay mode control signal IMP_TXC_DELAY according to the IMP interface to select the transmission data and control signals, and generate TXD[3:0] and TX_CTRL;

When the control signal IMP_TXC_DELAY is 0, select the mac_txd[3:0] and mac_tx_ctrl signals generated by the MAC module. When the control signal IMP_TXC_DELAY is 1, select the mac_txd_d[3:0] and mac_tx_ctrl_d signals generated by the Delay module.

Preferably, the MUX_7 module is used to receive the delay mode control signal IMP_RXC_DELAY according to the IMP interface to select the received data and control signals, and generate mac_rxd[3:0] and mac_rx_ctrl signals to the MAC module;

When the control signal IMP_RXC_DELAY is 1, select the rxd_d[3:0] and rx_ctrl_d signals generated by the Delay module, and when the control signal IMP_RXC_DELAY is 0, select the externally input RXD[3:0] and RX_CTRL signals.

A general clock management method for multiple Ethernet interface modes, comprising the following processes,

The PLL module multiplies the frequency of the input clock and outputs it to the Devider module. The Devider module divides the frequency of the clock output by the PLL module and transmits it to the MUX_1 module; the MUX_1 module selects the frequency-divided clock of the Devider module and transmits it to the MUX_2 module. ;

The MUX_2 module switches the four interface modes of GMII/MII/RGMII/RevMII according to the control signal; the MAC module is used to sample the clock and data after the four interface modes of GMII/MII/RGMII/RevMII and 10/100/1000Mbps rate selection ;

For the receiving channel, the RvMII interface mode selects the clock frequency output by the MUX_1 module. In the GMII/MII/RGMII three interface modes, select the external input IMP_RXCLK. If it is the RGMII interface mode, select the clock frequency after nominal and delay switching;

For the transmission channel, the GMII/RGMII/RvMII three interface modes select the clock frequency output by the MUX_1 module. In the MII interface mode, select the external input IMP_TXCLK. If the RGMII interface mode, select the clock frequency after nominal and delay switching.

Compared with the prior art, the present invention has the following beneficial technical effects:

The present invention provides a general clock management system for multiple Ethernet interface modes, by multiplexing clock signals in various interface modes and setting bidirectional pins, thereby reducing the number of signals; by separating the receiving and sending paths , making the interface clearer; users only need to select the port mode and operating frequency according to their own needs, and the structure will automatically switch to the clock frequency that matches it; for the two operating modes of the RGMII interface, in order to ensure the convergence of the physical implementation timing , using a design structure that separates the clock path from the data path.

A general clock management method for multiple Ethernet interface modes of the present invention supports various commonly used Ethernet interface modes, and can realize clock switching under various working modes and speed combinations, and the interface signals are simple, clear, and small in number , has high engineering application value. The invention performs function simulation on the invention and compares it with the traditional Ethernet switching circuit structure. In the test environment, 1000 groups of messages are randomly generated, the port mode is switched to GMII/MII/RGMII/RevMII, and the communication rate is switched to 10/100/1000Mbps, and the traditional Ethernet switching circuit structure and the general The clock management method exchanges and forwards these message tasks; wherein, the number of ports is 7, the working clock is 2.5/25/125MHz, the data bit width is 8 bits, and the continuous data communication method is adopted. The simulation results show that the general clock management method effectively solves the problems of complex clock structure, many interface signals, and difficult use by users; at the same time, the convergence of the physical implementation timing is ensured by separating the clock path and data path in the two working modes of the RGMII interface sex.

Description of drawings

Fig. 1 is a management port receiving channel clock structure diagram;

Fig. 2 is a clock structure diagram of the management port sending channel;

Fig. 3 is a management port RGMII mode sending path clock and data isolation structure diagram;

Figure 4 is a structural diagram of the clock and data isolation of the RGMII mode receiving channel of the management port.

Detailed ways

The present invention will be further described in detail below in conjunction with specific embodiments, which are explanations of the present invention rather than limitations.

Example

A general clock management system for multiple Ethernet interface modes of the present invention mainly includes a PLL module, a Devider module, a MUX_1 module, a MUX_2 module, a MAC module, a MUX_3 module, a Delay module, a MUX_4 module, a MUX_5 module, a MUX_6 module, MUX_7 module. Its structure is shown in Figure 1, Figure 2, Figure 3 and Figure 4; through the structure of Figure 1 and Figure 2, four interface modes of GMII/MII/RGMII/RevMII and pin multiplexing at 10/100/1000Mbps rate are realized . If pin multiplexing is not performed, the GMII interface mode requires 3 clock signals, the MII interface mode requires 2 clock signals, the RGMII interface mode requires 3 clock signals, and the RvMII interface mode requires 2 clock signals, a total of 10 clock signals , the 4 interface modes after multiplexing only need 3 clock signals, and the multiplexed clock pin signals are shown in the following table:

Through the structures shown in Figure 3 and Figure 4, the separation of the clock path and the data path in the normal and delay modes of the RGMII interface is realized, thereby ensuring the convergence of the physical implementation timing.

In Figure 3, the sending data and control signal paths in normal mode are the MAC module and the MUX_6 module, and the sending clock path is the MUX_4 module; only these two paths need to be checked for timing; in the delay mode, the sending data and control signal paths are For the MAC module, Delay module and MUX_6 module, the transmission clock path is the Delay module and MUX_4 module; only these two paths need to be checked for timing.

In Figure 4, the receiving data and control signal paths in normal mode are the MUX_7 module and the MAC module, and the receiving clock path is the MUX_3 module; only these two paths need to be checked for timing; in the delay mode, the receiving data and control signal paths are Delay module, MUX_7 module and MAC module, the receiving clock path is the Delay module and MUX_3 module; only these two paths need to be checked for timing.

The main function of the PLL module is to multiply the input 25MHz clock by 10 and generate a 250MHz clock for the Devider module.

The Devider module mainly implements the frequency division of the clock output by the PLL module to generate three clocks of 125MHz/25MHz/2.5MHz. 125MHz corresponds to a communication rate of 1000Mbps, 25MHz corresponds to a communication rate of 100Mbps, and 2.5MHz corresponds to a communication rate of 10Mbps.

The MUX_1 module mainly selects the three clock frequencies of 125MHz/25MHz/2.5MHz after the frequency division of the Devider module according to the control signal IMP_SPD_SEL[1:0]. IMP_SPD_SEL[1:0]: 00=10Mbps, select the 2.5MHz working clock; 01 =100Mbps, choose 25MHz working clock; 10=1000Mbps (default), choose 125MHz working clock; 11=lllegal.

The MUX_2 module mainly switches the four interface modes of GMII/MII/RGMII/RevMII according to the control signal IMP_MODE[1:0]. IMP_MODE[1:0]: 00=RGMII mode, 01=MII mode, 10=RvMII mode, 11=GMII mode.

For the receiving channel, the RvMII interface mode selects the clock frequency output by the MUX_1 module. In the GMII/MII/RGMII three interface modes, select the external input IMP_RXCLK (the direction of the bidirectional pin is input). If it is the RGMII interface mode, select nominal and delay switching after the clock frequency.

For the transmission channel, the GMII/RGMII/RvMII three interface modes select the clock frequency output by the MUX_1 module. In the MII interface mode, select the external input IMP_TXCLK (the direction of the bidirectional pin is input). If it is the RGMII interface mode, select nominal and delay switching after the clock frequency.

The MAC module mainly implements GMII/MII/RGMII/RevMII four interface modes and clock and data sampling after 10/100/1000Mbps rate selection. For the receiving channel, if it works in RGMII interface mode, the clock and data are based on the control signal After the IMP_RXC_DELAY switch.

The MUX_3 module mainly receives the delay mode control signal IMP_RXC_DELAY according to the IMP interface to realize the selection of IMP_RXCLK and imp_rxclk_d. When the IMP_RXC_DELAY signal is 1, the clock imp_rxclk_d is selected, otherwise the clock IMP_RXCLK is selected (the direction of the bidirectional pin is input), thus realizing the separation of the receiving clock path of the RGMII interface in normal and delay modes.

The Delay module mainly implements the delay of signals such as IMP_GTX_CLK, TXD[3:0], TX_CTRL, IMP_RXCLK, RXD[3:0], RX_CTRL, etc., and the delayed time particles are based on specific timing requirements, thus realizing the RGMII interface in delay mode path separation.

The MUX_4 module mainly sends the delay mode control signal IMP_TXC_DELAY according to the IMP interface to select the clock and generate the clock IMP_GTX_CLK. When the IMP_TXC_DELAY signal is 1, the clock after the delay module is selected, otherwise the clock generated by the MUX_1 module is selected, thereby realizing the separation of the sending clock path of the RGMII interface in normal and delay modes.

The MUX_5 module mainly realizes the selection of the IMP_GTX_CLK clock in GMII and RGMII modes according to the control signal IMP_MODE[1:0]. IMP_MODE[1:0]: 00=RGMII mode, select the clock generated by the MUX_4 module; 01=MII mode; 10=RvMII mode; 11=GMII mode, select the 125MHz clock generated by the Devider module.

The MUX_6 module mainly sends the delay mode control signal IMP_TXC_DELAY according to the IMP interface to realize the selection of sending data and control signals, and generates TXD[3:0] and TX_CTRL. When the control signal IMP_TXC_DELAY is 0, select the mac_txd[3:0] and mac_tx_ctrl signals generated by the MAC module, and when the control signal IMP_TXC_DELAY is 1, select the mac_txd_d[3:0] and mac_tx_ctrl_d signals generated by the Delay module; thus realizing RGMII The interface transmits data and separates control signal paths in two modes, normal and delay.

The MUX_7 module mainly receives the delay mode control signal IMP_RXC_DELAY according to the IMP interface to realize the selection of received data and control signals, and generates mac_rxd[3:0] and mac_rx_ctrl signals to the MAC module. When the control signal IMP_RXC_DELAY is 1, select the rxd_d[3:0] and rx_ctrl_d signals generated by the Delay module, and when the control signal IMP_RXC_DELAY is 0, select the externally input RXD[3:0] and RX_CTRL signals; thereby realizing the RGMII interface Separation of receive data and control signal paths in both normal and delay modes.

The present invention reduces the number of signals by multiplexing the clock signals in various modes and setting bidirectional pins; by separating the receiving and sending paths, the interface is clearer; the user only needs to select the port mode according to his own needs And the working frequency, the structure will automatically switch to the clock frequency that is adapted to it; for the two working modes of the RGMII interface, the design structure that separates the clock path and the data path ensures the convergence of the physical implementation timing.

A general clock management method for multiple Ethernet interface modes of the present invention supports various commonly used Ethernet interface modes, and can realize clock switching under various working modes and speed combinations, and the interface signals are simple, clear, and small in number , has high engineering application value.

Through the function simulation of the invention, it is compared with the traditional Ethernet switching circuit structure. In the test environment, 1000 groups of messages are randomly generated, the port mode is switched to GMII/MII/RGMII/RevMII, and the communication rate is switched to 10/100/1000Mbps, and the traditional Ethernet switching circuit structure and the general The clock management method exchanges and forwards these message tasks; wherein, the number of ports is 7, the working clock is 2.5/25/125MHz, the data bit width is 8 bits, and the continuous data communication method is adopted. The simulation results show that the general clock management method effectively solves the problems of complex clock structure, many interface signals, and difficult use by users; at the same time, the convergence of the physical implementation timing is ensured by separating the clock path and data path in the two working modes of the RGMII interface sex.

The management port receiving path clock structure diagram of the present invention is as shown in Figure 1, and the management port sending path clock structure diagram is as shown in Figure 2, and the IMP_RXC_Delay and IMP_TXC_Delay signals are controlled by external input pins; the management port RGMII mode transmits path clock and data isolation The structure is shown in Figure 3, and the receiving path clock and data isolation structure is shown in Figure 4.

The numbered modules in the figure are described below:

Module No. 1 is a PLL module, the number of which is 2, and is multiplexed in Fig. 1 and Fig. 2 . It mainly realizes that the input 25MHz clock is multiplied by 10 to generate a 250MHz clock.

The No. 2 module is a Devider module, the number of which is 2, and it is reused in Figure 1 and Figure 2. It mainly implements the frequency division of the clock output by module 1 to generate three clocks of 125MHz/25MHz/2.5MHz.

Module No. 3 is MUX_1 module, its number is 2, and it is multiplexed in Figure 1 and Figure 2. Mainly select the three clocks of 125MHz/25MHz/2.5MHz according to the IMP_SPD_SEL[1:0] signal.

Module No. 4 is the MUX_2 module, its quantity is 2, and it is multiplexed in Figure 1 and Figure 2. The four interface modes of GMII/MII/RGMII/RevMII are switched mainly according to the IMP_MODE[1:0] signal.

Module No. 5 is a MAC module, the number of which is 4, and is multiplexed in Figure 1, Figure 2, Figure 3 and Figure 4. It mainly implements sampling after interface mode and rate selection.

Module No. 6 is the MUX_3 module, its number is 2, and it is multiplexed in Figure 1 and Figure 4. The selection of IMP_RXCLK and imp_rxclk_d is mainly realized according to the IMP_RXC_DELAY signal.

Module No. 7 is a Delay module, the number of which is 6, and is reused in Figure 1, Figure 2, Figure 3 and Figure 4. It mainly realizes the delay of signals such as IMP_GTX_CLK, TXD[3:0], TX_CTRL, IMP_RXCLK, RXD[3:0], RX_CTRL, etc.

Module 8 is the MUX_4 module, its quantity is 2, and it is multiplexed in Figure 2 and Figure 3. The clock is selected mainly according to the IMP_TXC_DELAY signal to generate IMP_GTX_CLK.

Module No. 9 is the MUX_5 module, and its quantity is 1. It mainly realizes the selection of IMP_GTX_CLK clock in GMII and RGMII modes.

Module 10 is the MUX_6 module, and its quantity is 1. The selection of sending data and control signals is mainly realized according to the IMP_TXC_DELAY signal, and TXD[3:0] and TX_CTRL are generated.

Module 11 is the MUX_7 module, and its quantity is 1. Mainly realize the selection of RXD[3:0], RX_CTRL and rxd_d[3:0], rx_ctrl according to the IMP_RXC_DELAY signal, and generate mac_rxd[3:0] and mac_rx_ctrl signals to the No. 5 module.

The invention can be used in the design of Ethernet switching chips in the fields of Ethernet switches, network servers, computer data storage systems and the like.

At present, in the mainstream Ethernet switch chip, in order to facilitate the use of users, its management port will support multiple interface modes, such as GMII/MII/RGMII/RevMII, etc., in order to achieve better adaptation with the peer end, the RGMII interface supports both There are two modes: nominal and delay; since each interface mode has its own operating rate and clock frequency, the clock structure is complicated, the interface signals are many, and users are not easy to use; and the two operating modes of the RGMII interface have different requirements for timing , causing the physical implementation timing to be difficult to converge.

A general clock management method for multiple Ethernet interface modes proposed by the present invention can reduce the number of signals by multiplexing clock signals in various modes and setting bidirectional pins; Separation makes the interface clearer; users only need to select the port mode and operating frequency according to their own needs, and the structure will automatically switch to the clock frequency that matches it; for the two operating modes of the RGMII interface, in order to ensure the convergence of the physical implementation timing Reliability, using a design structure that separates the clock path from the data path.

According to the above solution, use Verilog language to describe the logic design of each module in the present invention, and perform system-level verification with other devices in the network device. The verification result shows that the present invention realizes the designed function, and the performance meets expectations.

Claims (10)

1. A general clock management system to multiple Ethernet interface modes, is characterized in that, comprises PLL module, Devider module, MUX_1 module, MUX_2 module, MAC module, MUX_3 module, MUX_4 module, MUX_6 module, MUX_7 module; The output end of the PLL module is connected to the input end of the Devider module, the output end of the Devider module is connected to the input end of the MUX_1 module, and the output end of the MUX_1 module is connected to the input end of the MUX_2 module; the input end of the MUX_2 module is connected to a bidirectional PAD circuit; The MUX_2 module is used to switch the four interface modes of GMII/MII/RGMII/RevMII according to the control signal; the output end of the MUX_2 module is connected to the input end of the MAC module; the MAC module is used for interface mode and rate selection sampling; For the receiving channel, the RvMII interface mode in the MUX_2 module selects the clock frequency output by the MUX_1 module. In the GMII/MII/RGMII three interface modes, select the external input IMP_RXCLK. If it is the RGMII interface mode, select the clock frequency after nominal and delay switching; MUX_3 The module is used to select IMP_RXCLK and imp_rxclk_d according to the delay mode control signal received by the IMP interface; the MUX_7 module is used to select the received data and control signals in the RGMII interface mode; For the transmission channel, the GMII/RGMII/RvMII three interface modes in the MUX_2 module select the clock frequency output by the MUX_1 module. In the MII interface mode, select the external input IMP_TXCLK. If it is the RGMII interface mode, select the clock frequency after nominal and delay switching; The MUX_4 module is used for selecting the clock according to the delay mode control signal; the MUX_6 module is used for the delay mode control signal to select the sending data and the control signal. 2. A kind of general clock management system to multiple Ethernet interface modes according to claim 1, is characterized in that, described PLL module is used for carrying out 10 frequency multiplications with the 25MHz clock of input, produces 250MHz clock and transmits to Devider module. 3. A kind of general clock management system to multiple Ethernet interface modes according to claim 1, is characterized in that, described Devider module is used for carrying out frequency division to the clock of PLL module output, produces 125MHz/25MHz/2.5 MHz three clocks. 4. A kind of general clock management system to multiple Ethernet interface modes according to claim 1, it is characterized in that, described MUX_1 module is used for the 125MHz/25MHz/2.5MHz after frequency division of Devider module according to control signal There are three clock frequencies to choose from. 5. A general clock management system for multiple Ethernet interface modes according to claim 1, further comprising a Delay module, the Delay module is used to delay the control signal. 6. A general clock management system for multiple Ethernet interface modes according to claim 1, wherein the MUX_3 module selects the clock imp_rxclk_d when the IMP_RXC_DELAY signal is 1, otherwise selects the clock IMP_RXCLK. 7. A kind of general clock management system to multiple Ethernet interface modes according to claim 1, it is characterized in that, described MUX_4 module is used for sending delay mode control signal IMP_TXC_DELAY to select clock according to IMP interface, produces clock IMP_GTX_CLK; when the IMP_TXC_DELAY signal is 1, select the clock after the delay module, otherwise select the clock generated by the MUX_1 module. 8. A kind of general clock management system to multiple Ethernet interface modes according to claim 1, it is characterized in that, described MUX_6 module is used for sending delay mode control signal IMP_TXC_DELAY according to IMP interface to send data and control signal The selection, generate TXD[3:0] and TX_CTRL; When the control signal IMP_TXC_DELAY is 0, select the mac_txd[3:0] and mac_tx_ctrl signals generated by the MAC module. When the control signal IMP_TXC_DELAY is 1, select the mac_txd_d[3:0] and mac_tx_ctrl_d signals generated by the Delay module. 9. A kind of general clock management system to multiple Ethernet interface modes according to claim 1, is characterized in that, described MUX_7 module is used for receiving delay mode control signal IMP_RXC_DELAY according to IMP interface and carries out receiving data and control signal Select, generate mac_rxd[3:0] and mac_rx_ctrl signals to the MAC module; When the control signal IMP_RXC_DELAY is 1, select the rxd_d[3:0] and rx_ctrl_d signals generated by the Delay module, and when the control signal IMP_RXC_DELAY is 0, select the externally input RXD[3:0] and RX_CTRL signals. 10. A general clock management method to multiple Ethernet interface modes, characterized in that, comprising the following processes, The PLL module multiplies the frequency of the input clock and outputs it to the Devider module. The Devider module divides the frequency of the clock output by the PLL module and transmits it to the MUX_1 module; the MUX_1 module selects the frequency-divided clock of the Devider module and transmits it to the MUX_2 module. ; The MUX_2 module switches the four interface modes of GMII/MII/RGMII/RevMII according to the control signal; the MAC module is used to sample the clock and data after the four interface modes of GMII/MII/RGMII/RevMII and 10/100/1000Mbps rate selection ; For the receiving channel, the RvMII interface mode selects the clock frequency output by the MUX_1 module. In the GMII/MII/RGMII three interface modes, select the external input IMP_RXCLK. If it is the RGMII interface mode, select the clock frequency after nominal and delay switching; For the transmission channel, the GMII/RGMII/RvMII three interface modes select the clock frequency output by the MUX_1 module. In the MII interface mode, select the external input IMP_TXCLK. If the RGMII interface mode, select the clock frequency after nominal and delay switching.

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