CN115694512A - Data conversion circuit, method and memory - Google Patents

Abstract

An embodiment of the present disclosure provides a data conversion circuit, method and memory, the circuit includes a conversion module, an adjustment module and a transmission module, one end of the adjustment module is used to receive a compensation signal, the other end of the adjustment module is connected to the output end of the conversion module and The input ends of the transmission modules are connected respectively, wherein: the conversion module is used to receive the initial data signal, and converts the initial data signal from parallel to serial to obtain the intermediate data signal; the adjustment module is used to perform the intermediate data signal according to the compensation signal. The compensation process is used to reduce the signal swing of the intermediate data signal; the transmission module is used to perform drive enhancement processing on the compensated intermediate data signal to obtain the target data signal. The embodiments of the present disclosure can reduce the signal swing of the intermediate data signal, increase the signal bandwidth, and improve the high-frequency performance of the circuit.

Description

A data conversion circuit, method and memory

technical field

The present disclosure relates to the technical field of semiconductors, in particular to a data conversion circuit, method and memory.

Background technique

In the process of data transmission, there is often a need to convert parallel data into serial data. In order to obtain faster data transmission speed, a series of memories that can transmit data at double data rate (DDR) have emerged as the times require. device. However, as the data rate increases, such as from 4266 megabits per second (Mbps) of LPDDR4 to 6400Mbps of LPDDR5, due to the limitation of device performance, for the circuit that converts parallel data into serial data, due to the The parasitic capacitance is large, limiting the high-frequency performance of the circuit.

Contents of the invention

Embodiments of the present disclosure provide a data conversion circuit, method and memory.

In the first aspect, the embodiment of the present disclosure provides a data conversion circuit, including a conversion module, an adjustment module and a transmission module, one end of the adjustment module is used to receive a compensation signal, and the other end of the adjustment module is connected to the conversion module The output end of and the input end of the transmission module are respectively connected, wherein:

The conversion module is configured to receive an initial data signal, perform parallel-to-serial processing on the initial data signal, and obtain an intermediate data signal;

The adjustment module is configured to perform compensation processing on the intermediate data signal according to the compensation signal, so as to reduce the signal swing of the intermediate data signal;

The transmission module is configured to perform drive enhancement processing on the intermediate data signal after compensation processing to obtain a target data signal.

In some embodiments, the adjustment module includes a transmission gate module, one end of the transmission gate module is used to receive the compensation signal, and the other end of the transmission gate module is connected to the output terminal of the conversion module and the transmission gate module. The input terminals of the modules are respectively connected, and the control terminal of the transmission gate module is used to receive the enable control signal, wherein:

When the enable control signal is in a valid state, the transmission gate module is turned on, so as to perform compensation processing on the intermediate data signal according to the compensation signal; or, when the enable control signal is in an invalid state, The transmission gate module is turned off.

In some embodiments, the enable control signal includes a first enable control signal and a second enable control signal, wherein:

The transmission gate module includes an NMOS transistor and a PMOS transistor, the first end of the NMOS transistor is connected to the first end of the PMOS transistor as one end of the transmission gate module, and the second end of the NMOS transistor is connected to the first end of the PMOS transistor. The second end of the PMOS tube is connected as the other end of the transmission gate module;

The control terminal of the transmission gate module includes a gate terminal of the NMOS transistor and a gate terminal of the PMOS transistor, the gate terminal of the NMOS transistor is connected to the first enabling control signal, and the gate terminal of the PMOS transistor connected to the second enable control signal, and the first enable control signal and the second enable control signal are mutually inverse signals.

In some embodiments, the adjustment module further includes a first NOT gate, the input terminal of the first NOT gate is connected to the gate terminal of the NMOS transistor, and the output terminal of the first NOT gate is connected to the gate terminal of the PMOS transistor. The gate terminal connection, where:

The first NOT gate is configured to receive the first enable control signal and perform inversion processing on the first enable control signal to obtain the second enable control signal.

In some embodiments, the adjustment module includes a resistance module, one end of the resistance module is used to receive the compensation signal, the other end of the resistance module is connected to the output end of the conversion module and the input of the transmission module The ends are respectively connected, where:

The resistance module is configured to perform compensation processing on the intermediate data signal according to the compensation signal, so as to reduce the signal swing of the intermediate data signal.

In some embodiments, the transmission module includes a first transmission submodule and a second transmission submodule, the input terminal of the first transmission submodule is connected to the output terminal of the conversion module, and the first transmission submodule The output terminal of is connected to the input terminal of the second transmission sub-module, wherein:

The first transmission sub-module is configured to perform inversion processing on the intermediate data signal after compensation processing to obtain an initial target data signal;

The second transmission sub-module is configured to perform inversion processing on the initial target data signal to obtain the target data signal.

In some embodiments, one end of the adjustment module is connected to the output end of the first transmission sub-module, and the other end of the adjustment module is connected to the input end of the first transmission sub-module, wherein:

The first transmission submodule is further configured to determine the initial target data signal as the compensation signal.

In some embodiments, the first transmission submodule includes a second NOT gate and a first NAND gate, the second transmission submodule includes a third NOT gate, and the first input terminal of the first NAND gate For receiving the transmission control signal, the second input terminal of the first NAND gate is connected with the output terminal of the second NOT gate and the input terminal of the third NOT gate, and the output of the first NAND gate The terminal is connected to the input terminal of the second NOT gate; wherein, the input terminal of the second NOT gate is used as the input terminal of the first transmission sub-module, and the output terminal of the second NOT gate is used as the first The output terminal of the transmission sub-module, the input terminal of the third NOT gate is used as the input terminal of the second transmission sub-module, and the output terminal of the third NOT gate is used as the output terminal of the second transmission sub-module.

In some embodiments, the conversion module includes a first conversion sub-module, a second conversion sub-module, a third conversion sub-module and a fourth conversion sub-module, and the initial data signal includes the first initial data, the second initial data , the third initial data and the fourth initial data, wherein:

The first conversion sub-module is configured to receive the first initial data and a first clock signal, and perform sampling processing on the first initial data according to the first clock signal to obtain first intermediate data;

The second conversion sub-module is configured to receive the second initial data and a second clock signal, and perform sampling processing on the second initial data according to the second clock signal to obtain second intermediate data;

The third conversion sub-module is configured to receive the third initial data and a third clock signal, and perform sampling processing on the third initial data according to the third clock signal to obtain third intermediate data;

The fourth conversion sub-module is configured to receive the fourth initial data and a fourth clock signal, and perform sampling processing on the fourth initial data according to the fourth clock signal to obtain fourth intermediate data;

Wherein, the phases of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are respectively 0 degrees, 90 degrees, 180 degrees and 270 degrees, and the first middle data, said second intermediate data, said third intermediate data and said fourth intermediate data constitute said intermediate data signal.

In some embodiments, the conversion module includes a first conversion module and a second conversion module, the initial data signal includes a first initial data signal and a second initial data signal, and the first initial data signal and the The second initial data signal is a pair of differential signals, and the intermediate data signal includes a first intermediate data signal and a second intermediate data signal, wherein:

The first conversion module is configured to receive the first initial data signal, perform parallel-to-serial conversion processing on the first initial data signal, and obtain the first intermediate data signal;

The second converting module is configured to receive the second initial data signal, perform parallel-to-serial conversion on the second initial data signal, and obtain the second intermediate data signal.

In some embodiments, said compensation signal comprises said first intermediate data signal and said second intermediate data signal, wherein:

The adjustment module is configured to perform compensation processing on the second intermediate data signal according to the first intermediate data signal, so as to reduce the signal swing of the second intermediate data signal; and according to the second intermediate data signal performing compensation processing on the first intermediate data signal to reduce a signal swing of the first intermediate data signal.

In some embodiments, the target data signal includes a first target data signal and a second target data signal, and the transmission module includes a first transmission module and a second transmission module, wherein:

The first transmission module is configured to perform drive enhancement processing on the compensated first intermediate data signal to obtain the first target data signal;

The second transmission module is configured to perform drive enhancement processing on the compensated second intermediate data signal to obtain the second target data signal.

In some embodiments, one end of the adjustment module is respectively connected to the output end of the first conversion module and the input end of the first transmission module, and the other end of the adjustment module is connected to the second conversion module The output end is connected to the input end of the second transmission module respectively.

In some embodiments, the initial data signal is a parallel data signal, and both the intermediate data signal and the target data signal are serial data signals.

In a second aspect, an embodiment of the present disclosure provides a data conversion method, including:

receiving the initial data signal through the conversion module, and performing parallel-to-serial processing on the initial data signal to obtain an intermediate data signal;

receiving the compensation signal through the adjustment module, and performing compensation processing on the intermediate data signal according to the compensation signal, so as to reduce the signal swing of the intermediate data signal;

The intermediate data signal after compensation processing is received by the transmission module, and driving enhancement processing is performed on the intermediate data signal after compensation processing to obtain a target data signal.

In a third aspect, an embodiment of the present disclosure provides a memory, including the data conversion circuit according to any one of the first aspect.

Embodiments of the present disclosure provide a data conversion circuit, method and memory, the circuit includes a conversion module, an adjustment module and a transmission module, one end of the adjustment module is used to receive a compensation signal, the other end of the adjustment module is connected to the output end of the conversion module and The input ends of the transmission modules are connected separately, wherein: the conversion module is used to receive the initial data signal, and converts the initial data signal from parallel to serial to obtain the intermediate data signal; the adjustment module is used to perform the intermediate data signal according to the compensation signal. The compensation process is used to reduce the signal swing of the intermediate data signal; the transmission module is used to perform drive enhancement processing on the compensated intermediate data signal to obtain the target data signal. In this way, by setting the adjustment module in the data conversion circuit, the adjustment module performs compensation processing on the intermediate data signal according to the compensation signal, so that the signal swing of the intermediate data signal can be reduced, that is, the signal swing of the connection node between the conversion module and the transmission module can be reduced. Amplitude, so that the signal bandwidth increases, and finally achieve the purpose of transmitting high-frequency data, and improve the high-frequency performance of the circuit.

Description of drawings

Fig. 1 is a schematic diagram of the composition of a parallel-to-serial circuit;

FIG. 2 is a first schematic diagram of the composition and structure of a data conversion circuit provided by an embodiment of the present disclosure;

FIG. 3 is a second schematic diagram of the composition and structure of a data conversion circuit provided by an embodiment of the present disclosure;

FIG. 4 is a third schematic diagram of the composition and structure of a data conversion circuit provided by an embodiment of the present disclosure;

FIG. 5 is a fourth schematic diagram of the composition and structure of a data conversion circuit provided by an embodiment of the present disclosure;

FIG. 6 is a schematic diagram 5 of a composition and structure of a data conversion circuit provided by an embodiment of the present disclosure;

FIG. 7 is a sixth schematic diagram of the composition and structure of a data conversion circuit provided by an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a specific structure of a data conversion circuit provided by an embodiment of the present disclosure;

FIG. 9 is a second schematic structural diagram of a data conversion circuit provided by an embodiment of the present disclosure;

FIG. 10 is a schematic structural diagram of a conversion module provided by an embodiment of the present disclosure;

FIG. 11 is a schematic diagram of signal timing provided by an embodiment of the present disclosure;

FIG. 12 is a schematic diagram 7 of a composition and structure of a data conversion circuit provided by an embodiment of the present disclosure;

FIG. 13 is a specific structural schematic diagram III of a data conversion circuit provided by an embodiment of the present disclosure;

FIG. 14 is a schematic flowchart of a data conversion method provided by an embodiment of the present disclosure;

FIG. 15 is a schematic diagram of the composition and structure of a memory provided by an embodiment of the present disclosure.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure with reference to the drawings in the embodiments of the present disclosure. It should be understood that the specific embodiments described here are only used to explain the relevant disclosure, not to limit the disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant disclosure are shown in the drawings.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure, and are not intended to limit the present disclosure.

In the following description, references to "some embodiments" describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or a different subset of all possible embodiments, and Can be combined with each other without conflict.

It should be pointed out that the term "first\second\third" involved in the embodiments of the present disclosure is only to distinguish similar objects, and does not represent a specific ordering of objects. Understandably, "first\second\third" Where permitted, the specific order or sequencing may be interchanged such that the embodiments of the disclosure described herein can be practiced in sequences other than those illustrated or described herein.

Before the embodiments of the present disclosure are further described in detail, the nouns and terms involved in the embodiments of the present disclosure are explained first, and the nouns and terms involved in the embodiments of the present disclosure are applicable to the following explanations:

Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM);

Double Data Rate (DDR);

P-type Metal Oxide Semiconductor Field Effect Transistor (Positive channel Metal Oxide Semiconductor field effect transistor, PMOS transistor);

N-type metal oxide semiconductor field effect transistor (Negative channel Metal Oxide Semiconductor field effect transistor, NMOS tube);

D flip-flop (D flip-flop, DFF).

FIG. 1 is a schematic diagram of the composition and structure of a parallel-to-serial circuit. As shown in Figure 1, the parallel-to-serial circuit 10 is a circuit for converting four parallel data into serial data, including four P2S4tol sub-circuits, and these four P2S4tol sub-circuits respectively receive four parallel data: DataER, DataEF, DataOR and DataOF, and receive four clock signals respectively: SedCKER, SedCKEF, SedCKOR and SedCKOF. The four P2S4tol sub-circuits sample the four parallel data according to the four clock signals and output the serial data at the PupMid node.

The serial data of the PupMid node is driven and enhanced through the inverter X1 and the inverter X2, and finally the serial data DataPu is obtained. At the same time, the NAND gate Xfb is connected in parallel with the inverter X1, and controls whether the serial data can be transmitted normally according to the DqRstN signal.

As the data rate increases, for example from LPDDR4 4266Mbps to LPDDR5 6400Mbps, due to the limitation of device performance, the performance of this circuit encounters a bottleneck. The main reason is that the PupMid node not only needs to connect four P2S4to1 sub-circuits, but also connects the output devices X1 and Xfb, which leads to a large parasitic capacitance of the PupMid node, which limits the high-frequency performance of the circuit. In order to improve the high-frequency performance of this circuit, one method is to reduce the parasitic capacitance of the PupMid node through the layout, but due to structural limitations, the parasitic capacitance cannot be reduced infinitely, which can be improved but there is a bottleneck.

Based on this, an embodiment of the present disclosure provides a data conversion circuit, the circuit includes a conversion module, an adjustment module and a transmission module, one end of the adjustment module is used to receive a compensation signal, and the other end of the adjustment module is connected to the output end of the conversion module and transmits The input ends of the modules are respectively connected, wherein: the conversion module is used to receive the initial data signal, and converts the initial data signal from parallel to serial to obtain the intermediate data signal; the adjustment module is used to compensate the intermediate data signal according to the compensation signal The processing is used to reduce the signal swing of the intermediate data signal; the transmission module is used to perform drive enhancement processing on the compensated intermediate data signal to obtain the target data signal. In this way, by setting the adjustment module in the data conversion circuit, the adjustment module performs compensation processing on the intermediate data signal according to the compensation signal, so that the signal swing of the intermediate data signal can be reduced, that is, the signal swing of the connection node between the conversion module and the transmission module can be reduced. Amplitude, so that the signal bandwidth increases, and finally achieve the purpose of transmitting high-frequency data, and improve the high-frequency performance of the circuit.

Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In an embodiment of the present disclosure, refer to FIG. 2 , which shows a first compositional structure diagram of a data conversion circuit provided by an embodiment of the present disclosure. As shown in Figure 2, the data conversion circuit 20 includes a conversion module 201, an adjustment module 202 and a transmission module 203, one end of the adjustment module 202 is used to receive the compensation signal, and the other end of the adjustment module 202 is connected to the output end of the conversion module 201 and transmits The input terminals of module 203 are respectively connected, wherein:

The conversion module 201 is used to receive the initial data signal, perform parallel-to-serial processing on the initial data signal, and obtain an intermediate data signal;

An adjustment module 202, configured to perform compensation processing on the intermediate data signal according to the compensation signal, so as to reduce the signal swing of the intermediate data signal;

The transmission module 203 is configured to perform drive enhancement processing on the compensated intermediate data signal to obtain a target data signal.

It should be noted that, in the data conversion circuit 20, the conversion module 201 receives parallel initial data signals, converts the parallel initial data signals into serial intermediate data signals, and the transmission module 203 drives and enhances the serial intermediate data signals , to get the serial target data signal. That is to say, in the embodiment of the present disclosure, the initial data signal is a parallel data signal, and both the intermediate data signal and the target data signal are serial data signals.

It should also be noted that, as shown in FIG. 2 , the output end of the conversion module 201 , the input end of the transmission module 203 , and one end of the adjustment module 202 are connected to the same node, and the signal at the node is an intermediate data signal. Since there are many devices connected to this node, the parasitic capacitance of this node is relatively large, which limits the high-frequency characteristics of the device. At this time, the adjustment module 202 may perform compensation processing on the node according to the received compensation signal to reduce the signal swing of the node, that is, perform compensation processing on the intermediate data signal to reduce the signal swing of the intermediate data signal. In this way, since the signal swing is reduced, the signal bandwidth is increased, thereby improving the high-frequency performance of the circuit and achieving the purpose of transmitting high-frequency data.

It should also be noted that the compensation signal is usually a signal opposite to the level state of the intermediate data signal. For example, if the intermediate data signal is at a high level and the compensation signal is at a low level, the low-level compensation signal will pass through the adjustment module 202 affects the voltage of the intermediate data signal, so that the voltage of the intermediate data signal is lower than the original high level; similarly, when the intermediate data signal is at low level and the compensation signal is at high level, the compensation signal passes through the adjustment module 202 It will also pull up the voltage of the intermediate data signal. Finally, the swing amplitude of the intermediate data signal can be reduced, thereby realizing the transmission of high-frequency data.

For the adjustment module 202, in a possible implementation, as shown in FIG. For the compensation signal, the other end of the transmission gate module 2021 is connected to the output terminal of the conversion module 201 and the input terminal of the transmission module 203 respectively, and the control terminal of the transmission gate module 2021 is used to receive the enable control signal, wherein:

When the enable control signal is in a valid state, the transmission gate module 2021 is turned on to perform compensation processing on the intermediate data signal according to the compensation signal; or, when the enable control signal is in an invalid state, the transmission gate module 2021 is turned off.

It should be noted that, as shown in FIG. 3 , the adjustment module 202 may be implemented by a transmission gate module 2021 . At this time, the compensation signal acts on the intermediate data signal through the transmission gate module 2021 to reduce the signal swing of the intermediate data signal.

It should also be noted that the embodiments of the present disclosure mainly perform compensation processing on the intermediate data signal when the high-frequency signal is transmitted, so as to meet the needs of the circuit for transmitting high-frequency signals. The data signal is compensated. Therefore, the enable control signal can also be used to control whether the transmission gate module 2021 is turned on, so that only when the signal swing of the intermediate data signal needs to be reduced, the enable control signal is in an active state, and at this time the transmission gate module 2021 is turned on ; When the intermediate data signal does not need to be compensated, the enable control signal is in an invalid state, and at this time the transmission gate module 2021 will not be turned on, and the intermediate data signal will not be compensated.

In this way, by enabling the control signal to control the transmission gate module 2021, not only can the signal swing of the intermediate data signal be reduced to meet the requirements of high-frequency data transmission, but also the transmission gate module 2021 can be turned off in other scenarios to save circuits. The power consumption meets the usage requirements of various scenarios and realizes flexible control.

Further, for the transmission gate module 2021, as shown in FIG. 4, the transmission gate module 2021 includes an NMOS transistor (N1) and a PMOS transistor (P1), and the first end of the NMOS transistor is connected to the first end of the PMOS transistor as a transmission One end of the gate module 2021, the second end of the NMOS transistor is connected to the second end of the PMOS transistor as the other end of the transmission gate module 2021;

The control terminal of the transmission gate module 2021 includes a gate terminal of an NMOS transistor and a gate terminal of a PMOS transistor. The gate terminal of the NMOS transistor is connected to the first enabling control signal, and the gate terminal of the PMOS transistor is connected to the second enabling control signal. The first enable control signal and the second enable control signal are mutually inverse signals.

It should be noted that, as shown in FIG. 4 , the transmission gate module 2021 may be formed by connecting an NMOS transistor and a PMOS transistor. At this time, the gate terminals of the NMOS transistor and the PMOS transistor are respectively used as the two control terminals of the transmission gate module 2021. Correspondingly, the enabling control signal includes a pair of antiphase signals: the first enabling control signal and the second enabling control signal The first end of the NMOS tube is connected to the first end of the PMOS tube as one end of the receiving compensation signal of the transmission gate module 2021, and the second end of the NMOS tube is connected to the second end of the PMOS tube as the AND conversion module of the transmission gate module 2021 The output end of 201 is connected to the other end of the input end of the transmission module 203 .

In this way, for the first enable control signal and the second enable control signal, the active state of the first enable control signal can be a high level state (logic "1"), and the active state of the second enable control signal May be low state (logic "0"). When the first enable control signal is in the high level state and/or the second enable control signal is in the low level state, the NMOS transistor and/or the PMOS transistor are turned on, so that the compensation signal can be transmitted to where the intermediate data signal is Node, to realize the compensation processing of the intermediate data signal; when the first enable control signal is in the low level state and the second enable control signal is in the high level state, neither the NMOS transistor nor the PMOS transistor is turned on, and the transmission gate module 2021 is turned off, the compensation signal will not be transmitted to the node where the intermediate data signal is located, and at this time, the intermediate data signal will not be compensated.

Since the first enable control signal and the second enable control signal are inversion signals, the first enable control signal can be inverted into the second enable control signal through a NOT gate. Therefore, in some embodiments, on the basis of the circuit shown in FIG. 4, as shown in FIG. connected, the output terminal of the first NOT gate 2022 is connected to the gate terminal of the PMOS transistor, wherein:

The first NOT gate 2022 is configured to receive the first enable control signal, and perform inversion processing on the first enable control signal to obtain the second enable control signal.

It should be noted that, as shown in FIG. 5 , the input end of the first NOT gate 2022 is connected to the gate end of the NMOS transistor, both of which are used to receive the first enable control signal, and the output end of the first NOT gate 2022 is connected to the gate end of the PMOS transistor. The gate terminal is connected, so that the first inverting gate 2022 can provide the second enable control signal obtained by inverting the first enable control signal to the gate terminal of the PMOS transistor.

It should also be noted that, as can be seen from FIG. 5, for the transmission gate module 2021, the two control terminals (the gate terminal of the PMOS transistor and the gate terminal of the NMOS transistor) respectively receive the first enabling control signal and the second enabling control signal. enable control signal, and for the adjustment module 202 as a whole, it only needs to receive a first enable control signal. In this way, since the transmission gate module can be turned on only in the high-speed mode of transmitting high-frequency data, the level state of the first enable control signal can be controlled. In the high-speed mode, the first enable control signal is high. Level (logic "1"), in an active state, so that the transmission gate module 2021 is turned on to reduce the signal swing of the intermediate data signal; in the non-high-speed mode, the first enable control signal is low level (logic " 0"), in an invalid state, the transmission gate module 2021 will not be turned on, saving power consumption. It can be seen that whether the first enable control signal is valid is determined according to whether high-frequency data is currently being transmitted, and then the transmission gate module 2021 is turned on or off. Therefore, the first enable control signal can also be called a high-speed enable signal (High Speed Enable, HSEn).

It should also be noted that the first NOT gate 2022 can also be connected in the following manner: the input terminal of the first NOT gate 2022 is connected to the gate terminal of the PMOS transistor, both of which are used to receive the second enable control signal, and the first NOT gate The output terminal of the gate is connected with the gate terminal of the NMOS transistor, and is used for outputting the first enabling control signal. At this time, the adjustment module 202 as a whole only needs to receive a second enabling control signal, the second enabling control signal is used as a high-speed enabling signal, its active state is low level (logic "0"), and its invalid state is high level (logic "1"). The control of the transmission gate module 2021 can also be realized.

For the adjustment module 202, in another possible implementation manner, as shown in FIG. The output end of the conversion module 201 is connected to the input end of the transmission module 203 respectively, wherein:

The resistance module 2023 is configured to perform compensation processing on the intermediate data signal according to the compensation signal, so as to reduce the signal swing of the intermediate data signal.

It should be noted that, as shown in FIG. 6 , the adjustment module 202 may also be realized by a resistance module 2023 . The function of the resistance module 2023 is similar to the aforementioned transmission gate module 2021. The compensation signal is transmitted to the node where the intermediate data signal is located through the resistance module 2023. The compensation signal is usually opposite to the state of the intermediate data signal level, so that for the high-level intermediate The voltage of the data signal can be pulled down, and the voltage of the low-level intermediate data signal can be pulled up, so as to finally reduce the signal swing of the intermediate data signal and achieve the purpose of transmitting high-frequency signals.

It should also be noted that the resistor module 2023 can be implemented as a fixed resistor or a variable resistor, or a combination of a fixed resistor and a variable resistor, which is not specifically limited here. In this way, the degree of compensation to the intermediate data signal can also be adjusted by adjusting the resistance value of the variable resistor, so as to realize flexible control.

For example, according to the frequency level of the data, it can be divided into low frequency, first level high frequency and second level high frequency in sequence from low to high. The signal can hardly pass through, which is equivalent to the disconnected state, so that the intermediate data signal is hardly compensated; in the first-level high-frequency scenario, the resistance value of the resistance module 2023 can be set to the first resistance value, so that the compensation signal can pass through However, there is a certain loss to achieve a certain degree of compensation for the intermediate data signal; in the second-level high-frequency scene, the resistance value of the resistance module 2023 can be set to the second resistance value (the second resistance value is smaller than the first resistance value ), so that the compensation signal can pass through with low loss, achieving a higher degree of compensation for the intermediate data signal.

Further, for the transmission module 203, as shown in FIG. 7, in some embodiments, the transmission module 203 includes a first transmission sub-module 2031 and a second transmission sub-module 2032, and the input terminal of the first transmission sub-module 2031 is connected to The output end of the conversion module 201 is connected, and the output end of the first transmission sub-module 2031 is connected with the input end of the second transmission sub-module 2032, wherein:

The first transmission sub-module 2031 is configured to perform inversion processing on the compensated intermediate data signal to obtain an initial target data signal;

The second transmission sub-module 2032 is configured to perform inversion processing on the initial target data signal to obtain the target data signal.

It should be noted that, as shown in FIG. 7, in the transmission module 203, the first transmission sub-module 2031 is connected to the conversion module 201 and the adjustment module 202 respectively, and is used to receive the intermediate data signal after compensation processing and perform inversion processing After obtaining the initial target data signal, send it to the second transmission sub-module 2032; after receiving the initial target data signal, the second transmission sub-module performs inversion processing again, and inverts the initial target data signal into a target data signal. Since the intermediate data signal is serial data, the initial target data signal and the target data signal are also serial data signals.

In this way, after the two-stage inversion processing of the first transmission sub-module 2031 and the second transmission sub-module 2032, compared with the intermediate data signal, the level state of the finally obtained target data signal remains unchanged, but the driving capability is enhanced and more Facilitate the transmission of data signals.

Since the compensation signal is usually a signal opposite to the level state of the intermediate data signal, and the initial target data signal is obtained by inverting the intermediate data signal, then the initial target data signal can be used as the compensation signal in the embodiment of the present disclosure . Therefore, as shown in FIG. 7, in some embodiments, one end of the adjustment module 202 is connected to the output end of the first transmission sub-module 2031, and the other end of the adjustment module 202 is connected to the input end of the first transmission sub-module 2032, wherein :

The first transmission sub-module 2031 is further configured to determine the initial target data signal as the compensation signal.

It should be noted that, as shown in FIG. 7, the output end of the first transmission sub-module 2031 can be connected to one end of the adjustment module 202, and the node where the intermediate data signal is located is denoted as the PupMid node, and the node where the initial target data signal is located is denoted as As a PupMidN node, the adjustment module 202 is connected between the PupMid node and the PupMidN node. In this way, for the data conversion circuit 20, the initial data signal is processed into an intermediate data signal by the conversion module 201, and the intermediate data signal is processed in reverse by the first conversion sub-module 2031 into an initial target data signal, and the initial target data signal is used as a compensation signal, which is an anti-phase signal with the intermediate data signal, and the adjustment module 202 performs compensation processing on the intermediate data signal according to the initial target data signal, so that the signal swing of the intermediate data signal is reduced, that is, the signal swing of the PupMid node is reduced, In turn, the high-frequency performance of the circuit can be improved, and the speed at which the circuit transmits data can be improved.

Further, FIG. 8 is a specific structural schematic diagram of a data conversion circuit provided by an embodiment of the present disclosure based on FIG. 5 , and FIG. 9 is a data conversion circuit provided by an embodiment of the present disclosure on the basis of FIG. 6 . Schematic diagram of the specific structure of the circuit II. The adjustment module 202 in FIG. 8 is realized by a transmission gate module 2021 and the first NOT gate 2022 , and the adjustment module 202 in FIG. 9 is realized by a resistance module 2023 .

It should be noted that, in FIG. 8, the output end of the first transmission sub-module 2031 is connected to the first end of the PMOS transistor and the NMOS transistor (the first end of the transmission gate module 2021). In FIG. 9, the first transmission sub-module The output end of the module 2031 is connected to one end of the resistance module 2023 . In this way, the first transmission sub-module 2031 can directly provide the output initial target data signal as a compensation signal to the adjustment module 202 for performing compensation processing on the intermediate data signal.

As shown in Figure 8 or Figure 9, in some embodiments, the first transmission sub-module 2031 includes a second NOT gate 2033 and a first NAND gate 2034, the second transmission sub-module 2032 includes a third NOT gate 2035, the first The first input end of the NAND gate 2034 is used to receive the transmission control signal, the second input end of the first NAND gate 2034 is connected with the output end of the second NOT gate 2033 and the input end of the third NOT gate 2035, the first AND The output end of the NOT gate 2034 is connected to the input end of the second NOT gate 2033; wherein, the input end of the second NOT gate 2033 is used as the input end of the first transmission submodule 2031, and the output end of the second NOT gate 2033 is used as the first transmission submodule. The output terminal of the sub-module 2031 and the input terminal of the third NOT gate 2035 serve as the input terminal of the second transmission sub-module 2032 , and the output terminal of the third NOT gate 2035 serves as the output terminal of the second transmission sub-module 2032 .

It should be noted that, as shown in FIG. 8 or FIG. 9, in the first transmission sub-module 2031, the first NAND gate 2034 and the second NAND gate 2033 are connected end to end, and the second input terminal of the first NAND gate 2034 is connected to In the PupMidN node, the output terminal is connected to the PupMid node.

In addition to receiving the initial target data signal output by the second NOT gate 2033 through the second input terminal, the first NAND gate 2034 also receives a transmission control signal (also called DQ reset N, DqRstN) through the first input terminal, and transmits the control signal Whether data can be normally transmitted by the first transmission sub-module 2031 can be controlled. When the transmission control signal is high level (logic “1”), data can be transmitted normally, and when the transmission control signal is low level (logic “0”), data cannot be transmitted normally. In this way, the embodiment of the present disclosure can also control whether the intermediate data signal is normally transmitted as the initial target data signal through the first NAND gate 2034 and the transmission control signal, which increases the flexibility of data conversion and avoids the need to transmit data In some cases, the data is wrongly transmitted and causes problems such as circuit interference.

That is to say, when the transmission control signal is at a high level, data transmission is not affected, and the first NAND gate 2034 and the second NAND gate 2033 form a latch to latch data. When the level state of the transmission control signal is low level, the PupMid node will always be high level and cannot transmit data normally.

As shown in Figure 8 or Figure 9, in some embodiments, for the conversion module 201, the conversion module 201 may include a first conversion sub-module 2011, a second conversion sub-module 2012, a third conversion sub-module 2013 and a fourth conversion sub-module 2013 Converting sub-module 2014, the initial data signal may include first initial data, second initial data, third initial data and fourth initial data, wherein:

The first conversion sub-module 2011 is configured to receive first initial data and a first clock signal, and perform sampling processing on the first initial data according to the first clock signal to obtain first intermediate data;

The second converting sub-module 2012 is configured to receive the second initial data and the second clock signal, perform sampling processing on the second initial data according to the second clock signal, and obtain the second intermediate data;

The third conversion sub-module 2013 is configured to receive third initial data and a third clock signal, and perform sampling processing on the third initial data according to the third clock signal to obtain third intermediate data;

The fourth conversion sub-module 2014 is configured to receive fourth initial data and a fourth clock signal, and perform sampling processing on the fourth initial data according to the fourth clock signal to obtain fourth intermediate data;

Wherein, the phases of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are 0 degrees, 90 degrees, 180 degrees and 270 degrees respectively, the first intermediate data, the second intermediate data, the third intermediate The data and the fourth intermediate data constitute an intermediate data signal.

It should be noted that, as shown in FIG. 8 or FIG. 9, taking the initial data signal including four channels of parallel data as an example, at this time, the conversion module 201 correspondingly includes four conversion sub-modules (also denoted as P2S4tol sub-circuits), respectively used The method is used to sample and process four channels of parallel data to output four intermediate data to form an intermediate data signal. Wherein, the output terminal of the first conversion submodule 2011, the output terminal of the second conversion submodule 2012, the output terminal of the third conversion submodule 2013 and the output terminal of the fourth conversion submodule 2014 are connected to the PupMid node as the conversion module 201 The output terminal is used to output the intermediate data signal.

It should also be noted that in each conversion sub-module, the clock signal is used to control the sampling time of the corresponding initial data, so as to ensure the timing among the four output intermediate data to form the intermediate data signal. Exemplarily, FIG. 10 shows a specific structural diagram of a conversion module 201 provided by an embodiment of the present disclosure, wherein the conversion module 201 may further include a clock signal generator 2015, and the clock signal generator 2015 receives a first clock signal ( SedCKER), the second clock signal (SedCKEF), the third clock signal (SedCKOR) and the fourth clock signal (SedCKOF), the first clock selection signal (SedCKERN) is generated according to the rising edge of the first clock signal (SedCKER), and the first clock selection signal (SedCKERN) is generated according to the The rising edge of the second clock signal (SedCKEF) generates the second clock selection signal (SedCKEFN), generates the third clock selection signal (SedCKORN) according to the rising edge of the third clock signal (SedCKOR), and generates the third clock selection signal (SedCKORN) according to the rising edge of the fourth clock signal (SedCKOF). The edge generates the fourth clock selection signal (SedCKOFN), and the pulse width of each clock selection signal is smaller than the pulse width of the corresponding clock signal. The signal timing of each clock signal and clock selection signal can be shown in FIG. 10 .

The first conversion sub-module 2011 may include a first flip-flop (DFF1) and a first switch (S1), the second conversion sub-module 2012 may include a second flip-flop (DFF2) and a second switch (S2), a third conversion sub-module The module 2013 may include a third flip-flop (DFF3) and a third switch (S3), and the fourth converting sub-module 2014 may include a fourth flip-flop (DFF4) and a fourth switch (S4).

In the first conversion sub-module 2011, the first flip-flop DFF1 samples the first initial data DataER at the rising edge of the first clock signal SedCKER, and the first switch S1 closed, so that the sampled signal passes through the first switch S1 to obtain the first intermediate data D1'. Similarly, in the second conversion sub-module 2012, the second flip-flop DFF2 samples the second initial data DataEF at the rising edge of the second clock signal SedCKEF, and during the period when the second selection clock signal SedCKEFN is in a high level state, the first The second switch S2 is closed, so that the sampled signal passes through the second switch S2 to obtain the second intermediate data D2'; The data DataOR is sampled, and during the period when the third selection clock signal SedCKORN is in a high level state, the third switch S3 is closed, so that the sampled signal passes through the third switch S3 to obtain the third intermediate data D3'; in the fourth conversion sub-module 2014 Among them, the fourth flip-flop DFF4 samples the fourth initial data DataOF at the rising edge of the fourth clock signal SedCKOF, and when the fourth select clock signal SedCKOFN is in the high level state, the fourth switch S4 is closed, so that the sampled signal The fourth intermediate data D4' is obtained through the fourth switch S4.

As shown in Figure 10 and Figure 11, due to the timing difference between the four clock selection signals, when sampling the parallel first initial data DataER, second initial data DataEF, third initial data DataOR and fourth initial data DataOF After being output, the four intermediate data can be output in sequence, and finally the serial intermediate data signal can be obtained at the PupMid node.

Further, the embodiments of the present disclosure may also be applied in scenarios where differences exist. As shown in Figure 12, in some embodiments, the conversion module 201 includes a first conversion module 204 and a second conversion module 205, the initial data signal includes a first initial data signal and a second initial data signal, and the first initial data signal and the second initial data signal are a pair of differential signals, and the intermediate data signal includes a first intermediate data signal and a second intermediate data signal, wherein:

The first conversion module 204 is configured to receive the first initial data signal, perform parallel-to-serial conversion processing on the first initial data signal, and obtain the first intermediate data signal;

The second conversion module 205 is configured to receive the second initial data signal, perform parallel-to-serial conversion processing on the second initial data signal, and obtain a second intermediate data signal.

It should be noted that, in the embodiment of the present disclosure, the initial data signal may be a pair of differential signals (or inverted signals), including a first initial data signal and a second initial data signal, and the first initial data signal and the second initial data signal Both initial data signals are parallel data signals; the first conversion module 204 processes the first initial data signal into a serial first intermediate data signal, and the second conversion module 205 processes the second initial data signal into a serial second intermediate data signal. It can be understood that the first intermediate data signal and the second intermediate data signal are also a pair of differential signals, and the level states of the two are opposite.

At this time, as shown in FIG. 12 , one end of the adjustment module 202 is connected to the output end of the first conversion module 204 , and the other end of the adjustment module 202 is connected to the output end of the second conversion module 205 . The second intermediate data signal is used as a compensation signal for compensating the first intermediate data signal, and the first intermediate data signal is used as a compensation signal for compensating the second intermediate data signal. That is, the compensation signal includes a first intermediate data signal and a second intermediate data signal, wherein:

An adjustment module 202, configured to perform compensation processing on the second intermediate data signal according to the first intermediate data signal, so as to reduce the signal swing of the second intermediate data signal; and perform compensation processing on the first intermediate data signal according to the second intermediate data signal , to reduce the signal swing of the first intermediate data signal.

It can be seen that for an application scenario where there is a difference, the embodiment of the present disclosure can also connect the adjustment module 202 between two differential signals (the first intermediate data signal and the second intermediate data signal), so as to reduce the first intermediate data signal and the second intermediate data signal at the same time. Signal swing of the second intermediate data signal.

Correspondingly, the target data signal includes a first target data signal and a second target data signal, and the transmission module 203 includes a first transmission module 206 and a second transmission module 207, wherein:

The first transmission module 206 is configured to perform drive enhancement processing on the compensated first intermediate data signal to obtain a first target data signal;

The second transmission module 207 is configured to perform drive enhancement processing on the compensated second intermediate data signal to obtain a second target data signal.

One end of the adjustment module 202 is connected to the output end of the first conversion module 204 and the input end of the first transmission module 206 respectively, and the other end of the adjustment module 202 is connected to the output end of the second conversion module 205 and the input end of the second transmission module 207 Connect separately.

It should be noted that, as shown in FIG. 12 , the connection node between the first conversion module 204 and the first transmission module 206 is designated as the PupMid1 node, and the connection node between the second conversion module 205 and the second transmission module 207 is designated as the PupMid2 node. . The adjustment module 202 is connected between the PupMid1 node and the PupMid2 node, and not only can compensate the first intermediate data signal according to the second intermediate data signal, but also reduce the signal swing of the first intermediate data signal, that is, reduce the signal swing of the PupMid1 node The second intermediate data signal can also be compensated according to the first intermediate data signal to reduce the signal swing of the second intermediate data signal, that is, reduce the signal swing of the PupMid2 node, and then obtain the second intermediate data signal through the first transmission module 206 A target data signal (also written as DataPu) is passed through the second transmission module 207 to obtain a second target data signal (also written as DataPd). It can be understood that the first target data signal and the second target data signal are also a pair of differential signals. are mutually anti-phase signals. Finally, it can be realized that both the first transmission path (the first conversion module 204 and the second transmission module 206) and the second transmission path (the second conversion module 205 and the second transmission module 207) can transmit high-frequency signals, effectively improving the high-frequency performance of the circuit.

Further, for an application scenario where there is a difference, take the adjustment module 202 including the transmission gate module 2021 and the first NOT gate 2022 as an example, see FIG. 13 , which shows a specific structure of a data conversion circuit provided by an embodiment of the present disclosure Diagram three. As shown in Figure 13, the structure and function of the first conversion module 204 and the second conversion module 205 are the same as the conversion module 201 in Figure 8 or Figure 9, and its specific structure and function can also be described with reference to Figure 10 and Figure 11 understand. At the same time, the first conversion module 204 and the second conversion module 205 can also share the same clock signal generator 2015; the structure and function of the first transmission module 206 and the second transmission module 207 are the same as those of the transmission module 203 in Figure 8 or Figure 9 same. For its specific function description, it will not be repeated here.

The difference in the differential scenario lies in the connection mode of the adjustment module 202. At this time, the adjustment module 202 is connected between the PupMid1 node and the PupMid2 node, thereby reducing the signal swing of the PupMid1 node according to the second intermediate data signal, and according to the first The intermediate data signal reduces the signal swing of the PupMid2 node.

Among them, the four initial data received by the first conversion module 204 are respectively: DataER, DataEF, DataOR and DataOF, and the four initial data received by the second conversion module 205 are respectively DataERN, DataEFN, DataORN and DataOFN. It can be understood that DataER and DataERN is a pair of anti-phase signals, and the clock signals for sampling the pair of anti-phase signals are both SedCKER; DataEF and DataEFN are a pair of anti-phase signals, and the clock signals for sampling the pair of anti-phase signals are both SedCKEF; DataOR and DataORN is a pair of anti-phase signals, and the clock signals for sampling the pair of anti-phase signals are both SedCKOR; DataOF and DataOFN are a pair of anti-phase signals, and the clock signals for sampling the pair of anti-phase signals are both SedCKOF.

Similarly, for an application scenario where there is a difference, the adjustment module 202 can be realized by the resistance module 2023. At this time, the resistance module 2023 is connected between the PupMid1 node and the PupMid2 node. Or, it is also possible to set two adjustment modules 202 to reduce the signal swings of the PupMid1 node and the PupMid2 node according to the connection method shown in FIG. 8 or FIG. 9 , which is also conducive to the transmission of high frequency data and improves the high frequency performance of the circuit. For a more specific description of FIG. 13 , it can be understood with reference to the foregoing FIG. 8 to FIG. 10 , and will not be repeated here.

In short, the data conversion circuit provided by the embodiments of the present disclosure can increase the conversion rate from parallel data to serial data. In order to improve the high-frequency performance of the data conversion circuit, the high-frequency performance is improved by reducing the swing of the PupMid node. The application scenarios with differences are mainly implemented through the adjustment module connected between the PupMid node and the PupMidN node. In high-speed mode, the HSEn signal is high, and the transmission tube is turned on, which reduces the swing of the PupMid node and increases the signal bandwidth, thereby achieving the purpose of transmitting high-frequency data; or, by connecting between the PupMid node and the PupMidN node The resistor module is realized. For the scenario where there is a difference, since the same data needs to be differentially output, when the PupMid1 node is high (High), the PdnMid2 node is (Low), so you can add a transmission tube between the PupMid1 node and the PdnMid2 node. At the same time, the voltage swing of the PupMid1 node and the PdnMid2 node is reduced to achieve the purpose of transmitting high-speed data.

An embodiment of the present disclosure provides a data conversion circuit, the circuit includes a conversion module, an adjustment module and a transmission module, one end of the adjustment module is used to receive a compensation signal, and the other end of the adjustment module is connected to the output end of the conversion module and the input of the transmission module The terminals are respectively connected, wherein: the conversion module is used to receive the initial data signal, and converts the initial data signal from parallel to serial to obtain the intermediate data signal; the adjustment module is used to perform compensation processing on the intermediate data signal according to the compensation signal, so as to The signal swing of the intermediate data signal is reduced; the transmission module is used for driving and enhancing the compensated intermediate data signal to obtain the target data signal. In this way, by setting the adjustment module in the data conversion circuit, the adjustment module performs compensation processing on the intermediate data signal according to the compensation signal, so that the signal swing of the intermediate data signal can be reduced, that is, the signal swing of the connection node between the conversion module and the transmission module can be reduced. Amplitude, so that the signal bandwidth increases, and finally achieve the purpose of transmitting high-frequency data, and improve the high-frequency performance of the circuit.

In another embodiment of the present disclosure, refer to FIG. 14 , which shows a schematic flowchart of a data conversion method provided by an embodiment of the present disclosure. As shown in Figure 14, the method may include:

S1001: Receive the initial data signal through the conversion module, perform parallel-to-serial processing on the initial data signal, and obtain an intermediate data signal.

S1002: Receive the compensation signal through the adjustment module, and perform compensation processing on the intermediate data signal according to the compensation signal, so as to reduce the signal swing of the intermediate data signal.

S1003: Receive the compensated intermediate data signal through the transmission module, and perform drive enhancement processing on the compensated intermediate data signal to obtain a target data signal.

In some embodiments, performing compensation processing on the intermediate data signal according to the compensation signal includes: when the enable control signal is in an active state, turning on the transmission gate module, so as to perform compensation processing on the intermediate data signal according to the compensation signal; or, at When the enable control signal is in an invalid state, the transmission gate module is turned off.

In some embodiments, the enable control signal includes a first enable control signal and a second enable control signal, and the method may further include: receiving the first enable control signal through a first NOT gate, and performing the first enable control signal Inverting the control signal to obtain a second enable control signal.

In some embodiments, performing compensation processing on the intermediate data signal according to the compensation signal includes: performing compensation processing on the intermediate data signal according to the compensation signal through a resistance module, so as to reduce a signal swing of the intermediate data signal.

In some embodiments, performing drive enhancement processing on the compensated intermediate data signal to obtain the target data signal includes:

Inverting the compensated intermediate data signal through the first transmission sub-module to obtain the initial target data signal;

The target data signal is obtained by inverting the initial target data signal through the second transmission sub-module.

In some embodiments, the method may further include: determining the initial target data signal as the compensation signal.

In some embodiments, parallel-to-serial processing is performed on the initial data signal to obtain an intermediate data signal, including:

receiving the first initial data and the first clock signal through the first conversion sub-module, and sampling the first initial data according to the first clock signal to obtain the first intermediate data;

receiving the second initial data and the second clock signal through the second converting sub-module, and sampling the second initial data according to the second clock signal to obtain the second intermediate data;

receiving the third initial data and the third clock signal through the third converting sub-module, and sampling the third initial data according to the third clock signal to obtain the third intermediate data;

receiving the fourth initial data and the fourth clock signal through the fourth conversion sub-module, and sampling the fourth initial data according to the fourth clock signal to obtain the fourth intermediate data;

Wherein, the phases of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are 0 degrees, 90 degrees, 180 degrees and 270 degrees respectively, the first intermediate data, the second intermediate data, the third intermediate The data and the fourth intermediate data constitute an intermediate data signal.

In some embodiments, the initial data signal includes a first initial data signal and a second initial data signal, and the first initial data signal and the second initial data signal are a pair of differential signals, and the intermediate data signal includes a first intermediate data signal and The second intermediate data signal is to perform parallel-to-serial processing on the initial data signal to obtain the intermediate data signal, including:

receiving the first initial data signal through the first conversion module, and performing parallel-to-serial conversion processing on the first initial data signal to obtain the first intermediate data signal;

The second initial data signal is received by the second converting module, and the parallel-to-serial conversion process is performed on the second initial data signal to obtain a second intermediate data signal.

In some embodiments, the compensation signal includes a first intermediate data signal and a second intermediate data signal, and performing compensation processing on the intermediate data signal according to the compensation signal includes:

The adjustment module performs compensation processing on the second intermediate data signal according to the first intermediate data signal to reduce the signal swing of the second intermediate data signal; and performs compensation processing on the first intermediate data signal according to the second intermediate data signal to reduce the Signal swing of the first intermediate data signal.

In some embodiments, the target data signal includes a first target data signal and a second target data signal, and performing drive enhancement processing on the compensated intermediate data signal to obtain the target data signal, including:

performing drive enhancement processing on the compensated first intermediate data signal through the first transmission module to obtain a first target data signal;

The driving enhancement processing is performed on the compensated second intermediate data signal through the second transmission module to obtain the second target data signal.

In some embodiments, the initial data signal is a parallel data signal, and both the intermediate data signal and the target data signal are serial data signals.

It should be noted that the data conversion method provided by the embodiments of the present disclosure can be applied to the data conversion circuit 20 described in the foregoing embodiments. For details not disclosed in the embodiments of the present disclosure, please refer to the descriptions of the foregoing embodiments for understanding.

The embodiment of the present disclosure provides a data conversion method, which performs compensation processing on the intermediate data signal according to the compensation signal, which can reduce the signal swing of the intermediate data signal, thereby increasing the signal bandwidth, and finally achieving the purpose of transmitting high-frequency data, improving the high-frequency performance of the circuit.

In yet another embodiment of the present disclosure, refer to FIG. 15 , which shows a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure. As shown in FIG. 15 , the semiconductor memory 150 may at least include the data conversion circuit 20 described in any one of the foregoing embodiments.

In some embodiments, the semiconductor memory 150 is a dynamic random access memory (DRAM) chip.

In the embodiment of the present disclosure, for DRAM, it can not only conform to memory specifications such as DDR, DDR2, DDR3, DDR4, and DDR5, but also can conform to memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, and LPDDR5. There is no limitation here.

In the embodiment of the present disclosure, for the semiconductor memory 150 , since it includes the data conversion circuit 20 described in the foregoing embodiments, the signal bandwidth is increased, and the purpose of transmitting high-frequency data is finally achieved, and the performance of the memory is improved.

The above descriptions are only exemplary embodiments of the present disclosure, and are not intended to limit the protection scope of the present disclosure.

It should be noted that in this disclosure, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements , but also includes other elements not expressly listed, or also includes elements inherent in such a process, method, article, or device. Without further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus comprising that element.

The serial numbers of the above-mentioned embodiments of the present disclosure are for description only, and do not represent the advantages and disadvantages of the embodiments.

The methods disclosed in the several method embodiments provided in the present disclosure can be combined arbitrarily to obtain new method embodiments if there is no conflict.

The features disclosed in several product embodiments provided in the present disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

The features disclosed in several method or device embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

The above is only a specific implementation of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope of the present disclosure. should fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the protection scope of the claims.

Claims (16)

1. A data conversion circuit is characterized by comprising a conversion module, an adjustment module and a transmission module, wherein one end of the adjustment module is used for receiving a compensation signal, and the other end of the adjustment module is respectively connected with the output end of the conversion module and the input end of the transmission module, wherein:

the conversion module is used for receiving an initial data signal and performing parallel-to-serial conversion on the initial data signal to obtain an intermediate data signal;

the adjusting module is used for performing compensation processing on the intermediate data signal according to a compensation signal so as to reduce the signal swing of the intermediate data signal;

and the transmission module is used for carrying out drive enhancement processing on the intermediate data signal after compensation processing to obtain a target data signal.

2. The data conversion circuit of claim 1, wherein the adjustment module comprises a transmission gate module, one end of the transmission gate module is configured to receive the compensation signal, the other end of the transmission gate module is connected to the output end of the conversion module and the input end of the transmission module, respectively, and a control end of the transmission gate module is configured to receive an enable control signal, wherein:

when the enable control signal is in an effective state, the transmission gate module is conducted so as to perform compensation processing on the intermediate data signal according to the compensation signal; or when the enable control signal is in an invalid state, the transmission gate module is turned off.

3. The data conversion circuit of claim 2, wherein the enable control signal comprises a first enable control signal and a second enable control signal, wherein:

the transmission gate module comprises an NMOS tube and a PMOS tube, wherein the first end of the NMOS tube and the first end of the PMOS tube are connected to serve as one end of the transmission gate module, and the second end of the NMOS tube and the second end of the PMOS tube are connected to serve as the other end of the transmission gate module;

the control end of the transmission gate module comprises a gate end of the NMOS tube and a gate end of the PMOS tube, the gate end of the NMOS tube is connected with the first enabling control signal, the gate end of the PMOS tube is connected with the second enabling control signal, and the first enabling control signal and the second enabling control signal are opposite-phase signals.

4. The data conversion circuit of claim 3, wherein the adjustment module further comprises a first not gate, an input terminal of the first not gate is connected to the gate terminal of the NMOS transistor, an output terminal of the first not gate is connected to the gate terminal of the PMOS transistor, wherein:

the first not gate is used for receiving the first enabling control signal and carrying out reverse phase processing on the first enabling control signal to obtain the second enabling control signal.

5. The data conversion circuit of claim 1, wherein the adjustment module comprises a resistor module, one end of the resistor module is configured to receive the compensation signal, and the other end of the resistor module is connected to the output end of the conversion module and the input end of the transmission module, respectively, wherein:

and the resistance module is used for performing compensation processing on the intermediate data signal according to the compensation signal so as to reduce the signal swing of the intermediate data signal.

6. The data conversion circuit of claim 2, wherein the transmission module comprises a first transmission submodule and a second transmission submodule, an input of the first transmission submodule being connected to an output of the conversion module, an output of the first transmission submodule being connected to an input of the second transmission submodule, wherein:

the first transmission submodule is used for carrying out phase reversal processing on the intermediate data signal after compensation processing to obtain an initial target data signal;

and the second transmission submodule is used for carrying out phase reversal processing on the initial target data signal to obtain the target data signal.

7. The data conversion circuit of claim 6, wherein one end of the scaling module is connected to the output of the first transmission submodule and the other end of the scaling module is connected to the input of the first transmission submodule, wherein:

the first transmission sub-module is further configured to determine the initial target data signal as the compensation signal.

8. The data conversion circuit of claim 6, wherein the first transmission submodule comprises a second not gate and a first nand gate, the second transmission submodule comprises a third not gate, a first input of the first nand gate is used for receiving a transmission control signal, a second input of the first nand gate is connected with an output of the second not gate and an input of the third not gate, and an output of the first nand gate is connected with an input of the second not gate; the input end of the second not gate is used as the input end of the first transmission submodule, the output end of the second not gate is used as the output end of the first transmission submodule, the input end of the third not gate is used as the input end of the second transmission submodule, and the output end of the third not gate is used as the output end of the second transmission submodule.

9. The data conversion circuit of claim 1, wherein the conversion module comprises a first conversion sub-module, a second conversion sub-module, a third conversion sub-module, and a fourth conversion sub-module, and the initial data signal comprises first initial data, second initial data, third initial data, and fourth initial data, wherein:

the first conversion sub-module is configured to receive the first initial data and a first clock signal, and perform sampling processing on the first initial data according to the first clock signal to obtain first intermediate data;

the second conversion submodule is configured to receive the second initial data and a second clock signal, and perform sampling processing on the second initial data according to the second clock signal to obtain second intermediate data;

the third conversion sub-module is configured to receive the third initial data and a third clock signal, and perform sampling processing on the third initial data according to the third clock signal to obtain third intermediate data;

the fourth conversion sub-module is configured to receive the fourth initial data and a fourth clock signal, and perform sampling processing on the fourth initial data according to the fourth clock signal to obtain fourth intermediate data;

wherein phases of the first, second, third, and fourth clock signals are 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively, and the first, second, third, and fourth intermediate data constitute the intermediate data signal.

10. The data conversion circuit of claim 1, wherein the conversion module comprises a first conversion module and a second conversion module, the initial data signal comprises a first initial data signal and a second initial data signal, and the first initial data signal and the second initial data signal are a pair of differential signals, the intermediate data signal comprises a first intermediate data signal and a second intermediate data signal, wherein:

the first conversion module is configured to receive the first initial data signal, and perform parallel-to-serial conversion on the first initial data signal to obtain the first intermediate data signal;

the second conversion module is configured to receive the second initial data signal, and perform parallel-to-serial conversion on the second initial data signal to obtain the second intermediate data signal.

11. The data conversion circuit of claim 10, wherein the compensation signal comprises the first intermediate data signal and the second intermediate data signal, wherein:

the adjusting module is configured to perform compensation processing on the second intermediate data signal according to the first intermediate data signal to reduce a signal swing of the second intermediate data signal; and performing compensation processing on the first intermediate data signal according to the second intermediate data signal to reduce the signal swing of the first intermediate data signal.

12. The data conversion circuit of claim 11, wherein the target data signal comprises a first target data signal and a second target data signal, and the transmission module comprises a first transmission module and a second transmission module, wherein:

the first transmission module is configured to perform drive enhancement processing on the compensated first intermediate data signal to obtain the first target data signal;

and the second transmission module is used for performing drive enhancement processing on the compensated second intermediate data signal to obtain the second target data signal.

13. The data conversion circuit according to claim 12, wherein one end of the adjusting module is connected to the output end of the first converting module and the input end of the first transmitting module, respectively, and the other end of the adjusting module is connected to the output end of the second converting module and the input end of the second transmitting module, respectively.

14. The data conversion circuit according to any one of claims 1 to 13, wherein the initial data signal is a parallel data signal, and the intermediate data signal and the target data signal are serial data signals.

15. A method of data conversion, the method comprising:

receiving an initial data signal through a conversion module, and performing parallel-to-serial conversion on the initial data signal to obtain an intermediate data signal;

receiving a compensation signal through an adjusting module, and performing compensation processing on the intermediate data signal according to the compensation signal so as to reduce the signal swing amplitude of the intermediate data signal;

and receiving the intermediate data signal after compensation processing through a transmission module, and performing drive enhancement processing on the intermediate data signal after compensation processing to obtain a target data signal.

16. A memory comprising a data conversion circuit as claimed in any one of claims 1 to 14.

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