CN115658586A - Resource management chip, method, electronic device and readable storage medium - Google Patents

Abstract

An embodiment of the present invention provides a resource management chip, including: a device controller, a hub, a plurality of bus devices, a plurality of first buffers, and an access controller; the hub comprises a plurality of ports and a plurality of first endpoints; the device controller is used for receiving the resource acquisition instruction, allocating bus equipment for receiving data, and configuring a corresponding port and a first endpoint for the bus equipment; the bus device includes a plurality of second endpoints; the bus equipment is used for sending the received data to the corresponding first buffer through the second endpoint; the first buffer is used for storing data and transmitting the data to the hub under the control of the access controller; the hub is used for receiving data through the first endpoint and outputting the data to the outside of the chip under the control of the access controller; and the access controller is used for receiving the control instruction sent by the device controller and controlling data transmission between the first buffer and the hub and between the hub and the outside of the chip according to the control instruction.

Description

Resource management chip, method, electronic device and readable storage medium

technical field

The invention belongs to the technical field of computers, and in particular relates to a resource management chip, a method, electronic equipment and a readable storage medium.

Background technique

Since its launch, the Universal Serial Bus (USB) has been widely used in the fields of computers, complex terminals, and network infrastructure, and has become one of the standard expansion interfaces and necessary interfaces in this century. The latest USB protocol has been developed to the USB 4.0 version. At present, the data interaction between smart devices such as computers and the outside world is mainly through the USB interface and the network.

In the prior art, for large-scale network devices such as servers or switches, on the device side on the USB bus, the USB devices include single-function and multi-function USB devices. However, whether it is a USB device with a single function or a multi-function, the functions and related configurations of the device have been solidified at the time of delivery. Therefore, there is a problem that the hardware of the USB device has a single function and resources cannot be allocated.

Contents of the invention

The present invention provides a resource management method, device, electronic equipment and readable storage medium in order to solve the problem of single function and unallocated resources on the hardware of the USB equipment.

In order to solve the problems of the technologies described above, the present invention is achieved in that:

In a first aspect, the present invention provides a resource management chip, the chip comprising: a device controller, a hub, multiple bus devices, multiple first buffers, and an access controller;

the hub includes a plurality of ports and a plurality of first endpoints;

The device controller is configured to receive a resource acquisition instruction, allocate a bus device for receiving data according to the resource acquisition instruction, and configure a corresponding port and a first endpoint for the bus device; wherein, the bus device accessing the hub through the port;

The bus device includes a plurality of second endpoints; the bus device is used to send the received data to the corresponding first buffer through the second endpoints;

the first buffer is used to store the data, and send the data to the hub under the control of the access controller;

The hub is used to receive the data through the first endpoint, and output the data to the outside of the chip under the control of the access controller;

The access controller is configured to receive a control instruction sent by the device controller, and control data transfer between the first buffer and the hub, and between the hub and the outside of the chip according to the control instruction. transmission.

Optionally, the device controller includes a first register, a second register, and a third register;

The first register is used to query the current state of each of the bus devices and the hub, and set the bus device for receiving data, the port corresponding to the bus device, and the first endpoint according to the resource acquisition instruction ;

The second register is used to send a first control instruction to the access controller, so that the access controller opens a specified data transmission channel according to the first control instruction;

The third register is used to respectively set corresponding first buffers for each bus device, and query the current state of each first buffer.

Optionally, the bus device includes a first interface; wherein, the first interface includes a second control endpoint, and the second endpoint is set in the first interface;

The second control endpoint is used to control the second endpoint to receive data under the control of the first register, and send the data to the corresponding first buffer;

The first register is also used to set the data transmission type of the first interface according to the resource acquisition instruction, so that the first interface receives data of the data transmission type through the second endpoint; wherein, the The data transmission type is any one of video control type, video transmission type, serial port transmission type, network transmission type and human-computer interaction type.

Optionally, the hub further includes a first control endpoint and a second buffer;

The first control endpoint is used to control the first endpoint to receive the data sent by the first buffer under the control of the first register, and send the data to the storing in the second buffer;

The second buffer is used to receive and store data sent by each of the first endpoints, and send the data to the outside of the chip according to a second control instruction sent by the access controller.

Optionally, the second buffer includes a frame linked list and a data linked list;

The data linked list is used to cache the data sent by the bus device to the hub through the first buffer;

The frame link list is used to determine the data to be transmitted by the hub, and send the data to be transmitted to the outside of the chip according to the second control instruction.

Optionally, the frame linked list is an array of pointers, and any pointer of the frame linked list points to a data in the data linked list;

The frame linked list is also used to set the ratio of various types of data packets to be transmitted in the current frame according to the second control instruction, and obtain from the data linked list according to the next pointer after sending the data of the current frame data to be transmitted in the next frame, and update the pointer to the device controller for storage.

Optionally, the access controller includes multiple transmission channels, a channel selection module and a bus arbiter;

Each of the plurality of transmission channels has a channel number and a corresponding channel priority;

The channel selection module is used to open the transmission channel specified by the first control command according to the first control command sent by the device controller; wherein, the first control command includes the channel number of the transmission channel to be opened;

The bus arbiter is used to sort the transmission channels according to the channel numbers when the channel priorities of the multiple transmission channels are the same, and control the transmission channels to perform data transmission according to the sort order.

Optionally, the first buffer includes a routing logic module, a shared transmission buffer and a dedicated transmission buffer;

The routing logic module is used to analyze the data packet type of the data sent by the bus device, and filter the data packets that do not meet the preset requirements, so as to determine that the data sent by the bus device is the first data that meets the first delay requirement or the second data meeting the second delay requirement;

The shared transmission buffer is used to receive the first data routed by the routing logic module, and send the first data to the hub under the control of the access controller;

The dedicated transmission buffer is used to receive the second data routed by the routing logic module, and send the second data to the hub under the control of the access controller.

In a second aspect, the present invention provides a resource management method, which is applied to the resource management chip as described above, and the method includes:

Sending a resource acquisition instruction to a device controller, controlling the device controller to allocate a bus device for receiving data according to the resource acquisition instruction, and configuring a corresponding hub port and a first endpoint for the bus device;

controlling the bus device to receive the data through the device controller, and sending the data to the corresponding first buffer through the second endpoint;

controlling the first buffer to receive and store data sent by the bus device through the device controller;

The device controller sends a control instruction to the access controller, controls the access controller to control the first buffer to send the data to the hub according to the control instruction, and controls the hub to pass through the first Endpoints receive the data and output the data outside the chip.

Optionally, the resource acquisition instruction is generated according to the remote access instruction sent by the remote client to the external device of the chip; when the remote access instruction indicates that the remote client sends data to the external device, Before sending the resource acquisition instruction to the device controller, the method further includes:

receiving the remote data packet sent by the remote client through a resource management program running on the chip;

sending the remote data packet to a data transmission program running on the chip for parsing and processing through the resource management program, so as to obtain a first data packet;

The sending a resource acquisition instruction to the device controller, controlling the device controller to allocate a bus device for receiving data according to the resource acquisition instruction, and configuring a corresponding hub port and a first endpoint for the bus device, include:

The resource management program sends a resource acquisition instruction to the device controller through a chip driver running on the chip, controls the device controller to allocate a bus device for receiving data according to the resource acquisition instruction, and, for The bus device is configured with a corresponding hub port and a first endpoint;

Sending a control instruction to the access controller through the device controller, controlling the access controller to control the first buffer to send the data to the hub according to the control instruction, and controlling the hub receiving the data through the first endpoint and outputting the data to the outside of the chip, including:

The device controller sends a control instruction to the access controller, controls the access controller to control the first buffer to send the data to the hub according to the control instruction, and controls the hub to pass through the first The endpoint receives the data and transmits the data to the external device, so as to realize the remote access of the remote client to the external device.

Optionally, in the case where the remote access instruction indicates that the external device sends data to the remote client, the sending a resource acquisition instruction to the device controller controls the device controller to obtain data according to the resource acquisition instruction Allocating a bus device for receiving data, and configuring a corresponding hub port and a first endpoint for the bus device, including:

The resource management program sends a resource acquisition instruction to the device controller through the chip driver, controls the device controller to allocate a bus device for receiving data according to the resource acquisition instruction, and configures a corresponding bus device for the bus device The hub port and first endpoint of the

The controlling the bus device to receive the data through the device controller, and sending the data to the corresponding first buffer through the second endpoint includes:

Controlling the bus device by the device controller to receive the local data packet sent by the central processor of the external device, and sending the local data packet to the corresponding first buffer through the second endpoint for storage;

Sending a control instruction to the access controller through the device controller, controlling the access controller to control the first buffer to send the data to the hub according to the control instruction, and controlling the hub receiving the data through the first endpoint and outputting the data to the outside of the chip, including:

The device controller sends a control instruction to the access controller, controls the access controller to control the first buffer to send the data to the hub according to the control instruction, and controls the hub to pass through the first an endpoint receives said data and transmits said data to said data transfer program;

Sending a control instruction to the access controller through the device controller, controlling the access controller to control the first buffer to send the data to the hub according to the control instruction, and controlling the hub to pass through After the first endpoint receives the data and transmits the data to the data transmission program, the method further includes:

Analyzing and processing the local data packet through the data transmission program to obtain a second data packet, and sending the second data packet to the resource management program;

The second data packet is sent to the remote client through the resource management program, so as to realize the remote access of the remote client to the external device.

In a third aspect, the present invention provides an electronic device, including any one of the above resource management chips.

In a fourth aspect, the present invention provides a readable storage medium. When the instructions in the storage medium are executed by the chip of the electronic device, the electronic device can execute the resource management method described above.

The resource management chip provided by the embodiment of the present invention can dynamically allocate the bus device for receiving data through the device controller in the chip, and configure the corresponding hub port and the first endpoint for the bus device, so that the multiple buses of the chip The multiple ports and multiple first endpoints of devices and hubs can be dynamically configured on the hardware, and can be flexibly configured through the device controller according to requirements to achieve a variety of different functions, and to a certain extent solve the resource curing of USB physical devices. The hardware has a single function and cannot allocate resources. In addition, setting the first buffer corresponding to each of the multiple bus devices in the chip can add a data buffer area for the bus device, thereby increasing the data storage capacity of the chip. In addition, the device controller can control the first buffer to send the stored data to the hub through the access controller, and control the hub to output the stored data to the outside of the chip. In this way, the access controller controls the data transmission between the first buffer and the hub, and between the hub and the outside of the chip, which can better coordinate multiple bus devices in the chip, multiple ports of the hub, and multiple first buffers. The endpoint also provides a hardware foundation for improving the overall data transmission efficiency of the chip.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a structural diagram of a resource management chip provided by an embodiment of the present invention;

Fig. 2 is the topological diagram of USB bus in the prior art;

FIG. 3 is a schematic diagram of the internal logic of a USB device in the prior art;

FIG. 4 is a structural diagram of another resource management chip provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of a time slice of the USB protocol in the prior art;

FIG. 6 is a schematic diagram of a DMA control logic according to an embodiment of the present invention;

FIG. 7 is a structural diagram of another resource management chip provided by an embodiment of the present invention;

FIG. 8 is a flowchart of steps of a resource management method provided by an embodiment of the present invention;

FIG. 9 is a schematic diagram of remote access to a server or switch provided by an embodiment of the present invention;

Fig. 10 is a structural diagram of an electronic device provided by an embodiment of the present invention.

Reference signs:

Device controller 10; hub 20; bus device 30; first buffer 40; access controller 50; port 201; first endpoint 202; second endpoint 301; first register 101; second register 102; third register 103.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

1 is a structural diagram of a resource management chip provided by an embodiment of the present invention, the chip includes: a device controller 10, a hub 20, a plurality of bus devices 30, a plurality of first buffers 40, and an access controller 50; The hub 20 includes a plurality of ports 201 and a plurality of first endpoints 202; the device controller 10 is configured to receive a resource acquisition instruction, and allocate a bus device 30 for receiving data according to the resource acquisition instruction, and, Configuring corresponding ports 201 and first endpoints 202 for the bus device 30; wherein, the bus device 30 accesses the hub 20 through the port 201; the bus device 30 includes a plurality of second endpoints 301; The bus device 30 is used to send the received data to the corresponding first buffer 40 through the second endpoint 301; the first buffer 40 is used to store the data, and, in the access control The data is sent to the hub 20 under the control of the access controller 50; the hub 20 is used to receive the data through the first endpoint 202, and output the data under the control of the access controller 50 to the outside of the chip; the access controller 50 is used to receive the control instruction sent by the device controller 10, and control the connection between the first buffer 40 and the hub 20 according to the control instruction, and the Data transmission is performed between the hub 20 and the outside of the chip.

In the embodiment of the present invention, the device controller 10 is connected to the hub 20 , multiple bus devices 30 , multiple first buffers 40 and the access controller 50 through circuits inside the chip. The device controller 10 can perform common logic settings on the hub 20 , multiple bus devices 30 , multiple first buffers 40 and the access controller 50 , and perform status inquiries on the hub 20 and multiple bus devices 30 . The device controller 10 can issue control instructions to the access controller 50, and control the access controller 50 to control the hub 20, multiple bus devices 30, and multiple first buffers 40 to perform data interaction between the internal chip and external devices connected to the chip.

In the embodiment of the present invention, the hub 20 includes multiple ports 201 and multiple first endpoints 202 . The device controller 10 is used to receive a resource acquisition instruction sent by software running on the chip or a software running on the central processing unit (Central Processing Unit, CPU) of the computer device attached to the chip, and according to the resource acquisition instruction A bus device 30 for receiving data is allocated, and a corresponding port 201 and a first endpoint 202 are configured for the bus device 30 . Wherein, multiple bus devices 30 are respectively connected to the hub 20 through multiple ports 201 of the hub 20 . The device controller 10 can configure the port 201 and the first endpoint 202 of the hub 20 for the bus device 30 to form a simulated "insert" action, so that the bus device 30 and the hub 20 establish an actual communication connection, and the bus device 30 can be accessed through the port 201 To the hub 20 , the first endpoint 202 of the hub 20 can receive the data sent by the bus device 30 .

In the embodiment of the present invention, the bus device 30 includes a plurality of second endpoints 301, the second endpoint 301 is the smallest addressable unit in the bus device 30, corresponding to a data buffer on the hardware of the bus device 30, and the second endpoint 301 uses to receive and send data. The second endpoint 301 may be a single-byte or 4-byte 32-bit buffer, which is only an example here, and is not limited by this embodiment of the present invention. The bus device 30 is used to receive data sent from outside the chip through the second terminal 301 , and send the received data to the corresponding first buffer 40 through the second terminal 301 . When there is data in the plurality of second endpoints 301 in the bus device 30, the data may be sent to the first buffer 40 corresponding to the bus device 30 in real time for storage. The device controller 10 configures corresponding first buffers 40 for multiple bus devices 30 during chip initialization, that is, by establishing address mapping between the first buffers 40 and the corresponding bus devices 30, so that the first buffers 40 Bind with the corresponding bus device 30 so as to receive the data sent by the bus device 30 through the second endpoint 301 .

In the embodiment of the present invention, the plurality of first buffers 40 is a random access memory (random access memory, RAM) divided into multiple regions in hardware, one region is used as a first buffer 40, and the first buffer 40 is larger than The second endpoint 301 has more storage space and can store more data than the second endpoint 301 . The first buffer 40 is used for storing data sent by the corresponding bus device 30 through the second endpoint 301 . When the first buffer 40 receives a data transmission instruction from the access controller 50, it can route corresponding data in the stored data to the first endpoint 20 corresponding to the bus device 30 in the hub 20 according to the data transmission instruction.

In the embodiment of the present invention, the hub 20 includes a plurality of ports 201, which can support the access of multiple bus devices 30, and the hub 20 can manage the connected multiple bus devices 30, and monitor hot plug events of the bus devices 30. The hub 20 is used for receiving the data sent by the bus device 30 through the first buffer through the first endpoint 202 . Wherein, the first endpoint 202 is the smallest addressable unit in the hub 20, corresponding to a data buffer on the hub 20, and the first endpoint 202 is used to receive and send data. The first endpoint 202 may be a single-byte or 4-byte 32-bit buffer, which is only used for illustration and not limited by this embodiment of the present invention. When there is data in the multiple first endpoints 202 in the hub 20, the data may be sent to the data cache area of the hub 20 in real time for storage. When the hub 20 receives a data transmission instruction from the access controller 50, it can output the data stored in the data cache area to the outside of the chip according to the data transmission instruction.

In the embodiment of the present invention, after the access controller 50 receives the control instruction sent by the device controller 10, it controls the first buffer 40 to send the stored data to the hub 20 according to the data transmission requirement represented by the control instruction, and the hub 20 Output the stored data to the outside of the chip.

For example, the resource management chip in the embodiment of the present invention can be a Field Programmable Gate Array chip (Field Programmable Gate Array, FPGA), and the USB function logic (USB IP) implemented inside the FPGA chip can include: a USB device controller, a USB hub (USB hub), a plurality of USB bus devices, a plurality of first buffers 40 and an access controller 50 . Wherein, the first buffer 40 may be a first-in-first-out memory (First Input First Output, FIFO), and the access controller 50 may be a direct access controller (Direct Memory Access, DMA). Wherein, the USB hub can include six downward ports 201 and 15 first endpoints 202, and can support up to six USB bus devices connected to the USB hub through the ports for management. The USB device may include 15 second endpoints 301 . Wherein, the first endpoint 202 and the second endpoint 301 of the embodiment of the present invention may be programmable endpoints, and the programmable endpoints support bulk transfer (Bulk transfer), control transfer (Control transfer), isochronous transfer (Isochronous transfer) and interrupt transfer ( Interrupt transfer) all four types of data transmission, and also supports dynamic adjustment of parameters, such as the maximum transmission packet size of data transmission, polling interval and other parameters.

It should be noted that, as a high-speed transmission bus, USB needs to carry data packet transmission of various types of services. In order to make full use of its bandwidth, in the USB protocol, the Data packets are divided into 4 transfer types: control transfer, isochronous transfer, interrupt transfer, and bulk transfer. Among them, the control transmission is used to transmit bursty and non-periodic data, the transmission data volume is small, and the bandwidth and delay requirements are not high, but the data must be correct, so the integrity check is required; the synchronous transmission is used for transmission, etc. Real-time data, with a large amount of data, has high requirements on bandwidth and delay, but does not require the data to be correct, such as a camera; interrupt transmission is used to transmit real-time data with a small amount of data, has high requirements on delay, and requires the data to be correct, such as Keyboard, mouse; batch transfer is used to transfer large amount of storage data, the delay requirement is not high, but the data must be correct, such as U disk.

The resource management chip provided by the embodiment of the present invention can dynamically allocate the bus device 30 for receiving data through the device controller 10 in the chip, and configure the corresponding port 201 and the first endpoint 202 for the bus device 30, so that the chip The multiple bus devices 30, the multiple ports 201 of the hub, and the multiple first endpoints 202 are dynamically configurable on the hardware, and can be flexibly configured through the device controller according to requirements, so as to realize various functions and solve the problem to a certain extent. The resources of the USB physical device are solidified, the hardware has a single function, and the resources cannot be allocated. In addition, setting the first buffer 40 corresponding to each of the multiple bus devices 30 in the chip can add a data buffer area for the bus device 30, thereby increasing the data storage capacity of the chip. In addition, the device controller 10 can control the first buffer 40 to send the stored data to the hub 20 by controlling the access controller 50 , and control the hub 20 to output the stored data to the outside of the chip. In this way, the access controller controls the data transmission between the first buffer 40 and the hub 20, and between the hub 20 and the outside of the chip, which can better coordinate multiple bus devices 30 and multiple ports 201 of the hub in the chip. and multiple first endpoints 202 also provide a hardware basis for improving the overall data transmission efficiency of the chip.

It should be noted that, in the prior art, the required components included in the USB bus topology are: a USB controller and a root hub (root hub). Wherein, the root hub is generally integrated inside the USB controller, and the optional components included in the root hub include: non-root hubs (hubs) of up to five levels and various USB devices. The USB controller and the root hub are hardware implementations on the host side, and are used to initiate a USB request block (USB Request Block, URB) request and detect a hot plug event of a USB device. The current USB controller standards include: OHCI interface standard (Open Host Controller Interface, OHCI), EHCI interface standard (Enhanced Host Controller Interface, EHCI) and XHCI interface standard (eXtensible Host Controller Interface, XHCI), respectively supporting USB1.1, USB2.0, and USB3.0 protocol. As the device side implementation on the USB bus, one functional logic of the USB device is called a function. A single-function USB device contains only one function, such as U disk, mouse, etc. There are two ways to realize the multifunctional USB device hardware design. One is called a compound device, which is composed of a hub and multiple functions bound to it. The other is called a composite device, which is directly composed of multiple independent functions internally, and is organized through an Interface Association Descriptor (IAD). Existing USB products, whether it is a single-function USB device, a compound device, or a composite device, have their functions fixed at the factory. For example, the U disk only supports the storage function, and the USB serial port only supports the serial communication function.

Figure 2 is a topology diagram of the USB bus in the prior art, as shown in Figure 2, the first layer is the host and the root hub, the root hub is generally integrated in the USB controller, the root hub can include up to 5 levels of non-root hubs and For various USB devices, a function logic of a USB device is called a function. In Figure 2, the second to sixth layers include five levels of non-root hubs: hub 2 to hub 7, the third to sixth layers also include multiple functions of USB devices, the sixth layer hub 7 and the seventh layer Functions can be composed into a composite device.

It should be noted that the resource management chip provided by the embodiment of the present invention can implement a composite device with dynamically configurable resources on the device side through the hub 20 and multiple bus devices 30 . In the USB protocol, the internal resources of the device are further subdivided into three levels, including configuration (Configuration), interface (Interface) and endpoint (Endpoint). An Interface represents a basic functional logic of a USB device. In the USB protocol, it is also called a function. When a USB device has multiple functions, it will contain multiple Interfaces. A combination of multiple Interfaces is called a Configuration, and different Configurations make the device display different combinations of functions. Endpoint is the smallest addressable unit in a USB device, corresponding to a data buffer on the hardware, used to store and send USB data, and an Interface can contain multiple Endpoints. Figure 3 is a schematic diagram of the internal logic of the USB device in the prior art. As shown in Figure 3, the device includes two function combinations of configuration 0 and configuration 1, configuration 0 includes two functions of interface 0 and interface 1, and configuration 1 includes interface 0, Interface 1 and interface 2 have three functions, and each interface includes 1 or 2 endpoints, which are used to store and send USB data.

4 is a structural diagram of another resource management chip provided by an embodiment of the present invention, the chip includes: a hub 20, a plurality of bus devices 30, a plurality of first buffers 40, an access controller 50, and a first register 101 , the second register 102 and the third register 103; the hub 20 includes a plurality of ports 201 and a plurality of first endpoints 202; the first register 101 is used to inquire about each of the bus devices 30 and the hub 20 The current state, and the bus device 30 for receiving data, the port 201 corresponding to the bus device 30 and the first endpoint 202 are set according to the resource acquisition instruction; the second register 102 is used to provide the access control The device 50 sends a first control instruction, so that the access controller 50 opens a specified data transmission channel according to the first control instruction; the third register 103 is used to set the corresponding first buffer for each bus device 30 40, and query the current status of each of the first buffers 40; wherein, the bus device 30 accesses the hub 20 through the port 201; the bus device 30 includes a plurality of second endpoints 301; the The bus device 30 is used to send the received data to the corresponding first buffer 40 through the second endpoint 301; the first buffer 40 is used to store the data, and, in the access controller 50 The data is sent to the hub 20 under the control; the hub 20 is used to receive the data through the first endpoint 202, and, under the control of the access controller 50, output the data to the outside the chip; the access controller 50 is configured to receive the first control instruction sent by the second register 102102, and control the connection between the first buffer 40 and the hub 20 according to the first control instruction, And data transmission is performed between the hub 20 and the outside of the chip.

It should be noted that, for the description of the hub 20, multiple bus devices 30, multiple first buffers 40, access controller 50, port 201, first endpoint 202, and second endpoint 301, reference may be made to the resource management chip above. Detailed description will not be repeated here.

In the embodiment of the present invention, the overall resources of the chip are configured and managed through the first register 101 , the second register 102 and the third register 103 . Among them, the first register 101 is used for general logic setting and status query, and can query the current status of each bus device 30 and hub 20 . After receiving the resource acquisition instruction sent by the software running on the chip or the software running on the CPU of the computer device attached to the chip, the bus device 30 for receiving data can be set according to the resource acquisition instruction, and for The bus device 30 configures the corresponding hub port 201 and the first end point 202 to form a simulated plug-in action, so that the bus device 30 establishes an actual communication connection with the hub 20, and the bus device 30 can access the hub 20 through the port 201, and the first terminal of the hub 20 An endpoint 202 can receive data sent by the bus device 30 .

In the embodiment of the present invention, the second register 102 is used to send the first control instruction to the access controller 50, so that the access controller 50 opens the specified data transmission channel according to the first control instruction, and transmits data according to the first control instruction. It is required to control the first buffer 40 to send the stored data to the hub 20, and the hub 20 to output the stored data to the outside of the chip. The third register 103 is used to configure the corresponding first buffers 40 for multiple bus devices 30 during chip initialization, that is, by establishing address mapping between the first buffers 40 and the corresponding bus devices 30, the first buffer The device 40 is bound to the corresponding bus device 30 so as to receive data sent by the bus device 30 through the second endpoint 301 . The third register 103 is also used to inquire about the current state of each first buffer 40, and supports the unique Internet exploration flow (Packet Internet Groper Flow, PING Flow) of the high-speed mode of the USB2. For the current idle request, before actually sending the data transmission request, determine whether the USB device is ready to receive data, which can provide hardware support for software optimization.

The resource management chip provided by the embodiment of the present invention can dynamically allocate the bus device 30 for receiving data through the first register 101 in the chip, and configure the corresponding port 201 and the first endpoint 202 for the bus device 30, so that the chip The multiple bus devices 30, the multiple ports 201 of the hub, and the multiple first endpoints 202 are dynamically configurable on the hardware, and can be flexibly configured through the device controller according to requirements, so as to realize various functions and solve the problem to a certain extent. The resources of the USB physical device are solidified, the hardware has a single function, and the resources cannot be allocated. In addition, setting the first buffer 40 corresponding to each of the multiple bus devices 30 in the chip can add a data buffer area for the bus device 30, thereby increasing the data storage capacity of the chip. In addition, the second register 102 can control the access controller 50 to control the first buffer 40 to send the stored data to the hub 20 , and control the hub 20 to output the stored data to the outside of the chip. In this way, the access controller controls the data transmission between the first buffer 40 and the hub 20, and between the hub 20 and the outside of the chip, which can better coordinate multiple bus devices 30 and multiple ports 201 of the hub in the chip. and a plurality of first endpoints 202 . The third register 103 can determine whether the USB device is ready to receive data by querying the current status of each first buffer 40 before actually sending the data transmission request, which can provide a hardware basis for improving the overall data transmission efficiency of the chip.

Optionally, the bus device 30 includes a first interface; wherein, the first interface includes a second control endpoint, and the second endpoint 301 is set in the first interface; the second control endpoint is used for Control the second endpoint 301 to receive data under the control of the first register 101, and send the data to the corresponding first buffer 40; the first register 101 is also used to acquire instructions according to the resource Set the data transmission type of the first interface so that the first interface receives the data of the data transmission type through the second endpoint 301; wherein, the data transmission type is video control type, video transmission type, serial port Any of transmission type, network transmission type, and human-computer interaction type.

In the embodiment of the present invention, an interface represents a basic functional logic of any bus device, and an interface may include multiple endpoints. The bus device 30 in the embodiment of the present invention includes an interface, that is, a first interface, which means that the bus device 30 has a functional logic. The bus device 30 in the embodiment of the present invention may have any function of video control, video transmission, serial port transmission, network transmission and human-computer interaction, which is not limited in the embodiment of the present invention. The first interface may include a second control endpoint and a plurality of second endpoints 301, the second control endpoint is used to control the plurality of second endpoints 301 to receive data, and send data to the first buffer 40 corresponding to the bus device 30 .

For example, the USB hub of the resource management chip in the embodiment of the present invention may include six downward ports 201 and 15 first endpoints 202, and may support up to six USB bus devices connected to the USB hub through the ports for management. Wherein, each USB bus device includes a first interface and a maximum of 15 second endpoints 301, the first interface may be a programmable interface, and each first interface may correspond to a function logic. In this way, the resource management chip of the embodiment of the present invention can have 6 programmable interfaces, which are respectively used for UVC video control, video transmission, CDC serial port transmission/ACM, CDC (ECM) network transmission and two groups of Human Interface Devices (Human Interface Devices). , HID). Compared with solid-state USB devices, the programmable interface can support dynamic adjustment of its own parameters, such as the flexible setting of the number of bound ports, whether to enable alternate settings, etc., and the interface can be dynamically combined through the USB device controller to form a functional combination. configuration, and can also be simulated by the USB device controller to trigger the action of plugging or unplugging a USB hub.

In the embodiment of the present invention, the first register 101 is also used to set the data transmission type of the first interface according to the resource acquisition instruction, that is, to set the function for the bus device 30, so that the bus device 30 can have video control, video transmission, serial port transmission, network Any function in transmission and human-computer interaction. Under the control of the first register 101, the first interface can receive data of the corresponding data transmission type through the second endpoint 301; wherein, the data transmission type is any of video control, video transmission, serial port transmission, network transmission and human-computer interaction A sort of.

The bus device 30 of the embodiment of the present invention includes a first interface; wherein, the first interface includes a second control endpoint, and the second endpoint is set 301 in the first interface; the second control endpoint is used for The first register 101 controls the second endpoint 301 to receive data, and sends the data to the corresponding first buffer 40; the first register 101 is also used to set according to the resource acquisition instruction The data transmission type of the first interface, so that the first interface receives the data of the data transmission type through the second endpoint 301; wherein, the data transmission type is video control type, video transmission type, serial port transmission Any of the types, network transmission types, and human-computer interaction types. In this way, the chip of the embodiment of the present invention can have bus devices 30 with multiple functions. Further, the first register 101 can be used to dynamically allocate multiple bus devices 30 according to actual needs, so as to solve the problem of bus device resource solidification and single function. , the problem that cannot be flexibly configured.

Optionally, the hub 20 further includes a first control endpoint and a second buffer; the first control endpoint is used to control the first endpoint 202 to receive the first buffer under the control of the first register 101. The data sent by the buffer 40, and send the data to the second buffer through the first endpoint 202 for storage; the second buffer is used to receive and store each data sent by the first endpoint 202 data, and, according to the second control instruction sent by the access controller 50, send the data to the outside of the chip.

In the embodiment of the present invention, the hub 20 may include a default control endpoint, that is, a first control endpoint and a second buffer. The second buffer is a cache area in hardware. The second buffer has more storage space than the first endpoint 202 and can store more data than the first endpoint 202 . The second buffer is used to receive and store the data sent by the first buffer 40 through each first endpoint 202 . After receiving the second control instruction sent by the access controller 50, the second buffer may send corresponding data to the outside of the chip according to the data transmission requirement represented by the second control instruction. Optionally, the hub 20 in this embodiment of the present invention may also include a status interrupt input endpoint, which is used to indicate that the endpoint is an input type, indicating that the direction of current data transmission is from the bus device to the host connected to the chip.

For example, a USB hub may include a first control endpoint, a status interrupt input endpoint, up to 15 first endpoints 202 and a second buffer. Wherein, the second buffer may be a FIFO memory. The USB hub can be connected to the USB host controller inside the CPU of the external computer device through the 4 external USB pins of the FPGA chip through the USB cable.

The hub 20 provided by the embodiment of the present invention can conveniently realize the data transmission between the first buffer 40 and the second buffer by controlling the first endpoint 202 through the first control endpoint, and setting the second buffer can be added to the hub 20 The data cache area, thereby increasing the data storage capacity of the chip. In addition, under the control of the access controller 50, the second buffer can conveniently realize the data transmission between the chip and the external device, and can provide a hardware basis for improving the overall data transmission efficiency of the chip.

Optionally, the second buffer includes a frame linked list and a data linked list; the data linked list is used to cache the data sent by the bus device 30 to the hub 20 through the first buffer 40; the frame linked list It is used for determining the data to be transmitted currently by the hub 20, and sending the data to be transmitted to the outside of the chip according to the second control instruction.

It should be noted that, in order to meet the transmission of multiple types of data on the same shared channel, the USB protocol divides data transmission into multiple time slices from the time dimension. Each time slice is called a frame or microframe. Up to 80% of the time in the frame is used to preferentially transmit data with high latency requirements, such as interrupt transmission and synchronous transmission type data, and transmit data with low latency requirements in the remaining time, such as control transmission and Bulk transfer type of data.

The second buffer in the embodiment of the present invention includes a two-level linked list, the first level is a data linked list, and the second level is a frame linked list. Wherein, the frame linked list is used to determine the data to be transmitted in the current time slice of the hub 20, and according to the second control instruction of the access controller 50, the interrupt transmission and synchronous transmission types of data are preferentially transmitted in each frame at most 80% of the time, In the remaining time, data of control transfer and bulk transfer type are transferred, and the data to be transferred is sent to the outside of the chip.

FIG. 5 is a schematic diagram of a time slice of the USB protocol in the prior art. As shown in FIG. 5 , the time slice size of a full-speed or low-speed frame is 1 millisecond, and each frame includes a full-speed isochronous data payload. The time slice size of the high-speed micro-frame is 125 microseconds. In the USB2.0 protocol, the scale of the high-speed micro-frame is 1/8 of the full-speed frame. Each frame includes high-speed isochronous data payloads, and each frame includes full-speed In the maximum 80% of the isochronous data payload, interrupt transfer and isochronous transfer type data are transmitted preferentially, and control transfer and bulk transfer type data are transmitted in the remaining time.

The second buffer of the embodiment of the present invention can meet the requirements of the bus protocol to the data transmission time slice through the frame linked list and the data linked list, which can make the chip of the embodiment of the present invention have better compatibility and practical value, and can also improve The chip's overall data transfer efficiency provides the hardware foundation.

Optionally, the frame linked list is an array of pointers, and any pointer of the frame linked list points to a piece of data in the data linked list; the frame linked list is also used to set the current frame to be stored according to the second control instruction The proportion of each type of data packets transmitted, and, after sending the data of the current frame, obtain the data to be transmitted of the next frame from the data link list according to the next pointer, and update the pointer to the device control stored in the device.

In the embodiment of the present invention, the frame linked list is an array of pointers, including multiple pointers. Each pointer in the frame linked list points to a plurality of data in the data linked list respectively. After receiving the second control instruction sent by the access controller 50, the frame linked list can set the proportion of various types of data packets to be transmitted in the current frame according to the second control instruction, and determine the priority transmission interruption within 80% of the current frame. Transfer and isochronous transfer types of data, and control transfer and bulk transfer type data for the remainder of the time. After the transmission of the current frame is started, the frame link list can prepare the data to be sent in the next frame, that is, select the specified data to be transmitted from the data link list through the pointer, and send the pointer corresponding to the selected data to the frame in the device controller The register corresponding to the linked list.

The frame linked list in the embodiment of the present invention can reasonably arrange the sequence and type of data transmission through each pointer, and conveniently realize the requirement of the bus protocol on the time slice of data transmission.

Optionally, the access controller 50 includes multiple transmission channels, a channel selection module, and a bus arbiter; each of the multiple transmission channels has a channel number and a corresponding channel priority; The first control instruction sent by the device controller opens the transmission channel specified by the first control instruction; wherein, the first control instruction includes the channel number of the transmission channel to be opened; the bus arbiter is used for multiple When the channel priorities of the transmission channels are the same, the transmission channels are sorted according to the channel numbers, and the transmission channels are controlled to perform data transmission according to the sort order.

In the embodiment of the present invention, the access controller 50 may include a plurality of storage device-type transmission channels, and the software running on the chip or the software running on the CPU of the computer device connected to the chip can be set when the chip is initialized. For the priority of each transmission channel, the access controller in the embodiment of the present invention can support up to four priority settings. After the channel selection module receives the first control instruction sent by the register related to the access controller in the device controller 10, at first the software running on the chip or the software running on the CPU of the computer device connected to the chip Carry out arbitration in the software stage, determine the priority of the transmission channel designated to be opened by the first control instruction, and open the designated transmission channel according to the channel priority. In the case of the same channel priority of multiple transmission channels in the arbitration of the software stage, the bus arbiter can sort the transmission channels of the same priority according to the channel number, and determine that the transmission channel with a lower number is better than the transmission channel with a higher number. It has a higher transmission priority, and controls each transmission channel for data transmission according to the sort order.

For example, the access controller 50 in the embodiment of the present invention can be a DMA controller, and the DMA controller can include 8 memory-device type DMA transmission channels, and the software running on the chip or running on the chip The software on the CPU of the connected computer device can control the channel selection module to open the specified transmission channel through the DMA related register provided by the USB device controller. The bus arbiter can preferentially transmit the data of the specified transmission channel according to the priority of the DMA transmission request.

It should be noted that, in order to meet the requirements of USB data bandwidth and service response speed, the chip in the embodiment of the present invention includes DMA control logic for transferring data between the hardware FIFO corresponding to the USB device and the internal memory. The DMA controller can be directly connected to the 32-bit Advanced High Performance Bus (AHB), and supports all 4G bus address access. It should be noted that the number of FIFOs used in real time in software services may be greater than the number of DMA transmission channels. Therefore, the software running on the chip or the software running on the CPU of the computer device connected to the chip can apply for Re-initiate DMA transfer request on failure.

In the embodiment of the present invention, the access controller 50 can conveniently control the data transmission in multiple transmission channels through the channel selection module and the bus arbiter, and reasonably arrange the data transmission sequence on the bus according to the number and priority of each transmission channel, It can provide hardware support for improving the overall transmission efficiency of the chip.

Fig. 6 is the schematic diagram of the DMA control logic of the embodiment of the present invention, as shown in Fig. 6, DMA controller comprises a plurality of transmission channels, channel selection module and bus arbiter, and a plurality of transmission channels of DMA controller can be connected with a plurality of FIFOs To establish a connection, the registers related to the DMA controller in the device controller can establish a connection with the channel selection module and the bus arbiter, the channel selection module can open the specified transmission channel according to the first control command sent by the device controller, and the bus arbiter is in the After receiving the control command of the hardware arbitration, the transmission channels of the same priority can be sorted according to the channel number, and it is determined that the transmission channel with a lower number has a higher transmission priority than the transmission channel with a higher number, and passes through according to the sorting order. The channel selection module controls each transmission channel to perform data transmission, so that the DMA controller can perform data transmission between the FIFO and the memory of the chip external device under the control of the device controller.

Optionally, the first buffer 40 includes a routing logic module, a shared transmission buffer and a dedicated transmission buffer; the routing logic module is used to analyze the packet type of the data sent by the bus device 30, and filter the data packets that do not meet the A predetermined data packet is preset to determine that the data sent by the bus device 30 is the first data meeting the first delay requirement or the second data meeting the second delay requirement; the shared transmission buffer is used to receive the The first data routed by the routing logic module, and, under the control of the access controller 50, the first data is sent to the hub 20; the dedicated transmission buffer is used to receive the routing logic module route the incoming second data, and, under the control of the access controller 50, send the second data to the hub 20.

The routing logic module in the embodiment of the present invention can analyze the data packet type of the data sent by the bus device 30, and can also filter illegal data packets by judging the data packet type. Among them, the data packet type includes four transmission types: control transmission, synchronous transmission, interrupt transmission, and batch transmission. Among them, the data packets of the control transmission and bulk transfer types have low requirements on time delay during transmission, and the data sent by the bus device 30 can be determined as the first data that has low requirements on time delay, that is, meets the first time delay requirement. Data, the first data is transmitted by the shared transmission buffer. Wherein, the data packets of the synchronous transmission and interrupt transmission types have high requirements on time delay during transmission, and the data sent by the bus device 30 to the time delay requirements can be high, that is, data that meets the second time delay requirement, can be determined as the second time delay requirement. data, and the second data is transmitted by a dedicated transmission buffer.

For example, the first buffer 40 may be a FIFO memory, and then the first buffer 40 may include a FIFO routing logic module, a shared transmission FIFO and a dedicated transmission FIFO. Optionally, the software running on the chip or the software running on the CPU of the computer device connected to the chip can set the type, size and FIFO interrupt of this part of the FIFO through the FIFO-related registers in the USB device manager. The trigger threshold and other parameters.

The first buffer 40 of the embodiment of the present invention can conveniently analyze the data packet type, filter the data packets that do not meet the preset regulations through the routing logic module, the shared transmission buffer and the dedicated transmission buffer, and reasonably Select the shared transmission buffer and the dedicated transmission buffer to transmit corresponding data respectively, so that the chip of the embodiment of the present invention can meet the requirements of the data transmission type in the bus protocol, can carry the data packet transmission of various business types, and fully utilize the bandwidth .

It should be noted that the device manager 10 of the embodiment of the present invention can support an automatic retry mechanism when the data packet transmission fails, and the USB device controller hardware supports checking the number of bytes driven by each frame of complete data on the bus. When the actual number of frame data bytes does not match it, the data corresponding to the current frame on the data link list will not be deleted from the linked list, and the data in the frame linked list will be cleared. At the same time, the driver of the software layer is notified through the status register, and the driver re-adds this frame of data to the scheduling queue, and at an appropriate point in time, recomposes a new frame of data, that is, updates the frame linked list. The device manager 10 in the embodiment of the present invention can also support a USB remote wake-up function, and the remote wake-up function can be used when binding the HID human-computer interaction interface. When the USB bus is idle and the USB host controller enters the suspend state, the remote keyboard or mouse can wake up the USB host controller through the remote wake-up function, so that the host controller returns from the suspend state to the standby state.

Fig. 7 is a structural diagram of another resource management chip according to an embodiment of the present invention. As shown in Fig. 7, the chip includes a USB device controller, a USB hub, a USB device, DMA controller scheduling, and a FIFO routing logic module of the first buffer , Shared transmission FIFO and dedicated transmission FIFO, frame linked list and data linked list of USB hub. Among them, the USB device controller includes DMA controller registers, control and status registers and FIFO control registers. The USB device includes a plurality of second ports 1 to X, and the USB hub includes a plurality of ports 0 to X and a plurality of first endpoints 1 to X. Wherein, the frame linked list and the data linked list are in the second buffer of the USB hub. The resource management chip in the embodiment of the present invention can be a PCB circuit board, and the device controller connects the DMA controller register with the DMA controller through the circuit on the chip, so that the control and status registers are connected with the USB device and the USB hub, so that The FIFO control register is connected with the first buffer and the second buffer in the USB hub. The USB hub can respectively establish a communication connection with each data buffer in the data link list through a plurality of second endpoints. The pointer of the frame linked list points to a piece of data in the data linked list.

It should be noted that, through the dynamically configurable USB interface and endpoints, the resource management chip of the present invention can obtain the effect that USB resources can be applied for and released dynamically, so as to solve the problem that USB physical device resources are fixed and cannot be flexibly configured according to product requirements. At the same time, the resource management chip of the present invention provides a chip-level USB resource set, provides hardware support for the cooperation between on-chip USB devices, and cooperates with software-driven algorithms based on FIFO hardware to improve the overall transmission efficiency of the USB bus and devices. On this basis, the USB resource pool based on the FPGA chip adopts a modular design and has good scalability. According to the specific project product requirements, the USB resources on the FPGA chip can be cut, and the total amount of USB resources and various USB resources can be flexibly set. Combination, so that USB resources are sufficient and not wasted.

Fig. 8 is a flow chart of the steps of a resource management method provided by an embodiment of the present invention. As shown in Fig. 8, a resource management method is applied to any of the chips described above, and the method includes:

Step 601: Send a resource acquisition instruction to the device controller, control the device controller to allocate a bus device for receiving data according to the resource acquisition instruction, and configure a corresponding hub port and a first endpoint for the bus device .

Step 602: Control the bus device to receive the data through the device controller, and send the data to the corresponding first buffer through the second endpoint.

Step 603: The device controller controls the first buffer to receive and store the data sent by the bus device.

Step 604: Send a control instruction to the access controller through the device controller, control the access controller to control the first buffer to send the data to the hub according to the control instruction, and control the hub receiving the data through the first endpoint and outputting the data to the outside of the chip.

In the embodiment of the present invention, the resource management program running on the chip can send a resource acquisition instruction to the device controller, and the device manager allocates a bus device for receiving data according to the data transmission requirements indicated by the resource acquisition instruction, and, for The bus device is configured with a corresponding hub port and a first endpoint. The bus device and the hub form a simulated "plug-in" action through the port to establish an actual communication connection, the bus device can access the hub through the port, and the first end point of the hub can receive the data sent by the bus device. For example, the resource management program may send a serial port transmission resource acquisition instruction to the device controller, control the device controller to allocate a bus device for receiving serial port logs, and configure a corresponding hub port and first endpoint for the bus device.

In the embodiment of the present invention, the resource management program running on the chip can control the bus device and the hub to transmit data between the remote client and the external device of the chip through the device manager, so as to realize the connection between the remote client and the external device of the chip. remote access. Wherein, the local CPU sends the URB data packet to the resource management chip of the embodiment of the present invention through the USB line and the USB protocol stack, and the resource management program can drive and control the bus device and the hub to receive the URB data packet through the device manager, and send the URB data packet For the resource management program, the resource management program is responsible for parsing the URB data packet and repackaging it into a network data packet, and transmitting it to the remote client through the network protocol stack and network path. After the resource management program receives the network data packet sent by the remote client, it is analyzed and repackaged by various drivers and protocol stacks running on the chip, and the raw data is given to the resource management chip of the embodiment of the present invention. Resource management The chips are then packaged into URB packets. The resource management program can drive and control the bus device and the hub through the device manager to send the URB data packet to the local CPU of the chip external device through the USB cable and the USB protocol stack.

In the embodiment of the present invention, by sending a resource acquisition instruction to the device controller, the device controller is controlled to allocate a bus device for receiving data according to the resource acquisition instruction, and configure the bus device with a corresponding hub port and first endpoint. Chip resources can be flexibly configured through the device controller according to requirements to realize various functions. Control the bus device to receive the data through the device controller, and send the data to the corresponding first buffer through the second endpoint; control the first buffer to receive and store the data through the device controller The data sent by the bus device; the device controller sends a control instruction to the access controller, and controls the access controller to control the first buffer to send the data to the hub according to the control instruction , and controlling the hub to receive the data through the first endpoint and output the data to the outside of the chip. In this way, multiple bus devices in the chip, multiple ports of the hub and multiple first endpoints can be better coordinated, and the overall data transmission efficiency of the chip can be improved.

Optionally, the resource acquisition instruction is generated according to the remote access instruction sent by the remote client to the external device of the chip; when the remote access instruction indicates that the remote client sends data to the external device, Before sending the resource acquisition instruction to the device controller, the method further includes:

Step 605: Receive the remote data packet sent by the remote client through the resource management program running on the chip.

Step 606: Send the remote data packet to a data transmission program running on the chip for parsing and processing through the resource management program, so as to obtain a first data packet.

Step 601 includes the following steps:

Step 6011, the resource management program sends a resource acquisition instruction to the device controller through the chip driver program running on the chip, and controls the device controller to allocate a bus device for receiving data according to the resource acquisition instruction, And, configuring a corresponding hub port and a first endpoint for the bus device.

Step 604 includes the following steps:

Step 6041: Send a control instruction to the access controller through the device controller, control the access controller to control the first buffer to send the data to the hub according to the control instruction, and control the hub receiving the data through the first endpoint and transmitting the data to the external device, so as to realize the remote access of the remote client to the external device.

In the embodiment of the present invention, the resource management program running on the chip can receive the remote access instruction sent by the remote client, and generate a resource acquisition instruction according to the remote access instruction. Wherein, the remote access instruction may include user security level verification, dynamic adjustment of device resources, and file encrypted transmission, which are only illustrated here, and are not limited in this embodiment of the present invention. Wherein, dynamically adjusting device resources includes inserting or removing a specified device, and adjusting parameters of the specified device. For example, the resource management program receives a client request sent by a remote personal computer (Personal Computer, PC) in the role of a server, and requests to access the serial port log of the server.

In the embodiment of the present invention, in the case where the remote access instruction indicates that the remote client sends data to the external device, the resource management program receives the remote data packet sent by the remote client, and the remote data packet is processed by the data transmission program running on the chip. Parse and repack to obtain the first packet. The resource management program can send a resource acquisition instruction to the device controller through the chip driver running on the chip, control the device controller to allocate a bus device for receiving data, and configure the corresponding hub port and first end for the bus device point. The bus device receives the first data packet sent by the resource management program under the control of the device controller, and sends the first data packet to the first buffer through the second endpoint for storage. Wherein, the chip driver includes a device manager driver.

In the embodiment of the present invention, the resource management program may drive and control the device manager through the device manager, and send the first data transmission instruction to the access controller. The access controller receives the first data transmission instruction, and controls the first buffer to send the first data packet to the hub according to the first data transmission instruction. The hub receives the first data packet sent by the first buffer through the first endpoint, and stores the first data packet into the second buffer. Under the control of the access controller, the hub sends the first data packet to the local central processing unit of the external device through the data linked list and the frame linked list in the second buffer, so as to realize the remote access of the remote client to the external device.

In the embodiment of the present invention, in the case that the remote access instruction indicates that the remote client sends data to the external device, the data sent by the remote client can be conveniently sent to the Chip peripherals. In addition, the access controller can improve the data transmission efficiency of the chip by controlling the first buffer and the hub, so that the remote client can obtain better access effect.

Optionally, when the remote access instruction indicates that the external device sends data to the remote client, step 601 may also include the following steps:

Step 6012, the resource management program sends a resource acquisition instruction to the device controller through the chip driver, controls the device controller to allocate a bus device for receiving data according to the resource acquisition instruction, and provides the bus The device configuration corresponds to the hub port and the first endpoint.

Step 602 may include the following steps:

Step 6021: Control the bus device through the device controller to receive the local data packet sent by the local CPU of the external device, and send the second end point of the local data packet to the corresponding first buffer for storage .

Step 604 may also include the following steps:

Step 6042: Send a control instruction to the access controller through the device controller, control the access controller to control the first buffer to send the data to the hub according to the control instruction, and control the hub The data is received through the first endpoint and transmitted to the data transmission program.

After step 6042, the method also includes:

Step 607: Analyze and process the local data packet through the data transmission program to obtain a second data packet, and send the second data packet to the resource management program.

Step 608: Send the second data packet to the remote client through the resource management program, so as to realize the remote access of the remote client to the external device.

In the embodiment of the present invention, in the case that the remote access command indicates that the external device sends data to the remote client, the resource management program can send a resource acquisition command to the device controller through the chip driver, and control the device controller to allocate the data for receiving data. A bus device, and a corresponding hub port and a first endpoint are configured for the bus device. Under the control of the device controller, the bus device receives the local data packet sent by the local CPU of the chip external device to the resource management chip, and sends the local data packet to the first buffer through the second endpoint for storage.

In the embodiment of the present invention, the resource management program may drive and control the device manager through the device manager, and send the second data transmission instruction to the access controller. The access controller receives the second data transmission instruction, and controls the first buffer to send the local data packet to the hub according to the second data transmission instruction. The hub receives the local data packet sent by the first buffer through the first endpoint, and stores the local data packet in the second buffer. Under the control of the access controller, the hub sends the local data packet to the data transmission program through the data linked list and the frame linked list in the second buffer. The data transmission program is responsible for parsing the local data packet and repackaging it into a network data packet, and transmits it to the remote client through the network protocol stack and network path under the control of the resource management program, so as to realize the connection between the remote client and the external device. remote access.

In the embodiment of the present invention, in the case that the remote access command indicates that the external device sends data to the remote client, through the allocated bus device, the port and the first endpoint of the hub, the data sent by the external device of the chip can be conveniently Data is sent to the remote client. In addition, the access controller can improve the data transmission efficiency of the chip by controlling the first buffer and the hub, so that the remote client can obtain better access effect.

Fig. 9 is a schematic diagram of remote access of a server or a switch according to an embodiment of the present invention. As shown in Fig. 9, the remote access function is divided into three parts as a whole, and the left part corresponds to the server or switch being accessed remotely, from top to bottom, respectively It is the USB customized user program in the user space, the USB device driver, the USB core layer and the USB host controller driver in the kernel space, and the CPU hardware entity of the board-level hardware, wherein the COU includes the USB host controller. From bottom to top, the middle part is the USB IP and network IP implemented inside the FPGA chip, the USB function driver, USB abstraction layer, USB control driver, network card, and USB resources in the user space in the Linux kernel running on the FPGA. hypervisor. On the right is the remote PC accessing the server or switch. The management and scheduling of the remote access function is in charge of the USB resource management program running on the FPGA. The main functions of the USB resource management program are described as follows: First, as a server, receive client requests from remote PCs. These requests include: User security level verification, dynamic adjustment of specified USB resources, file encrypted transmission, etc. Second, forward the interactive data between the local CPU and the remote PC, so as to realize the remote PC's access to the local server or switch. Among them, the local CPU sends URB data packets to it through the USB cable and USB protocol stack, and the USB resource management program is responsible for parsing the URB data packets and repackaging them into network data packets, which are transmitted to the remote client through the network protocol stack and network access end. The hardware support of the remote access function comes from the USB IP implemented inside the FPGA. The Linux kernel running on the FPGA includes various drivers corresponding to the internal USB IP of the FPGA, the USB IP resource management program exposed to the USB resource management program, and the transmission program for transparently transmitting interactive data between the remote PC and the local CPU.

It should be noted that, in the prior art, remote access to servers or switches, as well as USB resource pools shared between different virtual machines on the same physical device, all require multiple USB resources and need to support dynamic configurability of USB resources. application scenarios. In network infrastructure equipment such as servers and switches, it is a necessary function to support remote monitoring and debugging. The remote client can capture the serial port log output of the server site through the network, capture the real-time screen of the on-site device display, or operate the on-site device in real time through the local mouse and keyboard of the server, just like operating locally. The realization of remote access depends on various USB resources inside the server or switch device, and these USB resources should preferably support resource dynamic allocation. For example, when the server only wants to interact with remote devices through the serial port, it only needs to load the USB communication device ( Communications Device Class, CDC) resources, and for example, when the server does not need remote monitoring equipment, all USB resources can be unloaded to meet the possible USB function requirements of the equipment itself.

It should be noted that, in the prior art, in order to solve the problem of large investment in hardware equipment, a virtual machine rental service appears. Virtual machines with different performance configurations can be leased according to business needs. Behind the virtual machines are real hardware resources for support. The difference is that a traditional set of hardware resource configurations, such as CPU, memory, hard disk, peripherals, etc., is only allocated to one operating system for management and use, while a virtual machine is a set of hardware resource configurations shared by multiple operating systems. For example, if a piece of physical hardware contains 512G memory, it can support 16 virtual machines with 32G memory to run simultaneously. As a part of hardware resources, USB resources are diverse and dynamically configurable, and in this application scenario, they also become a necessary function item. It should be noted that the USB resource management program running on the FPGA and the associated management program and transmission program in the kernel space are unique to the remote access function of the server or switch. If the virtual machine shares the USB resource pool In the application scenario, this part of the functional logic can be in charge of the software running on the CPU.

In a third aspect, the present invention provides an electronic device 70, as shown in FIG. 10 , including the resource management chip 701 described above.

In a fourth aspect, the present invention provides a readable storage medium. When the instructions in the storage medium are executed by the chip of the electronic device, the electronic device can execute the resource management method described above.

As for the method embodiment, since it is basically similar to the chip embodiment, the description is relatively simple, and for related parts, refer to the part of the description of the chip embodiment.

The algorithms and displays presented herein are not inherently related to any particular computer, virtual system, or other device. The structure required to construct such a system is apparent from the above description. Furthermore, the present invention is not specific to any particular programming language. It should be understood that various programming languages can be used to implement the content of the present invention described herein, and the above description of specific languages is for disclosing the best mode of the present invention.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, in order to streamline the present disclosure and to facilitate an understanding of one or more of the various inventive aspects, various features of the invention are sometimes grouped together in a single embodiment, figure, or in its description. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this invention.

Those skilled in the art can understand that the modules in the device in the embodiment can be adaptively changed and arranged in one or more devices different from the embodiment. Modules or units or components in the embodiments may be combined into one module or unit or component, and furthermore may be divided into a plurality of sub-modules or sub-units or sub-assemblies. All features disclosed in this specification (including accompanying claims, abstract and drawings) and any method or method so disclosed may be used in any combination, except that at least some of such features and/or processes or units are mutually exclusive. All processes or units of equipment are combined. Each feature disclosed in this specification (including accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

The various component embodiments of the present invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art should understand that a microprocessor or a digital signal processor (DSP) can be used in practice to realize some or all functions of some or all components in the sorting device according to the present invention. The present invention can also be realized as a device or an apparatus program for performing a part or all of the methods described herein. Such a program for realizing the present invention may be stored on a computer-readable medium, or may be in the form of one or more signals. Such a signal may be downloaded from an Internet site, or provided on a carrier signal, or provided in any other form.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.

Those skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention. within the scope of protection.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

It should be noted that the various data-related processes in this embodiment of the application are all carried out under the premise of complying with the corresponding data protection laws and policies of the country where the device is located, and with the authorization granted by the corresponding device owner.

Claims (10)

1. A resource management chip, wherein the chip comprises: a device controller, a hub, a plurality of bus devices, a plurality of first buffers, and an access controller;

the hub comprises a plurality of ports and a plurality of first endpoints;

the device controller is used for receiving a resource acquisition instruction, allocating bus equipment for receiving data according to the resource acquisition instruction, and configuring a corresponding port and a first endpoint for the bus equipment; wherein the bus device accesses the hub through the port;

the bus device comprises a plurality of second endpoints; the bus equipment is used for sending the received data to the corresponding first buffer through the second endpoint;

the first buffer is used for storing the data and sending the data to the hub under the control of the access controller;

the hub is used for receiving the data through the first end point and outputting the data to the outside of the chip under the control of the access controller;

and the access controller is used for receiving a control instruction sent by the device controller, and controlling data transmission between the first buffer and the hub and between the hub and the outside of the chip according to the control instruction.

2. The chip of claim 1, wherein the device controller comprises a first register, a second register, and a third register;

the first register is used for inquiring the current states of each bus device and the hub, and setting the bus device for receiving data, a port corresponding to the bus device and a first endpoint according to the resource acquisition instruction;

the second register is used for sending a first control instruction to the access controller, so that the access controller opens a specified data transmission channel according to the first control instruction;

the third register is used for respectively setting corresponding first buffers for each bus device and inquiring the current state of each first buffer.

3. The chip of claim 2, wherein the bus device comprises a first interface; wherein the first interface comprises a second control endpoint disposed in the first interface;

the second control endpoint is used for controlling the second endpoint to receive data under the control of the first register and sending the data to a corresponding first buffer;

the first register is further configured to set a data transmission type of the first interface according to the resource obtaining instruction, so that the first interface receives data of the data transmission type through the second endpoint; the data transmission type is any one of a video control type, a video transmission type, a serial port transmission type, a network transmission type and a human-computer interaction type.

4. The chip of claim 2, wherein the hub further comprises a first control endpoint and a second buffer;

the first control endpoint is used for controlling the first endpoint to receive the data sent by the first buffer under the control of the first register and sending the data to the second buffer for storage through the first endpoint;

the second buffer is used for receiving and storing data sent by each first endpoint, and sending the data to the outside of the chip according to a second control instruction sent by the access controller.

5. The chip of claim 4, wherein the second buffer comprises a frame linked list and a data linked list;

the data link table is used for caching data sent to the hub by the bus equipment through the first buffer;

and the frame linked list is used for determining the current data to be transmitted by the hub and sending the data to be transmitted to the outside of the chip according to the second control instruction.

6. The chip of claim 1, wherein the access controller comprises a plurality of transmission channels, a channel selection module, and a bus arbiter;

the plurality of transmission channels each have a channel number and a corresponding channel priority;

the channel selection module is used for opening a transmission channel specified by a first control instruction according to the first control instruction sent by the equipment controller; wherein, the first control instruction comprises a channel number of a transmission channel to be opened;

the bus arbiter is used for sorting the transmission channels according to the channel numbers under the condition that the channel priorities of the transmission channels are the same, and controlling the transmission channels to transmit data according to the sorting sequence.

7. The chip of claim 1, wherein the first buffer comprises a routing logic module, a shared transmission buffer, and a dedicated transmission buffer;

the routing logic module is used for analyzing the data packet type of the data sent by the bus equipment and filtering the data packets which do not accord with preset regulations so as to determine that the data sent by the bus equipment is first data which accords with a first time delay requirement or second data which accords with a second time delay requirement;

the shared transmission buffer is used for receiving the first data routed by the routing logic module and sending the first data to the hub under the control of the access controller;

the dedicated transmission buffer is used for receiving the second data routed by the routing logic module and sending the second data to the hub under the control of the access controller.

8. A resource management method, applied to a chip according to any one of claims 1 to 7, the method comprising:

sending a resource acquisition instruction to a device controller, controlling the device controller to allocate bus equipment for receiving data according to the resource acquisition instruction, and configuring a port and a first endpoint of a corresponding hub for the bus equipment;

controlling the bus equipment to receive the data through the equipment controller, and sending the data to a corresponding first buffer through a second endpoint;

controlling the first buffer to receive and store the data sent by the bus equipment through the equipment controller;

and sending a control instruction to an access controller through the device controller, controlling the access controller to control the first buffer to send the data to the hub according to the control instruction, and controlling the hub to receive the data through a first endpoint and output the data to the outside of the chip.

9. An electronic device, characterized in that it comprises a resource management chip according to any one of claims 1 to 7.

10. A readable storage medium, wherein instructions in the storage medium, when executed by a chip of an electronic device, enable the electronic device to perform the resource management method of claim 8.

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