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CN115657513B - Signal processing device and method for digital pendulum inclinometer - Google Patents

Signal processing device and method for digital pendulum inclinometer Download PDF

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CN115657513B
CN115657513B CN202211137702.5A CN202211137702A CN115657513B CN 115657513 B CN115657513 B CN 115657513B CN 202211137702 A CN202211137702 A CN 202211137702A CN 115657513 B CN115657513 B CN 115657513B
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CN115657513A (en
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周云耀
闫柏霖
吕永清
齐军伟
张润民
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Seismological Bureau Of Hubei Province
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Seismological Bureau Of Hubei Province
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Abstract

The embodiment of the specification provides signal processing equipment and a signal processing method of a digital pendulum inclinometer, wherein the equipment comprises a sensor circuit, an ARM circuit and a logic gate circuit, wherein the sensor circuit is used for converting phase data into analog sine waves through a digital-to-analog converter, modulating the signals and sending the modulated signals into the ARM circuit, the ARM circuit is used for receiving the modulated signals, carrying out analog-to-digital conversion on the modulated signals and then carrying out noise reduction through a singular value decomposition algorithm, and the logic gate circuit is connected with the ARM circuit and used for demodulating the noise reduced signals, carrying out sampling processing on the demodulated signals and then outputting the sampled signals. The invention replaces most analog circuits with digital circuits, avoids noise in some circuits, improves the signal to noise ratio through a noise reduction algorithm, changes the traditional multi-equipment discrete signal processing method into an integrated processing mode, can reduce hardware cost, improves stability, and is beneficial to transportation, operation and maintenance.

Description

Signal processing equipment and method for digital pendulum inclinometer
Technical Field
The present document relates to the field of signal processing technologies, and in particular, to a signal processing device and method for a digital pendulum inclinometer.
Background
In order to observe solid tide, earthquake, and the like, it is necessary to acquire continuous terrain state information. The pendulum inclinometer is a terrain variation observation instrument widely applied, and usually when a sensor senses the surface variation, the pendulum inclinometer converts a ground movement signal into a digital signal through signal demodulation, type conversion and other processes.
The signal processing of a typical pendulum inclinometer is divided into two parts, demodulation and acquisition, and the two processes undergone by the signal processing are completed by two parts of circuits, namely an analog circuit and a digital circuit, and usually two separate sets of circuits, two devices and some peripheral devices. In order to extract the weak signal from the background noise, a method is generally adopted in which the signal is amplified and filtered, then demodulated, and finally converted into a digital signal.
The existing instrument signal processing method is mainly based on an analog circuit, and particularly is complete analog circuit processing before signal type conversion. The full analog circuit has the characteristics of simple circuit structure, low cost, obvious delay and circuit internal noise. The reason for the previous processing using the full simulation method is that the inclinometer data does not require a high sampling rate and control of hardware costs. However, in order to design an observation device with higher reliability and stability and obtain higher quality observation data, the delay and noise problems must be fundamentally solved, and the signal processing scheme of the pendulum inclinometer must be redesigned.
The specific problems to be solved are as follows:
1. signal delay problems including phase lag caused by amplifiers and capacitors, etc.;
2. noise problems including circuit internal noise and noise introduced by lines and interfaces;
3. the components are scattered, the circuit is complicated, the devices such as the sensor and the data collector are packaged separately, the transportation and the maintenance are inconvenient, and the additional interference is increased.
Disclosure of Invention
The method aims at providing signal processing equipment and method with high digitizing degree and high integration level, and combines transduction and data acquisition. Because digital circuits are substituted for most analog circuits, internal noise and delay in the circuit can be reduced, largely reducing interference from the environment external to the device. Besides, the signal processing circuit adopts an integrated and monolithic integrated design scheme, so that the volume of the instrument is smaller, redundant circuits, interfaces and the like are avoided, the transportation cost is reduced, and the operation difficulty is also reduced.
The embodiment of the invention provides signal processing equipment of a digital pendulum inclinometer, which is characterized by comprising a sensor circuit, an ARM circuit and a logic gate circuit;
The sensor circuit is connected with the logic gate circuit and the ARM circuit, converts phase data into analog sine waves through the digital-to-analog converter, modulates signals, and sends the modulated signals to the ARM circuit;
The ARM circuit receives the adjustment signal sent by the sensor circuit, and performs noise reduction treatment on the modulation signal through a singular value decomposition algorithm after analog-digital conversion;
And the logic gate circuit is connected with the ARM circuit and is used for demodulating the noise-reduced signal, sampling the demodulated signal and then outputting the sampled signal.
The embodiment of the invention provides a signal processing method of a digital pendulum inclinometer, which comprises the following steps:
After the type of the gambling signal of the sensor circuit is converted, the AXI bus is utilized to store data into the DDR3 memory, then the ARM circuit carries out noise reduction treatment on the data in the memory, wherein the noise reduction treatment realizes separation of useful signals and noise signals through a singular value decomposition algorithm, and the noise signals are removed;
The logic gate circuit reads the data after noise reduction in the memory, stores the data in the BRAM, keeps the real-time refreshing state of the data in the BRAM, and demodulates the signal;
And carrying out downsampling processing on the demodulated signal and then outputting the signal.
By adopting the embodiment of the invention to carry out brand new design on the pendulum inclinometer signal processing circuit, the control and operation design based on the embedded chip has higher digitization degree and circuit integration level, greatly reduces noise and delay, and can obviously enhance the stability and reliability of the system.
Drawings
For a clearer description of one or more embodiments of the present description or of the solutions of the prior art, the drawings that are necessary for the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description that follow are only some of the embodiments described in the description, from which, for a person skilled in the art, other drawings can be obtained without inventive faculty.
FIG. 1 is a schematic diagram of a signal processing apparatus for a digitized pendulum inclinometer in accordance with an embodiment of the present invention;
fig. 2 is a flow chart of a signal processing method of the digitized pendulum inclinometer according to an embodiment of the present invention.
Detailed Description
In order to enable a person skilled in the art to better understand the technical solutions in one or more embodiments of the present specification, the technical solutions in one or more embodiments of the present specification will be clearly and completely described below with reference to the drawings in one or more embodiments of the present specification, and it is obvious that the described embodiments are only some embodiments of the present specification, not all embodiments. All other embodiments, which can be made by one or more embodiments of the present disclosure without inventive faculty, are intended to be within the scope of the present disclosure.
Device embodiment
An embodiment of the present invention provides a signal processing device of a digital pendulum inclinometer, and fig. 1 is a schematic diagram of the signal processing device of the digital pendulum inclinometer according to the embodiment of the present invention, and according to the embodiment of fig. 1, the signal processing device of the digital pendulum inclinometer specifically includes:
sensor circuit 10, ARM circuit 20, and logic gate circuit 30;
The sensor circuit 10 is connected with the logic gate circuit 30 and the ARM circuit 20, converts phase data into analog sine waves through a digital-to-analog converter, modulates signals, and sends modulated signals to the ARM circuit 20;
The ARM circuit 20 receives the modulation signal sent by the sensor circuit 10, and performs noise reduction processing on the modulation signal through a singular value decomposition algorithm after analog-digital conversion;
the logic gate circuit 30 is connected to the ARM circuit 20, and is configured to demodulate the noise-reduced signal, and to sample and output the demodulated signal.
The sensor circuit 10 specifically includes an inverter 12, two digital-to-analog converters 11, and a capacitor 13;
the inverter 12 is connected in series with one of the digital-to-analog converters 11 and then connected in parallel with the other digital-to-analog converter 11, and phase data form two paths of sine waves with opposite phases and equal amplitude through the two digital-to-analog converters;
The capacitor 13 is composed of three parallel capacitance plates, two sine waves with opposite phases and equal amplitudes are added on the parallel capacitance plates at two sides, and the signals led out from the middle plate are modulated waves modulated by baseband signals and are sent to the ARM circuit 20.
The ARM circuit 20 specifically comprises an analog-to-digital converter 21 and a singular value decomposition processor 26;
An analog-to-digital converter 21 for converting the modulated wave into a digital signal;
The singular value decomposition processor 26 is configured to separate the useful signal from the noise signal and extract the noise signal to obtain a modulated signal containing only the topography information. The singular value decomposition processor 26 specifically includes a cache22, a DDR323, a floating point operator 25, and a clock circuit 24;
the Cache22 is used for temporarily storing the data participating in the operation;
DDR323, is used for storing the data that the analog-to-digital converter sends;
a floating-point operator 25 for operating on data that participates in the noise reduction process;
the SVD clock circuit 24 is used for controlling the data in DDR3 to be refreshed in real time.
The logic gate circuit 30 specifically includes a BRAM circuit 31, a demodulation circuit, a filtering down-sampling circuit 36, a logic operation circuit and a read-only memory 40;
the BRAM circuit 31 is used for receiving and temporarily storing data sent by the ARM circuit, and specifically comprises an AXI protocol communication control circuit 32 and a block memory circuit 33, wherein the AXI protocol communication control circuit is used for providing AXI communication protocol support for communication among the circuits, and the block memory circuit is used for storing the data sent by the ARM circuit.
A demodulation circuit that demodulates the modulated signal obtained after the noise reduction, and then removes the high-frequency signal using a low-pass filter 35;
A filter downsampling circuit 36 that samples the low-pass filtered signal using a cascaded integrator-comb filter to reduce the sampling rate and reduce the amount of data;
The logic circuit specifically includes an adder 39, a multiplier 38, and a subtractor 37 for providing multiplication for the demodulation circuit and addition and subtraction for the filter down-sampling circuit.
A read only memory 40 for accessing the phase data.
Wherein the logic gate circuit further comprises a clock circuit 34 for providing clock pulses to the signal processing device of the entire digitized pendulum inclinometer.
In the embodiment of the invention, a direct digital frequency synthesizer (DIRECT DIGITAL Frequency Synthesizer, DDS) is adopted to generate sine waves through a method of addressing the amplitude by a phase accumulator, the phase accumulator starts to accumulate by a frequency control input, phase data and the amplitude have a one-to-one correspondence in a read-only memory (ROM) address, the amplitude data are converted into continuous analog voltage signals through a DAC in the figure 1, and then the sine waves with specific frequency are obtained through filtering processing. The periodic waveform synthesized by the digital circuit is a signal with programmable control of frequency and amplitude.
In order to convert the tilt amount of the capacitor 13, which is the pendulum, into a voltage amount, it is necessary to modulate and demodulate a signal generated by the differential capacitor and extract a signal waveform of a target frequency band. Two paths of sine waves with opposite phases and equal amplitude are added to the capacitance polar plate of the pendulum body, and at the moment, the signal led out from the middle polar plate is a modulated wave modulated by the baseband signal. The modulated wave is converted into a digital signal through an ADC, then filtering and denoising processing is carried out through SVD, SVD is carried out on a matrix representing the signal, and only the first k larger singular values are reserved, so that main information of an image is reserved. This operation will greatly reduce the memory requirements for image storage. This can also be used for image denoising, since small singular values generally correspond to noise.
And multiplying the digital signal data obtained after noise reduction with carrier data in the read-only memory through a multiplier, and then using low-pass filtering. This process is a demodulation process of the signal, expressed mathematically as a multiplication of the signal again with a carrier, and then filtering the high frequency signal with a low pass filter. The whole modem process is expressed mathematically as original signal carrier carrier→lowpass filtering = 1/4 times original signal. Therefore, the high frequency part can be removed by using the low pass filter, and then a multiplier or an adder is added to multiply by four times, so that the baseband signal can be recovered.
The low-pass filtered signal is sampled using a cascaded integrator-comb filter to reduce the amount of data. The position of each frequency component on the frequency spectrum changes after sampling, and in order to avoid frequency aliasing caused by sampling, a cascade integrator-comb (CI C) filter is used for sampling. The circuit is realized by only needing circuits such as an adder, a subtracter, delay and the like, and has lower hardware cost and easy realization.
The method has the advantages that the signal processing circuit of the pendulum inclinometer is designed completely, the control and operation design is based on the embedded chip, the digitalization degree and the circuit integration level are high, the noise and the delay are greatly reduced, and the stability and the reliability of the system can be obviously enhanced. Compared with the prior art, the method has the advantages that the digitization degree of the technical route is higher, and the data processing speed is extremely high. The digital circuit is used for replacing most of the analog circuits, so that internal noise of some circuits can be avoided, the analog circuits generate interference to signals due to voltage fluctuation in the circuits, and the digital circuits digitize the signals, so that the influence of the interference to the signals is avoided. In addition, the introduction of the noise reduction algorithm can further improve the signal to noise ratio and the data quality. The signal processing is carried out by adopting the instruction set processor and the logic gate circuit, the parallel operation of the digital signal is realized, the processing speed is high, the traditional analog circuit connects all parts of the signal processing in series, the delay generated by all parts is inevitably accumulated, and the overlapped delay can be reduced by adopting the parallel calculation. Meanwhile, the traditional multi-equipment discrete signal processing method is changed into an integrated processing mode, so that the hardware cost can be reduced, the stability is improved, and transportation, operation and maintenance are facilitated.
By adopting the embodiment of the invention, the method has the following beneficial effects:
Signal processing is performed based on digital circuitry. Unlike the traditional full analog circuit built based on an amplifier, the method is based on an FPGA to build a digital circuit for signal processing. Except for the sensor circuit and the signal conversion circuit, are digital circuits.
Sensor transduction, data acquisition and data processing integrated design. Different from the traditional split structure of the sensor circuit and the data acquisition device circuit, the method uses the circuit structure design of the integrated functional circuit and the single board integration of each part.
The singular value decomposition algorithm reduces noise. The novel digital noise reduction function is added, and a singular value decomposition algorithm is used for preprocessing signals, so that the signal to noise ratio is improved.
All-digital demodulation. Unlike the traditional analog circuit using phase-locked amplifier circuit, the method is completed in digital detection and digital demodulation modes.
And (5) digital filtering. Different from the prior amplifier circuit filtering, the digital filtering is used, and the coefficients of the filtering, the delay of the filtering and the like of the digital filtering are completely manually controllable, so that different types of filters can be realized at low cost. The cascade integration comb filter is adopted for sampling operation, so that smooth sampling operation can be realized, and the calculation is simple and easy to realize.
The parameters such as filtering parameters, sampling frequency and the like can be changed in field programming, and the modification of the observation mode is very flexible.
Method embodiment
The embodiment of the invention provides a signal processing method of a digital pendulum inclinometer, which comprises the following steps:
after the type of the gambling signal of the sensor circuit is converted, the AXI bus is utilized to store data into the DDR3 memory, then the ARM circuit carries out noise reduction processing on the data in the memory, wherein the noise reduction processing realizes the separation of useful signals and noise signals through a singular value decomposition algorithm and eliminates the noise signals;
The logic gate circuit reads the data after noise reduction in the memory, stores the data in the BRAM, keeps the real-time refreshing state of the data in the BRAM, and demodulates the signal;
And carrying out downsampling processing on the demodulated signal and then outputting the signal.
As shown in fig. 2, which is a flowchart of a signal processing method of a digitized pendulum inclinometer according to an embodiment of the present invention, after signal type conversion is performed on sensor signals, data is stored in a DDR3 memory by using an AXI bus, and then noise reduction processing is performed on the data in the ARM check memory. The noise reduction process realizes the separation of useful signals and noise signals by a Singular Value Decomposition (SVD) algorithm, and eliminates the noise signals. The data after the noise reduction treatment is stored in the memory, the data storage addresses before and after the treatment are different, and the real-time refreshing state is maintained.
The logic gate circuit core reads the data after noise reduction in the memory, and stores the data in the BRAM, and the data in the BRAM is kept in a real-time refreshing state as the memory. The signal is then demodulated by a logic gate circuit, and the signal is calculated in parallel by a pipeline method or the like in order to increase the signal processing speed. Parallel computation of data from the hardware level is a big feature of logic gates.
And carrying out downsampling processing on the demodulated signal and then outputting the signal. The downsampling/sampling process adopts a cascade integral comb filter (CIC) for sampling, wherein the process comprises twice low-pass filtering and twice sampling, and the low-pass filtering adopts a logic gate circuit digital filter.
The design of the signal processing method comprises an analog circuit and a digital circuit except for a signal type conversion part, wherein the signal type conversion part comprises an analog-digital conversion part and a digital-analog conversion part. The digital circuit comprises a programmable logic gate circuit (FPGA) and a processor circuit (ARM). The noise reduction function of the signal is completed by a processor circuit, and the process comprises operations such as matrix addition, multiplication and the like, and memory reading and writing and the like. The control of the signal type converter, the read-only memory, the multiplier, the filter, etc. are all implemented by logic circuits.
It should be noted that the above embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the technical solution described in the above embodiments may be modified or some or all of the technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present invention.

Claims (10)

1.一种数字化摆式倾斜仪的信号处理设备,其特征在于,包括:传感器电路、ARM电路以及逻辑门电路;1. A signal processing device for a digital pendulum inclinometer, characterized in that it comprises: a sensor circuit, an ARM circuit and a logic gate circuit; 传感器电路,与逻辑门电路和ARM电路连接,将相位数据通过数-模转换器转换为模拟正弦波,进行信号调制,再将调制信号发送到ARM电路中;The sensor circuit is connected to the logic gate circuit and the ARM circuit, converts the phase data into an analog sine wave through a digital-to-analog converter, performs signal modulation, and then sends the modulated signal to the ARM circuit; ARM电路,接收所述传感器电路发送的调制信号,将所述调制信号进行模-数转换后通过奇异值分解算法进行降噪处理;An ARM circuit receives a modulation signal sent by the sensor circuit, performs analog-to-digital conversion on the modulation signal, and then performs noise reduction processing using a singular value decomposition algorithm; 逻辑门电路,与所述ARM电路连接,用于将所述降噪后的信号进行解调,对解调后的信号进行将采样处理然后输出。The logic gate circuit is connected to the ARM circuit and is used for demodulating the noise-reduced signal, sampling the demodulated signal and then outputting it. 2.根据权利要求1所述的设备,其特征在于,所述传感器电路具体包括:反相器、两个数模转换器、以及电容器;2. The device according to claim 1, characterized in that the sensor circuit specifically comprises: an inverter, two digital-to-analog converters, and a capacitor; 所述反相器与其中一个数模转换器串联后再与另一个数模转换器进行并联,将所述相位数据经过两个数模转换器形成两路相位相反振幅相等的正弦波;The inverter is connected in series with one of the digital-to-analog converters and then connected in parallel with the other digital-to-analog converter, and the phase data is passed through the two digital-to-analog converters to form two sinusoidal waves with opposite phases and equal amplitudes; 所述电容器由三个平行电容极板组成,所述两路相位相反振幅相等的正弦波加在两侧的平行电容极板上,由中间极板引出的信号为基带信号调制后的调制波发送到ARM电路。The capacitor is composed of three parallel capacitor plates. The two sinusoidal waves with opposite phases and equal amplitudes are added to the parallel capacitor plates on both sides. The signal drawn from the middle plate is a modulated wave modulated by the baseband signal and sent to the ARM circuit. 3.根据权利要求2所述的设备,其特征在于,所述ARM电路具体包括:模数转换器和奇异值分解处理器;3. The device according to claim 2, characterized in that the ARM circuit specifically comprises: an analog-to-digital converter and a singular value decomposition processor; 所述模数转换器,用于将所述调制后的调制波转换为数字信号;The analog-to-digital converter is used to convert the modulated wave into a digital signal; 奇异值分解处理器,用于将所述数字信号进行有用信号和噪声信号的分离,并将所述噪声信号提出,得到只含有地形变信息的调制信号。The singular value decomposition processor is used to separate the useful signal and the noise signal of the digital signal, and extract the noise signal to obtain a modulated signal containing only terrain deformation information. 4.根据权利要求1所述的设备,其特征在于,所述逻辑门电路具体包括:BRAM电路、解调电路、滤波降采样电路、逻辑运算电路以及只读存储器;4. The device according to claim 1, characterized in that the logic gate circuit specifically comprises: a BRAM circuit, a demodulation circuit, a filtering and downsampling circuit, a logic operation circuit and a read-only memory; BRAM电路,用于接收并暂存所述ARM电路发送的数据;A BRAM circuit, used for receiving and temporarily storing data sent by the ARM circuit; 解调电路,将降噪后得到的调制信号进行解调,然后使用低通滤波器率除掉高频信号;The demodulation circuit demodulates the modulated signal obtained after noise reduction, and then uses a low-pass filter to remove high-frequency signals; 滤波降采样电路,将低通滤波后的信号使用级联积分梳状滤波器进行抽样,以降低采样率减少数据量;The filtering and downsampling circuit samples the signal after low-pass filtering using a cascaded integral comb filter to reduce the sampling rate and the amount of data; 逻辑运算电路,用于为所述解调电路及所述滤波降采样电路提供运算支持;A logic operation circuit, used for providing operation support for the demodulation circuit and the filtering and down-sampling circuit; 只读存储器,用于存储所述相位数据。A read-only memory is used to store the phase data. 5.根据权利要求4所述的设备,其特征在于,所述逻辑运算电路具体包括:加法器、乘法器以及减法器,用于为所述解调电路提供乘法运算,为所述滤波降采样电路提供加法及减法运算。5. The device according to claim 4 is characterized in that the logic operation circuit specifically includes: an adder, a multiplier and a subtractor, which are used to provide multiplication operations for the demodulation circuit and provide addition and subtraction operations for the filtering and downsampling circuit. 6.根据权利要求4所述的设备,其特征在于,所述滤波降采样电路进行抽样时采用两次低通滤波和两次抽样的方式。6 . The device according to claim 4 , wherein the filtering and downsampling circuit performs sampling by performing two low-pass filtering and two sampling. 7.根据权利要求4所述的设备,其特征在于,所述BRAM电路具体包括:AXI协议通信控制电路以及块内存电路;7. The device according to claim 4, characterized in that the BRAM circuit specifically comprises: an AXI protocol communication control circuit and a block memory circuit; AXI协议通信控制电路,用于为各个电路之间的通信提供AXI通信协议支持;AXI protocol communication control circuit, used to provide AXI communication protocol support for communication between various circuits; 块内存电路,用于存储所述ARM电路发送的数据。The block memory circuit is used to store the data sent by the ARM circuit. 8.根据权利要求7所述的设备,其特征在于,所述逻辑门电路进一步包括:时钟电路,所述时钟电路用于为整个数字化摆式倾斜仪的信号处理设备提供时钟脉冲。8. The device according to claim 7, characterized in that the logic gate circuit further comprises: a clock circuit, wherein the clock circuit is used to provide clock pulses for the signal processing device of the entire digital pendulum inclinometer. 9.根据权利要求3所述的设备,其特征在于,所述奇异值分解处理器具体包括:cache、DDR3、浮点运算器以及SVD时钟电路;9. The device according to claim 3, characterized in that the singular value decomposition processor specifically comprises: cache, DDR3, floating point operator and SVD clock circuit; 所述cache,用于将参与运算的数据进行暂存;The cache is used to temporarily store the data involved in the calculation; 所述DDR3,用于存储所述模数转换器发送的数据;The DDR3 is used to store data sent by the analog-to-digital converter; 所述浮点运算器,用于对参与降噪处理的数据进行运算;The floating point operator is used to perform operations on the data involved in the noise reduction process; 所述SVD时钟电路,用于控制所述DDR3中的数据进行实时刷新。The SVD clock circuit is used to control the data in the DDR3 to be refreshed in real time. 10.一种数字化摆式倾斜仪的信号处理方法,其特征在于,基于权利要求1-9中任意一项所述的数字化摆式倾斜仪的信号处理设备,包括:10. A signal processing method for a digital pendulum inclinometer, characterized in that the signal processing device for the digital pendulum inclinometer according to any one of claims 1 to 9 comprises: 传感器电路对信号类型转换后,利用AXI总线将数据保存到DDR3内存中,接着ARM电路对内存中的数据进行降噪处理,其中,所述降噪处理通过奇异值分解算法实现有用信号和噪声信号的分离,并将噪声信号剔除;After the sensor circuit converts the signal type, it uses the AXI bus to save the data to the DDR3 memory, and then the ARM circuit performs noise reduction processing on the data in the memory, wherein the noise reduction processing separates the useful signal and the noise signal through the singular value decomposition algorithm and removes the noise signal; 逻辑门电路读取内存中降噪后的数据,并保存在BRAM中,BRAM中数据保持实时刷新状态,并对信号进行解调;The logic gate circuit reads the noise-reduced data in the memory and saves it in the BRAM. The data in the BRAM is kept refreshed in real time and the signal is demodulated. 对解调后的信号进行降采样处理,然后输出。The demodulated signal is downsampled and then output.
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