CN115632632A - FIR (finite Impulse response) general filter designed by adopting parallel flow and method - Google Patents
FIR (finite Impulse response) general filter designed by adopting parallel flow and method Download PDFInfo
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- CN115632632A CN115632632A CN202211377021.6A CN202211377021A CN115632632A CN 115632632 A CN115632632 A CN 115632632A CN 202211377021 A CN202211377021 A CN 202211377021A CN 115632632 A CN115632632 A CN 115632632A
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Abstract
The invention belongs to the field of filters, and particularly relates to an FIR (finite impulse response) general filter adopting parallel pipeline design and a method thereof; the FIR general filter comprises a configuration register, an AHB bus control module, a parallel data control module and a multiply-accumulate module; the configuration register is connected with the AHB bus control module and the parallel data control module through control signal lines, and the AHB bus control module is connected with the parallel data control module and the multiply-accumulate module through an AHB bus. The invention can realize the pipeline operation mode of continuously outputting the data to be processed by two methods of ping-pong buffer alternate data updating and cyclic shift data fetching, thereby improving the data processing efficiency. And taking one corresponding vector data each time, multiplying the vector data by the Q data respectively, and accumulating the product data respectively to obtain a calculation result. The invention has the characteristics of small hardware resource occupation, high processing speed, universality and the like.
Description
Technical Field
The invention belongs to the field of filters, and particularly relates to an FIR (finite impulse response) general filter adopting parallel pipeline design and a method thereof.
Background
The FIR (Finite Impulse Response) filter is a Finite single-bit Impulse Response filter, also called a non-recursive filter, and is the most basic element in a digital signal processing system, and it can guarantee any amplitude-frequency characteristic and simultaneously has strict linear phase-frequency characteristic, and its unit sampling Response is Finite, so that the filter is a stable system. Therefore, FIR filters are widely used in the fields of communications, image processing, pattern recognition, and the like.
The FIR filter contains many convolution operations consisting of multiplication and accumulation, and the most intuitive method is to use a multiply-accumulate device that can be time-division multiplexed. The realization mode occupies less resources, but has lower processing speed, so the realization mode can only be suitable for a system with simple structure and low requirement on the processing speed. If a parallel filter with a pipeline structure is adopted, the signal processing speed can be increased, and therefore the real-time requirement is met. If a large number of multiplier modules are used in parallel to implement a so-called parallel architecture, a large amount of resources will be occupied. Based on the analysis, how to optimize the parallel structure of the FIR filter is very urgent to solve the problems of large occupation of parallel structure resources, low parallel processing speed and the like.
Disclosure of Invention
Based on the problems in the prior art, the invention provides a new implementation scheme to balance the problems in the prior hardware implementation scheme, such as large occupation of parallel structure resources, low parallel processing speed and the like. A plurality of groups of data are processed simultaneously in a parallel mode, so that the processing efficiency is improved; the used ping-pong buf and the modes of cyclic access, shared multiplier resource and the like save the resource consumption of data processing and storage. The values and the lengths of the data to be processed and the vector data have no special requirements, and the universality is realized.
In a first aspect of the present invention, the present invention provides a method for FIR general-purpose filter design using parallel pipeline, the method comprising:
configuring an AHB bus data address, FIR filter parameters and the number Q of parallel processing by using a configuration register;
the parallel data control module sends a data request to the AHB bus control module to request to read data to be processed;
responding to the data request, the AHB bus control module returns a data response request to the parallel data control module;
responding to the response request, the AHB bus control module reads data according to an AHB bus data address configured by the configuration register and inputs Q data to be processed into the parallel data control module;
the parallel data control module reads Q data to be processed and K-order vector coefficients in parallel and outputs one multiplier x of Q multipliers and the other multiplier b of the Q multipliers;
and the Q multiply-accumulate modules carry out once multiply-accumulate operation on the multiplier x and the multiplier b according to the multiply-accumulate input enabling signals, and when the multiply-accumulate input signals are accumulated to the K +1 data, the Q multiply-accumulate modules output multiply-accumulate output enabling signals to the AHB bus control module and output multiply-accumulate results.
In a second aspect of the present invention, the present invention further provides a FIR general-purpose filter of parallel pipeline design, where the FIR general-purpose filter includes a configuration register, an AHB bus control module, a parallel data control module, and a multiply-accumulate module; the configuration register is connected with the AHB bus control module and the parallel data control module through control signal lines, and the AHB bus control module is connected with the parallel data control module and the multiply-accumulate module through an AHB bus.
The invention has the beneficial effects that:
the invention utilizes the parallel data control module to process a plurality of groups of data simultaneously, thus improving the processing efficiency of the FIR filter; the used ping-pong buffer unit and the vector buffer unit can read the data to be processed and the vector data in a parallel pipelining mode, so that the resource consumption of data processing and storage is saved, and the processing speed of the FIR filter can be increased by adopting a cyclic access mode. The values and the lengths of the data to be processed and the vector data have no special requirements, and the universality is realized.
Drawings
FIG. 1 is a schematic diagram of an FIR general filter structure using parallel pipeline design according to an embodiment of the present invention;
FIG. 2 is a block diagram of a multiply-accumulate module according to an embodiment of the present invention;
FIG. 3 is a flow chart of a method for applying a FIR general filter in a parallel pipeline design according to an embodiment of the present invention;
FIG. 4 is a flow chart of parallel processing of data according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
FIG. 1 is a schematic diagram of a FIR general filter designed in parallel pipeline according to an embodiment of the present invention, as shown in FIG. 1, the FIR general filter includes a configuration register, an AHB bus control module, a parallel data control module, and a multiply-accumulate module; the configuration register is connected with the AHB bus control module and the parallel data control module through control signal lines, and the AHB bus control module is connected with the parallel data control module and the multiply-accumulate module through an AHB bus.
In the embodiment of the invention, the configuration register is connected with the configuration source module through the APB BUS (APB _ BUS), so that low power consumption and simplified interface design can be realized, and the complexity of the interface design is reduced.
In the embodiment of the invention, the AHB bus control module is connected with a data source module through a bus, and can provide a high-bandwidth interface for a large number of data transmission modules.
In an embodiment of the present invention, the configuration register includes a plurality of configuration interfaces, one of the configuration interfaces is connected to the AHB bus control module, and the other configuration interface is connected to the parallel data control module, for example, the configuration interfaces may be connected through a control signal line.
In the embodiment of the invention, the configuration register further comprises an input interface, and the APB BUS (APB _ BUS) is connected with the configuration source module, so that low power consumption and simplified interface design can be realized, and the complexity of the interface design is reduced.
The AHB bus control module comprises a plurality of input ports and a plurality of output ports, the parallel pipeline design mode is adopted, reading is not required to be carried out depending on a memory in a traditional FIR filter, the parallel data control module directly reads data to be processed and vector coefficients from the AHB bus control module in real time, and resource consumption of data processing and storage can be saved.
In the embodiment of the present invention, the AHB BUS control module is connected to the data source module through a bidirectional AHB BUS (AHB _ BUS), and can provide a high-bandwidth interface between modules for transmitting a large amount of data.
The parallel data control module comprises an input data unit, a ping-pong buffer unit and a vector buffer unit; the input data unit and the vector buffer unit are respectively connected with the AHB bus control module through different read buses; the ping-pong buffer unit is connected with the input data unit; the ping-pong buffer unit and the vector buffer unit are respectively connected with the multiply-accumulate module through different data transmission lines.
In the embodiment of the present invention, fig. 2 is a schematic diagram of a multiply-accumulate module structure in the embodiment of the present invention, as shown in fig. 2, taking Q =4 as an example, each time, 4 data x (n), x (n-1), x (n-2), x (n-3) and K-order vector coefficients to be processed are read in parallel, the 4 read data x (n), x (n-1), x (n-2), x (n-3) to be processed are multiplied by 4 multipliers respectively with 4 identical coefficients b0 to obtain 4 intermediate results, then the data x (n-1), x (n-2), x (n-3), and x (n-4) to be processed are continuously calculated in a circulating shift manner in a pipeline manner and multiplied by 4 multipliers respectively with four identical coefficients b1 of the next order to obtain intermediate results, products of the data to be processed and the coefficients are sequentially obtained, and the products of the data x (n), x (n-1), x (n-2), x (n-3) to be processed and y (n-1), y (n-3), y (n-1), y (n-3) and y-1-n-3) which are accumulated one by one order, and y-4 are obtained after accumulation; and when the four data to be processed, namely x (n), x (n-1), x (n-2) and x (n-3), are processed, continuing to process the next four data to be processed until the multiply-accumulate processing of all the data to be processed is completed.
Fig. 3 is a flowchart of a method for FIR general-purpose filter design using parallel pipeline, where as shown in fig. 3, the method includes:
configuring an AHB bus data address, FIR filter parameters and the number Q of parallel processing by using a configuration register;
the parallel data control module sends a data request to the AHB bus control module to request to read data to be processed;
responding to the data request, the AHB bus control module returns a data response request to the parallel data control module;
responding to the response request, the AHB bus control module reads data according to an AHB bus data address configured by the configuration register and inputs Q data to be processed into the parallel data control module;
the parallel data control module reads Q data to be processed and K-order vector coefficients in parallel and outputs one multiplier x of Q multipliers and the other multiplier b of the Q multipliers;
the Q multiply-accumulate modules carry out one multiply-accumulate operation on the multiplier x and the multiplier b according to the multiply-accumulate input enabling signals, and when the multiply-accumulate input signals are accumulated to K +1 data, the Q multiply-accumulate modules output multiply-accumulate output enabling signals to the AHB bus control module and output multiply-accumulate results.
In the embodiment of the present invention, as shown in fig. 4, the parallel data control module reads Q pieces of data to be processed and K-order vector coefficients in parallel, and outputs one multiplier x of Q multipliers and another multiplier b of Q multipliers includes:
an input data unit of the parallel data control module reads Q data to be processed;
a ping-pong buffer unit of the parallel data control module initiates a data updating request to an input data unit of the parallel data control module to request real-time data updating;
responding to the data updating request, and replying an updating response request to the ping-pong buffer unit by the input data unit;
responding to the updating response request, and updating the Q data to be processed into a ping-pong buffer unit by the input data unit;
the ping-pong buffer unit takes out Q data to be processed as multiplier x of Q multipliers through cyclic shift;
and a vector buffer unit of the parallel data control module reads K-order vector coefficients from the configuration register, and takes the vector coefficients corresponding to Q data to be processed as a multiplier b of Q multipliers.
In the description of the present invention, it is to be understood that the terms "coaxial", "bottom", "one end", "top", "middle", "other end", "upper", "one side", "top", "inner", "outer", "front", "center", "both ends", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.
In the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "disposed," "connected," "fixed," "rotated," and the like are to be construed broadly, e.g., as being fixedly connected, detachably connected, or integrated; can be mechanically or electrically connected; the terms may be directly connected or indirectly connected through an intermediate, and may be communication between two elements or interaction relationship between two elements, unless otherwise specifically limited, and the specific meaning of the terms in the present invention will be understood by those skilled in the art according to specific situations.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (5)
1. The FIR general filter designed by parallel flow is characterized by comprising a configuration register, an AHB bus control module, a parallel data control module and a multiply-accumulate module; the configuration register is connected with the AHB bus control module and the parallel data control module through control signal lines, and the AHB bus control module is connected with the parallel data control module and the multiply-accumulate module through an AHB bus.
2. The apparatus of claim 1, wherein the parallel data control module comprises an input data unit, a ping-pong buffer unit and a vector buffer unit; the input data unit and the vector buffer unit are respectively connected with the AHB bus control module; the ping-pong buffer unit is connected with the input data unit; the ping-pong buffer unit and the vector buffer unit are respectively connected with the multiply-accumulate module.
3. The apparatus of claim 1, wherein the multiply-accumulate module comprises Q multipliers and Q accumulators, each multiplier is connected to a multiplier x and a multiplier b, and the integrals output by the Q multipliers are respectively fed to the Q accumulators for accumulation.
4. A method for FIR generic filters in a parallel pipeline design, the method comprising:
configuring an AHB bus data address, FIR filter parameters and the number Q of parallel processing by using a configuration register;
the parallel data control module sends a data request to the AHB bus control module to request to read data to be processed;
responding to the data request, the AHB bus control module returns a data response request to the parallel data control module;
responding to the response request, the AHB bus control module reads back data according to an AHB bus data address configured by the configuration register, and Q data to be processed are input into the parallel data control module;
the parallel data control module reads Q data to be processed and K-order vector coefficients in parallel and outputs one multiplier x of Q multipliers and the other multiplier b of the Q multipliers;
the Q multiply-accumulate modules carry out once multiply-accumulate operation on a multiplier x and another multiplier b according to the multiply-accumulate input enabling signals, when the multiply-accumulate input signals are accumulated to K +1 data, the Q multiply-accumulate modules output multiply-accumulate output enabling signals to the AHB bus control module, and output multiply-accumulate results.
5. The method of claim 4, wherein the parallel data control module reads Q data to be processed and K-order vector coefficients in parallel, and outputs a multiplier x of Q multipliers and another multiplier b of Q multipliers comprises:
an input data unit of the parallel data control module reads Q data to be processed;
a ping-pong buffer unit of the parallel data control module initiates a data updating request to an input data unit of the parallel data control module to request real-time data updating;
responding to the data updating request, and replying an updating response request to the ping-pong buffer unit by the input data unit;
responding to the updating response request, and updating the Q data to be processed into a ping-pong buffer unit by the input data unit;
the ping-pong buffer unit takes out Q data to be processed as a multiplier x of Q multipliers through cyclic shift;
and a vector buffer unit of the parallel data control module reads K-order vector coefficients from the configuration register, and takes vector coefficients corresponding to Q data to be processed as multipliers b of Q multipliers.
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| CN120811324A (en) * | 2025-09-16 | 2025-10-17 | 中国计量大学 | Digital filtering system |
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| CN120811324A (en) * | 2025-09-16 | 2025-10-17 | 中国计量大学 | Digital filtering system |
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