CN115622390B - An adaptive charge pump circuit - Google Patents
An adaptive charge pump circuitInfo
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- CN115622390B CN115622390B CN202211157997.2A CN202211157997A CN115622390B CN 115622390 B CN115622390 B CN 115622390B CN 202211157997 A CN202211157997 A CN 202211157997A CN 115622390 B CN115622390 B CN 115622390B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
本发明涉及一种自适应电荷泵电路，包括升压开关组电路，以及与所述升压开关组电路连接的电流采样电路、欠压判断电路，所述电流采样电路和所述欠压判断电路均与一逻辑电路连接，所述逻辑电路与一限流电路连接，所述限流电路与所述升压开关组电路，所述升压开关组电路外接一飞跨电容，且所述升压开关组电路和所述欠压判断电路均与一输出电容连接。本发明能够降低电荷泵模式切换时的过冲电流，有效解决了快速充电过程中充电电流峰值过大的问题，有利于提高电池的使用寿命。
This invention relates to an adaptive charge pump circuit, including a boost switch group circuit, a current sampling circuit, and an undervoltage detection circuit connected to the boost switch group circuit. Both the current sampling circuit and the undervoltage detection circuit are connected to a logic circuit, which is connected to a current limiting circuit. The current limiting circuit is connected to the boost switch group circuit. An external flying capacitor is connected to the boost switch group circuit, and both the boost switch group circuit and the undervoltage detection circuit are connected to an output capacitor. This invention can reduce the overshoot current during charge pump mode switching, effectively solving the problem of excessively high charging current peaks during fast charging, and thus improving battery lifespan.
Description
Technical Field
The invention relates to the technical field of charge pumps, in particular to an adaptive charge pump circuit for supplying power to an audio amplifier.
Background
The charge pump circuit is a common power management circuit, which can realize the boosting function compared with a linear voltage stabilizer, and has higher efficiency and load current. Compared with a switch type power management circuit, the charge pump circuit has the advantages that the output voltage ripple is small, an inductance device is not needed, and the switch type power management circuit is good in certain advantages. In the starting process of a conventional power management circuit, a soft start circuit is often used, for example, the charging speed of an output capacitor is controlled by slowly increasing a reference voltage or limiting current, so that the phenomenon that the output current is out of control and is overlarge is avoided, and voltage or heat damage is caused to a chip.
For a charge pump circuit to power an audio amplifier, the output power needs to be able to switch faster with the input signal, avoiding clipping distortion caused by the power not following the input signal. The fast switching requires fast current injection, and the current and power charging the output capacitor need to be controlled while ensuring a sufficiently large power input, so that the power of each switch is not too large, and large voltage spikes generated on parasitic inductance by large current burrs are avoided, and the chip is damaged after the voltage resistance of the device is exceeded.
However, it is difficult to realize faster switching of the output power supply along with the input signal by the existing charge pump circuit, and meanwhile, it is ensured that the current peak value when the output capacitor is charged is not too large.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides the self-adaptive charge pump circuit, which is used for limiting the current on the output capacitor through the current mirror, so that the problem of overlarge charging current peak value in the rapid charging process can be effectively solved.
The invention provides a self-adaptive charge pump circuit, which comprises a boost switch group circuit, a current sampling circuit and an undervoltage judging circuit, wherein the current sampling circuit and the undervoltage judging circuit are connected with the boost switch group circuit, the current sampling circuit and the undervoltage judging circuit are both connected with a logic circuit, the logic circuit is connected with a current limiting circuit, the current limiting circuit is connected with the boost switch group circuit, the boost switch group circuit is externally connected with a flying capacitor, and the boost switch group circuit and the undervoltage judging circuit are both connected with an output capacitor.
The boost switch group circuit comprises a first switch tube, a second switch tube, a third switch tube and a fourth switch tube which are connected with each other, wherein a source electrode of the first switch tube is connected with a power supply voltage, a drain electrode of the first switch tube is connected with a CP end of the flying capacitor, a grid electrode of the fourth switch tube inputs a first switch signal, a source electrode of the second switch tube is connected with the CP end, a drain electrode of the second switch tube is connected with one end of the output capacitor, the other end of the output capacitor is grounded, a grid electrode of the second switch tube inputs a second switch signal, a source electrode of the third switch tube is connected with the power supply voltage, a drain electrode of the third switch tube is connected with a CN end of the flying capacitor, a grid electrode of the third switch tube inputs a third switch signal, a drain electrode of the fourth switch tube is connected with the CN end, a source electrode of the fourth switch tube is grounded, and a grid electrode of the fourth switch tube inputs a fourth switch signal.
Further, the current sampling circuit comprises a first power switch transistor, wherein a grid electrode of the first power switch transistor is input with the fourth switch signal, a drain electrode of the first power switch transistor is connected with the CN end and is connected with a reverse input end of a first operational amplifier, a source electrode of the third transistor is connected with a source electrode of the fourth switch transistor, a positive input end of the first operational amplifier is connected with a drain electrode of the fourth switch transistor, an output end of the first transistor is connected with a grid electrode of the first transistor and a grid electrode of a second transistor, a drain electrode of the first transistor is connected with a positive input end of the first operational amplifier, a source electrode of the second transistor is connected with a grid electrode of the second transistor, a source electrode of the second transistor is connected with a grid electrode of a power supply, a grid electrode of the third transistor is connected with a drain electrode of the third transistor, a source electrode of the fourth transistor is grounded, a drain electrode of the fifth transistor is connected with a drain electrode of the fifth transistor, a source electrode of the fifth transistor is connected with a grid electrode of the power supply voltage, a source electrode of the first transistor is connected with a grid electrode of the sixth transistor, a source electrode of the sixth transistor is connected with a reverse input end of the first transistor is connected with a reference resistor, and a reverse input end of the third transistor is connected with a reverse input end of the first transistor.
Further, the current sampling circuit further comprises a second power switch tube, wherein the grid electrode of the second power switch tube inputs the third switch signal, the drain electrode of the second power switch tube is connected with the reverse input end of the second operational amplifier, the source electrode of the second power switch tube is connected with the source electrode of the third switch tube, the drain electrode of the third switch tube is connected with the positive input end of the second operational amplifier OP2, the output end of the second operational amplifier is respectively connected with the grid electrode of the seventh transistor and the grid electrode of the eighth transistor, the drain electrode of the seventh transistor is respectively connected with the positive input end of the second operational amplifier and the drain electrode of the third switch tube, the source electrode of the seventh transistor is grounded, and the drain electrode of the eighth transistor is connected with the drain electrode of the fourth transistor and the source electrode of the eighth transistor is grounded.
Further, the undervoltage judging circuit comprises a second comparator, wherein the positive input end of the second comparator is connected with the power supply voltage, the reverse input end of the second comparator is connected with a second resistor and a third resistor which are connected in parallel, and the third resistor R3 is grounded.
Further, the logic circuit comprises a current limiting signal control circuit and a switching signal control circuit.
Further, the overcurrent signal control circuit includes a nor gate and a second inverter connected to each other.
The switching signal control circuit further comprises an oscillator, wherein the oscillator is connected with the input end of a third inverter, the input end of the third inverter is connected with the first input end of a first NAND gate, the oscillator is connected with the first input end of a second NAND gate, the output end of the first NAND gate is connected with the input end of a fourth inverter, the output end of the fourth inverter is connected with the input end of a fifth inverter, the output end of the fifth inverter is connected with the second input end of a second NAND gate, the output end of the second NAND gate is connected with the input end of a sixth inverter, the output end of the sixth inverter is connected with the input end of a seventh inverter, the output end of the seventh inverter is connected with the second input end of the first NAND gate, the fourth inverter is connected with an eighth inverter, the eighth inverter is connected with a ninth inverter and a tenth inverter, and the sixth inverter is connected with an eleventh inverter and a twelfth inverter.
Further, the current limiting circuit comprises a first current mirror formed by the third switching tube and a ninth transistor, and a second current mirror formed by the fourth switching tube and a tenth transistor.
Further, the grid electrode of the third switch tube is connected with the grid electrode of the ninth transistor, the source electrode of the ninth transistor is connected with a power supply voltage, the grid electrode is in short circuit with the drain electrode and inputs the third switch signal, the drain electrode of the eleventh transistor is connected with the source electrode of the eleventh transistor, the grid electrode of the eleventh transistor inputs a reverse overcurrent signal, the drain electrode of the eleventh transistor is connected with the input end of the first current source, the output end of the first current source is grounded, the grid electrode of the fourth switch tube is connected with the grid electrode of the tenth transistor, the source electrode of the tenth transistor is grounded, the grid electrode and the drain electrode of the tenth transistor are in short circuit and input the fourth switch signal, the drain electrode of the twelfth transistor is connected with the source electrode of the twelfth transistor, the grid electrode of the twelfth transistor inputs an overcurrent signal, the drain electrode of the twelfth transistor is connected with the output end of the second current source, and the input end of the second current source is connected with the source electrode of the third switch tube.
According to the invention, the charge pump mode is switched through the boost switch group circuit and the logic circuit, the current limiting circuit is controlled through the current sampling circuit and the undervoltage judging circuit, the overshoot current during the charge pump mode switching is reduced, the problem of overlarge charging current peak value in the rapid charging process is effectively solved, and the service life of the battery is prolonged.
Drawings
Fig. 1 is a schematic diagram of the architecture of an adaptive charge pump circuit according to the present invention.
FIG. 2 is a schematic diagram of the boost switch set circuit and the phase of the switching signal in FIG. 1.
Fig. 3 is a schematic diagram of the current sampling circuit of fig. 1.
FIG. 4 is a schematic diagram of the brown-out judging circuit in FIG. 1.
Fig. 5 (a) is a schematic diagram of a current limit signal control circuit of the logic circuit in fig. 1, and fig. 5 (b) is a schematic diagram of a switching signal control circuit of the logic circuit in fig. 1.
Fig. 6 is a schematic diagram of the current limiting circuit of fig. 1.
Fig. 7 is a waveform diagram of an adaptive charge pump circuit in accordance with the present invention when in operation.
Detailed Description
Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
As shown in fig. 1, the self-adaptive charge pump circuit provided by the invention comprises a boost switch group circuit 1, a current sampling circuit 2 and an undervoltage judging circuit 3 which are connected with the boost switch group circuit 1, wherein the current sampling circuit 2 and the undervoltage judging circuit 3 are connected with a logic circuit 4, the logic circuit 4 is connected with a current limiting circuit 5, and the current limiting circuit 5 is connected with the boost switch group circuit 1. The boost switch group circuit 1 is externally connected with a flying capacitor Cfly for rapidly increasing and decreasing voltage, and the boost switch group circuit 1 and the undervoltage judging circuit 3 are connected with an output capacitor Cout.
The current sampling circuit 2 samples the current Isense generated by the boost switch group circuit 1, converts the sampled current into voltage, compares the voltage with a preset reference voltage Vref1, and outputs a reverse overcurrent signal OCZ through an inverter. The undervoltage judgment circuit 3 samples the output voltage PVDD generated by the step-up switch group circuit 1, compares the sampled voltage with the power supply voltage VDD, and outputs a low-value voltage signal UV. The reverse overcurrent signal OCZ and the low-value voltage signal UV are input together into the logic circuit 4, and are converted into the current limiting signal CL and the reverse current limiting signal CLZ. The current limit signal CL and the reverse current limit signal CLZ are input to the current limit circuit 5, and at the same time, the first switching signal S1, the second switching signal S2, the third switching signal S3, and the fourth switching signal S4 generated by the logic circuit 4 are input to the boost switch group circuit 1. The current limiting circuit 5 outputs a control current Ilimit to the boost switch group circuit 1 to control a current flowing across the flying capacitor Cfly in the boost switch group circuit 1.
The circuit modules are described in detail below.
As shown in fig. 2, the boost switch group circuit 1 includes a first switch tube MP1, a second switch tube MP2, a third switch tube MP3, and a fourth switch tube MN4 connected to each other. Specifically, the source electrode of the first switch tube MP1 is connected to the power supply voltage VDD, the drain electrode is connected to the CP end of the flying capacitor Cfly, the gate electrode inputs the first switch signal S1, the source electrode of the second switch tube MP2 is connected to the CP end of the flying capacitor Cfly, the drain electrode is connected to one end of the output capacitor Cout, the other end of the output capacitor Cout is grounded, the gate electrode of the second switch tube MP2 inputs the second switch signal S2, the source electrode of the third switch tube MP3 is connected to the power supply voltage VDD, the drain electrode is connected to the CN end of the flying capacitor Cfly, the gate electrode inputs the third switch signal S3, the drain electrode of the fourth switch tube MN4 is connected to the CN end of the flying capacitor Cfly, the source electrode is grounded, and the gate electrode inputs the fourth switch signal S4. The boost switch group circuit 1 generates an output voltage PVDD for powering the output capacitor Cout.
As shown in fig. 3, the current sampling circuit 2 includes a first power switching transistor MNN4 and a second power switching transistor MPP3, and the current Isense is a current flowing through the MNN4 and the MPP 3. The gate of the first power switch tube MNN4 inputs the fourth switch signal S4, the drain is connected to the CN end of the flying capacitor Cfly and to the inverting input end of the first operational amplifier OP1, and the source is connected to the source of the fourth switch tube MN4 of the boost switch group circuit 1. The positive input end of the first operational amplifier OP1 is connected to the drain electrode of the fourth switching transistor MN4, and the output end is connected to the gate electrode of the first transistor MP5 and the gate electrode of the second transistor MP 6. The drain of the first transistor MP5 is connected to the positive input terminal of the first operational amplifier OP1, and the source is connected to the source of the second transistor MP 6. The drain of the second transistor MP6 is connected to the drain of the third transistor MN9 and the gate of the fourth transistor MN10, and the source of the second transistor MP6 is connected to the power supply voltage VDD. The gate and drain of the third transistor MP9 are shorted, and the source is grounded. The gate of the fourth transistor MN10 is connected to the gate of the third transistor MP9, the source is grounded, and the drain is connected to the drain of the fifth transistor MP 11. The source of the fifth transistor MP11 is connected to the power supply voltage VDD, the drain and the gate are shorted, and the gate is connected to the gate of the sixth transistor MP 12. The source of the sixth transistor MP12 is connected to the power voltage VDD, the drain is connected to the inverting input terminal of the first comparator Comp1 and one end of the first resistor R1, and the other end of the resistor R1 is grounded. The positive input end of the first comparator Comp1 is connected to a preset reference voltage Vref1, and the output end of the first comparator Comp1 is connected to the first inverter Inv1. The first comparator Comp1 outputs an over-current signal OC, and the over-current signal OC outputs an inverted over-current signal OCZ thereof after passing through the inverter Inv 2.
The gate of the second power switch tube MPP3 inputs the third switch signal S3, the drain is connected to the inverting input end of the second operational amplifier OP2, and the source is connected to the source of the third switch tube MP3 of the voltage switch group circuit 1. The drain electrode of the third switching tube MP3 is connected to the positive input end of the second operational amplifier OP2, and the output end of the second operational amplifier OP2 is connected to the gate electrode of the seventh transistor MN7 and the gate electrode of the eighth transistor MN8, respectively. The drain of the seventh transistor MN7 is connected to the positive input terminal of the second operational amplifier OP2 and the drain of the third switching transistor MP3, respectively, and the source of the seventh transistor MN7 is grounded. The drain of the eighth transistor MN8 is connected to the drain of the fourth transistor MN10, and the source is grounded.
As shown in fig. 4, the undervoltage judging circuit 3 includes a second comparator Comp2, a positive input terminal of the second comparator Comp2 is connected to the power supply voltage VDD, a negative input terminal of the second comparator Comp2 is connected to the second resistor R2 and the third resistor R3 in parallel, and the third resistor R3 is grounded. The output voltage PVDD is input to the inverting input terminal of the second comparator Comp2 after being divided by the second resistor R2 and the third resistor R3, and the low-value voltage signal UV is output most.
The logic circuit 4 includes a current limit signal control circuit 41 and a switching signal control circuit 42, as shown in fig. 5 (a), which includes a nor gate OR1 and a second inverter Inv2 connected to each other. The nor gate OR1 has two input terminals to which the reverse overcurrent signal OCZ and the low-value voltage signal UV are input, and an output terminal to which the reverse current-limiting signal CLZ is output, and the reverse current-limiting signal CLZ is passed through the second inverter Inv2 to which the current-limiting signal CL is output.
As shown in fig. 5 (b), the switching signal control circuit 42 includes an oscillator OSC, the clock signal generated by the oscillator OSC is input to the first input terminal of the first nand gate nand1 through the third inverter inv3, and the clock signal is input to the first input terminal of the second nand gate nand 2. The output end of the first NAND gate nand1 is connected with the input end of a fourth inverter inv4, the output end of the fourth inverter inv4 is connected with the input end of a fifth inverter inv5, and the output end of the fifth inverter inv5 is connected with the second input end of the second NAND gate nand 2. The output end of the second NAND gate nand2 is connected with the input end of a sixth inverter inv6, the output end of the sixth inverter inv6 is connected with the input end of a seventh inverter inv7, and the output end of the seventh inverter inv7 is connected with the second input end of the first NAND gate nand 1. The fourth inverter inv4 outputs a first phase signal phase1, the first phase signal phase1 is input to the input end of the ninth inverter inv9 through the eighth inverter inv8, the ninth inverter inv9 outputs a first switching signal S1, and the first phase signal phase1 is input to the input end of the tenth inverter inv10 through the eighth inverter inv8, and the tenth inverter inv10 outputs a fourth switching signal S4. The sixth inverter inv6 outputs the second phase signal phase2, the second phase signal phase2 outputs the second switching signal S2 through the eleventh inverter inv11, and the third switching signal S3 through the twelfth inverter inv 12.
As shown in fig. 6, the current limiting current 5 includes a first current mirror constituted by the third switching transistor MP3 and the ninth transistor MCLP of the boost switching group circuit 1, and a second current mirror constituted by the fourth switching transistor MN4 and the tenth transistor MCLN of the boost switching group circuit 1. The gate of the third switch MP3 is connected to the gate of the ninth transistor MCLP. The ninth transistor MCLP has a source connected to the power supply voltage VDD, a gate shorted to a drain and inputting the third switching signal S3, and a drain connected to the source of the eleventh transistor MP 13. The gate of the eleventh transistor MP13 inputs the reverse overcurrent signal CLZ, the drain is connected to the input terminal of the first current source ICLP, and the output terminal of the first current source ICLP is grounded. The gate of the fourth switching transistor MN4 is connected to the gate of the tenth transistor MCLN, and the source is grounded. The source of the tenth transistor MCLN is grounded, the gate and the drain are shorted and the fourth switching signal S4 is input, and the drain is also connected to the source of the twelfth transistor MN 14. The twelfth transistor MN14 has a gate input the over-current signal CL, a drain connected to the output terminal of the second current source ICLN, and an input terminal of the second current source ICLN connected to the source of the third switching transistor MP 3.
For a better understanding, the working principle of the adaptive charge pump circuit of the present invention is described below with reference to fig. 1 to 6.
When the charge pump is in the 1-time mode, the first switch signal S1 input by the gate of the first switch tube MP1, the second switch signal S2 input by the gate of the second switch tube MP2, and the fourth switch signal S4 input by the gate of the fourth switch tube MN4 are connected to the low potential, and the third switch signal S3 input by the gate of the third switch tube MP3 is connected to the high potential. At this time, the first switching tube MP1 and the second switching tube MP2 are both turned on, and the power supply voltage is connected to PVDD, so that the voltage value of the output voltage PVDD is VDD.
When the charge pump is in the 2-time mode, the switching tube has two switching phases, namely a charging phase ph1 (i.e. the first phase signal phase 1) and a discharging phase ph2 (i.e. the second phase signal phase 2). When the charging phase ph1 is in the charging phase, the first switching signal S1 input by the gate of the first switching tube MP1 is at a low potential, the second switching signal S2 input by the gate of the second switching tube MP2, the third switching signal S3 input by the gate of the third switching tube MP3, and the fourth switching signal S4 input by the gate of the fourth switching tube MN4 are at a high potential, the power supply voltage VDD charges the flying capacitor Cfly through the first switching tube MP1 and the fourth switching tube MN4, and at this time, the output capacitor Cout discharges the load. When the discharge phase ph2 is set, the first switching signal S1 input by the gate of the first switching tube MP1 is at a high potential, the second switching signal S2 input by the gate of the second switching tube MP2, the third switching signal S3 input by the gate of the third switching tube MP3, and the fourth switching signal S4 input by the gate of the fourth switching tube MN4 are at a low potential, and at this time, the flying capacitor Cfly supplies power to the load and the output capacitor Cout at the same time.
In 1-fold mode, the voltage of the flying capacitor Cfly and the voltage of the output capacitor Cout are both equal to VDD. When the charge pump is switched from the 1-time mode to the 2-time mode, the second switching tube MP2 and the third switching tube MP3 are turned on, and the voltage at the CN end of the output capacitor Cout is 0 because the voltage of the flying capacitor Cfly does not suddenly change, at this time, vds (drain-source voltage) of the third switching tube MP3 is VDD, vgs (gate-source voltage) is VDD. According to the transfer characteristic curve of the MOS transistor, the Id (drain current) of the third switching transistor MP3 is very large at this time, and the current in such an operating state needs to be limited to prevent damage to the device.
When the charge pump is in the ph1 state of 2 times mode, the fourth switching signal S4 is at high potential, the fourth switching tube MN4 and the first power switching tube MNN4 are turned on, the power tube current information is sampled to the sixth transistor MP12 through the first operational amplifier OP1 and a current mirror with a certain proportion, converted into a voltage on the first resistor R1 and input to the inverting input terminal of the first comparator Comp 1. When the sampled current is greater than a certain threshold, the positive terminal voltage of the first resistor R1 is greater than the reference voltage Vref1, and at this time, the reverse overcurrent signal OCZ output by the first comparator Comp1 is low, and the current limit signal CL output by the logic circuit 4 is high.
When the charge pump is in the ph2 state of 2 times mode, the third switch signal S3 is at low potential, the third switch tube MP3 and the first power switch tube MPP3 are turned on, the power tube current information is sampled to the sixth transistor MP12 through the second operational amplifier OP2 and a current mirror with a certain proportion, converted into a voltage on the first resistor R1 and input to the inverting input terminal of the first comparator Comp 1. When the sampled current is greater than a certain threshold, the positive terminal voltage of the first resistor R1 is greater than the reference voltage Vref1, and at this time, the reverse overcurrent signal OCZ output by the first comparator Comp1 is low, and the current limit signal CL output by the logic circuit 4 is high.
When the charge pump is in the 2-time mode, if the output voltage PVDD is lower than 1.5 times VDD, UV is high, then the output CL of the logic circuit 4 is high regardless of whether the reverse overcurrent signal OCZ is high or low, if PVDD is greater than 1.5 times VDD, UV is low, then CL is high when OCZ is low, and CL is low when OCZ is high.
When CL is high, CLZ is low, and the twelfth transistor MN14 and the eleventh transistor MP13 are turned on. Since the third switching transistor MP3 and the ninth transistor MCLP constitute the first current mirror, and the fourth switching transistor MN4 and the tenth transistor MCLN constitute the first current mirror, the currents of the switching transistors MN4 and MP3 are affected by the limiting current flowing through the transistors MN14 and MP13, respectively, and the current sources ICLN and ICLP are used instead of the limiting current.
Fig. 7 is a waveform diagram of the charge pump circuit of the present invention when the charge pump is switched from the 1-time mode to the 2-time mode, when the PVDD voltage division sampled by the under-voltage judging circuit 3 is smaller than VDD in the immediately started charging period, UV is high, CL output by the logic circuit 4 is high, the current limiting circuit 5 limits the current at the end of the flying capacitor Cfly capacitor CN, and the charge pump is directly in the current limiting operation state without waiting for the sampling result of the over-current sampling. When the PVDD voltage sampled by the undervoltage judging circuit 3 is larger than 1.5 times VDD and UV is low, the current sampling circuit 2 and the undervoltage judging circuit 3 detect that the current exceeds the overcurrent threshold, OCZ is low, at the moment, the CL of the logic output is high, and the charge pump works in a current limiting mode. If PVDD is higher than 1.5 times VDD and the output load is small, CL is low, the charge pump works normally, the gate voltage of MP3 can be as low as 0, and the gate voltage of Mn4 can be as high as VDD.
The invention can change working modes according to the magnitude of the audio input signal, when the magnitude of the input audio signal is smaller, the required output power is small, high output voltage is not required, the output voltage and the input voltage of the charge pump are equal, and the charge pump switch group is configured into a 1-time mode. When the amplitude of the input audio signal is large, the required output power is large, the charge pump outputs twice the input voltage, and the charge pump switch group is configured in a 2-time mode. Thus, the voltage can be fully utilized in the whole input signal range, and the balance of the dynamic range and the efficiency of the output power can be realized.
The foregoing description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and various modifications can be made to the above-described embodiment of the present invention. All simple, equivalent changes and modifications made in accordance with the claims and the specification of this application fall within the scope of the patent claims. The present invention is not described in detail in the conventional art.
Claims (8)
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| CN202211157997.2A CN115622390B (en) | 2022-09-22 | 2022-09-22 | An adaptive charge pump circuit |
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| CN202211157997.2A CN115622390B (en) | 2022-09-22 | 2022-09-22 | An adaptive charge pump circuit |
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| CN115622390B true CN115622390B (en) | 2025-11-04 |
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| CN218771775U (en) * | 2022-09-22 | 2023-03-28 | 上海灿瑞科技股份有限公司 | Self-adaptive charge pump circuit |
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| JP4689394B2 (en) * | 2005-07-29 | 2011-05-25 | パナソニック株式会社 | Semiconductor integrated circuit |
| US9035626B2 (en) * | 2010-08-18 | 2015-05-19 | Volterra Semiconductor Corporation | Switching circuits for extracting power from an electric power source and associated methods |
| CN102832807B (en) * | 2012-08-31 | 2014-07-02 | 电子科技大学 | Current control circuit for charge pump |
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| CN218771775U (en) * | 2022-09-22 | 2023-03-28 | 上海灿瑞科技股份有限公司 | Self-adaptive charge pump circuit |
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